-@@ -2416,6 +2416,22 @@ ath5k_tx_complete_poll_work(struct work_
- * Initialization routines *
- \*************************/
-
-+static const struct ieee80211_iface_limit if_limits[] = {
-+ { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
-+ { .max = 4, .types =
-+#ifdef CONFIG_MAC80211_MESH
-+ BIT(NL80211_IFTYPE_MESH_POINT) |
-+#endif
-+ BIT(NL80211_IFTYPE_AP) },
-+};
-+
-+static const struct ieee80211_iface_combination if_comb = {
-+ .limits = if_limits,
-+ .n_limits = ARRAY_SIZE(if_limits),
-+ .max_interfaces = 2048,
-+ .num_different_channels = 1,
-+};
-+
- int __devinit
- ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
- {
-@@ -2437,6 +2453,9 @@ ath5k_init_ah(struct ath5k_hw *ah, const
- BIT(NL80211_IFTYPE_ADHOC) |
- BIT(NL80211_IFTYPE_MESH_POINT);
-
-+ hw->wiphy->iface_combinations = &if_comb;
-+ hw->wiphy->n_iface_combinations = 1;
-+
- /* SW support for IBSS_RSN is provided by mac80211 */
- hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
-
---- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
-+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
-@@ -618,19 +618,10 @@ static void ar5008_hw_init_bb(struct ath
- u32 synthDelay;
-
- synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
-- if (IS_CHAN_B(chan))
-- synthDelay = (4 * synthDelay) / 22;
-- else
-- synthDelay /= 10;
--
-- if (IS_CHAN_HALF_RATE(chan))
-- synthDelay *= 2;
-- else if (IS_CHAN_QUARTER_RATE(chan))
-- synthDelay *= 4;
-
- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
-
-- udelay(synthDelay + BASE_ACTIVATE_DELAY);
-+ ath9k_hw_synth_delay(ah, chan, synthDelay);
- }
-
- static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
-@@ -868,7 +859,7 @@ static int ar5008_hw_process_ini(struct
- ar5008_hw_set_channel_regs(ah, chan);
- ar5008_hw_init_chain_masks(ah);
- ath9k_olc_init(ah);
-- ath9k_hw_apply_txpower(ah, chan);
-+ ath9k_hw_apply_txpower(ah, chan, false);
-
- /* Write analog registers */
- if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
-@@ -948,12 +939,8 @@ static bool ar5008_hw_rfbus_req(struct a
- static void ar5008_hw_rfbus_done(struct ath_hw *ah)
- {
- u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
-- if (IS_CHAN_B(ah->curchan))
-- synthDelay = (4 * synthDelay) / 22;
-- else
-- synthDelay /= 10;
-
-- udelay(synthDelay + BASE_ACTIVATE_DELAY);
-+ ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
-
- REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
- }
---- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
-@@ -1000,10 +1000,12 @@ static bool ar9003_hw_init_cal(struct at
- if (mci && IS_CHAN_2GHZ(chan) && run_agc_cal)
- ar9003_mci_init_cal_req(ah, &is_reusable);
-
-- txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
-- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
-- udelay(5);
-- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
-+ if (!(IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))) {
-+ txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
-+ REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
-+ udelay(5);
-+ REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
-+ }
-
- skip_tx_iqcal:
- if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
---- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
-@@ -4281,18 +4281,10 @@ static int ar9003_hw_tx_power_regwrite(s
- #undef POW_SM
- }
-
--static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
-- u8 *targetPowerValT2)
-+static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
-+ u8 *targetPowerValT2,
-+ bool is2GHz)
- {
-- /* XXX: hard code for now, need to get from eeprom struct */
-- u8 ht40PowerIncForPdadc = 0;
-- bool is2GHz = false;
-- unsigned int i = 0;
-- struct ath_common *common = ath9k_hw_common(ah);
--
-- if (freq < 4000)
-- is2GHz = true;
--
- targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
- ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
- is2GHz);
-@@ -4305,6 +4297,11 @@ static void ar9003_hw_set_target_power_e
- targetPowerValT2[ALL_TARGET_LEGACY_54] =
- ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
- is2GHz);
-+}
-+
-+static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
-+ u8 *targetPowerValT2)
-+{
- targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
- ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
- freq);
-@@ -4314,6 +4311,11 @@ static void ar9003_hw_set_target_power_e
- ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
- targetPowerValT2[ALL_TARGET_LEGACY_11S] =
- ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
-+}
-+
-+static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
-+ u8 *targetPowerValT2, bool is2GHz)
-+{
- targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
- ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
- is2GHz);
-@@ -4356,6 +4358,16 @@ static void ar9003_hw_set_target_power_e
- targetPowerValT2[ALL_TARGET_HT20_23] =
- ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
- is2GHz);
-+}
-+
-+static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
-+ u16 freq,
-+ u8 *targetPowerValT2,
-+ bool is2GHz)
-+{
-+ /* XXX: hard code for now, need to get from eeprom struct */
-+ u8 ht40PowerIncForPdadc = 0;
-+
- targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
- ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
- is2GHz) + ht40PowerIncForPdadc;
-@@ -4399,6 +4411,26 @@ static void ar9003_hw_set_target_power_e
- targetPowerValT2[ALL_TARGET_HT40_23] =
- ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
- is2GHz) + ht40PowerIncForPdadc;
-+}
-+
-+static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
-+ struct ath9k_channel *chan,
-+ u8 *targetPowerValT2)
-+{
-+ bool is2GHz = IS_CHAN_2GHZ(chan);
-+ unsigned int i = 0;
-+ struct ath_common *common = ath9k_hw_common(ah);
-+ u16 freq = chan->channel;
-+
-+ if (is2GHz)
-+ ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
-+
-+ ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
-+ ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
-+
-+ if (IS_CHAN_HT40(chan))
-+ ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
-+ is2GHz);
-
- for (i = 0; i < ar9300RateSize; i++) {
- ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
-@@ -4778,9 +4810,6 @@ static void ar9003_hw_set_power_per_rate
- scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
- antenna_reduction);
-
-- /*
-- * Get target powers from EEPROM - our baseline for TX Power
-- */
- if (is2ghz) {
- /* Setup for CTL modes */
- /* CTL_11B, CTL_11G, CTL_2GHT20 */
-@@ -4952,7 +4981,12 @@ static void ath9k_hw_ar9300_set_txpower(
- unsigned int i = 0, paprd_scale_factor = 0;
- u8 pwr_idx, min_pwridx = 0;
-
-- ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
-+ memset(targetPowerValT2, 0 , sizeof(targetPowerValT2));
-+
-+ /*
-+ * Get target powers from EEPROM - our baseline for TX Power
-+ */
-+ ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
-
- if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
- if (IS_CHAN_2GHZ(chan))
---- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
-@@ -54,7 +54,7 @@ void ar9003_paprd_enable(struct ath_hw *
-
- if (val) {
- ah->paprd_table_write_done = true;
-- ath9k_hw_apply_txpower(ah, chan);
-+ ath9k_hw_apply_txpower(ah, chan, false);
- }
-
- REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
---- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
-+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
-@@ -526,22 +526,10 @@ static void ar9003_hw_init_bb(struct ath
- * Value is in 100ns increments.
- */
- synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
-- if (IS_CHAN_B(chan))
-- synthDelay = (4 * synthDelay) / 22;
-- else
-- synthDelay /= 10;
-
- /* Activate the PHY (includes baseband activate + synthesizer on) */
- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
--
-- /*
-- * There is an issue if the AP starts the calibration before
-- * the base band timeout completes. This could result in the
-- * rx_clear false triggering. As a workaround we add delay an
-- * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
-- * does not happen.
-- */
-- udelay(synthDelay + BASE_ACTIVATE_DELAY);
-+ ath9k_hw_synth_delay(ah, chan, synthDelay);
- }
-
- static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
-@@ -692,7 +680,7 @@ static int ar9003_hw_process_ini(struct
- ar9003_hw_override_ini(ah);
- ar9003_hw_set_channel_regs(ah, chan);
- ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
-- ath9k_hw_apply_txpower(ah, chan);
-+ ath9k_hw_apply_txpower(ah, chan, false);
-
- if (AR_SREV_9462(ah)) {
- if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
-@@ -723,6 +711,14 @@ static void ar9003_hw_set_rfmode(struct
-
- if (IS_CHAN_A_FAST_CLOCK(ah, chan))
- rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
-+ if (IS_CHAN_QUARTER_RATE(chan))
-+ rfMode |= AR_PHY_MODE_QUARTER;
-+ if (IS_CHAN_HALF_RATE(chan))
-+ rfMode |= AR_PHY_MODE_HALF;
-+
-+ if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
-+ REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
-+ AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
-
- REG_WRITE(ah, AR_PHY_MODE, rfMode);
- }
-@@ -793,12 +789,8 @@ static bool ar9003_hw_rfbus_req(struct a
- static void ar9003_hw_rfbus_done(struct ath_hw *ah)
- {
- u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
-- if (IS_CHAN_B(ah->curchan))
-- synthDelay = (4 * synthDelay) / 22;
-- else
-- synthDelay /= 10;
-
-- udelay(synthDelay + BASE_ACTIVATE_DELAY);
-+ ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);