toolchain/binutils/patches/2.21.1/700-avr32.patch

   1 --- a/bfd/archures.c
   2 +++ b/bfd/archures.c
   3 @@ -373,6 +373,12 @@ DESCRIPTION
   4  .#define bfd_mach_avr5         5
   5  .#define bfd_mach_avr51                51
   6  .#define bfd_mach_avr6         6
   7 +.  bfd_arch_avr32,     {* Atmel AVR32 *}
   8 +.#define bfd_mach_avr32_ap     7000
   9 +.#define bfd_mach_avr32_uc     3000
  10 +.#define bfd_mach_avr32_ucr1    3001
  11 +.#define bfd_mach_avr32_ucr2    3002
  12 +.#define bfd_mach_avr32_ucr3    3003
  13  .  bfd_arch_bfin,        {* ADI Blackfin *}
  14  .#define bfd_mach_bfin          1
  15  .  bfd_arch_cr16,       {* National Semiconductor CompactRISC (ie CR16). *}
  16 @@ -469,6 +475,7 @@ extern const bfd_arch_info_type bfd_alph
  17  extern const bfd_arch_info_type bfd_arc_arch;
  18  extern const bfd_arch_info_type bfd_arm_arch;
  19  extern const bfd_arch_info_type bfd_avr_arch;
  20 +extern const bfd_arch_info_type bfd_avr32_arch;
  21  extern const bfd_arch_info_type bfd_bfin_arch;
  22  extern const bfd_arch_info_type bfd_cr16_arch;
  23  extern const bfd_arch_info_type bfd_cr16c_arch;
  24 @@ -546,6 +553,7 @@ static const bfd_arch_info_type * const
  25      &bfd_arc_arch,
  26      &bfd_arm_arch,
  27      &bfd_avr_arch,
  28 +    &bfd_avr32_arch,
  29      &bfd_bfin_arch,
  30      &bfd_cr16_arch,
  31      &bfd_cr16c_arch,
  32 --- a/bfd/bfd-in2.h
  33 +++ b/bfd/bfd-in2.h
  34 @@ -2060,6 +2060,12 @@ enum bfd_architecture
  35  #define bfd_mach_avr5          5
  36  #define bfd_mach_avr51         51
  37  #define bfd_mach_avr6          6
  38 +  bfd_arch_avr32,     /* Atmel AVR32 */
  39 +#define bfd_mach_avr32_ap      7000
  40 +#define bfd_mach_avr32_uc      3000
  41 +#define bfd_mach_avr32_ucr1    3001
  42 +#define bfd_mach_avr32_ucr2    3002
  43 +#define bfd_mach_avr32_ucr3    3003
  44    bfd_arch_bfin,        /* ADI Blackfin */
  45  #define bfd_mach_bfin          1
  46    bfd_arch_cr16,       /* National Semiconductor CompactRISC (ie CR16). */
  47 @@ -3996,6 +4002,88 @@ instructions  */
  48    BFD_RELOC_RX_ABS16UL,
  49    BFD_RELOC_RX_RELAX,
  50
  51 +/* Difference between two labels: L2 - L1. The value of L1 is encoded
  52 +as sym + addend, while the initial difference after assembly is
  53 +inserted into the object file by the assembler.  */
  54 +  BFD_RELOC_AVR32_DIFF32,
  55 +  BFD_RELOC_AVR32_DIFF16,
  56 +  BFD_RELOC_AVR32_DIFF8,
  57 +
  58 +/* Reference to a symbol through the Global Offset Table. The linker
  59 +will allocate an entry for symbol in the GOT and insert the offset
  60 +of this entry as the relocation value.  */
  61 +  BFD_RELOC_AVR32_GOT32,
  62 +  BFD_RELOC_AVR32_GOT16,
  63 +  BFD_RELOC_AVR32_GOT8,
  64 +
  65 +/* Normal (non-pc-relative) code relocations. Alignment and signedness
  66 +is indicated by the suffixes. S means signed, U means unsigned. W
  67 +means word-aligned, H means halfword-aligned, neither means
  68 +byte-aligned (no alignment.) SUB5 is the same relocation as 16S.  */
  69 +  BFD_RELOC_AVR32_21S,
  70 +  BFD_RELOC_AVR32_16U,
  71 +  BFD_RELOC_AVR32_16S,
  72 +  BFD_RELOC_AVR32_SUB5,
  73 +  BFD_RELOC_AVR32_8S_EXT,
  74 +  BFD_RELOC_AVR32_8S,
  75 +  BFD_RELOC_AVR32_15S,
  76 +
  77 +/* PC-relative relocations are signed if neither 'U' nor 'S' is
  78 +specified. However, we explicitly tack on a 'B' to indicate no
  79 +alignment, to avoid confusion with data relocs. All of these resolve
  80 +to sym + addend - offset, except the one with 'N' (negated) suffix.
  81 +This particular one resolves to offset - sym - addend.  */
  82 +  BFD_RELOC_AVR32_22H_PCREL,
  83 +  BFD_RELOC_AVR32_18W_PCREL,
  84 +  BFD_RELOC_AVR32_16B_PCREL,
  85 +  BFD_RELOC_AVR32_16N_PCREL,
  86 +  BFD_RELOC_AVR32_14UW_PCREL,
  87 +  BFD_RELOC_AVR32_11H_PCREL,
  88 +  BFD_RELOC_AVR32_10UW_PCREL,
  89 +  BFD_RELOC_AVR32_9H_PCREL,
  90 +  BFD_RELOC_AVR32_9UW_PCREL,
  91 +
  92 +/* Subtract the link-time address of the GOT from (symbol + addend)
  93 +and insert the result.  */
  94 +  BFD_RELOC_AVR32_GOTPC,
  95 +
  96 +/* Reference to a symbol through the GOT. The linker will allocate an
  97 +entry for symbol in the GOT and insert the offset of this entry as
  98 +the relocation value. addend must be zero. As usual, 'S' means
  99 +signed, 'W' means word-aligned, etc.  */
 100 +  BFD_RELOC_AVR32_GOTCALL,
 101 +  BFD_RELOC_AVR32_LDA_GOT,
 102 +  BFD_RELOC_AVR32_GOT21S,
 103 +  BFD_RELOC_AVR32_GOT18SW,
 104 +  BFD_RELOC_AVR32_GOT16S,
 105 +
 106 +/* 32-bit constant pool entry. I don't think 8- and 16-bit entries make
 107 +a whole lot of sense.  */
 108 +  BFD_RELOC_AVR32_32_CPENT,
 109 +
 110 +/* Constant pool references. Some of these relocations are signed,
 111 +others are unsigned. It doesn't really matter, since the constant
 112 +pool always comes after the code that references it.  */
 113 +  BFD_RELOC_AVR32_CPCALL,
 114 +  BFD_RELOC_AVR32_16_CP,
 115 +  BFD_RELOC_AVR32_9W_CP,
 116 +
 117 +/* sym must be the absolute symbol. The addend specifies the alignment
 118 +order, e.g. if addend is 2, the linker must add padding so that the
 119 +next address is aligned to a 4-byte boundary.  */
 120 +  BFD_RELOC_AVR32_ALIGN,
 121 +
 122 +/* Code relocations that will never make it to the output file.  */
 123 +  BFD_RELOC_AVR32_14UW,
 124 +  BFD_RELOC_AVR32_10UW,
 125 +  BFD_RELOC_AVR32_10SW,
 126 +  BFD_RELOC_AVR32_STHH_W,
 127 +  BFD_RELOC_AVR32_7UW,
 128 +  BFD_RELOC_AVR32_6S,
 129 +  BFD_RELOC_AVR32_6UW,
 130 +  BFD_RELOC_AVR32_4UH,
 131 +  BFD_RELOC_AVR32_3U,
 132 +
 133  /* Direct 12 bit.  */
 134    BFD_RELOC_390_12,
 135
 136 --- a/bfd/config.bfd
 137 +++ b/bfd/config.bfd
 138 @@ -346,6 +346,10 @@ case "${targ}" in
 139      targ_underscore=yes
 140      ;;
 141
 142 +  avr32-*-*)
 143 +    targ_defvec=bfd_elf32_avr32_vec
 144 +    ;;
 145 +
 146    c30-*-*aout* | tic30-*-*aout*)
 147      targ_defvec=tic30_aout_vec
 148      ;;
 149 --- a/bfd/configure
 150 +++ b/bfd/configure
 151 @@ -15188,6 +15188,7 @@ do
 152      bfd_pei_ia64_vec)          tb="$tb pei-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;;
 153      bfd_elf32_am33lin_vec)     tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
 154      bfd_elf32_avr_vec)         tb="$tb elf32-avr.lo elf32.lo $elf" ;;
 155 +    bfd_elf32_avr32_vec)       tb="$tb elf32-avr32.lo elf32.lo $elf" ;;
 156      bfd_elf32_bfin_vec)                tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
 157      bfd_elf32_bfinfdpic_vec)   tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
 158      bfd_elf32_big_generic_vec)         tb="$tb elf32-gen.lo elf32.lo $elf" ;;
 159 --- a/bfd/configure.in
 160 +++ b/bfd/configure.in
 161 @@ -679,6 +679,7 @@ do
 162      bfd_pei_ia64_vec)          tb="$tb pei-ia64.lo pepigen.lo cofflink.lo"; target_size=64 ;;
 163      bfd_elf32_am33lin_vec)     tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
 164      bfd_elf32_avr_vec)         tb="$tb elf32-avr.lo elf32.lo $elf" ;;
 165 +    bfd_elf32_avr32_vec)       tb="$tb elf32-avr32.lo elf32.lo $elf" ;;
 166      bfd_elf32_bfin_vec)                tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
 167      bfd_elf32_bfinfdpic_vec)   tb="$tb elf32-bfin.lo elf32.lo $elf" ;;
 168      bfd_elf32_big_generic_vec)         tb="$tb elf32-gen.lo elf32.lo $elf" ;;
 169 --- /dev/null
 170 +++ b/bfd/cpu-avr32.c
 171 @@ -0,0 +1,52 @@
 172 +/* BFD library support routines for AVR32.
 173 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
 174 +
 175 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
 176 +
 177 +   This is part of BFD, the Binary File Descriptor library.
 178 +
 179 +   This program is free software; you can redistribute it and/or modify
 180 +   it under the terms of the GNU General Public License as published by
 181 +   the Free Software Foundation; either version 2 of the License, or
 182 +   (at your option) any later version.
 183 +
 184 +   This program is distributed in the hope that it will be useful,
 185 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
 186 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 187 +   GNU General Public License for more details.
 188 +
 189 +   You should have received a copy of the GNU General Public License
 190 +   along with this program; if not, write to the Free Software
 191 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 192 +
 193 +#include "bfd.h"
 194 +#include "sysdep.h"
 195 +#include "libbfd.h"
 196 +
 197 +#define N(machine, print, default, next)                       \
 198 +  {                                                            \
 199 +    32,                                /* 32 bits in a word */         \
 200 +    32,                                /* 32 bits in an address */     \
 201 +    8,                         /* 8 bits in a byte */          \
 202 +    bfd_arch_avr32,            /* architecture */              \
 203 +    machine,                   /* machine */                   \
 204 +    "avr32",                   /* arch name */                 \
 205 +    print,                     /* printable name */            \
 206 +    1,                         /* section align power */       \
 207 +    default,                   /* the default machine? */      \
 208 +    bfd_default_compatible,                                    \
 209 +    bfd_default_scan,                                          \
 210 +    next,                                                      \
 211 +  }
 212 +
 213 +static const bfd_arch_info_type cpu_info[] =
 214 +{
 215 +  N(bfd_mach_avr32_ap, "avr32:ap", FALSE, &cpu_info[1]),
 216 +  N(bfd_mach_avr32_uc, "avr32:uc", FALSE, &cpu_info[2]),
 217 +  N(bfd_mach_avr32_ucr1, "avr32:ucr1", FALSE, &cpu_info[3]),
 218 +  N(bfd_mach_avr32_ucr2, "avr32:ucr2", FALSE, &cpu_info[4]),
 219 +  N(bfd_mach_avr32_ucr3, "avr32:ucr3", FALSE, NULL),
 220 +};
 221 +
 222 +const bfd_arch_info_type bfd_avr32_arch =
 223 +  N(bfd_mach_avr32_ap, "avr32", TRUE, &cpu_info[0]);
 224 --- /dev/null
 225 +++ b/bfd/elf32-avr32.c
 226 @@ -0,0 +1,3944 @@
 227 +/* AVR32-specific support for 32-bit ELF.
 228 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
 229 +
 230 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
 231 +
 232 +   This file is part of BFD, the Binary File Descriptor library.
 233 +
 234 +   This program is free software; you can redistribute it and/or modify
 235 +   it under the terms of the GNU General Public License as published by
 236 +   the Free Software Foundation; either version 2 of the License, or
 237 +   (at your option) any later version.
 238 +
 239 +   This program is distributed in the hope that it will be useful,
 240 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
 241 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 242 +   GNU General Public License for more details.
 243 +
 244 +   You should have received a copy of the GNU General Public License
 245 +   along with this program; if not, write to the Free Software
 246 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
 247 +
 248 +#include "bfd.h"
 249 +#include "sysdep.h"
 250 +#include "bfdlink.h"
 251 +#include "libbfd.h"
 252 +#include "elf-bfd.h"
 253 +#include "elf/avr32.h"
 254 +#include "elf32-avr32.h"
 255 +
 256 +#define xDEBUG
 257 +#define xRELAX_DEBUG
 258 +
 259 +#ifdef DEBUG
 260 +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args)
 261 +#else
 262 +# define pr_debug(fmt, args...) do { } while (0)
 263 +#endif
 264 +
 265 +#ifdef RELAX_DEBUG
 266 +# define RDBG(fmt, args...) fprintf(stderr, fmt, ##args)
 267 +#else
 268 +# define RDBG(fmt, args...) do { } while (0)
 269 +#endif
 270 +
 271 +/* When things go wrong, we want it to blow up, damnit! */
 272 +#undef BFD_ASSERT
 273 +#undef abort
 274 +#define BFD_ASSERT(expr)                                       \
 275 +  do                                                           \
 276 +    {                                                          \
 277 +      if (!(expr))                                             \
 278 +       {                                                       \
 279 +         bfd_assert(__FILE__, __LINE__);                       \
 280 +         abort();                                              \
 281 +       }                                                       \
 282 +    }                                                          \
 283 +  while (0)
 284 +
 285 +/* The name of the dynamic interpreter. This is put in the .interp section. */
 286 +#define ELF_DYNAMIC_INTERPRETER                "/lib/ld.so.1"
 287 +
 288 +#define AVR32_GOT_HEADER_SIZE          8
 289 +#define AVR32_FUNCTION_STUB_SIZE       8
 290 +
 291 +#define ELF_R_INFO(x, y) ELF32_R_INFO(x, y)
 292 +#define ELF_R_TYPE(x) ELF32_R_TYPE(x)
 293 +#define ELF_R_SYM(x) ELF32_R_SYM(x)
 294 +
 295 +#define NOP_OPCODE 0xd703
 296 +
 297 +
 298 +/* Mapping between BFD relocations and ELF relocations */
 299 +
 300 +static reloc_howto_type *
 301 +bfd_elf32_bfd_reloc_type_lookup(bfd *abfd, bfd_reloc_code_real_type code);
 302 +
 303 +static reloc_howto_type *
 304 +bfd_elf32_bfd_reloc_name_lookup(bfd *abfd, const char *r_name);
 305 +
 306 +static void
 307 +avr32_info_to_howto (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst);
 308 +
 309 +/* Generic HOWTO */
 310 +#define GENH(name, align, size, bitsize, pcrel, bitpos, complain, mask)        \
 311 +  HOWTO(name, align, size, bitsize, pcrel, bitpos,                     \
 312 +       complain_overflow_##complain, bfd_elf_generic_reloc, #name,     \
 313 +       FALSE, 0, mask, pcrel)
 314 +
 315 +static reloc_howto_type elf_avr32_howto_table[] = {
 316 +  /*   NAME             ALN SZ BSZ PCREL  BP COMPLAIN  MASK        */
 317 +  GENH(R_AVR32_NONE,     0, 0, 0,  FALSE, 0, dont,     0x00000000),
 318 +
 319 +  GENH(R_AVR32_32,       0, 2, 32, FALSE, 0, dont,     0xffffffff),
 320 +  GENH(R_AVR32_16,       0, 1, 16, FALSE, 0, bitfield, 0x0000ffff),
 321 +  GENH(R_AVR32_8,        0, 0,  8, FALSE, 0, bitfield, 0x000000ff),
 322 +  GENH(R_AVR32_32_PCREL,  0, 2, 32, TRUE,  0, signed,   0xffffffff),
 323 +  GENH(R_AVR32_16_PCREL,  0, 1, 16, TRUE,  0, signed,   0x0000ffff),
 324 +  GENH(R_AVR32_8_PCREL,          0, 0,  8, TRUE,  0, signed,   0x000000ff),
 325 +
 326 +  /* Difference between two symbol (sym2 - sym1).  The reloc encodes
 327 +     the value of sym1.  The field contains the difference before any
 328 +     relaxing is done.  */
 329 +  GENH(R_AVR32_DIFF32,   0, 2, 32, FALSE, 0, dont,     0xffffffff),
 330 +  GENH(R_AVR32_DIFF16,   0, 1, 16, FALSE, 0, signed,   0x0000ffff),
 331 +  GENH(R_AVR32_DIFF8,    0, 0,  8, FALSE, 0, signed,   0x000000ff),
 332 +
 333 +  GENH(R_AVR32_GOT32,    0, 2, 32, FALSE, 0, signed,   0xffffffff),
 334 +  GENH(R_AVR32_GOT16,    0, 1, 16, FALSE, 0, signed,   0x0000ffff),
 335 +  GENH(R_AVR32_GOT8,     0, 0,  8, FALSE, 0, signed,   0x000000ff),
 336 +
 337 +  GENH(R_AVR32_21S,      0, 2, 21, FALSE, 0, signed,   0x1e10ffff),
 338 +  GENH(R_AVR32_16U,      0, 2, 16, FALSE, 0, unsigned, 0x0000ffff),
 339 +  GENH(R_AVR32_16S,      0, 2, 16, FALSE, 0, signed,   0x0000ffff),
 340 +  GENH(R_AVR32_8S,       0, 1,  8, FALSE, 4, signed,   0x00000ff0),
 341 +  GENH(R_AVR32_8S_EXT,   0, 2,  8, FALSE, 0, signed,   0x000000ff),
 342 +
 343 +  GENH(R_AVR32_22H_PCREL, 1, 2, 21, TRUE,  0, signed,  0x1e10ffff),
 344 +  GENH(R_AVR32_18W_PCREL, 2, 2, 16, TRUE,  0, signed,  0x0000ffff),
 345 +  GENH(R_AVR32_16B_PCREL, 0, 2, 16, TRUE,  0, signed,  0x0000ffff),
 346 +  GENH(R_AVR32_16N_PCREL, 0, 2, 16, TRUE,  0, signed,  0x0000ffff),
 347 +  GENH(R_AVR32_14UW_PCREL, 2, 2, 12, TRUE, 0, unsigned, 0x0000f0ff),
 348 +  GENH(R_AVR32_11H_PCREL, 1, 1, 10, TRUE,  4, signed,  0x00000ff3),
 349 +  GENH(R_AVR32_10UW_PCREL, 2, 2, 8, TRUE,  0, unsigned, 0x000000ff),
 350 +  GENH(R_AVR32_9H_PCREL,  1, 1,  8, TRUE,  4, signed,  0x00000ff0),
 351 +  GENH(R_AVR32_9UW_PCREL, 2, 1,  7, TRUE,  4, unsigned,        0x000007f0),
 352 +
 353 +  GENH(R_AVR32_HI16,    16, 2, 16, FALSE, 0, dont,     0x0000ffff),
 354 +  GENH(R_AVR32_LO16,     0, 2, 16, FALSE, 0, dont,     0x0000ffff),
 355 +
 356 +  GENH(R_AVR32_GOTPC,    0, 2, 32, FALSE, 0, dont,     0xffffffff),
 357 +  GENH(R_AVR32_GOTCALL,   2, 2, 21, FALSE, 0, signed,  0x1e10ffff),
 358 +  GENH(R_AVR32_LDA_GOT,          2, 2, 21, FALSE, 0, signed,   0x1e10ffff),
 359 +  GENH(R_AVR32_GOT21S,   0, 2, 21, FALSE, 0, signed,   0x1e10ffff),
 360 +  GENH(R_AVR32_GOT18SW,          2, 2, 16, FALSE, 0, signed,   0x0000ffff),
 361 +  GENH(R_AVR32_GOT16S,   0, 2, 16, FALSE, 0, signed,   0x0000ffff),
 362 +  GENH(R_AVR32_GOT7UW,   2, 1,  5, FALSE, 4, unsigned, 0x000001f0),
 363 +
 364 +  GENH(R_AVR32_32_CPENT,  0, 2, 32, FALSE, 0, dont,    0xffffffff),
 365 +  GENH(R_AVR32_CPCALL,   2, 2, 16, TRUE,  0, signed,   0x0000ffff),
 366 +  GENH(R_AVR32_16_CP,    0, 2, 16, TRUE,  0, signed,   0x0000ffff),
 367 +  GENH(R_AVR32_9W_CP,    2, 1,  7, TRUE,  4, unsigned, 0x000007f0),
 368 +
 369 +  GENH(R_AVR32_RELATIVE,  0, 2, 32, FALSE, 0, signed,  0xffffffff),
 370 +  GENH(R_AVR32_GLOB_DAT,  0, 2, 32, FALSE, 0, dont,    0xffffffff),
 371 +  GENH(R_AVR32_JMP_SLOT,  0, 2, 32, FALSE, 0, dont,    0xffffffff),
 372 +
 373 +  GENH(R_AVR32_ALIGN,    0, 1, 0,  FALSE, 0, unsigned, 0x00000000),
 374 +
 375 +  GENH(R_AVR32_15S,      2, 2, 15, FALSE, 0, signed,   0x00007fff),
 376 +};
 377 +
 378 +struct elf_reloc_map
 379 +{
 380 +  bfd_reloc_code_real_type bfd_reloc_val;
 381 +  unsigned char elf_reloc_val;
 382 +};
 383 +
 384 +static const struct elf_reloc_map avr32_reloc_map[] =
 385 +{
 386 +  { BFD_RELOC_NONE,                    R_AVR32_NONE },
 387 +
 388 +  { BFD_RELOC_32,                      R_AVR32_32 },
 389 +  { BFD_RELOC_16,                      R_AVR32_16 },
 390 +  { BFD_RELOC_8,                       R_AVR32_8 },
 391 +  { BFD_RELOC_32_PCREL,                        R_AVR32_32_PCREL },
 392 +  { BFD_RELOC_16_PCREL,                        R_AVR32_16_PCREL },
 393 +  { BFD_RELOC_8_PCREL,                 R_AVR32_8_PCREL },
 394 +  { BFD_RELOC_AVR32_DIFF32,            R_AVR32_DIFF32 },
 395 +  { BFD_RELOC_AVR32_DIFF16,            R_AVR32_DIFF16 },
 396 +  { BFD_RELOC_AVR32_DIFF8,             R_AVR32_DIFF8 },
 397 +  { BFD_RELOC_AVR32_GOT32,             R_AVR32_GOT32 },
 398 +  { BFD_RELOC_AVR32_GOT16,             R_AVR32_GOT16 },
 399 +  { BFD_RELOC_AVR32_GOT8,              R_AVR32_GOT8 },
 400 +
 401 +  { BFD_RELOC_AVR32_21S,               R_AVR32_21S },
 402 +  { BFD_RELOC_AVR32_16U,               R_AVR32_16U },
 403 +  { BFD_RELOC_AVR32_16S,               R_AVR32_16S },
 404 +  { BFD_RELOC_AVR32_SUB5,              R_AVR32_16S },
 405 +  { BFD_RELOC_AVR32_8S_EXT,            R_AVR32_8S_EXT },
 406 +  { BFD_RELOC_AVR32_8S,                        R_AVR32_8S },
 407 +
 408 +  { BFD_RELOC_AVR32_22H_PCREL,         R_AVR32_22H_PCREL },
 409 +  { BFD_RELOC_AVR32_18W_PCREL,         R_AVR32_18W_PCREL },
 410 +  { BFD_RELOC_AVR32_16B_PCREL,         R_AVR32_16B_PCREL },
 411 +  { BFD_RELOC_AVR32_16N_PCREL,         R_AVR32_16N_PCREL },
 412 +  { BFD_RELOC_AVR32_11H_PCREL,         R_AVR32_11H_PCREL },
 413 +  { BFD_RELOC_AVR32_10UW_PCREL,                R_AVR32_10UW_PCREL },
 414 +  { BFD_RELOC_AVR32_9H_PCREL,          R_AVR32_9H_PCREL },
 415 +  { BFD_RELOC_AVR32_9UW_PCREL,         R_AVR32_9UW_PCREL },
 416 +
 417 +  { BFD_RELOC_HI16,                    R_AVR32_HI16 },
 418 +  { BFD_RELOC_LO16,                    R_AVR32_LO16 },
 419 +
 420 +  { BFD_RELOC_AVR32_GOTPC,             R_AVR32_GOTPC },
 421 +  { BFD_RELOC_AVR32_GOTCALL,           R_AVR32_GOTCALL },
 422 +  { BFD_RELOC_AVR32_LDA_GOT,           R_AVR32_LDA_GOT },
 423 +  { BFD_RELOC_AVR32_GOT21S,            R_AVR32_GOT21S },
 424 +  { BFD_RELOC_AVR32_GOT18SW,           R_AVR32_GOT18SW },
 425 +  { BFD_RELOC_AVR32_GOT16S,            R_AVR32_GOT16S },
 426 +  /* GOT7UW should never be generated by the assembler */
 427 +
 428 +  { BFD_RELOC_AVR32_32_CPENT,          R_AVR32_32_CPENT },
 429 +  { BFD_RELOC_AVR32_CPCALL,            R_AVR32_CPCALL },
 430 +  { BFD_RELOC_AVR32_16_CP,             R_AVR32_16_CP },
 431 +  { BFD_RELOC_AVR32_9W_CP,             R_AVR32_9W_CP },
 432 +
 433 +  { BFD_RELOC_AVR32_ALIGN,             R_AVR32_ALIGN },
 434 +
 435 +  { BFD_RELOC_AVR32_15S,               R_AVR32_15S },
 436 +};
 437 +
 438 +static reloc_howto_type *
 439 +bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
 440 +                                bfd_reloc_code_real_type code)
 441 +{
 442 +  unsigned int i;
 443 +
 444 +  for (i = 0; i < sizeof(avr32_reloc_map) / sizeof(struct elf_reloc_map); i++)
 445 +    {
 446 +      if (avr32_reloc_map[i].bfd_reloc_val == code)
 447 +       return &elf_avr32_howto_table[avr32_reloc_map[i].elf_reloc_val];
 448 +    }
 449 +
 450 +  return NULL;
 451 +}
 452 +
 453 +static reloc_howto_type *
 454 +bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
 455 +                 const char *r_name)
 456 +{
 457 +  unsigned int i;
 458 +
 459 +  for (i = 0;
 460 +       i < sizeof (elf_avr32_howto_table) / sizeof (elf_avr32_howto_table[0]);
 461 +       i++)
 462 +    if (elf_avr32_howto_table[i].name != NULL
 463 +    && strcasecmp (elf_avr32_howto_table[i].name, r_name) == 0)
 464 +      return &elf_avr32_howto_table[i];
 465 +
 466 +  return NULL;
 467 +}
 468 +
 469 +/* Set the howto pointer for an AVR32 ELF reloc.  */
 470 +static void
 471 +avr32_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
 472 +                    arelent *cache_ptr,
 473 +                    Elf_Internal_Rela *dst)
 474 +{
 475 +  unsigned int r_type;
 476 +
 477 +  r_type = ELF32_R_TYPE (dst->r_info);
 478 +  BFD_ASSERT (r_type < (unsigned int) R_AVR32_max);
 479 +  cache_ptr->howto = &elf_avr32_howto_table[r_type];
 480 +}
 481 +
 482 +
 483 +/* AVR32 ELF linker hash table and associated hash entries. */
 484 +
 485 +static struct bfd_hash_entry *
 486 +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry,
 487 +                           struct bfd_hash_table *table,
 488 +                           const char *string);
 489 +static void
 490 +avr32_elf_copy_indirect_symbol(struct bfd_link_info *info,
 491 +                              struct elf_link_hash_entry *dir,
 492 +                              struct elf_link_hash_entry *ind);
 493 +static struct bfd_link_hash_table *
 494 +avr32_elf_link_hash_table_create(bfd *abfd);
 495 +
 496 +/*
 497 +  Try to limit memory usage to something reasonable when sorting the
 498 +  GOT.  If just a couple of entries end up getting more references
 499 +  than this, it won't affect performance at all, but if there are many
 500 +  of them, we could end up with the wrong symbols being assigned the
 501 +  first GOT entries.
 502 +*/
 503 +#define MAX_NR_GOT_HOLES       2048
 504 +
 505 +/*
 506 +  AVR32 GOT entry.  We need to keep track of refcounts and offsets
 507 +  simultaneously, since we need the offsets during relaxation, and we
 508 +  also want to be able to drop GOT entries during relaxation. In
 509 +  addition to this, we want to keep the list of GOT entries sorted so
 510 +  that we can keep the most-used entries at the lowest offsets.
 511 +*/
 512 +struct got_entry
 513 +{
 514 +  struct got_entry *next;
 515 +  struct got_entry **pprev;
 516 +  int refcount;
 517 +  bfd_signed_vma offset;
 518 +};
 519 +
 520 +struct elf_avr32_link_hash_entry
 521 +{
 522 +  struct elf_link_hash_entry root;
 523 +
 524 +  /* Number of runtime relocations against this symbol.  */
 525 +  unsigned int possibly_dynamic_relocs;
 526 +
 527 +  /* If there are anything but R_AVR32_GOT18 relocations against this
 528 +     symbol, it means that someone may be taking the address of the
 529 +     function, and we should therefore not create a stub.  */
 530 +  bfd_boolean no_fn_stub;
 531 +
 532 +  /* If there is a R_AVR32_32 relocation in a read-only section
 533 +     against this symbol, we could be in trouble. If we're linking a
 534 +     shared library or this symbol is defined in one, it means we must
 535 +     emit a run-time reloc for it and that's not allowed in read-only
 536 +     sections.  */
 537 +  asection *readonly_reloc_sec;
 538 +  bfd_vma readonly_reloc_offset;
 539 +
 540 +  /* Record which frag (if any) contains the symbol.  This is used
 541 +     during relaxation in order to avoid having to update all symbols
 542 +     whenever we move something.  For local symbols, this information
 543 +     is in the local_sym_frag member of struct elf_obj_tdata.  */
 544 +  struct fragment *sym_frag;
 545 +};
 546 +#define avr32_elf_hash_entry(ent) ((struct elf_avr32_link_hash_entry *)(ent))
 547 +
 548 +struct elf_avr32_link_hash_table
 549 +{
 550 +  struct elf_link_hash_table root;
 551 +
 552 +  /* Shortcuts to get to dynamic linker sections.  */
 553 +  asection *sgot;
 554 +  asection *srelgot;
 555 +  asection *sstub;
 556 +
 557 +  /* We use a variation of Pigeonhole Sort to sort the GOT.  After the
 558 +     initial refcounts have been determined, we initialize
 559 +     nr_got_holes to the highest refcount ever seen and allocate an
 560 +     array of nr_got_holes entries for got_hole.  Each GOT entry is
 561 +     then stored in this array at the index given by its refcount.
 562 +
 563 +     When a GOT entry has its refcount decremented during relaxation,
 564 +     it is moved to a lower index in the got_hole array.
 565 +   */
 566 +  struct got_entry **got_hole;
 567 +  int nr_got_holes;
 568 +
 569 +  /* Dynamic relocations to local symbols.  Only used when linking a
 570 +     shared library and -Bsymbolic is not given.  */
 571 +  unsigned int local_dynamic_relocs;
 572 +
 573 +  bfd_boolean relocations_analyzed;
 574 +  bfd_boolean symbols_adjusted;
 575 +  bfd_boolean repeat_pass;
 576 +  bfd_boolean direct_data_refs;
 577 +  unsigned int relax_iteration;
 578 +  unsigned int relax_pass;
 579 +};
 580 +#define avr32_elf_hash_table(p)                                \
 581 +  (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \
 582 +  == AVR32_ELF_DATA ? ((struct elf_avr32_link_hash_table *) ((p)->hash)) : NULL)
 583 +
 584 +static struct bfd_hash_entry *
 585 +avr32_elf_link_hash_newfunc(struct bfd_hash_entry *entry,
 586 +                           struct bfd_hash_table *table,
 587 +                           const char *string)
 588 +{
 589 +  struct elf_avr32_link_hash_entry *ret = avr32_elf_hash_entry(entry);
 590 +
 591 +  /* Allocate the structure if it hasn't already been allocated by a
 592 +     subclass */
 593 +  if (ret == NULL)
 594 +    ret = (struct elf_avr32_link_hash_entry *)
 595 +      bfd_hash_allocate(table, sizeof(struct elf_avr32_link_hash_entry));
 596 +
 597 +  if (ret == NULL)
 598 +    return NULL;
 599 +
 600 +  memset(ret, 0, sizeof(struct elf_avr32_link_hash_entry));
 601 +
 602 +  /* Give the superclass a chance */
 603 +  ret = (struct elf_avr32_link_hash_entry *)
 604 +    _bfd_elf_link_hash_newfunc((struct bfd_hash_entry *)ret, table, string);
 605 +
 606 +  return (struct bfd_hash_entry *)ret;
 607 +}
 608 +
 609 +/* Copy data from an indirect symbol to its direct symbol, hiding the
 610 +   old indirect symbol.  Process additional relocation information.
 611 +   Also called for weakdefs, in which case we just let
 612 +   _bfd_elf_link_hash_copy_indirect copy the flags for us.  */
 613 +
 614 +static void
 615 +avr32_elf_copy_indirect_symbol(struct bfd_link_info *info,
 616 +                              struct elf_link_hash_entry *dir,
 617 +                              struct elf_link_hash_entry *ind)
 618 +{
 619 +  struct elf_avr32_link_hash_entry *edir, *eind;
 620 +
 621 +  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
 622 +
 623 +  if (ind->root.type != bfd_link_hash_indirect)
 624 +    return;
 625 +
 626 +  edir = (struct elf_avr32_link_hash_entry *)dir;
 627 +  eind = (struct elf_avr32_link_hash_entry *)ind;
 628 +
 629 +  edir->possibly_dynamic_relocs += eind->possibly_dynamic_relocs;
 630 +  edir->no_fn_stub = edir->no_fn_stub || eind->no_fn_stub;
 631 +}
 632 +
 633 +static struct bfd_link_hash_table *
 634 +avr32_elf_link_hash_table_create(bfd *abfd)
 635 +{
 636 +  struct elf_avr32_link_hash_table *ret;
 637 +
 638 +  ret = bfd_zmalloc(sizeof(*ret));
 639 +  if (ret == NULL)
 640 +    return NULL;
 641 +
 642 +  if (! _bfd_elf_link_hash_table_init(&ret->root, abfd,
 643 +                                     avr32_elf_link_hash_newfunc,
 644 +                      sizeof (struct elf_avr32_link_hash_entry),
 645 +                      AVR32_ELF_DATA))
 646 +    {
 647 +      free(ret);
 648 +      return NULL;
 649 +    }
 650 +
 651 +  /* Prevent the BFD core from creating bogus got_entry pointers */
 652 +  ret->root.init_got_refcount.glist = NULL;
 653 +  ret->root.init_plt_refcount.glist = NULL;
 654 +  ret->root.init_got_offset.glist = NULL;
 655 +  ret->root.init_plt_offset.glist = NULL;
 656 +
 657 +  return &ret->root.root;
 658 +}
 659 +
 660 +
 661 +/* Initial analysis and creation of dynamic sections and symbols */
 662 +
 663 +static asection *
 664 +create_dynamic_section(bfd *dynobj, const char *name, flagword flags,
 665 +                      unsigned int align_power);
 666 +static struct elf_link_hash_entry *
 667 +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info,
 668 +                     const char *name, asection *sec,
 669 +                     bfd_vma offset);
 670 +static bfd_boolean
 671 +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info);
 672 +static bfd_boolean
 673 +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info);
 674 +static bfd_boolean
 675 +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec,
 676 +                   const Elf_Internal_Rela *relocs);
 677 +static bfd_boolean
 678 +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info,
 679 +                               struct elf_link_hash_entry *h);
 680 +
 681 +static asection *
 682 +create_dynamic_section(bfd *dynobj, const char *name, flagword flags,
 683 +                      unsigned int align_power)
 684 +{
 685 +  asection *sec;
 686 +
 687 +  sec = bfd_make_section(dynobj, name);
 688 +  if (!sec
 689 +      || !bfd_set_section_flags(dynobj, sec, flags)
 690 +      || !bfd_set_section_alignment(dynobj, sec, align_power))
 691 +    return NULL;
 692 +
 693 +  return sec;
 694 +}
 695 +
 696 +static struct elf_link_hash_entry *
 697 +create_dynamic_symbol(bfd *dynobj, struct bfd_link_info *info,
 698 +                     const char *name, asection *sec,
 699 +                     bfd_vma offset)
 700 +{
 701 +  struct bfd_link_hash_entry *bh = NULL;
 702 +  struct elf_link_hash_entry *h;
 703 +  const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
 704 +
 705 +  if (!(_bfd_generic_link_add_one_symbol
 706 +       (info, dynobj, name, BSF_GLOBAL, sec, offset, NULL, FALSE,
 707 +        bed->collect, &bh)))
 708 +    return NULL;
 709 +
 710 +  h = (struct elf_link_hash_entry *)bh;
 711 +  h->def_regular = 1;
 712 +  h->type = STT_OBJECT;
 713 +  h->other = STV_HIDDEN;
 714 +
 715 +  return h;
 716 +}
 717 +
 718 +static bfd_boolean
 719 +avr32_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info)
 720 +{
 721 +  struct elf_avr32_link_hash_table *htab;
 722 +  flagword flags;
 723 +  const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
 724 +
 725 +  htab = avr32_elf_hash_table(info);
 726 +  flags = bed->dynamic_sec_flags;
 727 +
 728 +  if (htab == NULL)
 729 +    return FALSE;
 730 +
 731 +  if (htab->sgot)
 732 +    return TRUE;
 733 +
 734 +  htab->sgot = create_dynamic_section(dynobj, ".got", flags, 2);
 735 +  if (!htab->srelgot)
 736 +    htab->srelgot = create_dynamic_section(dynobj, ".rela.got",
 737 +                                          flags | SEC_READONLY, 2);
 738 +
 739 +  if (!htab->sgot || !htab->srelgot)
 740 +    return FALSE;
 741 +
 742 +  htab->root.hgot = create_dynamic_symbol(dynobj, info, "_GLOBAL_OFFSET_TABLE_",
 743 +                                         htab->sgot, 0);
 744 +  if (!htab->root.hgot)
 745 +    return FALSE;
 746 +
 747 +  /* Make room for the GOT header */
 748 +  htab->sgot->size += bed->got_header_size;
 749 +
 750 +  return TRUE;
 751 +}
 752 +
 753 +/* (1) Create all dynamic (i.e. linker generated) sections that we may
 754 +   need during the link */
 755 +
 756 +static bfd_boolean
 757 +avr32_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
 758 +{
 759 +  struct elf_avr32_link_hash_table *htab;
 760 +  flagword flags;
 761 +  const struct elf_backend_data *bed = get_elf_backend_data (dynobj);
 762 +
 763 +  pr_debug("(1) create dynamic sections\n");
 764 +
 765 +  htab = avr32_elf_hash_table(info);
 766 +  flags = bed->dynamic_sec_flags;
 767 +
 768 +  if (htab == NULL)
 769 +    return FALSE;
 770 +
 771 +  if (!avr32_elf_create_got_section (dynobj, info))
 772 +    return FALSE;
 773 +
 774 +  if (!htab->sstub)
 775 +    htab->sstub = create_dynamic_section(dynobj, ".stub",
 776 +                                        flags | SEC_READONLY | SEC_CODE, 2);
 777 +
 778 +  if (!htab->sstub)
 779 +    return FALSE;
 780 +
 781 +  return TRUE;
 782 +}
 783 +
 784 +/* (2) Go through all the relocs and count any potential GOT- or
 785 +   PLT-references to each symbol */
 786 +
 787 +static bfd_boolean
 788 +avr32_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec,
 789 +                   const Elf_Internal_Rela *relocs)
 790 +{
 791 +  Elf_Internal_Shdr *symtab_hdr;
 792 +  struct elf_avr32_link_hash_table *htab;
 793 +  struct elf_link_hash_entry **sym_hashes;
 794 +  const Elf_Internal_Rela *rel, *rel_end;
 795 +  struct got_entry **local_got_ents;
 796 +  struct got_entry *got;
 797 +  const struct elf_backend_data *bed = get_elf_backend_data (abfd);
 798 +  asection *sgot;
 799 +  bfd *dynobj;
 800 +
 801 +  pr_debug("(2) check relocs for %s:<%s> (size 0x%lx)\n",
 802 +          abfd->filename, sec->name, sec->size);
 803 +
 804 +  if (info->relocatable)
 805 +    return TRUE;
 806 +
 807 +  dynobj = elf_hash_table(info)->dynobj;
 808 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
 809 +  sym_hashes = elf_sym_hashes(abfd);
 810 +  htab = avr32_elf_hash_table(info);
 811 +  if (htab == NULL)
 812 +    return FALSE;
 813 +
 814 +  local_got_ents = elf_local_got_ents(abfd);
 815 +  sgot = htab->sgot;
 816 +
 817 +  rel_end = relocs + sec->reloc_count;
 818 +  for (rel = relocs; rel < rel_end; rel++)
 819 +    {
 820 +      unsigned long r_symndx, r_type;
 821 +      struct elf_avr32_link_hash_entry *h;
 822 +
 823 +      r_symndx = ELF32_R_SYM(rel->r_info);
 824 +      r_type = ELF32_R_TYPE(rel->r_info);
 825 +
 826 +      /* Local symbols use local_got_ents, while others store the same
 827 +        information in the hash entry */
 828 +      if (r_symndx < symtab_hdr->sh_info)
 829 +       {
 830 +         pr_debug("  (2a) processing local symbol %lu\n", r_symndx);
 831 +         h = NULL;
 832 +       }
 833 +      else
 834 +       {
 835 +         h = (struct elf_avr32_link_hash_entry *)
 836 +           sym_hashes[r_symndx - symtab_hdr->sh_info];
 837 +         while (h->root.type == bfd_link_hash_indirect
 838 +                || h->root.type == bfd_link_hash_warning)
 839 +           h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link;
 840 +         pr_debug("  (2a) processing symbol %s\n", h->root.root.root.string);
 841 +       }
 842 +
 843 +      /* Some relocs require special sections to be created.  */
 844 +      switch (r_type)
 845 +       {
 846 +       case R_AVR32_GOT32:
 847 +       case R_AVR32_GOT16:
 848 +       case R_AVR32_GOT8:
 849 +       case R_AVR32_GOT21S:
 850 +       case R_AVR32_GOT18SW:
 851 +       case R_AVR32_GOT16S:
 852 +       case R_AVR32_GOT7UW:
 853 +       case R_AVR32_LDA_GOT:
 854 +       case R_AVR32_GOTCALL:
 855 +         if (rel->r_addend)
 856 +           {
 857 +             if (info->callbacks->reloc_dangerous
 858 +                 (info, _("Non-zero addend on GOT-relative relocation"),
 859 +                  abfd, sec, rel->r_offset) == FALSE)
 860 +               return FALSE;
 861 +           }
 862 +         /* fall through */
 863 +       case R_AVR32_GOTPC:
 864 +         if (dynobj == NULL)
 865 +           elf_hash_table(info)->dynobj = dynobj = abfd;
 866 +         if (sgot == NULL && !avr32_elf_create_got_section(dynobj, info))
 867 +           return FALSE;
 868 +         break;
 869 +       case R_AVR32_32:
 870 +         /* We may need to create .rela.dyn later on.  */
 871 +         if (dynobj == NULL
 872 +             && (info->shared || h != NULL)
 873 +             && (sec->flags & SEC_ALLOC))
 874 +           elf_hash_table(info)->dynobj = dynobj = abfd;
 875 +         break;
 876 +       }
 877 +
 878 +      if (h != NULL && r_type != R_AVR32_GOT18SW)
 879 +       h->no_fn_stub = TRUE;
 880 +
 881 +      switch (r_type)
 882 +       {
 883 +       case R_AVR32_GOT32:
 884 +       case R_AVR32_GOT16:
 885 +       case R_AVR32_GOT8:
 886 +       case R_AVR32_GOT21S:
 887 +       case R_AVR32_GOT18SW:
 888 +       case R_AVR32_GOT16S:
 889 +       case R_AVR32_GOT7UW:
 890 +       case R_AVR32_LDA_GOT:
 891 +       case R_AVR32_GOTCALL:
 892 +         if (h != NULL)
 893 +           {
 894 +             got = h->root.got.glist;
 895 +             if (!got)
 896 +               {
 897 +                 got = bfd_zalloc(abfd, sizeof(struct got_entry));
 898 +                 if (!got)
 899 +                   return FALSE;
 900 +                 h->root.got.glist = got;
 901 +               }
 902 +           }
 903 +         else
 904 +           {
 905 +             if (!local_got_ents)
 906 +               {
 907 +                 bfd_size_type size;
 908 +                 bfd_size_type i;
 909 +                 struct got_entry *tmp_entry;
 910 +
 911 +                 size = symtab_hdr->sh_info;
 912 +                 size *= sizeof(struct got_entry *) + sizeof(struct got_entry);
 913 +                 local_got_ents = bfd_zalloc(abfd, size);
 914 +                 if (!local_got_ents)
 915 +                   return FALSE;
 916 +
 917 +                 elf_local_got_ents(abfd) = local_got_ents;
 918 +
 919 +                 tmp_entry = (struct got_entry *)(local_got_ents
 920 +                                                  + symtab_hdr->sh_info);
 921 +                 for (i = 0; i < symtab_hdr->sh_info; i++)
 922 +                   local_got_ents[i] = &tmp_entry[i];
 923 +               }
 924 +
 925 +             got = local_got_ents[r_symndx];
 926 +           }
 927 +
 928 +         got->refcount++;
 929 +         if (got->refcount > htab->nr_got_holes)
 930 +           htab->nr_got_holes = got->refcount;
 931 +         break;
 932 +
 933 +       case R_AVR32_32:
 934 +         if ((info->shared || h != NULL)
 935 +             && (sec->flags & SEC_ALLOC))
 936 +           {
 937 +             if (htab->srelgot == NULL)
 938 +               {
 939 +                 htab->srelgot = create_dynamic_section(dynobj, ".rela.got",
 940 +                                                        bed->dynamic_sec_flags
 941 +                                                        | SEC_READONLY, 2);
 942 +                 if (htab->srelgot == NULL)
 943 +                   return FALSE;
 944 +               }
 945 +
 946 +             if (sec->flags & SEC_READONLY
 947 +                 && !h->readonly_reloc_sec)
 948 +               {
 949 +                 h->readonly_reloc_sec = sec;
 950 +                 h->readonly_reloc_offset = rel->r_offset;
 951 +               }
 952 +
 953 +             if (h != NULL)
 954 +               {
 955 +                 pr_debug("Non-GOT reference to symbol %s\n",
 956 +                          h->root.root.root.string);
 957 +                 h->possibly_dynamic_relocs++;
 958 +               }
 959 +             else
 960 +               {
 961 +                 pr_debug("Non-GOT reference to local symbol %lu\n",
 962 +                          r_symndx);
 963 +                 htab->local_dynamic_relocs++;
 964 +               }
 965 +           }
 966 +
 967 +         break;
 968 +
 969 +         /* TODO: GNU_VTINHERIT and GNU_VTENTRY */
 970 +       }
 971 +    }
 972 +
 973 +  return TRUE;
 974 +}
 975 +
 976 +/* (3) Adjust a symbol defined by a dynamic object and referenced by a
 977 +   regular object.  The current definition is in some section of the
 978 +   dynamic object, but we're not including those sections.  We have to
 979 +   change the definition to something the rest of the link can
 980 +   understand.  */
 981 +
 982 +static bfd_boolean
 983 +avr32_elf_adjust_dynamic_symbol(struct bfd_link_info *info,
 984 +                               struct elf_link_hash_entry *h)
 985 +{
 986 +  struct elf_avr32_link_hash_table *htab;
 987 +  struct elf_avr32_link_hash_entry *havr;
 988 +  bfd *dynobj;
 989 +
 990 +  pr_debug("(3) adjust dynamic symbol %s\n", h->root.root.string);
 991 +
 992 +  htab = avr32_elf_hash_table(info);
 993 +  havr = (struct elf_avr32_link_hash_entry *)h;
 994 +  dynobj = elf_hash_table(info)->dynobj;
 995 +
 996 +  if (htab == NULL)
 997 +    return FALSE;
 998 +
 999 +  /* Make sure we know what is going on here.  */
1000 +  BFD_ASSERT (dynobj != NULL
1001 +             && (h->u.weakdef != NULL
1002 +                 || (h->def_dynamic
1003 +                     && h->ref_regular
1004 +                     && !h->def_regular)));
1005 +
1006 +  /* We don't want dynamic relocations in read-only sections. */
1007 +  if (havr->readonly_reloc_sec)
1008 +    {
1009 +      if (info->callbacks->reloc_dangerous
1010 +         (info, _("dynamic relocation in read-only section"),
1011 +          havr->readonly_reloc_sec->owner, havr->readonly_reloc_sec,
1012 +          havr->readonly_reloc_offset) == FALSE)
1013 +       return FALSE;
1014 +    }
1015 +
1016 +  /* If this is a function, create a stub if possible and set the
1017 +     symbol to the stub location.  */
1018 +  if (0 && !havr->no_fn_stub)
1019 +    {
1020 +      if (!h->def_regular)
1021 +       {
1022 +         asection *s = htab->sstub;
1023 +
1024 +         BFD_ASSERT(s != NULL);
1025 +
1026 +         h->root.u.def.section = s;
1027 +         h->root.u.def.value = s->size;
1028 +         h->plt.offset = s->size;
1029 +         s->size += AVR32_FUNCTION_STUB_SIZE;
1030 +
1031 +         return TRUE;
1032 +       }
1033 +    }
1034 +  else if (h->type == STT_FUNC)
1035 +    {
1036 +      /* This will set the entry for this symbol in the GOT to 0, and
1037 +        the dynamic linker will take care of this. */
1038 +      h->root.u.def.value = 0;
1039 +      return TRUE;
1040 +    }
1041 +
1042 +  /* If this is a weak symbol, and there is a real definition, the
1043 +     processor independent code will have arranged for us to see the
1044 +     real definition first, and we can just use the same value.  */
1045 +  if (h->u.weakdef != NULL)
1046 +    {
1047 +      BFD_ASSERT(h->u.weakdef->root.type == bfd_link_hash_defined
1048 +                || h->u.weakdef->root.type == bfd_link_hash_defweak);
1049 +      h->root.u.def.section = h->u.weakdef->root.u.def.section;
1050 +      h->root.u.def.value = h->u.weakdef->root.u.def.value;
1051 +      return TRUE;
1052 +    }
1053 +
1054 +  /* This is a reference to a symbol defined by a dynamic object which
1055 +     is not a function.  */
1056 +
1057 +  return TRUE;
1058 +}
1059 +
1060 +
1061 +/* Garbage-collection of unused sections */
1062 +
1063 +static asection *
1064 +avr32_elf_gc_mark_hook(asection *sec,
1065 +                      struct bfd_link_info *info ATTRIBUTE_UNUSED,
1066 +                      Elf_Internal_Rela *rel,
1067 +                      struct elf_link_hash_entry *h,
1068 +                      Elf_Internal_Sym *sym)
1069 +{
1070 +  if (h)
1071 +    {
1072 +      switch (ELF32_R_TYPE(rel->r_info))
1073 +       {
1074 +         /* TODO: VTINHERIT/VTENTRY */
1075 +       default:
1076 +         switch (h->root.type)
1077 +           {
1078 +           case bfd_link_hash_defined:
1079 +           case bfd_link_hash_defweak:
1080 +             return h->root.u.def.section;
1081 +
1082 +           case bfd_link_hash_common:
1083 +             return h->root.u.c.p->section;
1084 +
1085 +           default:
1086 +             break;
1087 +           }
1088 +       }
1089 +    }
1090 +  else
1091 +    return bfd_section_from_elf_index(sec->owner, sym->st_shndx);
1092 +
1093 +  return NULL;
1094 +}
1095 +
1096 +/* Update the GOT entry reference counts for the section being removed. */
1097 +static bfd_boolean
1098 +avr32_elf_gc_sweep_hook(bfd *abfd,
1099 +                       struct bfd_link_info *info ATTRIBUTE_UNUSED,
1100 +                       asection *sec,
1101 +                       const Elf_Internal_Rela *relocs)
1102 +{
1103 +  Elf_Internal_Shdr *symtab_hdr;
1104 +  struct elf_avr32_link_hash_entry **sym_hashes;
1105 +  struct got_entry **local_got_ents;
1106 +  const Elf_Internal_Rela *rel, *relend;
1107 +
1108 +  if (!(sec->flags & SEC_ALLOC))
1109 +    return TRUE;
1110 +
1111 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
1112 +  sym_hashes = (struct elf_avr32_link_hash_entry **)elf_sym_hashes(abfd);
1113 +  local_got_ents = elf_local_got_ents(abfd);
1114 +
1115 +  relend = relocs + sec->reloc_count;
1116 +  for (rel = relocs; rel < relend; rel++)
1117 +    {
1118 +      unsigned long r_symndx;
1119 +      unsigned int r_type;
1120 +      struct elf_avr32_link_hash_entry *h = NULL;
1121 +
1122 +      r_symndx = ELF32_R_SYM(rel->r_info);
1123 +      if (r_symndx >= symtab_hdr->sh_info)
1124 +       {
1125 +         h = sym_hashes[r_symndx - symtab_hdr->sh_info];
1126 +         while (h->root.root.type == bfd_link_hash_indirect
1127 +                || h->root.root.type == bfd_link_hash_warning)
1128 +           h = (struct elf_avr32_link_hash_entry *)h->root.root.u.i.link;
1129 +       }
1130 +
1131 +      r_type = ELF32_R_TYPE(rel->r_info);
1132 +
1133 +      switch (r_type)
1134 +       {
1135 +       case R_AVR32_GOT32:
1136 +       case R_AVR32_GOT16:
1137 +       case R_AVR32_GOT8:
1138 +       case R_AVR32_GOT21S:
1139 +       case R_AVR32_GOT18SW:
1140 +       case R_AVR32_GOT16S:
1141 +       case R_AVR32_GOT7UW:
1142 +       case R_AVR32_LDA_GOT:
1143 +       case R_AVR32_GOTCALL:
1144 +         if (h)
1145 +           h->root.got.glist->refcount--;
1146 +         else
1147 +           local_got_ents[r_symndx]->refcount--;
1148 +         break;
1149 +
1150 +       case R_AVR32_32:
1151 +         if (info->shared || h)
1152 +           {
1153 +             if (h)
1154 +               h->possibly_dynamic_relocs--;
1155 +             else
1156 +               avr32_elf_hash_table(info)->local_dynamic_relocs--;
1157 +           }
1158 +
1159 +       default:
1160 +         break;
1161 +       }
1162 +    }
1163 +
1164 +  return TRUE;
1165 +}
1166 +
1167 +/* Sizing and refcounting of dynamic sections */
1168 +
1169 +static void
1170 +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1171 +static void
1172 +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1173 +static void
1174 +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got);
1175 +static bfd_boolean
1176 +assign_got_offsets(struct elf_avr32_link_hash_table *htab);
1177 +static bfd_boolean
1178 +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info);
1179 +static bfd_boolean
1180 +avr32_elf_size_dynamic_sections (bfd *output_bfd,
1181 +                                struct bfd_link_info *info);
1182 +
1183 +static void
1184 +insert_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1185 +{
1186 +  /* Any entries with got_refcount > htab->nr_got_holes end up in the
1187 +   * last pigeonhole without any sorting. We expect the number of such
1188 +   * entries to be small, so it is very unlikely to affect
1189 +   * performance.  */
1190 +  int entry = got->refcount;
1191 +
1192 +  if (entry > htab->nr_got_holes)
1193 +    entry = htab->nr_got_holes;
1194 +
1195 +  got->pprev = &htab->got_hole[entry];
1196 +  got->next = htab->got_hole[entry];
1197 +
1198 +  if (got->next)
1199 +    got->next->pprev = &got->next;
1200 +
1201 +  htab->got_hole[entry] = got;
1202 +}
1203 +
1204 +/* Decrement the refcount of a GOT entry and update its position in
1205 +   the pigeonhole array.  */
1206 +static void
1207 +unref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1208 +{
1209 +  BFD_ASSERT(got->refcount > 0);
1210 +
1211 +  if (got->next)
1212 +    got->next->pprev = got->pprev;
1213 +
1214 +  *(got->pprev) = got->next;
1215 +  got->refcount--;
1216 +  insert_got_entry(htab, got);
1217 +}
1218 +
1219 +static void
1220 +ref_got_entry(struct elf_avr32_link_hash_table *htab, struct got_entry *got)
1221 +{
1222 +  if (got->next)
1223 +    got->next->pprev = got->pprev;
1224 +
1225 +  *(got->pprev) = got->next;
1226 +  got->refcount++;
1227 +  insert_got_entry(htab, got);
1228 +
1229 +  BFD_ASSERT(got->refcount > 0);
1230 +}
1231 +
1232 +/* Assign offsets to all GOT entries we intend to keep.  The entries
1233 +   that are referenced most often are placed at low offsets so that we
1234 +   can use compact instructions as much as possible.
1235 +
1236 +   Returns TRUE if any offsets or the total size of the GOT changed.  */
1237 +
1238 +static bfd_boolean
1239 +assign_got_offsets(struct elf_avr32_link_hash_table *htab)
1240 +{
1241 +  struct got_entry *got;
1242 +  bfd_size_type got_size = 0;
1243 +  bfd_boolean changed = FALSE;
1244 +  bfd_signed_vma offset;
1245 +  int i;
1246 +
1247 +  /* The GOT header provides the address of the DYNAMIC segment, so
1248 +     we need that even if the GOT is otherwise empty.  */
1249 +  if (htab->root.dynamic_sections_created)
1250 +    got_size = AVR32_GOT_HEADER_SIZE;
1251 +
1252 +  for (i = htab->nr_got_holes; i > 0; i--)
1253 +    {
1254 +      got = htab->got_hole[i];
1255 +      while (got)
1256 +       {
1257 +         if (got->refcount > 0)
1258 +           {
1259 +             offset = got_size;
1260 +             if (got->offset != offset)
1261 +               {
1262 +                 RDBG("GOT offset changed: %ld -> %ld\n",
1263 +                      got->offset, offset);
1264 +                 changed = TRUE;
1265 +               }
1266 +             got->offset = offset;
1267 +             got_size += 4;
1268 +           }
1269 +         got = got->next;
1270 +       }
1271 +    }
1272 +
1273 +  if (htab->sgot->size != got_size)
1274 +    {
1275 +      RDBG("GOT size changed: %lu -> %lu\n", htab->sgot->size,
1276 +          got_size);
1277 +      changed = TRUE;
1278 +    }
1279 +  htab->sgot->size = got_size;
1280 +
1281 +  RDBG("assign_got_offsets: total size %lu (%s)\n",
1282 +       got_size, changed ? "changed" : "no change");
1283 +
1284 +  return changed;
1285 +}
1286 +
1287 +static bfd_boolean
1288 +allocate_dynrelocs(struct elf_link_hash_entry *h, void *_info)
1289 +{
1290 +  struct bfd_link_info *info = _info;
1291 +  struct elf_avr32_link_hash_table *htab;
1292 +  struct elf_avr32_link_hash_entry *havr;
1293 +  struct got_entry *got;
1294 +
1295 +  pr_debug("  (4b) allocate_dynrelocs: %s\n", h->root.root.string);
1296 +
1297 +  if (h->root.type == bfd_link_hash_indirect)
1298 +    return TRUE;
1299 +
1300 +  if (h->root.type == bfd_link_hash_warning)
1301 +    /* When warning symbols are created, they **replace** the "real"
1302 +       entry in the hash table, thus we never get to see the real
1303 +       symbol in a hash traversal.  So look at it now.  */
1304 +    h = (struct elf_link_hash_entry *) h->root.u.i.link;
1305 +
1306 +  htab = avr32_elf_hash_table(info);
1307 +  havr = (struct elf_avr32_link_hash_entry *)h;
1308 +
1309 +  if (htab == NULL)
1310 +    return FALSE;
1311 +
1312 +  got = h->got.glist;
1313 +
1314 +  /* If got is NULL, the symbol is never referenced through the GOT */
1315 +  if (got && got->refcount > 0)
1316 +    {
1317 +      insert_got_entry(htab, got);
1318 +
1319 +      /* Shared libraries need relocs for all GOT entries unless the
1320 +        symbol is forced local or -Bsymbolic is used.  Others need
1321 +        relocs for everything that is not guaranteed to be defined in
1322 +        a regular object.  */
1323 +      if ((info->shared
1324 +          && !info->symbolic
1325 +          && h->dynindx != -1)
1326 +         || (htab->root.dynamic_sections_created
1327 +             && h->def_dynamic
1328 +             && !h->def_regular))
1329 +       htab->srelgot->size += sizeof(Elf32_External_Rela);
1330 +    }
1331 +
1332 +  if (havr->possibly_dynamic_relocs
1333 +      && (info->shared
1334 +         || (elf_hash_table(info)->dynamic_sections_created
1335 +             && h->def_dynamic
1336 +             && !h->def_regular)))
1337 +    {
1338 +      pr_debug("Allocating %d dynamic reloc against symbol %s...\n",
1339 +              havr->possibly_dynamic_relocs, h->root.root.string);
1340 +      htab->srelgot->size += (havr->possibly_dynamic_relocs
1341 +                             * sizeof(Elf32_External_Rela));
1342 +    }
1343 +
1344 +  return TRUE;
1345 +}
1346 +
1347 +/* (4) Calculate the sizes of the linker-generated sections and
1348 +   allocate memory for them.  */
1349 +
1350 +static bfd_boolean
1351 +avr32_elf_size_dynamic_sections (bfd *output_bfd,
1352 +                                struct bfd_link_info *info)
1353 +{
1354 +  struct elf_avr32_link_hash_table *htab;
1355 +  bfd *dynobj;
1356 +  asection *s;
1357 +  bfd *ibfd;
1358 +  bfd_boolean relocs;
1359 +
1360 +  pr_debug("(4) size dynamic sections\n");
1361 +
1362 +  htab = avr32_elf_hash_table(info);
1363 +  if (htab == NULL)
1364 +    return FALSE;
1365 +
1366 +  dynobj = htab->root.dynobj;
1367 +  BFD_ASSERT(dynobj != NULL);
1368 +
1369 +  if (htab->root.dynamic_sections_created)
1370 +    {
1371 +      /* Initialize the contents of the .interp section to the name of
1372 +        the dynamic loader */
1373 +      if (info->executable)
1374 +       {
1375 +         s = bfd_get_section_by_name(dynobj, ".interp");
1376 +         BFD_ASSERT(s != NULL);
1377 +         s->size = sizeof(ELF_DYNAMIC_INTERPRETER);
1378 +         s->contents = (unsigned char *)ELF_DYNAMIC_INTERPRETER;
1379 +       }
1380 +    }
1381 +
1382 +  if (htab->nr_got_holes > 0)
1383 +    {
1384 +      /* Allocate holes for the pigeonhole sort algorithm */
1385 +      pr_debug("Highest GOT refcount: %d\n", htab->nr_got_holes);
1386 +
1387 +      /* Limit the memory usage by clipping the number of pigeonholes
1388 +       * at a predefined maximum. All entries with a higher refcount
1389 +       * will end up in the last pigeonhole.  */
1390 +    if (htab->nr_got_holes >= MAX_NR_GOT_HOLES)
1391 +    {
1392 +        htab->nr_got_holes = MAX_NR_GOT_HOLES - 1;
1393 +
1394 +        pr_debug("Limiting maximum number of GOT pigeonholes to %u\n",
1395 +                    htab->nr_got_holes);
1396 +    }
1397 +      htab->got_hole = bfd_zalloc(output_bfd,
1398 +                                 sizeof(struct got_entry *)
1399 +                                 * (htab->nr_got_holes + 1));
1400 +      if (!htab->got_hole)
1401 +       return FALSE;
1402 +
1403 +      /* Set up .got offsets for local syms.  */
1404 +      for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link_next)
1405 +       {
1406 +         struct got_entry **local_got;
1407 +         struct got_entry **end_local_got;
1408 +         Elf_Internal_Shdr *symtab_hdr;
1409 +         bfd_size_type locsymcount;
1410 +
1411 +         pr_debug("  (4a) processing file %s...\n", ibfd->filename);
1412 +
1413 +         BFD_ASSERT(bfd_get_flavour(ibfd) == bfd_target_elf_flavour);
1414 +
1415 +         local_got = elf_local_got_ents(ibfd);
1416 +         if (!local_got)
1417 +           continue;
1418 +
1419 +         symtab_hdr = &elf_tdata(ibfd)->symtab_hdr;
1420 +         locsymcount = symtab_hdr->sh_info;
1421 +         end_local_got = local_got + locsymcount;
1422 +
1423 +         for (; local_got < end_local_got; ++local_got)
1424 +           insert_got_entry(htab, *local_got);
1425 +       }
1426 +    }
1427 +
1428 +  /* Allocate global sym .got entries and space for global sym
1429 +     dynamic relocs */
1430 +  elf_link_hash_traverse(&htab->root, allocate_dynrelocs, info);
1431 +
1432 +  /* Now that we have sorted the GOT entries, we are ready to
1433 +     assign offsets and determine the initial size of the GOT. */
1434 +  if (htab->sgot)
1435 +    assign_got_offsets(htab);
1436 +
1437 +  /* Allocate space for local sym dynamic relocs */
1438 +  BFD_ASSERT(htab->local_dynamic_relocs == 0 || info->shared);
1439 +  if (htab->local_dynamic_relocs)
1440 +    htab->srelgot->size += (htab->local_dynamic_relocs
1441 +                           * sizeof(Elf32_External_Rela));
1442 +
1443 +  /* We now have determined the sizes of the various dynamic
1444 +     sections. Allocate memory for them. */
1445 +  relocs = FALSE;
1446 +  for (s = dynobj->sections; s; s = s->next)
1447 +    {
1448 +      if ((s->flags & SEC_LINKER_CREATED) == 0)
1449 +       continue;
1450 +
1451 +      if (s == htab->sgot
1452 +         || s == htab->sstub)
1453 +       {
1454 +         /* Strip this section if we don't need it */
1455 +       }
1456 +      else if (strncmp (bfd_get_section_name(dynobj, s), ".rela", 5) == 0)
1457 +       {
1458 +         if (s->size != 0)
1459 +           relocs = TRUE;
1460 +
1461 +         s->reloc_count = 0;
1462 +       }
1463 +      else
1464 +       {
1465 +         /* It's not one of our sections */
1466 +         continue;
1467 +       }
1468 +
1469 +      if (s->size == 0)
1470 +       {
1471 +         /* Strip unneeded sections */
1472 +         pr_debug("Stripping section %s from output...\n", s->name);
1473 +         /* deleted function in 2.17
1474 +      _bfd_strip_section_from_output(info, s);
1475 +      */
1476 +         continue;
1477 +       }
1478 +
1479 +      s->contents = bfd_zalloc(dynobj, s->size);
1480 +      if (s->contents == NULL)
1481 +       return FALSE;
1482 +    }
1483 +
1484 +  if (htab->root.dynamic_sections_created)
1485 +    {
1486 +      /* Add some entries to the .dynamic section.  We fill in the
1487 +        values later, in sh_elf_finish_dynamic_sections, but we
1488 +        must add the entries now so that we get the correct size for
1489 +        the .dynamic section.  The DT_DEBUG entry is filled in by the
1490 +        dynamic linker and used by the debugger.  */
1491 +#define add_dynamic_entry(TAG, VAL) _bfd_elf_add_dynamic_entry(info, TAG, VAL)
1492 +
1493 +      if (!add_dynamic_entry(DT_PLTGOT, 0))
1494 +       return FALSE;
1495 +      if (!add_dynamic_entry(DT_AVR32_GOTSZ, 0))
1496 +       return FALSE;
1497 +
1498 +      if (info->executable)
1499 +       {
1500 +         if (!add_dynamic_entry(DT_DEBUG, 0))
1501 +           return FALSE;
1502 +       }
1503 +      if (relocs)
1504 +       {
1505 +         if (!add_dynamic_entry(DT_RELA, 0)
1506 +             || !add_dynamic_entry(DT_RELASZ, 0)
1507 +             || !add_dynamic_entry(DT_RELAENT,
1508 +                                   sizeof(Elf32_External_Rela)))
1509 +           return FALSE;
1510 +       }
1511 +    }
1512 +#undef add_dynamic_entry
1513 +
1514 +  return TRUE;
1515 +}
1516 +
1517 +
1518 +/* Access to internal relocations, section contents and symbols.
1519 +   (stolen from the xtensa port)  */
1520 +
1521 +static Elf_Internal_Rela *
1522 +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory);
1523 +static void
1524 +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs);
1525 +static void
1526 +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs);
1527 +static bfd_byte *
1528 +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory);
1529 +/*
1530 +static void
1531 +pin_contents (asection *sec, bfd_byte *contents);
1532 +*/
1533 +static void
1534 +release_contents (asection *sec, bfd_byte *contents);
1535 +static Elf_Internal_Sym *
1536 +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory);
1537 +/*
1538 +static void
1539 +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf);
1540 +*/
1541 +static void
1542 +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf);
1543 +
1544 +/* During relaxation, we need to modify relocations, section contents,
1545 +   and symbol definitions, and we need to keep the original values from
1546 +   being reloaded from the input files, i.e., we need to "pin" the
1547 +   modified values in memory.  We also want to continue to observe the
1548 +   setting of the "keep-memory" flag.  The following functions wrap the
1549 +   standard BFD functions to take care of this for us.  */
1550 +
1551 +static Elf_Internal_Rela *
1552 +retrieve_internal_relocs (bfd *abfd, asection *sec, bfd_boolean keep_memory)
1553 +{
1554 +  /* _bfd_elf_link_read_relocs knows about caching, so no need for us
1555 +     to be clever here.  */
1556 +  return _bfd_elf_link_read_relocs(abfd, sec, NULL, NULL, keep_memory);
1557 +}
1558 +
1559 +static void
1560 +pin_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs)
1561 +{
1562 +  elf_section_data (sec)->relocs = internal_relocs;
1563 +}
1564 +
1565 +static void
1566 +release_internal_relocs (asection *sec, Elf_Internal_Rela *internal_relocs)
1567 +{
1568 +  if (internal_relocs
1569 +      && elf_section_data (sec)->relocs != internal_relocs)
1570 +    free (internal_relocs);
1571 +}
1572 +
1573 +static bfd_byte *
1574 +retrieve_contents (bfd *abfd, asection *sec, bfd_boolean keep_memory)
1575 +{
1576 +  bfd_byte *contents;
1577 +  bfd_size_type sec_size;
1578 +
1579 +  sec_size = bfd_get_section_limit (abfd, sec);
1580 +  contents = elf_section_data (sec)->this_hdr.contents;
1581 +
1582 +  if (contents == NULL && sec_size != 0)
1583 +    {
1584 +      if (!bfd_malloc_and_get_section (abfd, sec, &contents))
1585 +       {
1586 +         if (contents)
1587 +           free (contents);
1588 +         return NULL;
1589 +       }
1590 +      if (keep_memory)
1591 +       elf_section_data (sec)->this_hdr.contents = contents;
1592 +    }
1593 +  return contents;
1594 +}
1595 +
1596 +/*
1597 +static void
1598 +pin_contents (asection *sec, bfd_byte *contents)
1599 +{
1600 +  elf_section_data (sec)->this_hdr.contents = contents;
1601 +}
1602 +*/
1603 +static void
1604 +release_contents (asection *sec, bfd_byte *contents)
1605 +{
1606 +  if (contents && elf_section_data (sec)->this_hdr.contents != contents)
1607 +    free (contents);
1608 +}
1609 +
1610 +static Elf_Internal_Sym *
1611 +retrieve_local_syms (bfd *input_bfd, bfd_boolean keep_memory)
1612 +{
1613 +  Elf_Internal_Shdr *symtab_hdr;
1614 +  Elf_Internal_Sym *isymbuf;
1615 +  size_t locsymcount;
1616 +
1617 +  symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1618 +  locsymcount = symtab_hdr->sh_info;
1619 +
1620 +  isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1621 +  if (isymbuf == NULL && locsymcount != 0)
1622 +    {
1623 +      isymbuf = bfd_elf_get_elf_syms (input_bfd, symtab_hdr, locsymcount, 0,
1624 +                                     NULL, NULL, NULL);
1625 +      if (isymbuf && keep_memory)
1626 +       symtab_hdr->contents = (unsigned char *) isymbuf;
1627 +    }
1628 +
1629 +  return isymbuf;
1630 +}
1631 +
1632 +/*
1633 +static void
1634 +pin_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf)
1635 +{
1636 +  elf_tdata (input_bfd)->symtab_hdr.contents = (unsigned char *)isymbuf;
1637 +}
1638 +
1639 +*/
1640 +static void
1641 +release_local_syms (bfd *input_bfd, Elf_Internal_Sym *isymbuf)
1642 +{
1643 +  if (isymbuf && (elf_tdata (input_bfd)->symtab_hdr.contents
1644 +                 != (unsigned char *)isymbuf))
1645 +    free (isymbuf);
1646 +}
1647 +
1648 +\f/* Data structures used during relaxation. */
1649 +
1650 +enum relax_state_id {
1651 +  RS_ERROR = -1,
1652 +  RS_NONE = 0,
1653 +  RS_ALIGN,
1654 +  RS_CPENT,
1655 +  RS_PIC_CALL,
1656 +  RS_PIC_MCALL,
1657 +  RS_PIC_RCALL2,
1658 +  RS_PIC_RCALL1,
1659 +  RS_PIC_LDA,
1660 +  RS_PIC_LDW4,
1661 +  RS_PIC_LDW3,
1662 +  RS_PIC_SUB5,
1663 +  RS_NOPIC_MCALL,
1664 +  RS_NOPIC_RCALL2,
1665 +  RS_NOPIC_RCALL1,
1666 +  RS_NOPIC_LDW4,
1667 +  RS_NOPIC_LDDPC,
1668 +  RS_NOPIC_SUB5,
1669 +  RS_NOPIC_MOV2,
1670 +  RS_NOPIC_MOV1,
1671 +  RS_RCALL2,
1672 +  RS_RCALL1,
1673 +  RS_BRC2,
1674 +  RS_BRC1,
1675 +  RS_BRAL,
1676 +  RS_RJMP,
1677 +  RS_MAX,
1678 +};
1679 +
1680 +enum reference_type {
1681 +  REF_ABSOLUTE,
1682 +  REF_PCREL,
1683 +  REF_CPOOL,
1684 +  REF_GOT,
1685 +};
1686 +
1687 +struct relax_state
1688 +{
1689 +  const char *name;
1690 +  enum relax_state_id id;
1691 +  enum relax_state_id direct;
1692 +  enum relax_state_id next;
1693 +  enum relax_state_id prev;
1694 +
1695 +  enum reference_type reftype;
1696 +
1697 +  unsigned int r_type;
1698 +
1699 +  bfd_vma opcode;
1700 +  bfd_vma opcode_mask;
1701 +
1702 +  bfd_signed_vma range_min;
1703 +  bfd_signed_vma range_max;
1704 +
1705 +  bfd_size_type size;
1706 +};
1707 +
1708 +/*
1709 + * This is for relocs that
1710 + *   a) has an addend or is of type R_AVR32_DIFF32, and
1711 + *   b) references a different section than it's in, and
1712 + *   c) references a section that is relaxable
1713 + *
1714 + * as well as relocs that references the constant pool, in which case
1715 + * the add_frag member points to the frag containing the constant pool
1716 + * entry.
1717 + *
1718 + * Such relocs must be fixed up whenever we delete any code. Sections
1719 + * that don't have any relocs with all of the above properties don't
1720 + * have any additional reloc data, but sections that do will have
1721 + * additional data for all its relocs.
1722 + */
1723 +struct avr32_reloc_data
1724 +{
1725 +  struct fragment *add_frag;
1726 +  struct fragment *sub_frag;
1727 +};
1728 +
1729 +/*
1730 + * A 'fragment' is a relaxable entity, that is, code may be added or
1731 + * deleted at the end of a fragment. When this happens, all subsequent
1732 + * fragments in the list will have their offsets updated.
1733 + */
1734 +struct fragment
1735 +{
1736 +  enum relax_state_id state;
1737 +  enum relax_state_id initial_state;
1738 +
1739 +  Elf_Internal_Rela *rela;
1740 +  bfd_size_type size;
1741 +  bfd_vma offset;
1742 +  int size_adjust;
1743 +  int offset_adjust;
1744 +  bfd_boolean has_grown;
1745 +
1746 +  /* Only used by constant pool entries.  When this drops to zero, the
1747 +     frag is discarded (i.e. size_adjust is set to -4.)  */
1748 +  int refcount;
1749 +};
1750 +
1751 +struct avr32_relax_data
1752 +{
1753 +  unsigned int frag_count;
1754 +  struct fragment *frag;
1755 +  struct avr32_reloc_data *reloc_data;
1756 +
1757 +  /* TRUE if this section has one or more relaxable relocations */
1758 +  bfd_boolean is_relaxable;
1759 +  unsigned int iteration;
1760 +};
1761 +
1762 +struct avr32_section_data
1763 +{
1764 +  struct bfd_elf_section_data elf;
1765 +  struct avr32_relax_data relax_data;
1766 +};
1767 +
1768 +\f/* Relax state definitions */
1769 +
1770 +#define PIC_MOV2_OPCODE                0xe0600000
1771 +#define PIC_MOV2_MASK          0xe1e00000
1772 +#define PIC_MOV2_RANGE_MIN     (-1048576 * 4)
1773 +#define PIC_MOV2_RANGE_MAX     (1048575 * 4)
1774 +#define PIC_MCALL_OPCODE       0xf0160000
1775 +#define PIC_MCALL_MASK         0xffff0000
1776 +#define PIC_MCALL_RANGE_MIN    (-131072)
1777 +#define PIC_MCALL_RANGE_MAX    (131068)
1778 +#define RCALL2_OPCODE          0xe0a00000
1779 +#define RCALL2_MASK            0xe1ef0000
1780 +#define RCALL2_RANGE_MIN       (-2097152)
1781 +#define RCALL2_RANGE_MAX       (2097150)
1782 +#define RCALL1_OPCODE          0xc00c0000
1783 +#define RCALL1_MASK            0xf00c0000
1784 +#define RCALL1_RANGE_MIN       (-1024)
1785 +#define RCALL1_RANGE_MAX       (1022)
1786 +#define PIC_LDW4_OPCODE                0xecf00000
1787 +#define PIC_LDW4_MASK          0xfff00000
1788 +#define PIC_LDW4_RANGE_MIN     (-32768)
1789 +#define PIC_LDW4_RANGE_MAX     (32767)
1790 +#define PIC_LDW3_OPCODE                0x6c000000
1791 +#define PIC_LDW3_MASK          0xfe000000
1792 +#define PIC_LDW3_RANGE_MIN     (0)
1793 +#define PIC_LDW3_RANGE_MAX     (124)
1794 +#define SUB5_PC_OPCODE         0xfec00000
1795 +#define SUB5_PC_MASK           0xfff00000
1796 +#define SUB5_PC_RANGE_MIN      (-32768)
1797 +#define SUB5_PC_RANGE_MAX      (32767)
1798 +#define NOPIC_MCALL_OPCODE     0xf01f0000
1799 +#define NOPIC_MCALL_MASK       0xffff0000
1800 +#define NOPIC_MCALL_RANGE_MIN  PIC_MCALL_RANGE_MIN
1801 +#define NOPIC_MCALL_RANGE_MAX  PIC_MCALL_RANGE_MAX
1802 +#define NOPIC_LDW4_OPCODE      0xfef00000
1803 +#define NOPIC_LDW4_MASK                0xfff00000
1804 +#define NOPIC_LDW4_RANGE_MIN   PIC_LDW4_RANGE_MIN
1805 +#define NOPIC_LDW4_RANGE_MAX   PIC_LDW4_RANGE_MAX
1806 +#define LDDPC_OPCODE           0x48000000
1807 +#define LDDPC_MASK             0xf8000000
1808 +#define LDDPC_RANGE_MIN                0
1809 +#define LDDPC_RANGE_MAX                508
1810 +
1811 +#define NOPIC_MOV2_OPCODE  0xe0600000
1812 +#define NOPIC_MOV2_MASK        0xe1e00000
1813 +#define NOPIC_MOV2_RANGE_MIN   (-1048576)
1814 +#define NOPIC_MOV2_RANGE_MAX   (1048575)
1815 +#define NOPIC_MOV1_OPCODE  0x30000000
1816 +#define NOPIC_MOV1_MASK        0xf0000000
1817 +#define NOPIC_MOV1_RANGE_MIN   (-128)
1818 +#define NOPIC_MOV1_RANGE_MAX   (127)
1819 +
1820 +/* Only brc2 variants with cond[3] == 0 is considered, since the
1821 +   others are not relaxable.  bral is a special case and is handled
1822 +   separately.  */
1823 +#define BRC2_OPCODE            0xe0800000
1824 +#define BRC2_MASK              0xe1e80000
1825 +#define BRC2_RANGE_MIN         (-2097152)
1826 +#define BRC2_RANGE_MAX         (2097150)
1827 +#define BRC1_OPCODE            0xc0000000
1828 +#define BRC1_MASK              0xf0080000
1829 +#define BRC1_RANGE_MIN         (-256)
1830 +#define BRC1_RANGE_MAX         (254)
1831 +#define BRAL_OPCODE            0xe08f0000
1832 +#define BRAL_MASK              0xe1ef0000
1833 +#define BRAL_RANGE_MIN         BRC2_RANGE_MIN
1834 +#define BRAL_RANGE_MAX         BRC2_RANGE_MAX
1835 +#define RJMP_OPCODE            0xc0080000
1836 +#define RJMP_MASK              0xf00c0000
1837 +#define RJMP_RANGE_MIN         (-1024)
1838 +#define RJMP_RANGE_MAX         (1022)
1839 +
1840 +/* Define a relax state using the GOT  */
1841 +#define RG(id, dir, next, prev, r_type, opc, size)                     \
1842 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_GOT,                \
1843 +      R_AVR32_##r_type,        opc##_OPCODE, opc##_MASK,                       \
1844 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1845 +/* Define a relax state using the Constant Pool  */
1846 +#define RC(id, dir, next, prev, r_type, opc, size)                     \
1847 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_CPOOL,      \
1848 +      R_AVR32_##r_type,        opc##_OPCODE, opc##_MASK,                       \
1849 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1850 +
1851 +/* Define a relax state using pc-relative direct reference  */
1852 +#define RP(id, dir, next, prev, r_type, opc, size)                     \
1853 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_PCREL,      \
1854 +      R_AVR32_##r_type,        opc##_OPCODE, opc##_MASK,                       \
1855 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1856 +
1857 +/* Define a relax state using non-pc-relative direct reference */
1858 +#define RD(id, dir, next, prev, r_type, opc, size)         \
1859 +  { "RS_"#id, RS_##id, RS_##dir, RS_##next, RS_##prev, REF_ABSOLUTE,   \
1860 +      R_AVR32_##r_type,    opc##_OPCODE, opc##_MASK,           \
1861 +      opc##_RANGE_MIN, opc##_RANGE_MAX, size }
1862 +
1863 +/* Define a relax state that will be handled specially  */
1864 +#define RS(id, r_type, size)                                           \
1865 +  { "RS_"#id, RS_##id, RS_NONE, RS_NONE, RS_NONE, REF_ABSOLUTE,                \
1866 +      R_AVR32_##r_type, 0, 0, 0, 0, size }
1867 +
1868 +const struct relax_state relax_state[RS_MAX] = {
1869 +  RS(NONE, NONE, 0),
1870 +  RS(ALIGN, ALIGN, 0),
1871 +  RS(CPENT, 32_CPENT, 4),
1872 +
1873 +  RG(PIC_CALL, PIC_RCALL1, PIC_MCALL, NONE, GOTCALL, PIC_MOV2, 10),
1874 +  RG(PIC_MCALL, PIC_RCALL1, NONE, PIC_CALL, GOT18SW, PIC_MCALL, 4),
1875 +  RP(PIC_RCALL2, NONE, PIC_RCALL1, PIC_MCALL, 22H_PCREL, RCALL2, 4),
1876 +  RP(PIC_RCALL1, NONE, NONE, PIC_RCALL2, 11H_PCREL, RCALL1, 2),
1877 +
1878 +  RG(PIC_LDA, PIC_SUB5, PIC_LDW4, NONE, LDA_GOT, PIC_MOV2, 8),
1879 +  RG(PIC_LDW4, PIC_SUB5, PIC_LDW3, PIC_LDA, GOT16S, PIC_LDW4, 4),
1880 +  RG(PIC_LDW3, PIC_SUB5, NONE, PIC_LDW4, GOT7UW, PIC_LDW3, 2),
1881 +  RP(PIC_SUB5, NONE, NONE, PIC_LDW3, 16N_PCREL, SUB5_PC, 4),
1882 +
1883 +  RC(NOPIC_MCALL, NOPIC_RCALL1, NONE, NONE, CPCALL, NOPIC_MCALL, 4),
1884 +  RP(NOPIC_RCALL2, NONE, NOPIC_RCALL1, NOPIC_MCALL, 22H_PCREL, RCALL2, 4),
1885 +  RP(NOPIC_RCALL1, NONE, NONE, NOPIC_RCALL2, 11H_PCREL, RCALL1, 2),
1886 +
1887 +  RC(NOPIC_LDW4, NOPIC_MOV1, NOPIC_LDDPC, NONE, 16_CP, NOPIC_LDW4, 4),
1888 +  RC(NOPIC_LDDPC, NOPIC_MOV1, NONE, NOPIC_LDW4, 9W_CP, LDDPC, 2),
1889 +  RP(NOPIC_SUB5, NOPIC_MOV1, NONE, NOPIC_LDDPC, 16N_PCREL, SUB5_PC, 4),
1890 +  RD(NOPIC_MOV2, NONE, NOPIC_MOV1, NOPIC_SUB5, 21S, NOPIC_MOV2, 4),
1891 +  RD(NOPIC_MOV1, NONE, NONE, NOPIC_MOV2, 8S, NOPIC_MOV1, 2),
1892 +
1893 +  RP(RCALL2, NONE, RCALL1, NONE, 22H_PCREL, RCALL2, 4),
1894 +  RP(RCALL1, NONE, NONE, RCALL2, 11H_PCREL, RCALL1, 2),
1895 +  RP(BRC2, NONE, BRC1, NONE, 22H_PCREL, BRC2, 4),
1896 +  RP(BRC1, NONE, NONE, BRC2, 9H_PCREL, BRC1, 2),
1897 +  RP(BRAL, NONE, RJMP, NONE, 22H_PCREL, BRAL, 4),
1898 +  RP(RJMP, NONE, NONE, BRAL, 11H_PCREL, RJMP, 2),
1899 +};
1900 +
1901 +static bfd_boolean
1902 +avr32_elf_new_section_hook(bfd *abfd, asection *sec)
1903 +{
1904 +  struct avr32_section_data *sdata;
1905 +
1906 +  sdata = bfd_zalloc(abfd, sizeof(struct avr32_section_data));
1907 +  if (!sdata)
1908 +    return FALSE;
1909 +
1910 +  sec->used_by_bfd = sdata;
1911 +  return _bfd_elf_new_section_hook(abfd, sec);
1912 +}
1913 +
1914 +static struct avr32_relax_data *
1915 +avr32_relax_data(asection *sec)
1916 +{
1917 +  struct avr32_section_data *sdata;
1918 +
1919 +  BFD_ASSERT(sec->used_by_bfd);
1920 +
1921 +  sdata = (struct avr32_section_data *)elf_section_data(sec);
1922 +  return &sdata->relax_data;
1923 +}
1924 +
1925 +\f/* Link-time relaxation */
1926 +
1927 +static bfd_boolean
1928 +avr32_elf_relax_section(bfd *abfd, asection *sec,
1929 +                       struct bfd_link_info *info, bfd_boolean *again);
1930 +
1931 +enum relax_pass_id {
1932 +  RELAX_PASS_SIZE_FRAGS,
1933 +  RELAX_PASS_MOVE_DATA,
1934 +};
1935 +
1936 +/* Stolen from the xtensa port */
1937 +static int
1938 +internal_reloc_compare (const void *ap, const void *bp)
1939 +{
1940 +  const Elf_Internal_Rela *a = (const Elf_Internal_Rela *) ap;
1941 +  const Elf_Internal_Rela *b = (const Elf_Internal_Rela *) bp;
1942 +
1943 +  if (a->r_offset != b->r_offset)
1944 +    return (a->r_offset - b->r_offset);
1945 +
1946 +  /* We don't need to sort on these criteria for correctness,
1947 +     but enforcing a more strict ordering prevents unstable qsort
1948 +     from behaving differently with different implementations.
1949 +     Without the code below we get correct but different results
1950 +     on Solaris 2.7 and 2.8.  We would like to always produce the
1951 +     same results no matter the host.  */
1952 +
1953 +  if (a->r_info != b->r_info)
1954 +    return (a->r_info - b->r_info);
1955 +
1956 +  return (a->r_addend - b->r_addend);
1957 +}
1958 +
1959 +static enum relax_state_id
1960 +get_pcrel22_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info,
1961 +                       const Elf_Internal_Rela *rela)
1962 +{
1963 +  bfd_byte *contents;
1964 +  bfd_vma insn;
1965 +  enum relax_state_id rs = RS_NONE;
1966 +
1967 +  contents = retrieve_contents(abfd, sec, info->keep_memory);
1968 +  if (!contents)
1969 +    return RS_ERROR;
1970 +
1971 +  insn = bfd_get_32(abfd, contents + rela->r_offset);
1972 +  if ((insn & RCALL2_MASK) == RCALL2_OPCODE)
1973 +    rs = RS_RCALL2;
1974 +  else if ((insn & BRAL_MASK) == BRAL_OPCODE)
1975 +    /* Optimizing bral -> rjmp gets us into all kinds of
1976 +       trouble with jump tables. Better not do it.  */
1977 +    rs = RS_NONE;
1978 +  else if ((insn & BRC2_MASK) == BRC2_OPCODE)
1979 +    rs = RS_BRC2;
1980 +
1981 +  release_contents(sec, contents);
1982 +
1983 +  return rs;
1984 +}
1985 +
1986 +static enum relax_state_id
1987 +get_initial_relax_state(bfd *abfd, asection *sec, struct bfd_link_info *info,
1988 +                       const Elf_Internal_Rela *rela)
1989 +{
1990 +  switch (ELF_R_TYPE(rela->r_info))
1991 +    {
1992 +    case R_AVR32_GOTCALL:
1993 +      return RS_PIC_CALL;
1994 +    case R_AVR32_GOT18SW:
1995 +      return RS_PIC_MCALL;
1996 +    case R_AVR32_LDA_GOT:
1997 +      return RS_PIC_LDA;
1998 +    case R_AVR32_GOT16S:
1999 +      return RS_PIC_LDW4;
2000 +    case R_AVR32_CPCALL:
2001 +      return RS_NOPIC_MCALL;
2002 +    case R_AVR32_16_CP:
2003 +      return RS_NOPIC_LDW4;
2004 +    case R_AVR32_9W_CP:
2005 +      return RS_NOPIC_LDDPC;
2006 +    case R_AVR32_ALIGN:
2007 +      return RS_ALIGN;
2008 +    case R_AVR32_32_CPENT:
2009 +      return RS_CPENT;
2010 +    case R_AVR32_22H_PCREL:
2011 +      return get_pcrel22_relax_state(abfd, sec, info, rela);
2012 +    case R_AVR32_9H_PCREL:
2013 +      return RS_BRC1;
2014 +    default:
2015 +      return RS_NONE;
2016 +    }
2017 +}
2018 +
2019 +static bfd_boolean
2020 +reloc_is_cpool_ref(const Elf_Internal_Rela *rela)
2021 +{
2022 +  switch (ELF_R_TYPE(rela->r_info))
2023 +    {
2024 +    case R_AVR32_CPCALL:
2025 +    case R_AVR32_16_CP:
2026 +    case R_AVR32_9W_CP:
2027 +      return TRUE;
2028 +    default:
2029 +      return FALSE;
2030 +    }
2031 +}
2032 +
2033 +static struct fragment *
2034 +new_frag(bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
2035 +        struct avr32_relax_data *rd, enum relax_state_id state,
2036 +        Elf_Internal_Rela *rela)
2037 +{
2038 +  struct fragment *frag;
2039 +  bfd_size_type r_size;
2040 +  bfd_vma r_offset;
2041 +  unsigned int i = rd->frag_count;
2042 +
2043 +  BFD_ASSERT(state >= RS_NONE && state < RS_MAX);
2044 +
2045 +  rd->frag_count++;
2046 +  frag = bfd_realloc(rd->frag, sizeof(struct fragment) * rd->frag_count);
2047 +  if (!frag)
2048 +    return NULL;
2049 +  rd->frag = frag;
2050 +
2051 +  frag += i;
2052 +  memset(frag, 0, sizeof(struct fragment));
2053 +
2054 +  if (state == RS_ALIGN)
2055 +    r_size = (((rela->r_offset + (1 << rela->r_addend) - 1)
2056 +              & ~((1 << rela->r_addend) - 1)) - rela->r_offset);
2057 +  else
2058 +    r_size = relax_state[state].size;
2059 +
2060 +  if (rela)
2061 +    r_offset = rela->r_offset;
2062 +  else
2063 +    r_offset = sec->size;
2064 +
2065 +  if (i == 0)
2066 +    {
2067 +      frag->offset = 0;
2068 +      frag->size = r_offset + r_size;
2069 +    }
2070 +  else
2071 +    {
2072 +      frag->offset = rd->frag[i - 1].offset + rd->frag[i - 1].size;
2073 +      frag->size = r_offset + r_size - frag->offset;
2074 +    }
2075 +
2076 +  if (state != RS_CPENT)
2077 +    /* Make sure we don't discard this frag */
2078 +    frag->refcount = 1;
2079 +
2080 +  frag->initial_state = frag->state = state;
2081 +  frag->rela = rela;
2082 +
2083 +  return frag;
2084 +}
2085 +
2086 +static struct fragment *
2087 +find_frag(asection *sec, bfd_vma offset)
2088 +{
2089 +  struct fragment *first, *last;
2090 +  struct avr32_relax_data *rd = avr32_relax_data(sec);
2091 +
2092 +  if (rd->frag_count == 0)
2093 +    return NULL;
2094 +
2095 +  first = &rd->frag[0];
2096 +  last = &rd->frag[rd->frag_count - 1];
2097 +
2098 +  /* This may be a reloc referencing the end of a section.  The last
2099 +     frag will never have a reloc associated with it, so its size will
2100 +     never change, thus the offset adjustment of the last frag will
2101 +     always be the same as the offset adjustment of the end of the
2102 +     section.  */
2103 +  if (offset == sec->size)
2104 +    {
2105 +      BFD_ASSERT(last->offset + last->size == sec->size);
2106 +      BFD_ASSERT(!last->rela);
2107 +      return last;
2108 +    }
2109 +
2110 +  while (first <= last)
2111 +    {
2112 +      struct fragment *mid;
2113 +
2114 +      mid = (last - first) / 2 + first;
2115 +      if ((mid->offset + mid->size) <= offset)
2116 +       first = mid + 1;
2117 +      else if (mid->offset > offset)
2118 +       last = mid - 1;
2119 +      else
2120 +       return mid;
2121 +    }
2122 +
2123 +  return NULL;
2124 +}
2125 +
2126 +/* Look through all relocs in a section and determine if any relocs
2127 +   may be affected by relaxation in other sections.  If so, allocate
2128 +   an array of additional relocation data which links the affected
2129 +   relocations to the frag(s) where the relaxation may occur.
2130 +
2131 +   This function also links cpool references to cpool entries and
2132 +   increments the refcount of the latter when this happens.  */
2133 +
2134 +static bfd_boolean
2135 +allocate_reloc_data(bfd *abfd, asection *sec, Elf_Internal_Rela *relocs,
2136 +                   struct bfd_link_info *info)
2137 +{
2138 +  Elf_Internal_Shdr *symtab_hdr;
2139 +  Elf_Internal_Sym *isymbuf = NULL;
2140 +  struct avr32_relax_data *rd;
2141 +  unsigned int i;
2142 +  bfd_boolean ret = FALSE;
2143 +
2144 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2145 +  rd = avr32_relax_data(sec);
2146 +
2147 +  RDBG("%s<%s>: allocate_reloc_data\n", abfd->filename, sec->name);
2148 +
2149 +  for (i = 0; i < sec->reloc_count; i++)
2150 +    {
2151 +      Elf_Internal_Rela *rel = &relocs[i];
2152 +      asection *sym_sec;
2153 +      unsigned long r_symndx;
2154 +      bfd_vma sym_value;
2155 +
2156 +      if (!rel->r_addend && ELF_R_TYPE(rel->r_info) != R_AVR32_DIFF32
2157 +         && !reloc_is_cpool_ref(rel))
2158 +       continue;
2159 +
2160 +      r_symndx = ELF_R_SYM(rel->r_info);
2161 +
2162 +      if (r_symndx < symtab_hdr->sh_info)
2163 +       {
2164 +         Elf_Internal_Sym *isym;
2165 +
2166 +         if (!isymbuf)
2167 +           isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2168 +         if (!isymbuf)
2169 +           return FALSE;
2170 +
2171 +         isym = &isymbuf[r_symndx];
2172 +         sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2173 +         sym_value = isym->st_value;
2174 +       }
2175 +      else
2176 +       {
2177 +         struct elf_link_hash_entry *h;
2178 +
2179 +         h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info];
2180 +
2181 +         while (h->root.type == bfd_link_hash_indirect
2182 +                || h->root.type == bfd_link_hash_warning)
2183 +           h = (struct elf_link_hash_entry *)h->root.u.i.link;
2184 +
2185 +         if (h->root.type != bfd_link_hash_defined
2186 +             && h->root.type != bfd_link_hash_defweak)
2187 +           continue;
2188 +
2189 +         sym_sec = h->root.u.def.section;
2190 +         sym_value = h->root.u.def.value;
2191 +       }
2192 +
2193 +      if (sym_sec && avr32_relax_data(sym_sec)->is_relaxable)
2194 +       {
2195 +         bfd_size_type size;
2196 +         struct fragment *frag;
2197 +
2198 +         if (!rd->reloc_data)
2199 +           {
2200 +             size = sizeof(struct avr32_reloc_data) * sec->reloc_count;
2201 +             rd->reloc_data = bfd_zalloc(abfd, size);
2202 +             if (!rd->reloc_data)
2203 +               goto out;
2204 +           }
2205 +
2206 +         RDBG("[%3d] 0x%04lx: target: 0x%lx + 0x%lx",
2207 +              i, rel->r_offset, sym_value, rel->r_addend);
2208 +
2209 +         frag = find_frag(sym_sec, sym_value + rel->r_addend);
2210 +         BFD_ASSERT(frag);
2211 +         rd->reloc_data[i].add_frag = frag;
2212 +
2213 +         RDBG(" -> %s<%s>:%04lx\n", sym_sec->owner->filename, sym_sec->name,
2214 +              frag->rela ? frag->rela->r_offset : sym_sec->size);
2215 +
2216 +         if (reloc_is_cpool_ref(rel))
2217 +           {
2218 +             BFD_ASSERT(ELF_R_TYPE(frag->rela->r_info) == R_AVR32_32_CPENT);
2219 +             frag->refcount++;
2220 +           }
2221 +
2222 +         if (ELF_R_TYPE(rel->r_info) == R_AVR32_DIFF32)
2223 +           {
2224 +             bfd_byte *contents;
2225 +             bfd_signed_vma diff;
2226 +
2227 +             contents = retrieve_contents(abfd, sec, info->keep_memory);
2228 +             if (!contents)
2229 +               goto out;
2230 +
2231 +             diff = bfd_get_signed_32(abfd, contents + rel->r_offset);
2232 +             frag = find_frag(sym_sec, sym_value + rel->r_addend + diff);
2233 +             BFD_ASSERT(frag);
2234 +             rd->reloc_data[i].sub_frag = frag;
2235 +
2236 +             release_contents(sec, contents);
2237 +           }
2238 +       }
2239 +    }
2240 +
2241 +  ret = TRUE;
2242 +
2243 + out:
2244 +  release_local_syms(abfd, isymbuf);
2245 +  return ret;
2246 +}
2247 +
2248 +static bfd_boolean
2249 +global_sym_set_frag(struct elf_avr32_link_hash_entry *havr,
2250 +                   struct bfd_link_info *info ATTRIBUTE_UNUSED)
2251 +{
2252 +  struct fragment *frag;
2253 +  asection *sec;
2254 +
2255 +  if (havr->root.root.type != bfd_link_hash_defined
2256 +      && havr->root.root.type != bfd_link_hash_defweak)
2257 +    return TRUE;
2258 +
2259 +  sec = havr->root.root.u.def.section;
2260 +  if (bfd_is_const_section(sec)
2261 +      || !avr32_relax_data(sec)->is_relaxable)
2262 +    return TRUE;
2263 +
2264 +  frag = find_frag(sec, havr->root.root.u.def.value);
2265 +  if (!frag)
2266 +    {
2267 +      unsigned int i;
2268 +      struct avr32_relax_data *rd = avr32_relax_data(sec);
2269 +
2270 +      RDBG("In %s: No frag for %s <%s+%lu> (limit %lu)\n",
2271 +          sec->owner->filename, havr->root.root.root.string,
2272 +          sec->name, havr->root.root.u.def.value, sec->size);
2273 +      for (i = 0; i < rd->frag_count; i++)
2274 +       RDBG("    %8lu - %8lu\n", rd->frag[i].offset,
2275 +            rd->frag[i].offset + rd->frag[i].size);
2276 +    }
2277 +  BFD_ASSERT(frag);
2278 +
2279 +  havr->sym_frag = frag;
2280 +  return TRUE;
2281 +}
2282 +
2283 +static bfd_boolean
2284 +analyze_relocations(struct bfd_link_info *info)
2285 +{
2286 +  bfd *abfd;
2287 +  asection *sec;
2288 +
2289 +  /* Divide all relaxable sections into fragments */
2290 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2291 +    {
2292 +      if (!(elf_elfheader(abfd)->e_flags & EF_AVR32_LINKRELAX))
2293 +       {
2294 +         if (!(*info->callbacks->warning)
2295 +             (info, _("input is not relaxable"), NULL, abfd, NULL, 0))
2296 +           return FALSE;
2297 +         continue;
2298 +       }
2299 +
2300 +      for (sec = abfd->sections; sec; sec = sec->next)
2301 +       {
2302 +         struct avr32_relax_data *rd;
2303 +         struct fragment *frag;
2304 +         Elf_Internal_Rela *relocs;
2305 +         unsigned int i;
2306 +         bfd_boolean ret = TRUE;
2307 +
2308 +         if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
2309 +           continue;
2310 +
2311 +         rd = avr32_relax_data(sec);
2312 +
2313 +         relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2314 +         if (!relocs)
2315 +           return FALSE;
2316 +
2317 +         qsort(relocs, sec->reloc_count, sizeof(Elf_Internal_Rela),
2318 +               internal_reloc_compare);
2319 +
2320 +         for (i = 0; i < sec->reloc_count; i++)
2321 +           {
2322 +             enum relax_state_id state;
2323 +
2324 +             ret = FALSE;
2325 +             state = get_initial_relax_state(abfd, sec, info, &relocs[i]);
2326 +             if (state == RS_ERROR)
2327 +               break;
2328 +
2329 +             if (state)
2330 +               {
2331 +                 frag = new_frag(abfd, sec, rd, state, &relocs[i]);
2332 +                 if (!frag)
2333 +                   break;
2334 +
2335 +                 pin_internal_relocs(sec, relocs);
2336 +                 rd->is_relaxable = TRUE;
2337 +               }
2338 +
2339 +             ret = TRUE;
2340 +           }
2341 +
2342 +         release_internal_relocs(sec, relocs);
2343 +         if (!ret)
2344 +           return ret;
2345 +
2346 +         if (rd->is_relaxable)
2347 +           {
2348 +             frag = new_frag(abfd, sec, rd, RS_NONE, NULL);
2349 +             if (!frag)
2350 +               return FALSE;
2351 +           }
2352 +       }
2353 +    }
2354 +
2355 +  /* Link each global symbol to the fragment where it's defined.  */
2356 +  elf_link_hash_traverse(elf_hash_table(info), global_sym_set_frag, info);
2357 +
2358 +  /* Do the same for local symbols. */
2359 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2360 +    {
2361 +      Elf_Internal_Sym *isymbuf, *isym;
2362 +      struct fragment **local_sym_frag;
2363 +      unsigned int i, sym_count;
2364 +
2365 +      sym_count = elf_tdata(abfd)->symtab_hdr.sh_info;
2366 +      if (sym_count == 0)
2367 +       continue;
2368 +
2369 +      local_sym_frag = bfd_zalloc(abfd, sym_count * sizeof(struct fragment *));
2370 +      if (!local_sym_frag)
2371 +       return FALSE;
2372 +      elf_tdata(abfd)->local_sym_frag = local_sym_frag;
2373 +
2374 +      isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2375 +      if (!isymbuf)
2376 +       return FALSE;
2377 +
2378 +      for (i = 0; i < sym_count; i++)
2379 +       {
2380 +         struct avr32_relax_data *rd;
2381 +         struct fragment *frag;
2382 +         asection *sec;
2383 +
2384 +         isym = &isymbuf[i];
2385 +
2386 +         sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2387 +         if (!sec)
2388 +           continue;
2389 +
2390 +         rd = avr32_relax_data(sec);
2391 +         if (!rd->is_relaxable)
2392 +           continue;
2393 +
2394 +         frag = find_frag(sec, isym->st_value);
2395 +         BFD_ASSERT(frag);
2396 +
2397 +         local_sym_frag[i] = frag;
2398 +       }
2399 +
2400 +      release_local_syms(abfd, isymbuf);
2401 +    }
2402 +
2403 +  /* And again for relocs with addends and constant pool references */
2404 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2405 +    for (sec = abfd->sections; sec; sec = sec->next)
2406 +      {
2407 +       Elf_Internal_Rela *relocs;
2408 +       bfd_boolean ret;
2409 +
2410 +       if (!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
2411 +         continue;
2412 +
2413 +       relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2414 +       if (!relocs)
2415 +         return FALSE;
2416 +
2417 +       ret = allocate_reloc_data(abfd, sec, relocs, info);
2418 +
2419 +       release_internal_relocs(sec, relocs);
2420 +       if (ret == FALSE)
2421 +         return ret;
2422 +      }
2423 +
2424 +  return TRUE;
2425 +}
2426 +
2427 +static bfd_boolean
2428 +rs_is_good_enough(const struct relax_state *rs, struct fragment *frag,
2429 +                 bfd_vma symval, bfd_vma addr, struct got_entry *got,
2430 +                 struct avr32_reloc_data *ind_data,
2431 +                 bfd_signed_vma offset_adjust)
2432 +{
2433 +  bfd_signed_vma target = 0;
2434 +
2435 +  switch (rs->reftype)
2436 +    {
2437 +    case REF_ABSOLUTE:
2438 +      target = symval;
2439 +      break;
2440 +    case REF_PCREL:
2441 +      target = symval - addr;
2442 +      break;
2443 +    case REF_CPOOL:
2444 +      /* cpool frags are always in the same section and always after
2445 +        all frags referring to it.  So it's always correct to add in
2446 +        offset_adjust here.  */
2447 +      target = (ind_data->add_frag->offset + ind_data->add_frag->offset_adjust
2448 +               + offset_adjust - frag->offset - frag->offset_adjust);
2449 +      break;
2450 +    case REF_GOT:
2451 +      target = got->offset;
2452 +      break;
2453 +    default:
2454 +      abort();
2455 +    }
2456 +
2457 +  if (target >= rs->range_min && target <= rs->range_max)
2458 +    return TRUE;
2459 +  else
2460 +    return FALSE;
2461 +}
2462 +
2463 +static bfd_boolean
2464 +avr32_size_frags(bfd *abfd, asection *sec, struct bfd_link_info *info)
2465 +{
2466 +  struct elf_avr32_link_hash_table *htab;
2467 +  struct avr32_relax_data *rd;
2468 +  Elf_Internal_Shdr *symtab_hdr;
2469 +  Elf_Internal_Rela *relocs = NULL;
2470 +  Elf_Internal_Sym *isymbuf = NULL;
2471 +  struct got_entry **local_got_ents;
2472 +  struct fragment **local_sym_frag;
2473 +  bfd_boolean ret = FALSE;
2474 +  bfd_signed_vma delta = 0;
2475 +  unsigned int i;
2476 +
2477 +  htab = avr32_elf_hash_table(info);
2478 +  rd = avr32_relax_data(sec);
2479 +
2480 +  if (sec == htab->sgot)
2481 +    {
2482 +      RDBG("Relaxing GOT section (vma: 0x%lx)\n",
2483 +          sec->output_section->vma + sec->output_offset);
2484 +      if (assign_got_offsets(htab))
2485 +       htab->repeat_pass = TRUE;
2486 +      return TRUE;
2487 +    }
2488 +
2489 +  if (!rd->is_relaxable)
2490 +    return TRUE;
2491 +
2492 +  if (!sec->rawsize)
2493 +    sec->rawsize = sec->size;
2494 +
2495 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2496 +  relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2497 +  if (!relocs)
2498 +    goto out;
2499 +
2500 +  isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2501 +  if (!isymbuf)
2502 +    goto out;
2503 +
2504 +  local_got_ents = elf_local_got_ents(abfd);
2505 +  local_sym_frag = elf_tdata(abfd)->local_sym_frag;
2506 +
2507 +  RDBG("size_frags: %s<%s>\n  vma: 0x%08lx, size: 0x%08lx\n",
2508 +       abfd->filename, sec->name,
2509 +       sec->output_section->vma + sec->output_offset, sec->size);
2510 +
2511 +  for (i = 0; i < rd->frag_count; i++)
2512 +    {
2513 +      struct fragment *frag = &rd->frag[i];
2514 +      struct avr32_reloc_data *r_data = NULL, *ind_data = NULL;
2515 +      const struct relax_state *state, *next_state;
2516 +      struct fragment *target_frag = NULL;
2517 +      asection *sym_sec = NULL;
2518 +      Elf_Internal_Rela *rela;
2519 +      struct got_entry *got;
2520 +      bfd_vma symval, r_offset, addend, addr;
2521 +      bfd_signed_vma size_adjust = 0, distance;
2522 +      unsigned long r_symndx;
2523 +      bfd_boolean defined = TRUE, dynamic = FALSE;
2524 +      unsigned char sym_type;
2525 +
2526 +      frag->offset_adjust += delta;
2527 +      state = next_state = &relax_state[frag->state];
2528 +      rela = frag->rela;
2529 +
2530 +      BFD_ASSERT(state->id == frag->state);
2531 +
2532 +      RDBG("  0x%04lx%c%d: %s [size %ld]", rela ? rela->r_offset : sec->rawsize,
2533 +          (frag->offset_adjust < 0)?'-':'+',
2534 +          abs(frag->offset_adjust), state->name, state->size);
2535 +
2536 +      if (!rela)
2537 +       {
2538 +         RDBG(": no reloc, ignoring\n");
2539 +         continue;
2540 +       }
2541 +
2542 +      BFD_ASSERT((unsigned int)(rela - relocs) < sec->reloc_count);
2543 +      BFD_ASSERT(state != RS_NONE);
2544 +
2545 +      r_offset = rela->r_offset + frag->offset_adjust;
2546 +      addr = sec->output_section->vma + sec->output_offset + r_offset;
2547 +
2548 +      switch (frag->state)
2549 +       {
2550 +       case RS_ALIGN:
2551 +         size_adjust = ((addr + (1 << rela->r_addend) - 1)
2552 +                        & ~((1 << rela->r_addend) - 1));
2553 +         size_adjust -= (sec->output_section->vma + sec->output_offset
2554 +                         + frag->offset + frag->offset_adjust
2555 +                         + frag->size + frag->size_adjust);
2556 +
2557 +         RDBG(": adjusting size %lu -> %lu\n", frag->size + frag->size_adjust,
2558 +              frag->size + frag->size_adjust + size_adjust);
2559 +         break;
2560 +
2561 +       case RS_CPENT:
2562 +         if (frag->refcount == 0 && frag->size_adjust == 0)
2563 +           {
2564 +             RDBG(": discarding frag\n");
2565 +             size_adjust = -4;
2566 +           }
2567 +         else if (frag->refcount > 0 && frag->size_adjust < 0)
2568 +           {
2569 +             RDBG(": un-discarding frag\n");
2570 +             size_adjust = 4;
2571 +           }
2572 +         break;
2573 +
2574 +       default:
2575 +         if (rd->reloc_data)
2576 +           r_data = &rd->reloc_data[frag->rela - relocs];
2577 +
2578 +         /* If this is a cpool reference, we want the symbol that the
2579 +            cpool entry refers to, not the symbol for the cpool entry
2580 +            itself, as we already know what frag it's in.  */
2581 +         if (relax_state[frag->initial_state].reftype == REF_CPOOL)
2582 +           {
2583 +             Elf_Internal_Rela *irela = r_data->add_frag->rela;
2584 +
2585 +             r_symndx = ELF_R_SYM(irela->r_info);
2586 +             addend = irela->r_addend;
2587 +
2588 +             /* The constant pool must be in the same section as the
2589 +                reloc referring to it.  */
2590 +             BFD_ASSERT((unsigned long)(irela - relocs) < sec->reloc_count);
2591 +
2592 +             ind_data = r_data;
2593 +             r_data = &rd->reloc_data[irela - relocs];
2594 +           }
2595 +         else
2596 +           {
2597 +             r_symndx = ELF_R_SYM(rela->r_info);
2598 +             addend = rela->r_addend;
2599 +           }
2600 +
2601 +         /* Get the value of the symbol referred to by the reloc.  */
2602 +         if (r_symndx < symtab_hdr->sh_info)
2603 +           {
2604 +             Elf_Internal_Sym *isym;
2605 +
2606 +             isym = isymbuf + r_symndx;
2607 +             symval = 0;
2608 +
2609 +             RDBG(" local sym %lu: ", r_symndx);
2610 +
2611 +             if (isym->st_shndx == SHN_UNDEF)
2612 +               defined = FALSE;
2613 +             else if (isym->st_shndx == SHN_ABS)
2614 +               sym_sec = bfd_abs_section_ptr;
2615 +             else if (isym->st_shndx == SHN_COMMON)
2616 +               sym_sec = bfd_com_section_ptr;
2617 +             else
2618 +               sym_sec = bfd_section_from_elf_index(abfd, isym->st_shndx);
2619 +
2620 +             symval = isym->st_value;
2621 +             sym_type = ELF_ST_TYPE(isym->st_info);
2622 +             target_frag = local_sym_frag[r_symndx];
2623 +
2624 +             if (local_got_ents)
2625 +               got = local_got_ents[r_symndx];
2626 +             else
2627 +               got = NULL;
2628 +           }
2629 +         else
2630 +           {
2631 +             /* Global symbol */
2632 +             unsigned long index;
2633 +             struct elf_link_hash_entry *h;
2634 +             struct elf_avr32_link_hash_entry *havr;
2635 +
2636 +             index = r_symndx - symtab_hdr->sh_info;
2637 +             h = elf_sym_hashes(abfd)[index];
2638 +             BFD_ASSERT(h != NULL);
2639 +
2640 +             while (h->root.type == bfd_link_hash_indirect
2641 +                    || h->root.type == bfd_link_hash_warning)
2642 +               h = (struct elf_link_hash_entry *)h->root.u.i.link;
2643 +
2644 +             havr = (struct elf_avr32_link_hash_entry *)h;
2645 +             got = h->got.glist;
2646 +
2647 +             symval = 0;
2648 +
2649 +             RDBG(" %s: ", h->root.root.string);
2650 +
2651 +             if (h->root.type != bfd_link_hash_defined
2652 +                 && h->root.type != bfd_link_hash_defweak)
2653 +               {
2654 +                 RDBG("(undef)");
2655 +                 defined = FALSE;
2656 +               }
2657 +             else if ((info->shared && !info->symbolic && h->dynindx != -1)
2658 +                      || (htab->root.dynamic_sections_created
2659 +                          && h->def_dynamic && !h->def_regular))
2660 +               {
2661 +                 RDBG("(dynamic)");
2662 +                 dynamic = TRUE;
2663 +                 sym_sec = h->root.u.def.section;
2664 +               }
2665 +             else
2666 +               {
2667 +                 sym_sec = h->root.u.def.section;
2668 +                 symval = h->root.u.def.value;
2669 +                 target_frag = havr->sym_frag;
2670 +               }
2671 +
2672 +             sym_type = h->type;
2673 +           }
2674 +
2675 +         /* Thanks to elf32-ppc for this one.  */
2676 +         if (sym_sec && sym_sec->sec_info_type == ELF_INFO_TYPE_MERGE)
2677 +           {
2678 +             /* At this stage in linking, no SEC_MERGE symbol has been
2679 +                adjusted, so all references to such symbols need to be
2680 +                passed through _bfd_merged_section_offset.  (Later, in
2681 +                relocate_section, all SEC_MERGE symbols *except* for
2682 +                section symbols have been adjusted.)
2683 +
2684 +                SEC_MERGE sections are not relaxed by us, as they
2685 +                shouldn't contain any code.  */
2686 +
2687 +             BFD_ASSERT(!target_frag && !(r_data && r_data->add_frag));
2688 +
2689 +             /* gas may reduce relocations against symbols in SEC_MERGE
2690 +                sections to a relocation against the section symbol when
2691 +                the original addend was zero.  When the reloc is against
2692 +                a section symbol we should include the addend in the
2693 +                offset passed to _bfd_merged_section_offset, since the
2694 +                location of interest is the original symbol.  On the
2695 +                other hand, an access to "sym+addend" where "sym" is not
2696 +                a section symbol should not include the addend;  Such an
2697 +                access is presumed to be an offset from "sym";  The
2698 +                location of interest is just "sym".  */
2699 +             RDBG("\n    MERGE: %s: 0x%lx+0x%lx+0x%lx -> ",
2700 +                  (sym_type == STT_SECTION)?"section":"not section",
2701 +                  sym_sec->output_section->vma + sym_sec->output_offset,
2702 +                  symval, addend);
2703 +
2704 +             if (sym_type == STT_SECTION)
2705 +               symval += addend;
2706 +
2707 +             symval = (_bfd_merged_section_offset
2708 +                       (abfd, &sym_sec,
2709 +                        elf_section_data(sym_sec)->sec_info, symval));
2710 +
2711 +             if (sym_type != STT_SECTION)
2712 +               symval += addend;
2713 +           }
2714 +         else
2715 +           symval += addend;
2716 +
2717 +         if (defined && !dynamic)
2718 +           {
2719 +             RDBG("0x%lx+0x%lx",
2720 +                  sym_sec->output_section->vma + sym_sec->output_offset,
2721 +                  symval);
2722 +             symval += sym_sec->output_section->vma + sym_sec->output_offset;
2723 +           }
2724 +
2725 +         if (r_data && r_data->add_frag)
2726 +           /* If the add_frag pointer is set, it means that this reloc
2727 +              has an addend that may be affected by relaxation.  */
2728 +           target_frag = r_data->add_frag;
2729 +
2730 +         if (target_frag)
2731 +           {
2732 +             symval += target_frag->offset_adjust;
2733 +
2734 +             /* If target_frag comes after this frag in the same
2735 +                section, we should assume that it will be moved by
2736 +                the same amount we are.  */
2737 +             if ((target_frag - rd->frag) < (int)rd->frag_count
2738 +                 && target_frag > frag)
2739 +               symval += delta;
2740 +           }
2741 +
2742 +         distance = symval - addr;
2743 +
2744 +         /* First, try to make a direct reference.  If the symbol is
2745 +            dynamic or undefined, we must take care not to change its
2746 +            reference type, that is, we can't make it direct.
2747 +
2748 +            Also, it seems like some sections may actually be resized
2749 +            after the relaxation code is done, so we can't really
2750 +            trust that our "distance" is correct.  There's really no
2751 +            easy solution to this problem, so we'll just disallow
2752 +            direct references to SEC_DATA sections.
2753 +
2754 +            Oh, and .bss isn't actually SEC_DATA, so we disallow
2755 +            !SEC_HAS_CONTENTS as well. */
2756 +         if (!dynamic && defined
2757 +             && (htab->direct_data_refs
2758 +                 || (!(sym_sec->flags & SEC_DATA)
2759 +                     && (sym_sec->flags & SEC_HAS_CONTENTS)))
2760 +             && next_state->direct)
2761 +           {
2762 +             next_state = &relax_state[next_state->direct];
2763 +             RDBG(" D-> %s", next_state->name);
2764 +           }
2765 +
2766 +         /* Iterate backwards until we find a state that fits.  */
2767 +         while (next_state->prev
2768 +                && !rs_is_good_enough(next_state, frag, symval, addr,
2769 +                                      got, ind_data, delta))
2770 +           {
2771 +             next_state = &relax_state[next_state->prev];
2772 +             RDBG(" P-> %s", next_state->name);
2773 +           }
2774 +
2775 +         /* Then try to find the best possible state.  */
2776 +         while (next_state->next)
2777 +           {
2778 +             const struct relax_state *candidate;
2779 +
2780 +             candidate = &relax_state[next_state->next];
2781 +             if (!rs_is_good_enough(candidate, frag, symval, addr, got,
2782 +                                    ind_data, delta))
2783 +               break;
2784 +
2785 +             next_state = candidate;
2786 +             RDBG(" N-> %s", next_state->name);
2787 +           }
2788 +
2789 +         RDBG(" [size %ld]\n", next_state->size);
2790 +
2791 +         BFD_ASSERT(next_state->id);
2792 +         BFD_ASSERT(!dynamic || next_state->reftype == REF_GOT);
2793 +
2794 +         size_adjust = next_state->size - state->size;
2795 +
2796 +         /* There's a theoretical possibility that shrinking one frag
2797 +            may cause another to grow, which may cause the first one to
2798 +            grow as well, and we're back where we started.  Avoid this
2799 +            scenario by disallowing a frag that has grown to ever
2800 +            shrink again.  */
2801 +         if (state->reftype == REF_GOT && next_state->reftype != REF_GOT)
2802 +           {
2803 +             if (frag->has_grown)
2804 +               next_state = state;
2805 +             else
2806 +               unref_got_entry(htab, got);
2807 +           }
2808 +         else if (state->reftype != REF_GOT && next_state->reftype == REF_GOT)
2809 +           {
2810 +             ref_got_entry(htab, got);
2811 +             frag->has_grown = TRUE;
2812 +           }
2813 +         else if (state->reftype == REF_CPOOL
2814 +                  && next_state->reftype != REF_CPOOL)
2815 +           {
2816 +             if (frag->has_grown)
2817 +               next_state = state;
2818 +             else
2819 +               ind_data->add_frag->refcount--;
2820 +           }
2821 +         else if (state->reftype != REF_CPOOL
2822 +                  && next_state->reftype == REF_CPOOL)
2823 +           {
2824 +             ind_data->add_frag->refcount++;
2825 +             frag->has_grown = TRUE;
2826 +           }
2827 +         else
2828 +           {
2829 +             if (frag->has_grown && size_adjust < 0)
2830 +               next_state = state;
2831 +             else if (size_adjust > 0)
2832 +               frag->has_grown = TRUE;
2833 +           }
2834 +
2835 +         size_adjust = next_state->size - state->size;
2836 +         frag->state = next_state->id;
2837 +
2838 +         break;
2839 +       }
2840 +
2841 +      if (size_adjust)
2842 +       htab->repeat_pass = TRUE;
2843 +
2844 +      frag->size_adjust += size_adjust;
2845 +      sec->size += size_adjust;
2846 +      delta += size_adjust;
2847 +
2848 +      BFD_ASSERT((frag->offset + frag->offset_adjust
2849 +                 + frag->size + frag->size_adjust)
2850 +                == (frag[1].offset + frag[1].offset_adjust + delta));
2851 +    }
2852 +
2853 +  ret = TRUE;
2854 +
2855 + out:
2856 +  release_local_syms(abfd, isymbuf);
2857 +  release_internal_relocs(sec, relocs);
2858 +  return ret;
2859 +}
2860 +
2861 +static bfd_boolean
2862 +adjust_global_symbol(struct elf_avr32_link_hash_entry *havr,
2863 +                    struct bfd_link_info *info ATTRIBUTE_UNUSED)
2864 +{
2865 +  struct elf_link_hash_entry *h = &havr->root;
2866 +
2867 +  if (havr->sym_frag && (h->root.type == bfd_link_hash_defined
2868 +                        || h->root.type == bfd_link_hash_defweak))
2869 +    {
2870 +      RDBG("adjust_global_symbol: %s 0x%08lx -> 0x%08lx\n",
2871 +          h->root.root.string, h->root.u.def.value,
2872 +          h->root.u.def.value + havr->sym_frag->offset_adjust);
2873 +      h->root.u.def.value += havr->sym_frag->offset_adjust;
2874 +    }
2875 +  return TRUE;
2876 +}
2877 +
2878 +static bfd_boolean
2879 +adjust_syms(struct bfd_link_info *info)
2880 +{
2881 +  struct elf_avr32_link_hash_table *htab;
2882 +  bfd *abfd;
2883 +
2884 +  htab = avr32_elf_hash_table(info);
2885 +  elf_link_hash_traverse(&htab->root, adjust_global_symbol, info);
2886 +
2887 +  for (abfd = info->input_bfds; abfd; abfd = abfd->link_next)
2888 +    {
2889 +      Elf_Internal_Sym *isymbuf;
2890 +      struct fragment **local_sym_frag, *frag;
2891 +      unsigned int i, sym_count;
2892 +
2893 +      sym_count = elf_tdata(abfd)->symtab_hdr.sh_info;
2894 +      if (sym_count == 0)
2895 +       continue;
2896 +
2897 +      isymbuf = retrieve_local_syms(abfd, info->keep_memory);
2898 +      if (!isymbuf)
2899 +       return FALSE;
2900 +
2901 +      local_sym_frag = elf_tdata(abfd)->local_sym_frag;
2902 +
2903 +      for (i = 0; i < sym_count; i++)
2904 +       {
2905 +         frag = local_sym_frag[i];
2906 +         if (frag)
2907 +           {
2908 +             RDBG("adjust_local_symbol: %s[%u] 0x%08lx -> 0x%08lx\n",
2909 +                  abfd->filename, i, isymbuf[i].st_value,
2910 +                  isymbuf[i].st_value + frag->offset_adjust);
2911 +             isymbuf[i].st_value += frag->offset_adjust;
2912 +           }
2913 +       }
2914 +
2915 +      release_local_syms(abfd, isymbuf);
2916 +    }
2917 +
2918 +  htab->symbols_adjusted = TRUE;
2919 +  return TRUE;
2920 +}
2921 +
2922 +static bfd_boolean
2923 +adjust_relocs(bfd *abfd, asection *sec, struct bfd_link_info *info)
2924 +{
2925 +  struct avr32_relax_data *rd;
2926 +  Elf_Internal_Rela *relocs;
2927 +  Elf_Internal_Shdr *symtab_hdr;
2928 +  unsigned int i;
2929 +  bfd_boolean ret = FALSE;
2930 +
2931 +  rd = avr32_relax_data(sec);
2932 +  if (!rd->reloc_data)
2933 +    return TRUE;
2934 +
2935 +  RDBG("adjust_relocs: %s<%s> (count: %u)\n", abfd->filename, sec->name,
2936 +       sec->reloc_count);
2937 +
2938 +  relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
2939 +  if (!relocs)
2940 +    return FALSE;
2941 +
2942 +  symtab_hdr = &elf_tdata(abfd)->symtab_hdr;
2943 +
2944 +  for (i = 0; i < sec->reloc_count; i++)
2945 +    {
2946 +      Elf_Internal_Rela *rela = &relocs[i];
2947 +      struct avr32_reloc_data *r_data = &rd->reloc_data[i];
2948 +      struct fragment *sym_frag;
2949 +      unsigned long r_symndx;
2950 +
2951 +      if (r_data->add_frag)
2952 +       {
2953 +         r_symndx = ELF_R_SYM(rela->r_info);
2954 +
2955 +         if (r_symndx < symtab_hdr->sh_info)
2956 +           sym_frag = elf_tdata(abfd)->local_sym_frag[r_symndx];
2957 +         else
2958 +           {
2959 +             struct elf_link_hash_entry *h;
2960 +
2961 +             h = elf_sym_hashes(abfd)[r_symndx - symtab_hdr->sh_info];
2962 +
2963 +             while (h->root.type == bfd_link_hash_indirect
2964 +                    || h->root.type == bfd_link_hash_warning)
2965 +               h = (struct elf_link_hash_entry *)h->root.u.i.link;
2966 +
2967 +             BFD_ASSERT(h->root.type == bfd_link_hash_defined
2968 +                        || h->root.type == bfd_link_hash_defweak);
2969 +
2970 +             sym_frag = ((struct elf_avr32_link_hash_entry *)h)->sym_frag;
2971 +           }
2972 +
2973 +         RDBG("    addend: 0x%08lx -> 0x%08lx\n",
2974 +              rela->r_addend,
2975 +              rela->r_addend + r_data->add_frag->offset_adjust
2976 +              - (sym_frag ? sym_frag->offset_adjust : 0));
2977 +
2978 +         /* If this is against a section symbol, we won't find any
2979 +            sym_frag, so we'll just adjust the addend.  */
2980 +         rela->r_addend += r_data->add_frag->offset_adjust;
2981 +         if (sym_frag)
2982 +           rela->r_addend -= sym_frag->offset_adjust;
2983 +
2984 +         if (r_data->sub_frag)
2985 +           {
2986 +             bfd_byte *contents;
2987 +             bfd_signed_vma diff;
2988 +
2989 +             contents = retrieve_contents(abfd, sec, info->keep_memory);
2990 +             if (!contents)
2991 +               goto out;
2992 +
2993 +             /* I realize now that sub_frag is misnamed.  It's
2994 +                actually add_frag which is subtracted in this
2995 +                case...  */
2996 +             diff = bfd_get_signed_32(abfd, contents + rela->r_offset);
2997 +             diff += (r_data->sub_frag->offset_adjust
2998 +                      - r_data->add_frag->offset_adjust);
2999 +             bfd_put_32(abfd, diff, contents + rela->r_offset);
3000 +
3001 +             RDBG("   0x%lx: DIFF32 updated: 0x%lx\n", rela->r_offset, diff);
3002 +
3003 +             release_contents(sec, contents);
3004 +           }
3005 +       }
3006 +      else
3007 +       BFD_ASSERT(!r_data->sub_frag);
3008 +    }
3009 +
3010 +  ret = TRUE;
3011 +
3012 + out:
3013 +  release_internal_relocs(sec, relocs);
3014 +  return ret;
3015 +}
3016 +
3017 +static bfd_boolean
3018 +avr32_move_data(bfd *abfd, asection *sec, struct bfd_link_info *info)
3019 +{
3020 +  struct elf_avr32_link_hash_table *htab;
3021 +  struct avr32_relax_data *rd;
3022 +  struct fragment *frag, *fragend;
3023 +  Elf_Internal_Rela *relocs = NULL;
3024 +  bfd_byte *contents = NULL;
3025 +  unsigned int i;
3026 +  bfd_boolean ret = FALSE;
3027 +
3028 +  htab = avr32_elf_hash_table(info);
3029 +  rd = avr32_relax_data(sec);
3030 +
3031 +  if (!htab->symbols_adjusted)
3032 +    if (!adjust_syms(info))
3033 +      return FALSE;
3034 +
3035 +  if (rd->is_relaxable)
3036 +    {
3037 +      /* Resize the section first, so that we can be sure that enough
3038 +        memory is allocated in case the section has grown.  */
3039 +      if (sec->size > sec->rawsize
3040 +         && elf_section_data(sec)->this_hdr.contents)
3041 +       {
3042 +         /* We must not use cached data if the section has grown.  */
3043 +         free(elf_section_data(sec)->this_hdr.contents);
3044 +         elf_section_data(sec)->this_hdr.contents = NULL;
3045 +       }
3046 +
3047 +      relocs = retrieve_internal_relocs(abfd, sec, info->keep_memory);
3048 +      if (!relocs)
3049 +       goto out;
3050 +      contents = retrieve_contents(abfd, sec, info->keep_memory);
3051 +      if (!contents)
3052 +       goto out;
3053 +
3054 +      fragend = rd->frag + rd->frag_count;
3055 +
3056 +      RDBG("move_data: %s<%s>: relocs=%p, contents=%p\n",
3057 +          abfd->filename, sec->name, relocs, contents);
3058 +
3059 +      /* First, move the data into place. We must take care to move
3060 +        frags in the right order so that we don't accidentally
3061 +        overwrite parts of the next frag.  */
3062 +      for (frag = rd->frag; frag < fragend; frag++)
3063 +       {
3064 +         RDBG("    0x%08lx%c0x%x: size 0x%lx%c0x%x\n",
3065 +              frag->offset, frag->offset_adjust >= 0 ? '+' : '-',
3066 +              abs(frag->offset_adjust),
3067 +              frag->size, frag->size_adjust >= 0 ? '+' : '-',
3068 +              abs(frag->size_adjust));
3069 +         if (frag->offset_adjust > 0)
3070 +           {
3071 +             struct fragment *prev = frag - 1;
3072 +             struct fragment *last;
3073 +
3074 +             for (last = frag; last < fragend && last->offset_adjust > 0;
3075 +                  last++) ;
3076 +
3077 +             if (last == fragend)
3078 +               last--;
3079 +
3080 +             for (frag = last; frag != prev; frag--)
3081 +               {
3082 +                 if (frag->offset_adjust
3083 +                     && frag->size + frag->size_adjust > 0)
3084 +                   {
3085 +                     RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n",
3086 +                          frag->offset, frag->offset + frag->offset_adjust,
3087 +                          frag->size + frag->size_adjust);
3088 +                     memmove(contents + frag->offset + frag->offset_adjust,
3089 +                             contents + frag->offset,
3090 +                             frag->size + frag->size_adjust);
3091 +                   }
3092 +               }
3093 +             frag = last;
3094 +           }
3095 +         else if (frag->offset_adjust && frag->size + frag->size_adjust > 0)
3096 +           {
3097 +             RDBG("memmove 0x%lx -> 0x%lx (size %lu)\n",
3098 +                  frag->offset, frag->offset + frag->offset_adjust,
3099 +                  frag->size + frag->size_adjust);
3100 +             memmove(contents + frag->offset + frag->offset_adjust,
3101 +                     contents + frag->offset,
3102 +                     frag->size + frag->size_adjust);
3103 +           }
3104 +       }
3105 +
3106 +      i = 0;
3107 +
3108 +      for (frag = rd->frag; frag < fragend; frag++)
3109 +       {
3110 +         const struct relax_state *state, *istate;
3111 +         struct avr32_reloc_data *r_data = NULL;
3112 +
3113 +         istate = &relax_state[frag->initial_state];
3114 +         state = &relax_state[frag->state];
3115 +
3116 +         if (rd->reloc_data)
3117 +           r_data = &rd->reloc_data[frag->rela - relocs];
3118 +
3119 +         BFD_ASSERT((long)(frag->size + frag->size_adjust) >= 0);
3120 +         BFD_ASSERT(state->reftype != REF_CPOOL
3121 +                    || r_data->add_frag->refcount > 0);
3122 +
3123 +         if (istate->reftype == REF_CPOOL && state->reftype != REF_CPOOL)
3124 +           {
3125 +             struct fragment *ifrag;
3126 +
3127 +             /* An indirect reference through the cpool has been
3128 +                converted to a direct reference.  We must update the
3129 +                reloc to point to the symbol itself instead of the
3130 +                constant pool entry.  The reloc type will be updated
3131 +                later.  */
3132 +             ifrag = r_data->add_frag;
3133 +             frag->rela->r_info = ifrag->rela->r_info;
3134 +             frag->rela->r_addend = ifrag->rela->r_addend;
3135 +
3136 +             /* Copy the reloc data so the addend will be adjusted
3137 +                correctly later.  */
3138 +             *r_data = rd->reloc_data[ifrag->rela - relocs];
3139 +           }
3140 +
3141 +         /* Move all relocs covered by this frag.  */
3142 +         if (frag->rela)
3143 +           BFD_ASSERT(&relocs[i] <= frag->rela);
3144 +         else
3145 +           BFD_ASSERT((frag + 1) == fragend && frag->state == RS_NONE);
3146 +
3147 +         if (frag == rd->frag)
3148 +           BFD_ASSERT(i == 0);
3149 +         else
3150 +           BFD_ASSERT(&relocs[i] > frag[-1].rela);
3151 +
3152 +         /* If non-null, frag->rela is the last relocation in the
3153 +            fragment.  frag->rela can only be null in the last
3154 +            fragment, so in that case, we'll just do the rest.  */
3155 +         for (; (i < sec->reloc_count
3156 +                 && (!frag->rela || &relocs[i] <= frag->rela)); i++)
3157 +           {
3158 +             RDBG("[%4u] r_offset 0x%08lx -> 0x%08lx\n", i, relocs[i].r_offset,
3159 +                  relocs[i].r_offset + frag->offset_adjust);
3160 +             relocs[i].r_offset += frag->offset_adjust;
3161 +           }
3162 +
3163 +         if (frag->refcount == 0)
3164 +           {
3165 +             /* If this frag is to be discarded, make sure we won't
3166 +                relocate it later on.  */
3167 +             BFD_ASSERT(frag->state == RS_CPENT);
3168 +             frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info),
3169 +                                           R_AVR32_NONE);
3170 +           }
3171 +         else if (frag->state == RS_ALIGN)
3172 +           {
3173 +             bfd_vma addr, addr_end;
3174 +
3175 +             addr = frag->rela->r_offset;
3176 +             addr_end = (frag->offset + frag->offset_adjust
3177 +                         + frag->size + frag->size_adjust);
3178 +
3179 +             /* If the section is executable, insert NOPs.
3180 +                Otherwise, insert zeroes.  */
3181 +             if (sec->flags & SEC_CODE)
3182 +               {
3183 +                 if (addr & 1)
3184 +                   {
3185 +                     bfd_put_8(abfd, 0, contents + addr);
3186 +                     addr++;
3187 +                   }
3188 +
3189 +                 BFD_ASSERT(!((addr_end - addr) & 1));
3190 +
3191 +                 while (addr < addr_end)
3192 +                   {
3193 +                     bfd_put_16(abfd, NOP_OPCODE, contents + addr);
3194 +                     addr += 2;
3195 +                   }
3196 +               }
3197 +             else
3198 +               memset(contents + addr, 0, addr_end - addr);
3199 +           }
3200 +         else if (state->opcode_mask)
3201 +           {
3202 +             bfd_vma insn;
3203 +
3204 +             /* Update the opcode and the relocation type unless it's a
3205 +                "special" relax state (i.e. RS_NONE, RS_ALIGN or
3206 +                RS_CPENT.), in which case the opcode mask is zero.  */
3207 +             insn = bfd_get_32(abfd, contents + frag->rela->r_offset);
3208 +             insn &= ~state->opcode_mask;
3209 +             insn |= state->opcode;
3210 +             RDBG("    0x%lx: inserting insn %08lx\n",
3211 +                  frag->rela->r_offset, insn);
3212 +             bfd_put_32(abfd, insn, contents + frag->rela->r_offset);
3213 +
3214 +             frag->rela->r_info = ELF_R_INFO(ELF_R_SYM(frag->rela->r_info),
3215 +                                             state->r_type);
3216 +           }
3217 +
3218 +         if ((frag + 1) == fragend)
3219 +           BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust
3220 +                       + frag->size_adjust) == sec->size);
3221 +         else
3222 +           BFD_ASSERT((frag->offset + frag->size + frag->offset_adjust
3223 +                       + frag->size_adjust)
3224 +                      == (frag[1].offset + frag[1].offset_adjust));
3225 +       }
3226 +    }
3227 +
3228 +  /* Adjust reloc addends and DIFF32 differences */
3229 +  if (!adjust_relocs(abfd, sec, info))
3230 +    return FALSE;
3231 +
3232 +  ret = TRUE;
3233 +
3234 + out:
3235 +  release_contents(sec, contents);
3236 +  release_internal_relocs(sec, relocs);
3237 +  return ret;
3238 +}
3239 +
3240 +static bfd_boolean
3241 +avr32_elf_relax_section(bfd *abfd, asection *sec,
3242 +                       struct bfd_link_info *info, bfd_boolean *again)
3243 +{
3244 +  struct elf_avr32_link_hash_table *htab;
3245 +  struct avr32_relax_data *rd;
3246 +
3247 +  *again = FALSE;
3248 +  if (info->relocatable)
3249 +    return TRUE;
3250 +
3251 +  htab = avr32_elf_hash_table(info);
3252 +  if ((!(sec->flags & SEC_RELOC) || sec->reloc_count == 0)
3253 +      && sec != htab->sgot)
3254 +    return TRUE;
3255 +
3256 +  if (!htab->relocations_analyzed)
3257 +    {
3258 +      if (!analyze_relocations(info))
3259 +       return FALSE;
3260 +      htab->relocations_analyzed = TRUE;
3261 +    }
3262 +
3263 +  rd = avr32_relax_data(sec);
3264 +
3265 +  if (rd->iteration != htab->relax_iteration)
3266 +    {
3267 +      if (!htab->repeat_pass)
3268 +       htab->relax_pass++;
3269 +      htab->relax_iteration++;
3270 +      htab->repeat_pass = FALSE;
3271 +    }
3272 +
3273 +  rd->iteration++;
3274 +
3275 +  switch (htab->relax_pass)
3276 +    {
3277 +    case RELAX_PASS_SIZE_FRAGS:
3278 +      if (!avr32_size_frags(abfd, sec, info))
3279 +       return FALSE;
3280 +      *again = TRUE;
3281 +      break;
3282 +    case RELAX_PASS_MOVE_DATA:
3283 +      if (!avr32_move_data(abfd, sec, info))
3284 +       return FALSE;
3285 +      break;
3286 +  }
3287 +
3288 +  return TRUE;
3289 +}
3290 +
3291 +
3292 +/* Relocation */
3293 +
3294 +static bfd_reloc_status_type
3295 +avr32_check_reloc_value(asection *sec, Elf_Internal_Rela *rela,
3296 +                       bfd_signed_vma relocation, reloc_howto_type *howto);
3297 +static bfd_reloc_status_type
3298 +avr32_final_link_relocate(reloc_howto_type *howto, bfd *input_bfd,
3299 +                         asection *input_section, bfd_byte *contents,
3300 +                         Elf_Internal_Rela *rel, bfd_vma value);
3301 +static bfd_boolean
3302 +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info,
3303 +                          bfd *input_bfd, asection *input_section,
3304 +                          bfd_byte *contents, Elf_Internal_Rela *relocs,
3305 +                          Elf_Internal_Sym *local_syms,
3306 +                          asection **local_sections);
3307 +
3308 +
3309 +#define symbol_address(symbol) \
3310 +  symbol->value + symbol->section->output_section->vma \
3311 +  + symbol->section->output_offset
3312 +
3313 +#define avr32_elf_insert_field(size, field, abfd, reloc_entry, data)   \
3314 +  do                                                                   \
3315 +    {                                                                  \
3316 +      unsigned long x;                                                 \
3317 +      x = bfd_get_##size (abfd, data + reloc_entry->address);          \
3318 +      x &= ~reloc_entry->howto->dst_mask;                              \
3319 +      x |= field & reloc_entry->howto->dst_mask;                       \
3320 +      bfd_put_##size (abfd, (bfd_vma) x, data + reloc_entry->address); \
3321 +    }                                                                  \
3322 +  while(0)
3323 +
3324 +static bfd_reloc_status_type
3325 +avr32_check_reloc_value(asection *sec ATTRIBUTE_UNUSED,
3326 +                       Elf_Internal_Rela *rela ATTRIBUTE_UNUSED,
3327 +                       bfd_signed_vma relocation,
3328 +                       reloc_howto_type *howto)
3329 +{
3330 +  bfd_vma reloc_u;
3331 +
3332 +  /* We take "complain_overflow_dont" to mean "don't complain on
3333 +     alignment either". This way, we don't have to special-case
3334 +     R_AVR32_HI16 */
3335 +  if (howto->complain_on_overflow == complain_overflow_dont)
3336 +    return bfd_reloc_ok;
3337 +
3338 +  /* Check if the value is correctly aligned */
3339 +  if (relocation & ((1 << howto->rightshift) - 1))
3340 +    {
3341 +      RDBG("misaligned: %s<%s+%lx>: %s: 0x%lx (align %u)\n",
3342 +          sec->owner->filename, sec->name, rela->r_offset,
3343 +          howto->name, relocation, howto->rightshift);
3344 +      return bfd_reloc_overflow;
3345 +    }
3346 +
3347 +  /* Now, get rid of the unnecessary bits */
3348 +  relocation >>= howto->rightshift;
3349 +  reloc_u = (bfd_vma)relocation;
3350 +
3351 +  switch (howto->complain_on_overflow)
3352 +    {
3353 +    case complain_overflow_unsigned:
3354 +    case complain_overflow_bitfield:
3355 +      if (reloc_u > (unsigned long)((1 << howto->bitsize) - 1))
3356 +       {
3357 +         RDBG("unsigned overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n",
3358 +              sec->owner->filename, sec->name, rela->r_offset,
3359 +              howto->name, reloc_u, howto->bitsize);
3360 +         RDBG("reloc vma: 0x%lx\n",
3361 +              sec->output_section->vma + sec->output_offset + rela->r_offset);
3362 +
3363 +         return bfd_reloc_overflow;
3364 +       }
3365 +      break;
3366 +    case complain_overflow_signed:
3367 +      if (relocation > (1 << (howto->bitsize - 1)) - 1)
3368 +       {
3369 +         RDBG("signed overflow: %s<%s+%lx>: %s: 0x%lx (size %u)\n",
3370 +              sec->owner->filename, sec->name, rela->r_offset,
3371 +              howto->name, reloc_u, howto->bitsize);
3372 +         RDBG("reloc vma: 0x%lx\n",
3373 +              sec->output_section->vma + sec->output_offset + rela->r_offset);
3374 +
3375 +         return bfd_reloc_overflow;
3376 +       }
3377 +      if (relocation < -(1 << (howto->bitsize - 1)))
3378 +       {
3379 +         RDBG("signed overflow: %s<%s+%lx>: %s: -0x%lx (size %u)\n",
3380 +              sec->owner->filename, sec->name, rela->r_offset,
3381 +              howto->name, -relocation, howto->bitsize);
3382 +         RDBG("reloc vma: 0x%lx\n",
3383 +              sec->output_section->vma + sec->output_offset + rela->r_offset);
3384 +
3385 +         return bfd_reloc_overflow;
3386 +       }
3387 +      break;
3388 +    default:
3389 +      abort();
3390 +    }
3391 +
3392 +  return bfd_reloc_ok;
3393 +}
3394 +
3395 +
3396 +static bfd_reloc_status_type
3397 +avr32_final_link_relocate(reloc_howto_type *howto,
3398 +                         bfd *input_bfd,
3399 +                         asection *input_section,
3400 +                         bfd_byte *contents,
3401 +                         Elf_Internal_Rela *rel,
3402 +                         bfd_vma value)
3403 +{
3404 +  bfd_vma field;
3405 +  bfd_vma relocation;
3406 +  bfd_reloc_status_type status;
3407 +  bfd_byte *p = contents + rel->r_offset;
3408 +  unsigned long x;
3409 +
3410 +  pr_debug("  (6b) final link relocate\n");
3411 +
3412 +  /* Sanity check the address */
3413 +  if (rel->r_offset > input_section->size)
3414 +    {
3415 +      (*_bfd_error_handler)
3416 +       ("%B: %A+0x%lx: offset out of range (section size: 0x%lx)",
3417 +        input_bfd, input_section, rel->r_offset, input_section->size);
3418 +      return bfd_reloc_outofrange;
3419 +    }
3420 +
3421 +  relocation = value + rel->r_addend;
3422 +
3423 +  if (howto->pc_relative)
3424 +    {
3425 +      bfd_vma addr;
3426 +
3427 +      addr = input_section->output_section->vma
3428 +       + input_section->output_offset + rel->r_offset;
3429 +      addr &= ~0UL << howto->rightshift;
3430 +      relocation -= addr;
3431 +    }
3432 +
3433 +  switch (ELF32_R_TYPE(rel->r_info))
3434 +    {
3435 +    case R_AVR32_16N_PCREL:
3436 +      /* sub reg, pc, . - (sym + addend) */
3437 +      relocation = -relocation;
3438 +      break;
3439 +    }
3440 +
3441 +  status = avr32_check_reloc_value(input_section, rel, relocation, howto);
3442 +
3443 +  relocation >>= howto->rightshift;
3444 +  if (howto->bitsize == 21)
3445 +    field = (relocation & 0xffff)
3446 +      | ((relocation & 0x10000) << 4)
3447 +      | ((relocation & 0x1e0000) << 8);
3448 +  else if (howto->bitsize == 12)
3449 +    field = (relocation & 0xff) | ((relocation & 0xf00) << 4);
3450 +  else if (howto->bitsize == 10)
3451 +    field = ((relocation & 0xff) << 4)
3452 +      | ((relocation & 0x300) >> 8);
3453 +  else
3454 +    field = relocation << howto->bitpos;
3455 +
3456 +  switch (howto->size)
3457 +    {
3458 +    case 0:
3459 +      x = bfd_get_8 (input_bfd, p);
3460 +      x &= ~howto->dst_mask;
3461 +      x |= field & howto->dst_mask;
3462 +      bfd_put_8 (input_bfd, (bfd_vma) x, p);
3463 +      break;
3464 +    case 1:
3465 +      x = bfd_get_16 (input_bfd, p);
3466 +      x &= ~howto->dst_mask;
3467 +      x |= field & howto->dst_mask;
3468 +      bfd_put_16 (input_bfd, (bfd_vma) x, p);
3469 +      break;
3470 +    case 2:
3471 +      x = bfd_get_32 (input_bfd, p);
3472 +      x &= ~howto->dst_mask;
3473 +      x |= field & howto->dst_mask;
3474 +      bfd_put_32 (input_bfd, (bfd_vma) x, p);
3475 +      break;
3476 +    default:
3477 +      abort();
3478 +    }
3479 +
3480 +  return status;
3481 +}
3482 +
3483 +/* (6) Apply relocations to the normal (non-dynamic) sections */
3484 +
3485 +static bfd_boolean
3486 +avr32_elf_relocate_section(bfd *output_bfd, struct bfd_link_info *info,
3487 +                          bfd *input_bfd, asection *input_section,
3488 +                          bfd_byte *contents, Elf_Internal_Rela *relocs,
3489 +                          Elf_Internal_Sym *local_syms,
3490 +                          asection **local_sections)
3491 +{
3492 +  struct elf_avr32_link_hash_table *htab;
3493 +  Elf_Internal_Shdr *symtab_hdr;
3494 +  Elf_Internal_Rela *rel, *relend;
3495 +  struct elf_link_hash_entry **sym_hashes;
3496 +  struct got_entry **local_got_ents;
3497 +  asection *sgot;
3498 +  asection *srelgot;
3499 +
3500 +  pr_debug("(6) relocate section %s:<%s> (size 0x%lx)\n",
3501 +          input_bfd->filename, input_section->name, input_section->size);
3502 +
3503 +  /* If we're doing a partial link, we don't have to do anything since
3504 +     we're using RELA relocations */
3505 +  if (info->relocatable)
3506 +    return TRUE;
3507 +
3508 +  htab = avr32_elf_hash_table(info);
3509 +  if (htab == NULL)
3510 +    return FALSE;
3511 +
3512 +  symtab_hdr = &elf_tdata(input_bfd)->symtab_hdr;
3513 +  sym_hashes = elf_sym_hashes(input_bfd);
3514 +  local_got_ents = elf_local_got_ents(input_bfd);
3515 +  sgot = htab->sgot;
3516 +  srelgot = htab->srelgot;
3517 +
3518 +  relend = relocs + input_section->reloc_count;
3519 +  for (rel = relocs; rel < relend; rel++)
3520 +    {
3521 +      unsigned long r_type, r_symndx;
3522 +      reloc_howto_type *howto;
3523 +      Elf_Internal_Sym *sym = NULL;
3524 +      struct elf_link_hash_entry *h = NULL;
3525 +      asection *sec = NULL;
3526 +      bfd_vma value;
3527 +      bfd_vma offset;
3528 +      bfd_reloc_status_type status;
3529 +
3530 +      r_type = ELF32_R_TYPE(rel->r_info);
3531 +      r_symndx = ELF32_R_SYM(rel->r_info);
3532 +
3533 +      if (r_type == R_AVR32_NONE
3534 +         || r_type == R_AVR32_ALIGN
3535 +         || r_type == R_AVR32_DIFF32
3536 +         || r_type == R_AVR32_DIFF16
3537 +         || r_type == R_AVR32_DIFF8)
3538 +       continue;
3539 +
3540 +      /* Sanity check */
3541 +      if (r_type > R_AVR32_max)
3542 +       {
3543 +         bfd_set_error(bfd_error_bad_value);
3544 +         return FALSE;
3545 +       }
3546 +
3547 +      howto = &elf_avr32_howto_table[r_type];
3548 +
3549 +      if (r_symndx < symtab_hdr->sh_info)
3550 +       {
3551 +         sym = local_syms + r_symndx;
3552 +         sec = local_sections[r_symndx];
3553 +
3554 +         pr_debug("  (6a) processing %s against local symbol %lu\n",
3555 +                  howto->name, r_symndx);
3556 +
3557 +         /* The following function changes rel->r_addend behind our back. */
3558 +         value = _bfd_elf_rela_local_sym(output_bfd, sym, &sec, rel);
3559 +         pr_debug("    => value: %lx, addend: %lx\n", value, rel->r_addend);
3560 +       }
3561 +      else
3562 +       {
3563 +         if (sym_hashes == NULL)
3564 +           return FALSE;
3565 +
3566 +         h = sym_hashes[r_symndx - symtab_hdr->sh_info];
3567 +         while (h->root.type == bfd_link_hash_indirect
3568 +                || h->root.type == bfd_link_hash_warning)
3569 +           h = (struct elf_link_hash_entry *)h->root.u.i.link;
3570 +
3571 +         pr_debug("  (6a) processing %s against symbol %s\n",
3572 +                  howto->name, h->root.root.string);
3573 +
3574 +         if (h->root.type == bfd_link_hash_defined
3575 +             || h->root.type == bfd_link_hash_defweak)
3576 +           {
3577 +             bfd_boolean dyn;
3578 +
3579 +             dyn = htab->root.dynamic_sections_created;
3580 +             sec = h->root.u.def.section;
3581 +
3582 +             if (sec->output_section)
3583 +               value = (h->root.u.def.value
3584 +                        + sec->output_section->vma
3585 +                        + sec->output_offset);
3586 +             else
3587 +               value = h->root.u.def.value;
3588 +           }
3589 +         else if (h->root.type == bfd_link_hash_undefweak)
3590 +           value = 0;
3591 +         else if (info->unresolved_syms_in_objects == RM_IGNORE
3592 +                  && ELF_ST_VISIBILITY(h->other) == STV_DEFAULT)
3593 +           value = 0;
3594 +         else
3595 +           {
3596 +             bfd_boolean err;
3597 +             err = (info->unresolved_syms_in_objects == RM_GENERATE_ERROR
3598 +                    || ELF_ST_VISIBILITY(h->other) != STV_DEFAULT);
3599 +             if (!info->callbacks->undefined_symbol
3600 +                 (info, h->root.root.string, input_bfd,
3601 +                  input_section, rel->r_offset, err))
3602 +               return FALSE;
3603 +             value = 0;
3604 +           }
3605 +
3606 +         pr_debug("    => value: %lx, addend: %lx\n", value, rel->r_addend);
3607 +       }
3608 +
3609 +      switch (r_type)
3610 +       {
3611 +       case R_AVR32_GOT32:
3612 +       case R_AVR32_GOT16:
3613 +       case R_AVR32_GOT8:
3614 +       case R_AVR32_GOT21S:
3615 +       case R_AVR32_GOT18SW:
3616 +       case R_AVR32_GOT16S:
3617 +       case R_AVR32_GOT7UW:
3618 +       case R_AVR32_LDA_GOT:
3619 +       case R_AVR32_GOTCALL:
3620 +         BFD_ASSERT(sgot != NULL);
3621 +
3622 +         if (h != NULL)
3623 +           {
3624 +             BFD_ASSERT(h->got.glist->refcount > 0);
3625 +             offset = h->got.glist->offset;
3626 +
3627 +             BFD_ASSERT(offset < sgot->size);
3628 +             if (!elf_hash_table(info)->dynamic_sections_created
3629 +                 || (h->def_regular
3630 +                     && (!info->shared
3631 +                         || info->symbolic
3632 +                         || h->dynindx == -1)))
3633 +               {
3634 +                 /* This is actually a static link, or it is a
3635 +                    -Bsymbolic link and the symbol is defined
3636 +                    locally, or the symbol was forced to be local.  */
3637 +                 bfd_put_32(output_bfd, value, sgot->contents + offset);
3638 +               }
3639 +           }
3640 +         else
3641 +           {
3642 +             BFD_ASSERT(local_got_ents &&
3643 +                        local_got_ents[r_symndx]->refcount > 0);
3644 +             offset = local_got_ents[r_symndx]->offset;
3645 +
3646 +             /* Local GOT entries don't have relocs.  If this is a
3647 +                shared library, the dynamic linker will add the load
3648 +                address to the initial value at startup.  */
3649 +             BFD_ASSERT(offset < sgot->size);
3650 +             pr_debug("Initializing GOT entry at offset %lu: 0x%lx\n",
3651 +                      offset, value);
3652 +             bfd_put_32 (output_bfd, value, sgot->contents + offset);
3653 +           }
3654 +
3655 +         value = sgot->output_offset + offset;
3656 +         pr_debug("GOT reference: New value %lx\n", value);
3657 +         break;
3658 +
3659 +       case R_AVR32_GOTPC:
3660 +         /* This relocation type is for constant pool entries used in
3661 +            the calculation "Rd = PC - (PC - GOT)", where the
3662 +            constant pool supplies the constant (PC - GOT)
3663 +            offset. The symbol value + addend indicates where the
3664 +            value of PC is taken. */
3665 +         value -= sgot->output_section->vma;
3666 +         break;
3667 +
3668 +       case R_AVR32_32_PCREL:
3669 +         /* We must adjust r_offset to account for discarded data in
3670 +            the .eh_frame section.  This is probably not the right
3671 +            way to do this, since AFAICS all other architectures do
3672 +            it some other way.  I just can't figure out how...  */
3673 +         {
3674 +           bfd_vma r_offset;
3675 +
3676 +           r_offset = _bfd_elf_section_offset(output_bfd, info,
3677 +                                              input_section,
3678 +                                              rel->r_offset);
3679 +           if (r_offset == (bfd_vma)-1
3680 +               || r_offset == (bfd_vma)-2)
3681 +             continue;
3682 +           rel->r_offset = r_offset;
3683 +         }
3684 +         break;
3685 +
3686 +       case R_AVR32_32:
3687 +         /* We need to emit a run-time relocation in the following cases:
3688 +              - we're creating a shared library
3689 +              - the symbol is not defined in any regular objects
3690 +
3691 +            Of course, sections that aren't going to be part of the
3692 +            run-time image will not get any relocs, and undefined
3693 +            symbols won't have any either (only weak undefined
3694 +            symbols should get this far).  */
3695 +         if ((info->shared
3696 +              || (elf_hash_table(info)->dynamic_sections_created
3697 +                  && h != NULL
3698 +                  && h->def_dynamic
3699 +                  && !h->def_regular))
3700 +             && r_symndx != 0
3701 +             && (input_section->flags & SEC_ALLOC))
3702 +           {
3703 +             Elf_Internal_Rela outrel;
3704 +             bfd_byte *loc;
3705 +             bfd_boolean skip, relocate;
3706 +             struct elf_avr32_link_hash_entry *avrh;
3707 +
3708 +             pr_debug("Going to generate dynamic reloc...\n");
3709 +
3710 +             skip = FALSE;
3711 +             relocate = FALSE;
3712 +
3713 +             outrel.r_offset = _bfd_elf_section_offset(output_bfd, info,
3714 +                                                       input_section,
3715 +                                                       rel->r_offset);
3716 +             if (outrel.r_offset == (bfd_vma)-1)
3717 +               skip = TRUE;
3718 +             else if (outrel.r_offset == (bfd_vma)-2)
3719 +               skip = TRUE, relocate = TRUE;
3720 +
3721 +             outrel.r_offset += (input_section->output_section->vma
3722 +                                 + input_section->output_offset);
3723 +
3724 +             pr_debug("    ... offset %lx, dynindx %ld\n",
3725 +                      outrel.r_offset, h ? h->dynindx : -1);
3726 +
3727 +             if (skip)
3728 +               memset(&outrel, 0, sizeof(outrel));
3729 +             else
3730 +               {
3731 +                 avrh = (struct elf_avr32_link_hash_entry *)h;
3732 +                 /* h->dynindx may be -1 if this symbol was marked to
3733 +                    become local.  */
3734 +                 if (h == NULL
3735 +                     || ((info->symbolic || h->dynindx == -1)
3736 +                         && h->def_regular))
3737 +                   {
3738 +                     relocate = TRUE;
3739 +                     outrel.r_info = ELF32_R_INFO(0, R_AVR32_RELATIVE);
3740 +                     outrel.r_addend = value + rel->r_addend;
3741 +                     pr_debug("    ... R_AVR32_RELATIVE\n");
3742 +                   }
3743 +                 else
3744 +                   {
3745 +                     BFD_ASSERT(h->dynindx != -1);
3746 +                     relocate = TRUE;
3747 +                     outrel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT);
3748 +                     outrel.r_addend = rel->r_addend;
3749 +                     pr_debug("    ... R_AVR32_GLOB_DAT\n");
3750 +                   }
3751 +               }
3752 +
3753 +             pr_debug("srelgot reloc_count: %d, size %lu\n",
3754 +                      srelgot->reloc_count, srelgot->size);
3755 +
3756 +             loc = srelgot->contents;
3757 +             loc += srelgot->reloc_count++ * sizeof(Elf32_External_Rela);
3758 +             bfd_elf32_swap_reloca_out(output_bfd, &outrel, loc);
3759 +
3760 +             BFD_ASSERT(srelgot->reloc_count * sizeof(Elf32_External_Rela)
3761 +                        <= srelgot->size);
3762 +
3763 +             if (!relocate)
3764 +               continue;
3765 +           }
3766 +         break;
3767 +       }
3768 +
3769 +      status = avr32_final_link_relocate(howto, input_bfd, input_section,
3770 +                                        contents, rel, value);
3771 +
3772 +      switch (status)
3773 +       {
3774 +       case bfd_reloc_ok:
3775 +         break;
3776 +
3777 +       case bfd_reloc_overflow:
3778 +         {
3779 +           const char *name;
3780 +
3781 +           if (h != NULL)
3782 +             name = h->root.root.string;
3783 +           else
3784 +             {
3785 +               name = bfd_elf_string_from_elf_section(input_bfd,
3786 +                                                      symtab_hdr->sh_link,
3787 +                                                      sym->st_name);
3788 +               if (name == NULL)
3789 +                 return FALSE;
3790 +               if (*name == '\0')
3791 +                 name = bfd_section_name(input_bfd, sec);
3792 +             }
3793 +           if (!((*info->callbacks->reloc_overflow)
3794 +                 (info, (h ? &h->root : NULL), name, howto->name,
3795 +                  rel->r_addend, input_bfd, input_section, rel->r_offset)))
3796 +             return FALSE;
3797 +         }
3798 +         break;
3799 +
3800 +       case bfd_reloc_outofrange:
3801 +       default:
3802 +         abort();
3803 +       }
3804 +    }
3805 +
3806 +  return TRUE;
3807 +}
3808 +
3809 +
3810 +/* Additional processing of dynamic sections after relocation */
3811 +
3812 +static bfd_boolean
3813 +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info,
3814 +                               struct elf_link_hash_entry *h,
3815 +                               Elf_Internal_Sym *sym);
3816 +static bfd_boolean
3817 +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info);
3818 +
3819 +
3820 +/* (7) Initialize the contents of a dynamic symbol and/or emit
3821 +   relocations for it */
3822 +
3823 +static bfd_boolean
3824 +avr32_elf_finish_dynamic_symbol(bfd *output_bfd, struct bfd_link_info *info,
3825 +                               struct elf_link_hash_entry *h,
3826 +                               Elf_Internal_Sym *sym)
3827 +{
3828 +  struct elf_avr32_link_hash_table *htab;
3829 +  struct got_entry *got;
3830 +
3831 +  pr_debug("(7) finish dynamic symbol: %s\n", h->root.root.string);
3832 +
3833 +  htab = avr32_elf_hash_table(info);
3834 +  if (htab == NULL)
3835 +    return FALSE;
3836 +
3837 +  got = h->got.glist;
3838 +
3839 +  if (got && got->refcount > 0)
3840 +    {
3841 +      asection *sgot;
3842 +      asection *srelgot;
3843 +      Elf_Internal_Rela rel;
3844 +      bfd_byte *loc;
3845 +
3846 +      /* This symbol has an entry in the GOT. Set it up. */
3847 +      sgot = htab->sgot;
3848 +      srelgot = htab->srelgot;
3849 +      BFD_ASSERT(sgot && srelgot);
3850 +
3851 +      rel.r_offset = (sgot->output_section->vma
3852 +                     + sgot->output_offset
3853 +                     + got->offset);
3854 +
3855 +      /* If this is a static link, or it is a -Bsymbolic link and the
3856 +        symbol is defined locally or was forced to be local because
3857 +        of a version file, we just want to emit a RELATIVE reloc. The
3858 +        entry in the global offset table will already have been
3859 +        initialized in the relocate_section function. */
3860 +      if ((info->shared
3861 +          && !info->symbolic
3862 +          && h->dynindx != -1)
3863 +         || (htab->root.dynamic_sections_created
3864 +             && h->def_dynamic
3865 +             && !h->def_regular))
3866 +       {
3867 +         bfd_put_32(output_bfd, 0, sgot->contents + got->offset);
3868 +         rel.r_info = ELF32_R_INFO(h->dynindx, R_AVR32_GLOB_DAT);
3869 +         rel.r_addend = 0;
3870 +
3871 +         pr_debug("GOT reloc R_AVR32_GLOB_DAT, dynindx: %ld\n", h->dynindx);
3872 +         pr_debug("    srelgot reloc_count: %d, size: %lu\n",
3873 +                  srelgot->reloc_count, srelgot->size);
3874 +
3875 +         loc = (srelgot->contents
3876 +                + srelgot->reloc_count++ * sizeof(Elf32_External_Rela));
3877 +         bfd_elf32_swap_reloca_out(output_bfd, &rel, loc);
3878 +
3879 +         BFD_ASSERT(srelgot->reloc_count * sizeof(Elf32_External_Rela)
3880 +                    <= srelgot->size);
3881 +       }
3882 +    }
3883 +
3884 +  /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute */
3885 +  if (strcmp(h->root.root.string, "_DYNAMIC") == 0
3886 +      || strcmp(h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0)
3887 +    sym->st_shndx = SHN_ABS;
3888 +
3889 +  return TRUE;
3890 +}
3891 +
3892 +/* (8) Do any remaining initialization of the dynamic sections */
3893 +
3894 +static bfd_boolean
3895 +avr32_elf_finish_dynamic_sections(bfd *output_bfd, struct bfd_link_info *info)
3896 +{
3897 +  struct elf_avr32_link_hash_table *htab;
3898 +  asection *sgot, *sdyn;
3899 +
3900 +  pr_debug("(8) finish dynamic sections\n");
3901 +
3902 +  htab = avr32_elf_hash_table(info);
3903 +  if (htab == NULL)
3904 +    return FALSE;
3905 +
3906 +  sgot = htab->sgot;
3907 +  sdyn = bfd_get_section_by_name(htab->root.dynobj, ".dynamic");
3908 +
3909 +  if (htab->root.dynamic_sections_created)
3910 +    {
3911 +      Elf32_External_Dyn *dyncon, *dynconend;
3912 +
3913 +      BFD_ASSERT(sdyn && sgot && sgot->size >= AVR32_GOT_HEADER_SIZE);
3914 +
3915 +      dyncon = (Elf32_External_Dyn *)sdyn->contents;
3916 +      dynconend = (Elf32_External_Dyn *)(sdyn->contents + sdyn->size);
3917 +      for (; dyncon < dynconend; dyncon++)
3918 +       {
3919 +         Elf_Internal_Dyn dyn;
3920 +         asection *s;
3921 +
3922 +         bfd_elf32_swap_dyn_in(htab->root.dynobj, dyncon, &dyn);
3923 +
3924 +         switch (dyn.d_tag)
3925 +           {
3926 +           default:
3927 +             break;
3928 +
3929 +           case DT_PLTGOT:
3930 +             s = sgot->output_section;
3931 +             BFD_ASSERT(s != NULL);
3932 +             dyn.d_un.d_ptr = s->vma;
3933 +             bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon);
3934 +             break;
3935 +
3936 +           case DT_AVR32_GOTSZ:
3937 +             s = sgot->output_section;
3938 +             BFD_ASSERT(s != NULL);
3939 +             dyn.d_un.d_val = s->size;
3940 +             bfd_elf32_swap_dyn_out(output_bfd, &dyn, dyncon);
3941 +             break;
3942 +           }
3943 +       }
3944 +
3945 +      /* Fill in the first two entries in the global offset table */
3946 +      bfd_put_32(output_bfd,
3947 +                sdyn->output_section->vma + sdyn->output_offset,
3948 +                sgot->contents);
3949 +
3950 +      /* The runtime linker will fill this one in with the address of
3951 +        the run-time link map */
3952 +      bfd_put_32(output_bfd, 0, sgot->contents + 4);
3953 +    }
3954 +
3955 +  if (sgot)
3956 +    elf_section_data(sgot->output_section)->this_hdr.sh_entsize = 4;
3957 +
3958 +  return TRUE;
3959 +}
3960 +
3961 +
3962 +/* AVR32-specific private ELF data */
3963 +
3964 +static bfd_boolean
3965 +avr32_elf_set_private_flags(bfd *abfd, flagword flags);
3966 +static bfd_boolean
3967 +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd);
3968 +static bfd_boolean
3969 +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd);
3970 +static bfd_boolean
3971 +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr);
3972 +
3973 +static bfd_boolean
3974 +avr32_elf_set_private_flags(bfd *abfd, flagword flags)
3975 +{
3976 +  elf_elfheader(abfd)->e_flags = flags;
3977 +  elf_flags_init(abfd) = TRUE;
3978 +
3979 +  return TRUE;
3980 +}
3981 +
3982 +/* Copy backend specific data from one object module to another.  */
3983 +
3984 +static bfd_boolean
3985 +avr32_elf_copy_private_bfd_data(bfd *ibfd, bfd *obfd)
3986 +{
3987 +  elf_elfheader(obfd)->e_flags = elf_elfheader(ibfd)->e_flags;
3988 +  return TRUE;
3989 +}
3990 +
3991 +/* Merge backend specific data from an object file to the output
3992 +   object file when linking.  */
3993 +
3994 +static bfd_boolean
3995 +avr32_elf_merge_private_bfd_data(bfd *ibfd, bfd *obfd)
3996 +{
3997 +  flagword out_flags, in_flags;
3998 +
3999 +  pr_debug("(0) merge_private_bfd_data: %s -> %s\n",
4000 +          ibfd->filename, obfd->filename);
4001 +
4002 +  in_flags = elf_elfheader(ibfd)->e_flags;
4003 +  out_flags = elf_elfheader(obfd)->e_flags;
4004 +
4005 +  if (elf_flags_init(obfd))
4006 +    {
4007 +      /* If one of the inputs are non-PIC, the output must be
4008 +        considered non-PIC.  The same applies to linkrelax.  */
4009 +      if (!(in_flags & EF_AVR32_PIC))
4010 +       out_flags &= ~EF_AVR32_PIC;
4011 +      if (!(in_flags & EF_AVR32_LINKRELAX))
4012 +       out_flags &= ~EF_AVR32_LINKRELAX;
4013 +    }
4014 +  else
4015 +    {
4016 +      elf_flags_init(obfd) = TRUE;
4017 +      out_flags = in_flags;
4018 +    }
4019 +
4020 +  elf_elfheader(obfd)->e_flags = out_flags;
4021 +
4022 +  return TRUE;
4023 +}
4024 +
4025 +static bfd_boolean
4026 +avr32_elf_print_private_bfd_data(bfd *abfd, void *ptr)
4027 +{
4028 +  FILE *file = (FILE *)ptr;
4029 +  unsigned long flags;
4030 +
4031 +  BFD_ASSERT(abfd != NULL && ptr != NULL);
4032 +
4033 +  _bfd_elf_print_private_bfd_data(abfd, ptr);
4034 +
4035 +  flags = elf_elfheader(abfd)->e_flags;
4036 +
4037 +  fprintf(file, _("private flags = %lx:"), elf_elfheader(abfd)->e_flags);
4038 +
4039 +  if (flags & EF_AVR32_PIC)
4040 +    fprintf(file, " [PIC]");
4041 +  if (flags & EF_AVR32_LINKRELAX)
4042 +    fprintf(file, " [linker relaxable]");
4043 +
4044 +  flags &= ~(EF_AVR32_PIC | EF_AVR32_LINKRELAX);
4045 +
4046 +  if (flags)
4047 +    fprintf(file, _("<Unrecognized flag bits set>"));
4048 +
4049 +  fputc('\n', file);
4050 +
4051 +  return TRUE;
4052 +}
4053 +
4054 +/* Set avr32-specific linker options.  */
4055 +void bfd_elf32_avr32_set_options(struct bfd_link_info *info,
4056 +                                int direct_data_refs)
4057 +{
4058 +  struct elf_avr32_link_hash_table *htab;
4059 +
4060 +  htab = avr32_elf_hash_table (info);
4061 +  htab->direct_data_refs = !!direct_data_refs;
4062 +}
4063 +
4064 +
4065 +
4066 +/* Understanding core dumps */
4067 +
4068 +static bfd_boolean
4069 +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note);
4070 +static bfd_boolean
4071 +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note);
4072 +
4073 +static bfd_boolean
4074 +avr32_elf_grok_prstatus(bfd *abfd, Elf_Internal_Note *note)
4075 +{
4076 +  /* Linux/AVR32B elf_prstatus */
4077 +  if (note->descsz != 148)
4078 +    return FALSE;
4079 +
4080 +  /* pr_cursig */
4081 +  elf_tdata(abfd)->core_signal = bfd_get_16(abfd, note->descdata + 12);
4082 +
4083 +  /* pr_pid */
4084 +  elf_tdata(abfd)->core_pid = bfd_get_32(abfd, note->descdata + 24);
4085 +
4086 +  /* Make a ".reg/999" section for pr_reg. The size is for 16
4087 +     general-purpose registers, SR and r12_orig (18 * 4 = 72).  */
4088 +  return _bfd_elfcore_make_pseudosection(abfd, ".reg", 72,
4089 +                                        note->descpos + 72);
4090 +}
4091 +
4092 +static bfd_boolean
4093 +avr32_elf_grok_psinfo(bfd *abfd, Elf_Internal_Note *note)
4094 +{
4095 +  /* Linux/AVR32B elf_prpsinfo */
4096 +  if (note->descsz != 128)
4097 +    return FALSE;
4098 +
4099 +  elf_tdata(abfd)->core_program
4100 +    = _bfd_elfcore_strndup(abfd, note->descdata + 32, 16);
4101 +  elf_tdata(abfd)->core_command
4102 +    = _bfd_elfcore_strndup(abfd, note->descdata + 48, 80);
4103 +
4104 +  /* Note that for some reason, a spurious space is tacked
4105 +     onto the end of the args in some (at least one anyway)
4106 +     implementations, so strip it off if it exists.  */
4107 +
4108 +  {
4109 +    char *command = elf_tdata (abfd)->core_command;
4110 +    int n = strlen (command);
4111 +
4112 +    if (0 < n && command[n - 1] == ' ')
4113 +      command[n - 1] = '\0';
4114 +  }
4115 +
4116 +  return TRUE;
4117 +}
4118 +
4119 +
4120 +#define ELF_ARCH                       bfd_arch_avr32
4121 +#define ELF_MACHINE_CODE               EM_AVR32
4122 +#define ELF_MAXPAGESIZE                        1024
4123 +
4124 +#define TARGET_BIG_SYM                 bfd_elf32_avr32_vec
4125 +#define TARGET_BIG_NAME                        "elf32-avr32"
4126 +
4127 +#define elf_backend_grok_prstatus      avr32_elf_grok_prstatus
4128 +#define elf_backend_grok_psinfo                avr32_elf_grok_psinfo
4129 +
4130 +/* Only RELA relocations are used */
4131 +#define elf_backend_may_use_rel_p      0
4132 +#define elf_backend_may_use_rela_p     1
4133 +#define elf_backend_default_use_rela_p 1
4134 +#define elf_backend_rela_normal                1
4135 +#define elf_info_to_howto_rel          NULL
4136 +#define elf_info_to_howto              avr32_info_to_howto
4137 +
4138 +#define bfd_elf32_bfd_copy_private_bfd_data    avr32_elf_copy_private_bfd_data
4139 +#define bfd_elf32_bfd_merge_private_bfd_data   avr32_elf_merge_private_bfd_data
4140 +#define bfd_elf32_bfd_set_private_flags                avr32_elf_set_private_flags
4141 +#define bfd_elf32_bfd_print_private_bfd_data   avr32_elf_print_private_bfd_data
4142 +#define bfd_elf32_new_section_hook             avr32_elf_new_section_hook
4143 +
4144 +#define elf_backend_gc_mark_hook               avr32_elf_gc_mark_hook
4145 +#define elf_backend_gc_sweep_hook              avr32_elf_gc_sweep_hook
4146 +#define elf_backend_relocate_section   avr32_elf_relocate_section
4147 +#define elf_backend_copy_indirect_symbol avr32_elf_copy_indirect_symbol
4148 +#define elf_backend_create_dynamic_sections avr32_elf_create_dynamic_sections
4149 +#define bfd_elf32_bfd_link_hash_table_create avr32_elf_link_hash_table_create
4150 +#define elf_backend_adjust_dynamic_symbol avr32_elf_adjust_dynamic_symbol
4151 +#define elf_backend_size_dynamic_sections avr32_elf_size_dynamic_sections
4152 +#define elf_backend_finish_dynamic_symbol avr32_elf_finish_dynamic_symbol
4153 +#define elf_backend_finish_dynamic_sections avr32_elf_finish_dynamic_sections
4154 +
4155 +#define bfd_elf32_bfd_relax_section    avr32_elf_relax_section
4156 +
4157 +/* Find out which symbols need an entry in .got. */
4158 +#define elf_backend_check_relocs       avr32_check_relocs
4159 +#define elf_backend_can_refcount       1
4160 +#define elf_backend_can_gc_sections    1
4161 +#define elf_backend_plt_readonly       1
4162 +#define elf_backend_plt_not_loaded     1
4163 +#define elf_backend_want_plt_sym       0
4164 +#define elf_backend_plt_alignment      2
4165 +#define elf_backend_want_dynbss                0
4166 +#define elf_backend_want_got_plt       0
4167 +#define elf_backend_want_got_sym       1
4168 +#define elf_backend_got_header_size    AVR32_GOT_HEADER_SIZE
4169 +
4170 +#include "elf32-target.h"
4171 --- /dev/null
4172 +++ b/bfd/elf32-avr32.h
4173 @@ -0,0 +1,23 @@
4174 +/* AVR32-specific support for 32-bit ELF.
4175 +   Copyright 2007,2008,2009 Atmel Corporation.
4176 +
4177 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
4178 +
4179 +   This file is part of BFD, the Binary File Descriptor library.
4180 +
4181 +   This program is free software; you can redistribute it and/or modify
4182 +   it under the terms of the GNU General Public License as published by
4183 +   the Free Software Foundation; either version 2 of the License, or
4184 +   (at your option) any later version.
4185 +
4186 +   This program is distributed in the hope that it will be useful,
4187 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
4188 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4189 +   GNU General Public License for more details.
4190 +
4191 +   You should have received a copy of the GNU General Public License
4192 +   along with this program; if not, write to the Free Software
4193 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
4194 +
4195 +void bfd_elf32_avr32_set_options(struct bfd_link_info *info,
4196 +                                int direct_data_refs);
4197 --- a/bfd/elf-bfd.h
4198 +++ b/bfd/elf-bfd.h
4199 @@ -402,6 +402,7 @@ enum elf_target_id
4200    ALPHA_ELF_DATA = 1,
4201    ARM_ELF_DATA,
4202    AVR_ELF_DATA,
4203 +  AVR32_ELF_DATA,
4204    BFIN_ELF_DATA,
4205    CRIS_ELF_DATA,
4206    FRV_ELF_DATA,
4207 @@ -1549,6 +1550,10 @@ struct elf_obj_tdata
4208       find_nearest_line.  */
4209    struct mips_elf_find_line *find_line_info;
4210
4211 +  /* Used by AVR32 ELF relaxation code.  Contains an array of pointers
4212 +     for each local symbol to the fragment where it is defined.  */
4213 +  struct fragment **local_sym_frag;
4214 +
4215    /* A place to stash dwarf1 info for this bfd.  */
4216    struct dwarf1_debug *dwarf1_find_line_info;
4217
4218 --- a/bfd/libbfd.h
4219 +++ b/bfd/libbfd.h
4220 @@ -1783,6 +1783,48 @@ static const char *const bfd_reloc_code_
4221    "BFD_RELOC_AVR_LDI",
4222    "BFD_RELOC_AVR_6",
4223    "BFD_RELOC_AVR_6_ADIW",
4224 +  "BFD_RELOC_AVR32_DIFF32",
4225 +  "BFD_RELOC_AVR32_DIFF16",
4226 +  "BFD_RELOC_AVR32_DIFF8",
4227 +  "BFD_RELOC_AVR32_GOT32",
4228 +  "BFD_RELOC_AVR32_GOT16",
4229 +  "BFD_RELOC_AVR32_GOT8",
4230 +  "BFD_RELOC_AVR32_21S",
4231 +  "BFD_RELOC_AVR32_16U",
4232 +  "BFD_RELOC_AVR32_16S",
4233 +  "BFD_RELOC_AVR32_SUB5",
4234 +  "BFD_RELOC_AVR32_8S_EXT",
4235 +  "BFD_RELOC_AVR32_8S",
4236 +  "BFD_RELOC_AVR32_15S",
4237 +  "BFD_RELOC_AVR32_22H_PCREL",
4238 +  "BFD_RELOC_AVR32_18W_PCREL",
4239 +  "BFD_RELOC_AVR32_16B_PCREL",
4240 +  "BFD_RELOC_AVR32_16N_PCREL",
4241 +  "BFD_RELOC_AVR32_14UW_PCREL",
4242 +  "BFD_RELOC_AVR32_11H_PCREL",
4243 +  "BFD_RELOC_AVR32_10UW_PCREL",
4244 +  "BFD_RELOC_AVR32_9H_PCREL",
4245 +  "BFD_RELOC_AVR32_9UW_PCREL",
4246 +  "BFD_RELOC_AVR32_GOTPC",
4247 +  "BFD_RELOC_AVR32_GOTCALL",
4248 +  "BFD_RELOC_AVR32_LDA_GOT",
4249 +  "BFD_RELOC_AVR32_GOT21S",
4250 +  "BFD_RELOC_AVR32_GOT18SW",
4251 +  "BFD_RELOC_AVR32_GOT16S",
4252 +  "BFD_RELOC_AVR32_32_CPENT",
4253 +  "BFD_RELOC_AVR32_CPCALL",
4254 +  "BFD_RELOC_AVR32_16_CP",
4255 +  "BFD_RELOC_AVR32_9W_CP",
4256 +  "BFD_RELOC_AVR32_ALIGN",
4257 +  "BFD_RELOC_AVR32_14UW",
4258 +  "BFD_RELOC_AVR32_10UW",
4259 +  "BFD_RELOC_AVR32_10SW",
4260 +  "BFD_RELOC_AVR32_STHH_W",
4261 +  "BFD_RELOC_AVR32_7UW",
4262 +  "BFD_RELOC_AVR32_6S",
4263 +  "BFD_RELOC_AVR32_6UW",
4264 +  "BFD_RELOC_AVR32_4UH",
4265 +  "BFD_RELOC_AVR32_3U",
4266    "BFD_RELOC_RX_NEG8",
4267    "BFD_RELOC_RX_NEG16",
4268    "BFD_RELOC_RX_NEG24",
4269 --- a/bfd/Makefile.am
4270 +++ b/bfd/Makefile.am
4271 @@ -75,6 +75,7 @@ ALL_MACHINES = \
4272         cpu-arc.lo \
4273         cpu-arm.lo \
4274         cpu-avr.lo \
4275 +       cpu-avr32.lo \
4276         cpu-bfin.lo \
4277         cpu-cr16.lo \
4278         cpu-cr16c.lo \
4279 @@ -272,6 +273,7 @@ BFD32_BACKENDS = \
4280         elf32-arc.lo \
4281         elf32-arm.lo \
4282         elf32-avr.lo \
4283 +       elf32-avr32.lo \
4284         elf32-bfin.lo \
4285         elf32-cr16.lo \
4286         elf32-cr16c.lo \
4287 --- a/bfd/reloc.c
4288 +++ b/bfd/reloc.c
4289 @@ -4275,6 +4275,131 @@ ENUMDOC
4290    Renesas RX Relocations.
4291
4292  ENUM
4293 +  BFD_RELOC_AVR32_DIFF32
4294 +ENUMX
4295 +  BFD_RELOC_AVR32_DIFF16
4296 +ENUMX
4297 +  BFD_RELOC_AVR32_DIFF8
4298 +ENUMDOC
4299 +  Difference between two labels: L2 - L1. The value of L1 is encoded
4300 +  as sym + addend, while the initial difference after assembly is
4301 +  inserted into the object file by the assembler.
4302 +ENUM
4303 +  BFD_RELOC_AVR32_GOT32
4304 +ENUMX
4305 +  BFD_RELOC_AVR32_GOT16
4306 +ENUMX
4307 +  BFD_RELOC_AVR32_GOT8
4308 +ENUMDOC
4309 +  Reference to a symbol through the Global Offset Table. The linker
4310 +  will allocate an entry for symbol in the GOT and insert the offset
4311 +  of this entry as the relocation value.
4312 +ENUM
4313 +  BFD_RELOC_AVR32_21S
4314 +ENUMX
4315 +  BFD_RELOC_AVR32_16U
4316 +ENUMX
4317 +  BFD_RELOC_AVR32_16S
4318 +ENUMX
4319 +  BFD_RELOC_AVR32_SUB5
4320 +ENUMX
4321 +  BFD_RELOC_AVR32_8S_EXT
4322 +ENUMX
4323 +  BFD_RELOC_AVR32_8S
4324 +ENUMX
4325 +  BFD_RELOC_AVR32_15S
4326 +ENUMDOC
4327 +  Normal (non-pc-relative) code relocations. Alignment and signedness
4328 +  is indicated by the suffixes. S means signed, U means unsigned. W
4329 +  means word-aligned, H means halfword-aligned, neither means
4330 +  byte-aligned (no alignment.) SUB5 is the same relocation as 16S.
4331 +ENUM
4332 +  BFD_RELOC_AVR32_22H_PCREL
4333 +ENUMX
4334 +  BFD_RELOC_AVR32_18W_PCREL
4335 +ENUMX
4336 +  BFD_RELOC_AVR32_16B_PCREL
4337 +ENUMX
4338 +  BFD_RELOC_AVR32_16N_PCREL
4339 +ENUMX
4340 +  BFD_RELOC_AVR32_14UW_PCREL
4341 +ENUMX
4342 +  BFD_RELOC_AVR32_11H_PCREL
4343 +ENUMX
4344 +  BFD_RELOC_AVR32_10UW_PCREL
4345 +ENUMX
4346 +  BFD_RELOC_AVR32_9H_PCREL
4347 +ENUMX
4348 +  BFD_RELOC_AVR32_9UW_PCREL
4349 +ENUMDOC
4350 +  PC-relative relocations are signed if neither 'U' nor 'S' is
4351 +  specified. However, we explicitly tack on a 'B' to indicate no
4352 +  alignment, to avoid confusion with data relocs. All of these resolve
4353 +  to sym + addend - offset, except the one with 'N' (negated) suffix.
4354 +  This particular one resolves to offset - sym - addend.
4355 +ENUM
4356 +  BFD_RELOC_AVR32_GOTPC
4357 +ENUMDOC
4358 +  Subtract the link-time address of the GOT from (symbol + addend)
4359 +  and insert the result.
4360 +ENUM
4361 +  BFD_RELOC_AVR32_GOTCALL
4362 +ENUMX
4363 +  BFD_RELOC_AVR32_LDA_GOT
4364 +ENUMX
4365 +  BFD_RELOC_AVR32_GOT21S
4366 +ENUMX
4367 +  BFD_RELOC_AVR32_GOT18SW
4368 +ENUMX
4369 +  BFD_RELOC_AVR32_GOT16S
4370 +ENUMDOC
4371 +  Reference to a symbol through the GOT. The linker will allocate an
4372 +  entry for symbol in the GOT and insert the offset of this entry as
4373 +  the relocation value. addend must be zero. As usual, 'S' means
4374 +  signed, 'W' means word-aligned, etc.
4375 +ENUM
4376 +  BFD_RELOC_AVR32_32_CPENT
4377 +ENUMDOC
4378 +  32-bit constant pool entry. I don't think 8- and 16-bit entries make
4379 +  a whole lot of sense.
4380 +ENUM
4381 +  BFD_RELOC_AVR32_CPCALL
4382 +ENUMX
4383 +  BFD_RELOC_AVR32_16_CP
4384 +ENUMX
4385 +  BFD_RELOC_AVR32_9W_CP
4386 +ENUMDOC
4387 +  Constant pool references. Some of these relocations are signed,
4388 +  others are unsigned. It doesn't really matter, since the constant
4389 +  pool always comes after the code that references it.
4390 +ENUM
4391 +  BFD_RELOC_AVR32_ALIGN
4392 +ENUMDOC
4393 +  sym must be the absolute symbol. The addend specifies the alignment
4394 +  order, e.g. if addend is 2, the linker must add padding so that the
4395 +  next address is aligned to a 4-byte boundary.
4396 +ENUM
4397 +  BFD_RELOC_AVR32_14UW
4398 +ENUMX
4399 +  BFD_RELOC_AVR32_10UW
4400 +ENUMX
4401 +  BFD_RELOC_AVR32_10SW
4402 +ENUMX
4403 +  BFD_RELOC_AVR32_STHH_W
4404 +ENUMX
4405 +  BFD_RELOC_AVR32_7UW
4406 +ENUMX
4407 +  BFD_RELOC_AVR32_6S
4408 +ENUMX
4409 +  BFD_RELOC_AVR32_6UW
4410 +ENUMX
4411 +  BFD_RELOC_AVR32_4UH
4412 +ENUMX
4413 +  BFD_RELOC_AVR32_3U
4414 +ENUMDOC
4415 +  Code relocations that will never make it to the output file.
4416 +
4417 +ENUM
4418    BFD_RELOC_390_12
4419  ENUMDOC
4420     Direct 12 bit.
4421 --- a/bfd/targets.c
4422 +++ b/bfd/targets.c
4423 @@ -579,6 +579,7 @@ extern const bfd_target b_out_vec_big_ho
4424  extern const bfd_target b_out_vec_little_host;
4425  extern const bfd_target bfd_pei_ia64_vec;
4426  extern const bfd_target bfd_elf32_avr_vec;
4427 +extern const bfd_target bfd_elf32_avr32_vec;
4428  extern const bfd_target bfd_elf32_bfin_vec;
4429  extern const bfd_target bfd_elf32_bfinfdpic_vec;
4430  extern const bfd_target bfd_elf32_big_generic_vec;
4431 @@ -917,6 +918,7 @@ static const bfd_target * const _bfd_tar
4432         &bfd_pei_ia64_vec,
4433  #endif
4434         &bfd_elf32_avr_vec,
4435 +       &bfd_elf32_avr32_vec,
4436         &bfd_elf32_bfin_vec,
4437         &bfd_elf32_bfinfdpic_vec,
4438
4439 --- a/binutils/doc/binutils.info
4440 +++ b/binutils/doc/binutils.info
4441 @@ -1707,6 +1707,10 @@ equivalent.  At least one option from th
4442       useful when attempting to disassemble thumb code produced by other
4443       compilers.
4444
4445 +     For the AVR32 architectures that support Floating point unit (FPU),
4446 +     specifying '-M decode-fpu' will enable disassembler to print the
4447 +     floating point instruction instead of 'cop' instructions.
4448 +
4449       For the x86, some of the options duplicate functions of the `-m'
4450       switch, but allow finer grained control.  Multiple selections from
4451       the following may be specified as a comma separated string.
4452 --- a/binutils/doc/binutils.texi
4453 +++ b/binutils/doc/binutils.texi
4454 @@ -1982,6 +1982,10 @@ using the switch @option{--disassembler-
4455  useful when attempting to disassemble thumb code produced by other
4456  compilers.
4457
4458 +For the AVR32 architectures that support Floating point unit (FPU),
4459 +specifying @option{-M decode-fpu} will enable disassembler to print the
4460 +floating point instructions instead of 'cop' instructions.
4461 +
4462  For the x86, some of the options duplicate functions of the @option{-m}
4463  switch, but allow finer grained control.  Multiple selections from the
4464  following may be specified as a comma separated string.
4465 --- a/binutils/doc/objdump.1
4466 +++ b/binutils/doc/objdump.1
4467 @@ -425,6 +425,10 @@ using the switch \fB\-\-disassembler\-op
4468  useful when attempting to disassemble thumb code produced by other
4469  compilers.
4470  .Sp
4471 +For the \s-1AVR32\s0 architectures that support Floating point unit (FPU),
4472 +specifying \fB\-M decode\-fpu\fR will enable disassembler to print the
4473 +floating point instructions instead of 'cop' instructions.
4474 +.Sp
4475  For the x86, some of the options duplicate functions of the \fB\-m\fR
4476  switch, but allow finer grained control.  Multiple selections from the
4477  following may be specified as a comma separated string.
4478 --- a/binutils/readelf.c
4479 +++ b/binutils/readelf.c
4480 @@ -96,6 +96,7 @@
4481  #include "elf/arc.h"
4482  #include "elf/arm.h"
4483  #include "elf/avr.h"
4484 +#include "elf/avr32.h"
4485  #include "elf/bfin.h"
4486  #include "elf/cr16.h"
4487  #include "elf/cris.h"
4488 @@ -544,6 +545,7 @@ guess_is_rela (unsigned int e_machine)
4489      case EM_ALPHA:
4490      case EM_ALTERA_NIOS2:
4491      case EM_AVR:
4492 +    case EM_AVR32:
4493      case EM_AVR_OLD:
4494      case EM_BLACKFIN:
4495      case EM_CR16:
4496 @@ -997,6 +999,10 @@ dump_relocations (FILE * file,
4497           rtype = elf_avr_reloc_type (type);
4498           break;
4499
4500 +       case EM_AVR32:
4501 +         rtype = elf_avr32_reloc_type (type);
4502 +         break;
4503 +
4504         case EM_OLD_SPARCV9:
4505         case EM_SPARC32PLUS:
4506         case EM_SPARCV9:
4507 --- a/gas/as.c
4508 +++ b/gas/as.c
4509 @@ -464,10 +464,10 @@ parse_args (int * pargc, char *** pargv)
4510         the end of the preceeding line so that it is simpler to
4511         selectively add and remove lines from this list.  */
4512      {"alternate", no_argument, NULL, OPTION_ALTERNATE}
4513 -    /* The entry for "a" is here to prevent getopt_long_only() from
4514 -       considering that -a is an abbreviation for --alternate.  This is
4515 -       necessary because -a=<FILE> is a valid switch but getopt would
4516 -       normally reject it since --alternate does not take an argument.  */
4517 +    /* The next two entries are here to prevent getopt_long_only() from
4518 +       considering that -a or -al is an abbreviation for --alternate.
4519 +       This is necessary because -a=<FILE> is a valid switch but getopt
4520 +       would normally reject it since --alternate does not take an argument.  */
4521      ,{"a", optional_argument, NULL, 'a'}
4522      /* Handle -al=<FILE>.  */
4523      ,{"al", optional_argument, NULL, OPTION_AL}
4524 @@ -854,8 +854,15 @@ This program has absolutely no warranty.
4525         case 'a':
4526           if (optarg)
4527             {
4528 -             if (optarg != old_argv[optind] && optarg[-1] == '=')
4529 +             /* If optarg is part of the -a switch and not a separate argument
4530 +                in its own right, then scan backwards to the just after the -a.
4531 +                This means skipping over both '=' and 'l' which might have been
4532 +                taken to be part of the -a switch itself.  */
4533 +             if (optarg != old_argv[optind])
4534 +               {
4535 +                 while (optarg[-1] == '=' || optarg[-1] == 'l')
4536                 --optarg;
4537 +               }
4538
4539               if (md_parse_option (optc, optarg) != 0)
4540                 break;
4541 --- a/gas/as.h
4542 +++ b/gas/as.h
4543 @@ -82,6 +82,7 @@
4544  #endif
4545  #define gas_assert(P) \
4546    ((void) ((P) ? 0 : (as_assert (__FILE__, __LINE__, __PRETTY_FUNCTION__), 0)))
4547 +#define assert(P)   gas_assert(P)
4548  #undef abort
4549  #define abort()                as_abort (__FILE__, __LINE__, __PRETTY_FUNCTION__)
4550
4551 --- a/gas/atof-generic.c
4552 +++ b/gas/atof-generic.c
4553 @@ -121,6 +121,21 @@ atof_generic (/* return pointer to just
4554
4555    switch (first_digit[0])
4556      {
4557 +    case 's':
4558 +    case 'S':
4559 +    case 'q':
4560 +    case 'Q':
4561 +      if (!strncasecmp ("nan", first_digit+1, 3))
4562 +       {
4563 +         address_of_generic_floating_point_number->sign = 0;
4564 +         address_of_generic_floating_point_number->exponent = 0;
4565 +         address_of_generic_floating_point_number->leader =
4566 +           address_of_generic_floating_point_number->low;
4567 +         *address_of_string_pointer = first_digit + 4;
4568 +         return 0;
4569 +       }
4570 +      break;
4571 +
4572      case 'n':
4573      case 'N':
4574        if (!strncasecmp ("nan", first_digit, 3))
4575 --- a/gas/config/atof-vax.c
4576 +++ b/gas/config/atof-vax.c
4577 @@ -268,9 +268,27 @@ flonum_gen2vax (int format_letter, /* On
4578           int exponent_skippage;
4579           LITTLENUM_TYPE word1;
4580
4581 -         /* JF: Deal with new Nan, +Inf and -Inf codes.  */
4582 +         /* JF: Deal with new +/-(q/Q/s/S)Nan, +Inf and -Inf codes.  */
4583           if (f->sign != '-' && f->sign != '+')
4584             {
4585 +          if (f->sign == 0)
4586 +            {
4587 +              /* All NaNs are 0.  */
4588 +              memset (words, 0x00, sizeof (LITTLENUM_TYPE) * precision);
4589 +            }
4590 +          else if (f->sign == 'P')
4591 +            {
4592 +              /* Positive Infinity.  */
4593 +              memset (words, 0xff, sizeof (LITTLENUM_TYPE) * precision);
4594 +              words[0] &= 0x7fff;
4595 +            }
4596 +          else if (f->sign == 'N')
4597 +            {
4598 +              /* Negative Infinity.  */
4599 +              memset (words, 0x00, sizeof (LITTLENUM_TYPE) * precision);
4600 +              words[0] = 0x0080;
4601 +            }
4602 +          else
4603               make_invalid_floating_point_number (words);
4604               return return_value;
4605             }
4606 --- /dev/null
4607 +++ b/gas/config/tc-avr32.c
4608 @@ -0,0 +1,4839 @@
4609 +/* Assembler implementation for AVR32.
4610 +   Copyright 2003,2004,2005,2006,2007,2008,2009,2010 Atmel Corporation.
4611 +
4612 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
4613 +
4614 +   This file is part of GAS, the GNU Assembler.
4615 +
4616 +   GAS is free software; you can redistribute it and/or modify it
4617 +   under the terms of the GNU General Public License as published by
4618 +   the Free Software Foundation; either version 2, or (at your option)
4619 +   any later version.
4620 +
4621 +   GAS is distributed in the hope that it will be useful, but WITHOUT
4622 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
4623 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
4624 +   License for more details.
4625 +
4626 +   You should have received a copy of the GNU General Public License
4627 +   along with GAS; see the file COPYING.  If not, write to the Free
4628 +   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
4629 +   02111-1307, USA.  */
4630 +
4631 +#include <stdio.h>
4632 +#include "as.h"
4633 +#include "safe-ctype.h"
4634 +#include "subsegs.h"
4635 +#include "symcat.h"
4636 +#include "opcodes/avr32-opc.h"
4637 +#include "opcodes/avr32-asm.h"
4638 +#include "elf/avr32.h"
4639 +#include "dwarf2dbg.h"
4640 +
4641 +#define xDEBUG
4642 +#define xOPC_CONSISTENCY_CHECK
4643 +
4644 +#ifdef DEBUG
4645 +# define pr_debug(fmt, args...) fprintf(stderr, fmt, ##args)
4646 +#else
4647 +# define pr_debug(fmt, args...)
4648 +#endif
4649 +
4650 +/* 3 MSB of instruction word indicate group. Group 7 -> extended */
4651 +#define AVR32_COMPACT_P(opcode) ((opcode[0] & 0xe0) != 0xe0)
4652 +
4653 +#define streq(a, b)            (strcmp(a, b) == 0)
4654 +#define skip_whitespace(str)   do { while(*(str) == ' ') ++(str); } while(0)
4655 +
4656 +/* Flags given on the command line */
4657 +static int avr32_pic   = FALSE;
4658 +int linkrelax  = FALSE;
4659 +int avr32_iarcompat    = FALSE;
4660 +
4661 +/* This array holds the chars that always start a comment. */
4662 +const char comment_chars[]             = "#";
4663 +
4664 +/* This array holds the chars that only start a comment at the
4665 +   beginning of a line.  We must include '#' here because the compiler
4666 +   may produce #APP and #NO_APP in its output.  */
4667 +const char line_comment_chars[]                = "#";
4668 +
4669 +/* These may be used instead of newline (same as ';' in C).  */
4670 +const char line_separator_chars[]      = ";";
4671 +
4672 +/* Chars that can be used to separate mantissa from exponent in
4673 +   floating point numbers.  */
4674 +const char EXP_CHARS[]                 = "eE";
4675 +
4676 +/* Chars that mean this number is a floating point constant.  */
4677 +const char FLT_CHARS[]                 = "dD";
4678 +
4679 +/* Pre-defined "_GLOBAL_OFFSET_TABLE_"  */
4680 +symbolS *GOT_symbol;
4681 +
4682 +static struct hash_control *avr32_mnemonic_htab;
4683 +
4684 +struct avr32_ifield_data
4685 +{
4686 +  bfd_vma value;
4687 +  /* FIXME: Get rid of align_order and complain. complain is never
4688 +     used, align_order is used in one place.  Try to use the relax
4689 +     table instead.  */
4690 +  unsigned int align_order;
4691 +};
4692 +
4693 +struct avr32_insn
4694 +{
4695 +  const struct avr32_syntax *syntax;
4696 +  expressionS immediate;
4697 +  int pcrel;
4698 +  int force_extended;
4699 +  unsigned int next_slot;
4700 +  bfd_reloc_code_real_type r_type;
4701 +  struct avr32_ifield_data field_value[AVR32_MAX_FIELDS];
4702 +};
4703 +
4704 +static struct avr32_insn current_insn;
4705 +
4706 +/* The target specific pseudo-ops we support. */
4707 +static void s_rseg (int);
4708 +static void s_cpool(int);
4709 +
4710 +const pseudo_typeS md_pseudo_table[] =
4711 +{
4712 +  /* Make sure that .word is 32 bits */
4713 +  { "word", cons, 4 },
4714 +  { "file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 },
4715 +  { "loc", dwarf2_directive_loc, 0 },
4716 +
4717 +  /* .lcomm requires an explicit alignment parameter */
4718 +  { "lcomm", s_lcomm, 1 },
4719 +
4720 +  /* AVR32-specific pseudo-ops */
4721 +  { "cpool", s_cpool, 0},
4722 +
4723 +  /* IAR compatible pseudo-ops */
4724 +  { "program", s_ignore, 0 },
4725 +  { "public", s_globl, 0 },
4726 +  { "extern", s_ignore, 0 },
4727 +  { "module", s_ignore, 0 },
4728 +  { "rseg", s_rseg, 0 },
4729 +  { "dc8", cons, 1 },
4730 +  { "dc16", cons, 2 },
4731 +  { "dc32", cons, 4 },
4732 +
4733 +  { NULL, NULL, 0 }
4734 +};
4735 +
4736 +/* Questionable stuff starts here */
4737 +
4738 +enum avr32_opinfo {
4739 +  AVR32_OPINFO_NONE = BFD_RELOC_NONE,
4740 +  AVR32_OPINFO_GOT,
4741 +  AVR32_OPINFO_TLSGD,
4742 +  AVR32_OPINFO_HI,
4743 +  AVR32_OPINFO_LO,
4744 +};
4745 +
4746 +enum avr32_arch {
4747 +  ARCH_TYPE_AP,
4748 +  ARCH_TYPE_UCR1,
4749 +  ARCH_TYPE_UCR2,
4750 +  ARCH_TYPE_UCR3,
4751 +  ARCH_TYPE_UCR3FP
4752 +};
4753 +
4754 +struct arch_type_s
4755 +{
4756 +  /* Architecture name */
4757 +  char *name;
4758 +  /* Instruction Set Architecture Flags */
4759 +  unsigned long isa_flags;
4760 +};
4761 +
4762 +struct part_type_s
4763 +{
4764 +  /* Part name */
4765 +  char *name;
4766 +  /* Architecture type */
4767 +  unsigned int arch;
4768 +};
4769 +
4770 +static struct arch_type_s arch_types[] =
4771 +{
4772 +    {"ap", AVR32_V1 | AVR32_SIMD | AVR32_DSP | AVR32_PICO},
4773 +    {"ucr1", AVR32_V1 | AVR32_DSP | AVR32_RMW},
4774 +    {"ucr2", AVR32_V1 | AVR32_V2 | AVR32_DSP | AVR32_RMW},
4775 +    {"ucr3", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_DSP | AVR32_RMW},
4776 +    {"ucr3fp", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_DSP | AVR32_RMW | AVR32_V3FP},
4777 +    {"all-insn", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_V3FP | AVR32_PICO},
4778 +    {NULL, 0}
4779 +};
4780 +
4781 +static struct part_type_s part_types[] =
4782 +{
4783 +    {"ap7000",        ARCH_TYPE_AP},
4784 +    {"ap7001",        ARCH_TYPE_AP},
4785 +    {"ap7002",        ARCH_TYPE_AP},
4786 +    {"ap7200",        ARCH_TYPE_AP},
4787 +    {"uc3a0128",      ARCH_TYPE_UCR2},
4788 +    {"uc3a0256",      ARCH_TYPE_UCR2},
4789 +    {"uc3a0512es",    ARCH_TYPE_UCR1},
4790 +    {"uc3a0512",      ARCH_TYPE_UCR2},
4791 +    {"uc3a1128",      ARCH_TYPE_UCR2},
4792 +    {"uc3a1256es",    ARCH_TYPE_UCR1},
4793 +    {"uc3a1256",      ARCH_TYPE_UCR2},
4794 +    {"uc3a1512es",    ARCH_TYPE_UCR1},
4795 +    {"uc3a1512",      ARCH_TYPE_UCR2},
4796 +    {"uc3a364",       ARCH_TYPE_UCR2},
4797 +    {"uc3a364s",      ARCH_TYPE_UCR2},
4798 +    {"uc3a3128",      ARCH_TYPE_UCR2},
4799 +    {"uc3a3128s",     ARCH_TYPE_UCR2},
4800 +    {"uc3a3256",      ARCH_TYPE_UCR2},
4801 +    {"uc3a3256s",     ARCH_TYPE_UCR2},
4802 +    {"uc3b064",       ARCH_TYPE_UCR1},
4803 +    {"uc3b0128",      ARCH_TYPE_UCR1},
4804 +    {"uc3b0256es",    ARCH_TYPE_UCR1},
4805 +    {"uc3b0256",      ARCH_TYPE_UCR1},
4806 +    {"uc3b0512",      ARCH_TYPE_UCR2},
4807 +    {"uc3b0512revc",  ARCH_TYPE_UCR2},
4808 +    {"uc3b164",       ARCH_TYPE_UCR1},
4809 +    {"uc3b1128",      ARCH_TYPE_UCR1},
4810 +    {"uc3b1256",      ARCH_TYPE_UCR1},
4811 +    {"uc3b1256es",    ARCH_TYPE_UCR1},
4812 +    {"uc3b1512",      ARCH_TYPE_UCR2},
4813 +    {"uc3b1512revc",  ARCH_TYPE_UCR2},
4814 +    {"uc3c0512crevc", ARCH_TYPE_UCR3},
4815 +    {"uc3c1512crevc", ARCH_TYPE_UCR3},
4816 +    {"uc3c2512crevc", ARCH_TYPE_UCR3},
4817 +    {"atuc3l0256",    ARCH_TYPE_UCR3},
4818 +    {"mxt768e",       ARCH_TYPE_UCR3},
4819 +    {"uc3l064",       ARCH_TYPE_UCR3},
4820 +    {"uc3l032",       ARCH_TYPE_UCR3},
4821 +    {"uc3l016",       ARCH_TYPE_UCR3},
4822 +    {"uc3l064revb",   ARCH_TYPE_UCR3},
4823 +    {"uc3c064c",  ARCH_TYPE_UCR3FP},
4824 +    {"uc3c0128c",   ARCH_TYPE_UCR3FP},
4825 +    {"uc3c0256c",   ARCH_TYPE_UCR3FP},
4826 +    {"uc3c0512c",   ARCH_TYPE_UCR3FP},
4827 +    {"uc3c164c",  ARCH_TYPE_UCR3FP},
4828 +    {"uc3c1128c",   ARCH_TYPE_UCR3FP},
4829 +    {"uc3c1256c",   ARCH_TYPE_UCR3FP},
4830 +    {"uc3c1512c",   ARCH_TYPE_UCR3FP},
4831 +    {"uc3c264c",  ARCH_TYPE_UCR3FP},
4832 +    {"uc3c2128c",   ARCH_TYPE_UCR3FP},
4833 +    {"uc3c2256c",   ARCH_TYPE_UCR3FP},
4834 +    {"uc3c2512c",   ARCH_TYPE_UCR3FP},
4835 +    {NULL, 0}
4836 +};
4837 +
4838 +/* Current architecture type.  */
4839 +static struct arch_type_s default_arch = {"all-insn", AVR32_V1 | AVR32_V2 | AVR32_V3 | AVR32_SIMD | AVR32_DSP | AVR32_RMW | AVR32_V3FP | AVR32_PICO };
4840 +static struct arch_type_s *avr32_arch = &default_arch;
4841 +
4842 +/* Display nicely formatted list of known part- and architecture names.  */
4843 +
4844 +static void
4845 +show_arch_list (FILE *stream)
4846 +{
4847 +  int i, x;
4848 +
4849 +  fprintf (stream, _("Known architecture names:"));
4850 +  x = 1000;
4851 +
4852 +  for (i = 0; arch_types[i].name; i++)
4853 +    {
4854 +      int len = strlen (arch_types[i].name);
4855 +
4856 +      x += len + 1;
4857 +
4858 +      if (x < 75)
4859 +       fprintf (stream, " %s", arch_types[i].name);
4860 +      else
4861 +       {
4862 +         fprintf (stream, "\n  %s", arch_types[i].name);
4863 +         x = len + 2;
4864 +       }
4865 +    }
4866 +
4867 +  fprintf (stream, "\n");
4868 +}
4869 +
4870 +static void
4871 +show_part_list (FILE *stream)
4872 +{
4873 +  int i, x;
4874 +
4875 +  fprintf (stream, _("Known part names:"));
4876 +  x = 1000;
4877 +
4878 +  for (i = 0; part_types[i].name; i++)
4879 +    {
4880 +      int len = strlen(part_types[i].name);
4881 +
4882 +      x += len + 1;
4883 +
4884 +      if (x < 75)
4885 +       fprintf (stream, " %s", part_types[i].name);
4886 +      else
4887 +       {
4888 +         fprintf(stream, "\n  %s", part_types[i].name);
4889 +         x = len + 2;
4890 +       }
4891 +    }
4892 +
4893 +  fprintf (stream, "\n");
4894 +}
4895 +
4896 +const char *md_shortopts = "";
4897 +struct option md_longopts[] =
4898 +{
4899 +#define OPTION_ARCH            (OPTION_MD_BASE)
4900 +#define OPTION_PART            (OPTION_ARCH + 1)
4901 +#define OPTION_IAR             (OPTION_PART + 1)
4902 +#define OPTION_PIC             (OPTION_IAR + 1)
4903 +#define OPTION_NOPIC           (OPTION_PIC + 1)
4904 +#define OPTION_LINKRELAX       (OPTION_NOPIC + 1)
4905 +#define OPTION_NOLINKRELAX     (OPTION_LINKRELAX + 1)
4906 +#define OPTION_DIRECT_DATA_REFS (OPTION_NOLINKRELAX + 1)
4907 +  {"march",            required_argument, NULL, OPTION_ARCH},
4908 +  {"mpart",            required_argument, NULL, OPTION_PART},
4909 +  {"iar",              no_argument, NULL, OPTION_IAR},
4910 +  {"pic",              no_argument, NULL, OPTION_PIC},
4911 +  {"no-pic",           no_argument, NULL, OPTION_NOPIC},
4912 +  {"linkrelax",                no_argument, NULL, OPTION_LINKRELAX},
4913 +  {"no-linkrelax",     no_argument, NULL, OPTION_NOLINKRELAX},
4914 +  /* deprecated alias for -mpart=xxx */
4915 +  {"mcpu",             required_argument, NULL, OPTION_PART},
4916 +  {NULL,               no_argument, NULL, 0}
4917 +};
4918 +
4919 +size_t md_longopts_size = sizeof (md_longopts);
4920 +
4921 +void
4922 +md_show_usage (FILE *stream)
4923 +{
4924 +  fprintf (stream, _("\
4925 +AVR32 options:\n\
4926 +  -march=[arch-name]      Select cpu architecture. [Default `all-insn']\n\
4927 +  -mpart=[part-name]      Select specific part. [Default `none']\n\
4928 +  --pic                   Produce Position-Independent Code\n\
4929 +  --no-pic                Don't produce Position-Independent Code\n\
4930 +  --linkrelax             Produce output suitable for linker relaxing\n\
4931 +  --no-linkrelax          Don't produce output suitable for linker relaxing\n"));
4932 +  show_arch_list(stream);
4933 +}
4934 +
4935 +int
4936 +md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
4937 +{
4938 +  switch (c)
4939 +    {
4940 +    case OPTION_ARCH:
4941 +      {
4942 +       int i;
4943 +       char *s = alloca (strlen (arg) + 1);
4944 +
4945 +       {
4946 +         char *t = s;
4947 +         char *arg1 = arg;
4948 +
4949 +         do
4950 +           *t = TOLOWER (*arg1++);
4951 +         while (*t++);
4952 +       }
4953 +
4954 +        /* Add backward compability */
4955 +        if (strcmp ("uc", s)== 0)
4956 +          {
4957 +            as_warn("Deprecated arch `%s' specified. "
4958 +                    "Please use '-march=ucr1' instead. "
4959 +                    "Converting to arch 'ucr1'\n",
4960 +                     s);
4961 +            s="ucr1";
4962 +          }
4963 +
4964 +       for (i = 0; arch_types[i].name; ++i)
4965 +         if (strcmp (arch_types[i].name, s) == 0)
4966 +           break;
4967 +
4968 +       if (!arch_types[i].name)
4969 +         {
4970 +           show_arch_list (stderr);
4971 +           as_fatal (_("unknown architecture: %s\n"), arg);
4972 +         }
4973 +
4974 +        avr32_arch = &arch_types[i];
4975 +       break;
4976 +      }
4977 +    case OPTION_PART:
4978 +      {
4979 +       int i;
4980 +       char *s = alloca (strlen (arg) + 1);
4981 +       char *t = s;
4982 +       char *p = arg;
4983 +
4984 +       /* If arch type has already been set, don't bother.
4985 +          -march= always overrides -mpart=  */
4986 +       if (avr32_arch != &default_arch)
4987 +         break;
4988 +
4989 +       do
4990 +         *t = TOLOWER (*p++);
4991 +       while (*t++);
4992 +
4993 +       for (i = 0; part_types[i].name; ++i)
4994 +         if (strcmp (part_types[i].name, s) == 0)
4995 +           break;
4996 +
4997 +       if (!part_types[i].name)
4998 +         {
4999 +           show_part_list (stderr);
5000 +           as_fatal (_("unknown part: %s\n"), arg);
5001 +         }
5002 +
5003 +       avr32_arch = &arch_types[part_types[i].arch];
5004 +       break;
5005 +      }
5006 +    case OPTION_IAR:
5007 +      avr32_iarcompat = 1;
5008 +      break;
5009 +    case OPTION_PIC:
5010 +      avr32_pic = 1;
5011 +      break;
5012 +    case OPTION_NOPIC:
5013 +      avr32_pic = 0;
5014 +      break;
5015 +    case OPTION_LINKRELAX:
5016 +      linkrelax = 1;
5017 +      break;
5018 +    case OPTION_NOLINKRELAX:
5019 +      linkrelax = 0;
5020 +      break;
5021 +    default:
5022 +      return 0;
5023 +    }
5024 +  return 1;
5025 +}
5026 +
5027 +/* Can't use symbol_new here, so have to create a symbol and then at
5028 +   a later date assign it a value. Thats what these functions do.
5029 +
5030 +   Shamelessly stolen from ARM.  */
5031 +
5032 +static void
5033 +symbol_locate (symbolS *    symbolP,
5034 +              const char * name,       /* It is copied, the caller can modify.  */
5035 +              segT         segment,    /* Segment identifier (SEG_<something>).  */
5036 +              valueT       valu,       /* Symbol value.  */
5037 +              fragS *      frag)       /* Associated fragment.  */
5038 +{
5039 +  unsigned int name_length;
5040 +  char * preserved_copy_of_name;
5041 +
5042 +  name_length = strlen (name) + 1;   /* +1 for \0.  */
5043 +  obstack_grow (&notes, name, name_length);
5044 +  preserved_copy_of_name = obstack_finish (&notes);
5045 +#ifdef STRIP_UNDERSCORE
5046 +  if (preserved_copy_of_name[0] == '_')
5047 +    preserved_copy_of_name++;
5048 +#endif
5049 +
5050 +#ifdef tc_canonicalize_symbol_name
5051 +  preserved_copy_of_name =
5052 +    tc_canonicalize_symbol_name (preserved_copy_of_name);
5053 +#endif
5054 +
5055 +  S_SET_NAME (symbolP, preserved_copy_of_name);
5056 +
5057 +  S_SET_SEGMENT (symbolP, segment);
5058 +  S_SET_VALUE (symbolP, valu);
5059 +  symbol_clear_list_pointers (symbolP);
5060 +
5061 +  symbol_set_frag (symbolP, frag);
5062 +
5063 +  /* Link to end of symbol chain.  */
5064 +  {
5065 +    extern int symbol_table_frozen;
5066 +
5067 +    if (symbol_table_frozen)
5068 +      abort ();
5069 +  }
5070 +
5071 +  symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
5072 +
5073 +  obj_symbol_new_hook (symbolP);
5074 +
5075 +#ifdef tc_symbol_new_hook
5076 +  tc_symbol_new_hook (symbolP);
5077 +#endif
5078 +
5079 +#ifdef DEBUG_SYMS
5080 +  verify_symbol_chain (symbol_rootP, symbol_lastP);
5081 +#endif /* DEBUG_SYMS  */
5082 +}
5083 +
5084 +struct cpool_entry
5085 +{
5086 +  int                  refcount;
5087 +  offsetT              offset;
5088 +  expressionS          exp;
5089 +};
5090 +
5091 +struct cpool
5092 +{
5093 +  struct cpool         *next;
5094 +  int                  used;
5095 +  struct cpool_entry   *literals;
5096 +  unsigned int         padding;
5097 +  unsigned int         next_free_entry;
5098 +  unsigned int         id;
5099 +  symbolS              *symbol;
5100 +  segT                 section;
5101 +  subsegT              sub_section;
5102 +};
5103 +
5104 +struct cpool *cpool_list = NULL;
5105 +
5106 +static struct cpool *
5107 +find_cpool(segT section, subsegT sub_section)
5108 +{
5109 +  struct cpool *pool;
5110 +
5111 +  for (pool = cpool_list; pool != NULL; pool = pool->next)
5112 +    {
5113 +      if (!pool->used
5114 +         && pool->section == section
5115 +         && pool->sub_section == sub_section)
5116 +       break;
5117 +    }
5118 +
5119 +  return pool;
5120 +}
5121 +
5122 +static struct cpool *
5123 +find_or_make_cpool(segT section, subsegT sub_section)
5124 +{
5125 +  static unsigned int next_cpool_id = 0;
5126 +  struct cpool *pool;
5127 +
5128 +  pool = find_cpool(section, sub_section);
5129 +
5130 +  if (!pool)
5131 +    {
5132 +      pool = xmalloc(sizeof(*pool));
5133 +      if (!pool)
5134 +       return NULL;
5135 +
5136 +      pool->used = 0;
5137 +      pool->literals = NULL;
5138 +      pool->padding = 0;
5139 +      pool->next_free_entry = 0;
5140 +      pool->section = section;
5141 +      pool->sub_section = sub_section;
5142 +      pool->next = cpool_list;
5143 +      pool->symbol = NULL;
5144 +
5145 +      cpool_list = pool;
5146 +    }
5147 +
5148 +  /* NULL symbol means that the pool is new or has just been emptied.  */
5149 +  if (!pool->symbol)
5150 +    {
5151 +      pool->symbol = symbol_create(FAKE_LABEL_NAME, undefined_section,
5152 +                                  0, &zero_address_frag);
5153 +      pool->id = next_cpool_id++;
5154 +    }
5155 +
5156 +  return pool;
5157 +}
5158 +
5159 +static struct cpool *
5160 +add_to_cpool(expressionS *exp, unsigned int *index, int ref)
5161 +{
5162 +  struct cpool *pool;
5163 +  unsigned int entry;
5164 +
5165 +  pool = find_or_make_cpool(now_seg, now_subseg);
5166 +
5167 +  /* Check if this constant is already in the pool.  */
5168 +  for (entry = 0; entry < pool->next_free_entry; entry++)
5169 +    {
5170 +      if ((pool->literals[entry].exp.X_op == exp->X_op)
5171 +         && (exp->X_op == O_constant)
5172 +         && (pool->literals[entry].exp.X_add_number
5173 +             == exp->X_add_number)
5174 +         && (pool->literals[entry].exp.X_unsigned
5175 +             == exp->X_unsigned))
5176 +       break;
5177 +
5178 +      if ((pool->literals[entry].exp.X_op == exp->X_op)
5179 +         && (exp->X_op == O_symbol)
5180 +         && (pool->literals[entry].exp.X_add_number
5181 +             == exp->X_add_number)
5182 +         && (pool->literals[entry].exp.X_add_symbol
5183 +             == exp->X_add_symbol)
5184 +         && (pool->literals[entry].exp.X_op_symbol
5185 +             == exp->X_op_symbol))
5186 +       break;
5187 +    }
5188 +
5189 +  /* Create an entry if we didn't find a match */
5190 +  if (entry == pool->next_free_entry)
5191 +    {
5192 +      pool->literals = xrealloc(pool->literals,
5193 +                               sizeof(struct cpool_entry) * (entry + 1));
5194 +      pool->literals[entry].exp = *exp;
5195 +      pool->literals[entry].refcount = 0;
5196 +      pool->next_free_entry++;
5197 +    }
5198 +
5199 +  if (index)
5200 +    *index = entry;
5201 +  if (ref)
5202 +    pool->literals[entry].refcount++;
5203 +
5204 +  return pool;
5205 +}
5206 +
5207 +struct avr32_operand
5208 +{
5209 +  int id;
5210 +  int is_signed;
5211 +  int is_pcrel;
5212 +  int align_order;
5213 +  int (*match)(char *str);
5214 +  void (*parse)(const struct avr32_operand *op, char *str, int opindex);
5215 +};
5216 +
5217 +static int
5218 +match_anything(char *str ATTRIBUTE_UNUSED)
5219 +{
5220 +  return 1;
5221 +}
5222 +
5223 +static int
5224 +match_intreg(char *str)
5225 +{
5226 +  int regid, ret = 1;
5227 +
5228 +  regid = avr32_parse_intreg(str);
5229 +  if (regid < 0)
5230 +    ret = 0;
5231 +
5232 +  pr_debug("match_intreg: `%s': %d\n", str, ret);
5233 +
5234 +  return ret;
5235 +}
5236 +
5237 +static int
5238 +match_intreg_predec(char *str)
5239 +{
5240 +  int regid;
5241 +
5242 +  if (str[0] != '-' || str[1] != '-')
5243 +    return 0;
5244 +
5245 +  regid = avr32_parse_intreg(str + 2);
5246 +  if (regid < 0)
5247 +    return 0;
5248 +
5249 +  return 1;
5250 +}
5251 +
5252 +static int
5253 +match_intreg_postinc(char *str)
5254 +{
5255 +  int regid, ret = 1;
5256 +  char *p, c;
5257 +
5258 +  for (p = str; *p; p++)
5259 +    if (*p == '+')
5260 +      break;
5261 +
5262 +  if (p[0] != '+' || p[1] != '+')
5263 +    return 0;
5264 +
5265 +  c = *p, *p = 0;
5266 +  regid = avr32_parse_intreg(str);
5267 +  if (regid < 0)
5268 +    ret = 0;
5269 +
5270 +  *p = c;
5271 +  return ret;
5272 +}
5273 +
5274 +static int
5275 +match_intreg_lsl(char *str)
5276 +{
5277 +  int regid, ret = 1;
5278 +  char *p, c;
5279 +
5280 +  for (p = str; *p; p++)
5281 +    if (*p == '<')
5282 +      break;
5283 +
5284 +  if (p[0] && p[1] != '<')
5285 +    return 0;
5286 +
5287 +  c = *p, *p = 0;
5288 +  regid = avr32_parse_intreg(str);
5289 +  if (regid < 0)
5290 +    ret = 0;
5291 +
5292 +  *p = c;
5293 +  return ret;
5294 +}
5295 +
5296 +static int
5297 +match_intreg_lsr(char *str)
5298 +{
5299 +  int regid, ret = 1;
5300 +  char *p, c;
5301 +
5302 +  for (p = str; *p; p++)
5303 +    if (*p == '>')
5304 +      break;
5305 +
5306 +  if (p[0] && p[1] != '>')
5307 +    return 0;
5308 +
5309 +  c = *p, *p = 0;
5310 +
5311 +  regid = avr32_parse_intreg(str);
5312 +  if (regid < 0)
5313 +    ret = 0;
5314 +
5315 +  *p = c;
5316 +  return ret;
5317 +}
5318 +
5319 +static int
5320 +match_intreg_part(char *str)
5321 +{
5322 +  int regid, ret = 1;
5323 +  char *p, c;
5324 +
5325 +  for (p = str; *p; p++)
5326 +    if (*p == ':')
5327 +      break;
5328 +
5329 +  if (p[0] != ':' || !ISPRINT(p[1]) || p[2] != '\0')
5330 +    return 0;
5331 +
5332 +  c = *p, *p = 0;
5333 +  regid = avr32_parse_intreg(str);
5334 +  if (regid < 0)
5335 +    ret = 0;
5336 +
5337 +  *p = c;
5338 +
5339 +  return ret;
5340 +}
5341 +
5342 +#define match_intreg_disp match_anything
5343 +
5344 +static int
5345 +match_intreg_index(char *str)
5346 +{
5347 +  int regid, ret = 1;
5348 +  char *p, *end, c;
5349 +
5350 +  for (p = str; *p; p++)
5351 +    if (*p == '[')
5352 +      break;
5353 +
5354 +  /* don't allow empty displacement here (it makes no sense) */
5355 +  if (p[0] != '[')
5356 +    return 0;
5357 +
5358 +  for (end = p + 1; *end; end++) ;
5359 +  if (*(--end) != ']')
5360 +    return 0;
5361 +
5362 +  c = *end, *end = 0;
5363 +  if (!match_intreg_lsl(p + 1))
5364 +    ret = 0;
5365 +  *end = c;
5366 +
5367 +  if (ret)
5368 +    {
5369 +      c = *p, *p = 0;
5370 +      regid = avr32_parse_intreg(str);
5371 +      if (regid < 0)
5372 +       ret = 0;
5373 +      *p = c;
5374 +    }
5375 +
5376 +  return ret;
5377 +}
5378 +
5379 +static int
5380 +match_intreg_xindex(char *str)
5381 +{
5382 +  int regid, ret = 1;
5383 +  char *p, *end, c;
5384 +
5385 +  for (p = str; *p; p++)
5386 +    if (*p == '[')
5387 +      break;
5388 +
5389 +  /* empty displacement makes no sense here either */
5390 +  if (p[0] != '[')
5391 +    return 0;
5392 +
5393 +  for (end = p + 1; *end; end++)
5394 +    if (*end == '<')
5395 +      break;
5396 +
5397 +  if (!streq(end, "<<2]"))
5398 +    return 0;
5399 +
5400 +  c = *end, *end = 0;
5401 +  if (!match_intreg_part(p + 1))
5402 +    ret = 0;
5403 +  *end = c;
5404 +
5405 +  if (ret)
5406 +    {
5407 +      c = *p, *p = 0;
5408 +      regid = avr32_parse_intreg(str);
5409 +      if (regid < 0)
5410 +       ret = 0;
5411 +      *p = c;
5412 +    }
5413 +
5414 +  return ret;
5415 +}
5416 +
5417 +/* The PC_UDISP_W operator may show up as a label or as a pc[disp]
5418 +   expression.  So there's no point in attempting to match this...  */
5419 +#define match_pc_disp  match_anything
5420 +
5421 +static int
5422 +match_sp(char *str)
5423 +{
5424 +  /* SP in any form will do */
5425 +  return avr32_parse_intreg(str) == AVR32_REG_SP;
5426 +}
5427 +
5428 +static int
5429 +match_sp_disp(char *str)
5430 +{
5431 +  int regid, ret = 1;
5432 +  char *p, c;
5433 +
5434 +  for (p = str; *p; p++)
5435 +    if (*p == '[')
5436 +      break;
5437 +
5438 +  /* allow empty displacement, meaning zero */
5439 +  if (p[0] == '[')
5440 +    {
5441 +      char *end;
5442 +      for (end = p + 1; *end; end++) ;
5443 +      if (end[-1] != ']')
5444 +       return 0;
5445 +    }
5446 +
5447 +  c = *p, *p = 0;
5448 +  regid = avr32_parse_intreg(str);
5449 +  if (regid != AVR32_REG_SP)
5450 +    ret = 0;
5451 +
5452 +  *p = c;
5453 +  return ret;
5454 +}
5455 +
5456 +static int
5457 +match_cpno(char *str)
5458 +{
5459 +  if (strncasecmp(str, "cp", 2) != 0)
5460 +    return 0;
5461 +  return 1;
5462 +}
5463 +
5464 +static int
5465 +match_cpreg(char *str)
5466 +{
5467 +  if (strncasecmp(str, "cr", 2) != 0)
5468 +    return 0;
5469 +  return 1;
5470 +}
5471 +
5472 +/* We allow complex expressions, and register names may show up as
5473 +   symbols.  Just make sure immediate expressions are always matched
5474 +   last.  */
5475 +#define match_const            match_anything
5476 +#define match_jmplabel         match_anything
5477 +#define match_number           match_anything
5478 +
5479 +/* Mnemonics that take reglists never accept anything else */
5480 +#define match_reglist8         match_anything
5481 +#define match_reglist9         match_anything
5482 +#define match_reglist16                match_anything
5483 +#define match_reglist_ldm      match_anything
5484 +#define match_reglist_cp8      match_anything
5485 +#define match_reglist_cpd8     match_anything
5486 +
5487 +/* Ditto for retval, jospinc and mcall */
5488 +#define match_retval           match_anything
5489 +#define match_jospinc          match_anything
5490 +#define match_mcall            match_anything
5491 +
5492 +/* COH is used to select between two different syntaxes */
5493 +static int
5494 +match_coh(char *str)
5495 +{
5496 +  return strcasecmp(str, "coh") == 0;
5497 +}
5498 +#if 0
5499 +static int
5500 +match_fpreg(char *str)
5501 +{
5502 +  unsigned long regid;
5503 +  char *endptr;
5504 +
5505 +  if ((str[0] != 'f' && str[0] != 'F')
5506 +      || (str[1] != 'r' && str[1] != 'R'))
5507 +    return 0;
5508 +
5509 +  str += 2;
5510 +  regid = strtoul(str, &endptr, 10);
5511 +  if (!*str || *endptr)
5512 +    return 0;
5513 +
5514 +  return 1;
5515 +}
5516 +#endif
5517 +
5518 +static int
5519 +match_picoreg(char *str)
5520 +{
5521 +  int regid;
5522 +
5523 +  regid = avr32_parse_picoreg(str);
5524 +  if (regid < 0)
5525 +    return 0;
5526 +  return 1;
5527 +}
5528 +
5529 +#define match_pico_reglist_w   match_anything
5530 +#define match_pico_reglist_d   match_anything
5531 +
5532 +static int
5533 +match_pico_in(char *str)
5534 +{
5535 +  unsigned long regid;
5536 +  char *end;
5537 +
5538 +  if (strncasecmp(str, "in", 2) != 0)
5539 +    return 0;
5540 +
5541 +  str += 2;
5542 +  regid = strtoul(str, &end, 10);
5543 +  if (!*str || *end)
5544 +    return 0;
5545 +
5546 +  return 1;
5547 +}
5548 +
5549 +static int
5550 +match_pico_out0(char *str)
5551 +{
5552 +  if (strcasecmp(str, "out0") != 0)
5553 +    return 0;
5554 +  return 1;
5555 +}
5556 +
5557 +static int
5558 +match_pico_out1(char *str)
5559 +{
5560 +  if (strcasecmp(str, "out1") != 0)
5561 +    return 0;
5562 +  return 1;
5563 +}
5564 +
5565 +static int
5566 +match_pico_out2(char *str)
5567 +{
5568 +  if (strcasecmp(str, "out2") != 0)
5569 +    return 0;
5570 +  return 1;
5571 +}
5572 +
5573 +static int
5574 +match_pico_out3(char *str)
5575 +{
5576 +  if (strcasecmp(str, "out3") != 0)
5577 +    return 0;
5578 +  return 1;
5579 +}
5580 +
5581 +static void parse_nothing(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5582 +                         char *str ATTRIBUTE_UNUSED,
5583 +                         int opindex ATTRIBUTE_UNUSED)
5584 +{
5585 +  /* Do nothing (this is used for "match-only" operands like COH) */
5586 +}
5587 +
5588 +static void
5589 +parse_const(const struct avr32_operand *op, char *str,
5590 +           int opindex ATTRIBUTE_UNUSED)
5591 +{
5592 +  expressionS *exp = &current_insn.immediate;
5593 +  expressionS *sym_exp;
5594 +  int slot;
5595 +  char *save;
5596 +
5597 +  pr_debug("parse_const: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5598 +          str, op->is_signed, op->is_pcrel, op->align_order);
5599 +
5600 +  save = input_line_pointer;
5601 +  input_line_pointer = str;
5602 +
5603 +  expression(exp);
5604 +
5605 +  slot = current_insn.next_slot++;
5606 +  current_insn.field_value[slot].align_order = op->align_order;
5607 +  current_insn.pcrel = op->is_pcrel;
5608 +
5609 +  switch (exp->X_op)
5610 +    {
5611 +    case O_illegal:
5612 +      as_bad(_("illegal operand"));
5613 +      break;
5614 +    case O_absent:
5615 +      as_bad(_("missing operand"));
5616 +      break;
5617 +    case O_constant:
5618 +      pr_debug("  -> constant: %ld\n", (long)exp->X_add_number);
5619 +      current_insn.field_value[slot].value = exp->X_add_number;
5620 +      break;
5621 +    case O_uminus:
5622 +      pr_debug("  -> uminus\n");
5623 +      sym_exp = symbol_get_value_expression(exp->X_add_symbol);
5624 +      switch (sym_exp->X_op) {
5625 +      case O_subtract:
5626 +       pr_debug("     -> subtract: switching operands\n");
5627 +       exp->X_op_symbol = sym_exp->X_add_symbol;
5628 +       exp->X_add_symbol = sym_exp->X_op_symbol;
5629 +       exp->X_op = O_subtract;
5630 +       /* TODO: Remove the old X_add_symbol */
5631 +       break;
5632 +      default:
5633 +       as_bad(_("Expression too complex\n"));
5634 +       break;
5635 +      }
5636 +      break;
5637 +#if 0
5638 +    case O_subtract:
5639 +      /* Any expression subtracting a symbol from the current section
5640 +        can be made PC-relative by adding the right offset.  */
5641 +      if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg)
5642 +       current_insn.pcrel = TRUE;
5643 +      pr_debug("  -> subtract: pcrel? %s\n",
5644 +              current_insn.pcrel ? "yes" : "no");
5645 +      /* fall through */
5646 +#endif
5647 +    default:
5648 +      pr_debug("  -> (%p <%d> %p + %d)\n",
5649 +              exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5650 +              exp->X_add_number);
5651 +      current_insn.field_value[slot].value = 0;
5652 +      break;
5653 +    }
5654 +
5655 +  input_line_pointer = save;
5656 +}
5657 +
5658 +static void
5659 +parse_jmplabel(const struct avr32_operand *op, char *str,
5660 +              int opindex ATTRIBUTE_UNUSED)
5661 +{
5662 +  expressionS *exp = &current_insn.immediate;
5663 +  int slot;
5664 +  char *save;
5665 +
5666 +  pr_debug("parse_jmplabel: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5667 +          str, op->is_signed, op->is_pcrel, op->align_order);
5668 +
5669 +  save = input_line_pointer;
5670 +  input_line_pointer = str;
5671 +
5672 +  expression(exp);
5673 +
5674 +  slot = current_insn.next_slot++;
5675 +  current_insn.field_value[slot].align_order = op->align_order;
5676 +  current_insn.pcrel = TRUE;
5677 +
5678 +  switch (exp->X_op)
5679 +    {
5680 +    case O_illegal:
5681 +      as_bad(_("illegal operand"));
5682 +      break;
5683 +    case O_absent:
5684 +      as_bad(_("missing operand"));
5685 +      break;
5686 +    case O_constant:
5687 +      pr_debug("  -> constant: %ld\n", (long)exp->X_add_number);
5688 +      current_insn.field_value[slot].value = exp->X_add_number;
5689 +      current_insn.pcrel = 0;
5690 +      break;
5691 +    default:
5692 +      pr_debug("  -> (%p <%d> %p + %d)\n",
5693 +              exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5694 +              exp->X_add_number);
5695 +      current_insn.field_value[slot].value = 0;
5696 +      break;
5697 +    }
5698 +
5699 +  input_line_pointer = save;
5700 +}
5701 +
5702 +static void
5703 +parse_intreg(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5704 +            char *str, int opindex ATTRIBUTE_UNUSED)
5705 +{
5706 +  int regid, slot;
5707 +
5708 +  pr_debug("parse_intreg: `%s'\n", str);
5709 +
5710 +  regid = avr32_parse_intreg(str);
5711 +  assert(regid >= 0);
5712 +
5713 +  slot = current_insn.next_slot++;
5714 +  current_insn.field_value[slot].value = regid;
5715 +  current_insn.field_value[slot].align_order = op->align_order;
5716 +}
5717 +
5718 +static void
5719 +parse_intreg_predec(const struct avr32_operand *op, char *str, int opindex)
5720 +{
5721 +  parse_intreg(op, str + 2, opindex);
5722 +}
5723 +
5724 +static void
5725 +parse_intreg_postinc(const struct avr32_operand *op, char *str, int opindex)
5726 +{
5727 +  char *p, c;
5728 +
5729 +  pr_debug("parse_intreg_postinc: `%s'\n", str);
5730 +
5731 +  for (p = str; *p != '+'; p++) ;
5732 +
5733 +  c = *p, *p = 0;
5734 +  parse_intreg(op, str, opindex);
5735 +  *p = c;
5736 +}
5737 +
5738 +static void
5739 +parse_intreg_shift(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5740 +                  char *str, int opindex ATTRIBUTE_UNUSED)
5741 +{
5742 +  int regid, slot, shift = 0;
5743 +  char *p, c;
5744 +  char shiftop;
5745 +
5746 +  pr_debug("parse Ry<<sa: `%s'\n", str);
5747 +
5748 +  for (p = str; *p; p++)
5749 +    if (*p == '<' || *p == '>')
5750 +      break;
5751 +
5752 +  shiftop = *p;
5753 +
5754 +  c = *p, *p = 0;
5755 +  regid = avr32_parse_intreg(str);
5756 +  assert(regid >= 0);
5757 +  *p = c;
5758 +
5759 +  if (c)
5760 +    {
5761 +      if (p[0] != shiftop || p[1] != shiftop)
5762 +       as_bad(_("expected shift operator in `%s'"), p);
5763 +      else
5764 +       {
5765 +         expressionS exp;
5766 +         char *saved;
5767 +
5768 +         saved = input_line_pointer;
5769 +         input_line_pointer = p + 2;
5770 +         expression(&exp);
5771 +         input_line_pointer = saved;
5772 +
5773 +         if (exp.X_op != O_constant)
5774 +           as_bad(_("shift amount must be a numeric constant"));
5775 +         else
5776 +           shift = exp.X_add_number;
5777 +       }
5778 +    }
5779 +
5780 +  slot = current_insn.next_slot++;
5781 +  current_insn.field_value[slot].value = regid;
5782 +  slot = current_insn.next_slot++;
5783 +  current_insn.field_value[slot].value = shift;
5784 +}
5785 +
5786 +/* The match() function selected the right opcode, so it doesn't
5787 +   matter which way we shift any more.  */
5788 +#define parse_intreg_lsl       parse_intreg_shift
5789 +#define parse_intreg_lsr       parse_intreg_shift
5790 +
5791 +static void
5792 +parse_intreg_part(const struct avr32_operand *op, char *str,
5793 +                 int opindex ATTRIBUTE_UNUSED)
5794 +{
5795 +  static const char bparts[] = { 'b', 'l', 'u', 't' };
5796 +  static const char hparts[] = { 'b', 't' };
5797 +  unsigned int slot, sel;
5798 +  int regid;
5799 +  char *p, c;
5800 +
5801 +  pr_debug("parse reg:part `%s'\n", str);
5802 +
5803 +  for (p = str; *p; p++)
5804 +    if (*p == ':')
5805 +      break;
5806 +
5807 +  c = *p, *p = 0;
5808 +  regid = avr32_parse_intreg(str);
5809 +  assert(regid >= 0);
5810 +  *p = c;
5811 +
5812 +  assert(c == ':');
5813 +
5814 +  if (op->align_order)
5815 +    {
5816 +      for (sel = 0; sel < sizeof(hparts); sel++)
5817 +       if (TOLOWER(p[1]) == hparts[sel])
5818 +         break;
5819 +
5820 +      if (sel >= sizeof(hparts))
5821 +       {
5822 +         as_bad(_("invalid halfword selector `%c' (must be either b or t)"),
5823 +                p[1]);
5824 +         sel = 0;
5825 +       }
5826 +    }
5827 +  else
5828 +    {
5829 +      for (sel = 0; sel < sizeof(bparts); sel++)
5830 +       if (TOLOWER(p[1]) == bparts[sel])
5831 +         break;
5832 +
5833 +      if (sel >= sizeof(bparts))
5834 +       {
5835 +         as_bad(_("invalid byte selector `%c' (must be one of b,l,u,t)"),
5836 +                p[1]);
5837 +         sel = 0;
5838 +       }
5839 +    }
5840 +
5841 +  slot = current_insn.next_slot++;
5842 +  current_insn.field_value[slot].value = regid;
5843 +  slot = current_insn.next_slot++;
5844 +  current_insn.field_value[slot].value = sel;
5845 +}
5846 +
5847 +/* This is the parser for "Rp[displacement]" expressions.  In addition
5848 +   to the "official" syntax, we accept a label as a replacement for
5849 +   the register expression.  This syntax implies Rp=PC and the
5850 +   displacement is the pc-relative distance to the label.  */
5851 +static void
5852 +parse_intreg_disp(const struct avr32_operand *op, char *str, int opindex)
5853 +{
5854 +  expressionS *exp = &current_insn.immediate;
5855 +  int slot, regid;
5856 +  char *save, *p, c;
5857 +
5858 +  pr_debug("parse_intreg_disp: `%s' (signed: %d, pcrel: %d, align: %d)\n",
5859 +          str, op->is_signed, op->is_pcrel, op->align_order);
5860 +
5861 +  for (p = str; *p; p++)
5862 +    if (*p == '[')
5863 +      break;
5864 +
5865 +  slot = current_insn.next_slot++;
5866 +
5867 +  /* First, check if we have a valid register either before '[' or as
5868 +     the sole expression.  If so, we use the Rp[disp] syntax.  */
5869 +  c = *p, *p = 0;
5870 +  regid = avr32_parse_intreg(str);
5871 +  *p = c;
5872 +
5873 +  if (regid >= 0)
5874 +    {
5875 +      current_insn.field_value[slot].value = regid;
5876 +
5877 +      slot = current_insn.next_slot++;
5878 +      current_insn.field_value[slot].align_order = op->align_order;
5879 +
5880 +      if (c == '[')
5881 +       {
5882 +         save = input_line_pointer;
5883 +         input_line_pointer = p + 1;
5884 +
5885 +         expression(exp);
5886 +
5887 +         if (*input_line_pointer != ']')
5888 +           as_bad(_("junk after displacement expression"));
5889 +
5890 +         input_line_pointer = save;
5891 +
5892 +         switch (exp->X_op)
5893 +           {
5894 +           case O_illegal:
5895 +             as_bad(_("illegal displacement expression"));
5896 +             break;
5897 +           case O_absent:
5898 +             as_bad(_("missing displacement expression"));
5899 +             break;
5900 +           case O_constant:
5901 +             pr_debug("  -> constant: %ld\n", exp->X_add_number);
5902 +             current_insn.field_value[slot].value = exp->X_add_number;
5903 +             break;
5904 +#if 0
5905 +           case O_subtract:
5906 +             if (S_GET_SEGMENT(exp->X_op_symbol) == now_seg)
5907 +               current_insn.pcrel = TRUE;
5908 +             pr_debug("  -> subtract: pcrel? %s\n",
5909 +                      current_insn.pcrel ? "yes" : "no");
5910 +             /* fall through */
5911 +#endif
5912 +           default:
5913 +             pr_debug("  -> (%p <%d> %p + %d)\n",
5914 +                      exp->X_add_symbol, exp->X_op, exp->X_op_symbol,
5915 +                      exp->X_add_number);
5916 +             current_insn.field_value[slot].value = 0;
5917 +           }
5918 +       }
5919 +      else
5920 +       {
5921 +         exp->X_op = O_constant;
5922 +         exp->X_add_number = 0;
5923 +         current_insn.field_value[slot].value = 0;
5924 +       }
5925 +    }
5926 +  else
5927 +    {
5928 +      /* Didn't find a valid register.  Try parsing it as a label.  */
5929 +      current_insn.field_value[slot].value = AVR32_REG_PC;
5930 +      parse_jmplabel(op, str, opindex);
5931 +    }
5932 +}
5933 +
5934 +static void
5935 +parse_intreg_index(const struct avr32_operand *op ATTRIBUTE_UNUSED,
5936 +                  char *str, int opindex ATTRIBUTE_UNUSED)
5937 +{
5938 +  int slot, regid;
5939 +  char *p, *end, c;
5940 +
5941 +  for (p = str; *p; p++)
5942 +    if (*p == '[')
5943 +      break;
5944 +
5945 +  assert(*p);
5946 +
5947 +  c = *p, *p = 0;
5948 +  regid = avr32_parse_intreg(str);
5949 +  assert(regid >= 0);
5950 +  *p = c;
5951 +
5952 +  slot = current_insn.next_slot++;
5953 +  current_insn.field_value[slot].value = regid;
5954 +
5955 +  p++;
5956 +  for (end = p; *end; end++)
5957 +    if (*end == ']' || *end == '<')
5958 +      break;
5959 +
5960 +  assert(*end);
5961 +
5962 +  c = *end, *end = 0;
5963 +  regid = avr32_parse_intreg(p);
5964 +  assert(regid >= 0);
5965 +  *end = c;
5966 +
5967 +  slot = current_insn.next_slot++;
5968 +  current_insn.field_value[slot].value = regid;
5969 +
5970 +  slot = current_insn.next_slot++;
5971 +  current_insn.field_value[slot].value = 0;
5972 +
5973 +  if (*end == '<')
5974 +    {
5975 +      expressionS exp;
5976 +      char *save;
5977 +
5978 +      p = end + 2;
5979 +      for (end = p; *end; end++)
5980 +       if (*end == ']')
5981 +         break;
5982 +
5983 +      assert(*end == ']');
5984 +
5985 +      c = *end, *end = 0;
5986 +      save = input_line_pointer;
5987 +      input_line_pointer = p;
5988 +      expression(&exp);
5989 +
5990 +      if (*input_line_pointer)
5991 +       as_bad(_("junk after shift expression"));
5992 +
5993 +      *end = c;
5994 +      input_line_pointer = save;
5995 +
5996 +      if (exp.X_op == O_constant)
5997 +       current_insn.field_value[slot].value = exp.X_add_number;
5998 +      else
5999 +       as_bad(_("shift expression too complex"));
6000 +    }
6001 +}
6002 +
6003 +static void
6004 +parse_intreg_xindex(const struct avr32_operand *op, char *str, int opindex)
6005 +{
6006 +  int slot, regid;
6007 +  char *p, *end, c;
6008 +
6009 +  for (p = str; *p; p++)
6010 +    if (*p == '[')
6011 +      break;
6012 +
6013 +  assert(*p);
6014 +
6015 +  c = *p, *p = 0;
6016 +  regid = avr32_parse_intreg(str);
6017 +  assert(regid >= 0);
6018 +  *p = c;
6019 +
6020 +  slot = current_insn.next_slot++;
6021 +  current_insn.field_value[slot].value = regid;
6022 +
6023 +  p++;
6024 +  for (end = p; *end; end++)
6025 +    if (*end == '<')
6026 +      break;
6027 +
6028 +  assert(*end);
6029 +
6030 +  c = *end, *end = 0;
6031 +  parse_intreg_part(op, p, opindex);
6032 +  *end = c;
6033 +}
6034 +
6035 +static void
6036 +parse_pc_disp(const struct avr32_operand *op, char *str, int opindex)
6037 +{
6038 +  char *p, c;
6039 +
6040 +  for (p = str; *p; p++)
6041 +    if (*p == '[')
6042 +      break;
6043 +
6044 +  /* The lddpc instruction comes in two different syntax variants:
6045 +       lddpc reg, expression
6046 +       lddpc reg, pc[disp]
6047 +     If the operand contains a '[', we use the second form.  */
6048 +  if (*p)
6049 +    {
6050 +      int regid;
6051 +
6052 +      c = *p, *p = 0;
6053 +      regid = avr32_parse_intreg(str);
6054 +      *p = c;
6055 +      if (regid == AVR32_REG_PC)
6056 +       {
6057 +         char *end;
6058 +
6059 +         for (end = ++p; *end; end++) ;
6060 +         if (*(--end) != ']')
6061 +           as_bad(_("unrecognized form of instruction: `%s'"), str);
6062 +         else
6063 +           {
6064 +             c = *end, *end = 0;
6065 +             parse_const(op, p, opindex);
6066 +             *end = c;
6067 +             current_insn.pcrel = 0;
6068 +           }
6069 +       }
6070 +      else
6071 +       as_bad(_("unrecognized form of instruction: `%s'"), str);
6072 +    }
6073 +  else
6074 +    {
6075 +      parse_jmplabel(op, str, opindex);
6076 +    }
6077 +}
6078 +
6079 +static void parse_sp(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6080 +                    char *str ATTRIBUTE_UNUSED,
6081 +                    int opindex ATTRIBUTE_UNUSED)
6082 +{
6083 +  int slot;
6084 +
6085 +  slot = current_insn.next_slot++;
6086 +  current_insn.field_value[slot].value = AVR32_REG_SP;
6087 +}
6088 +
6089 +static void
6090 +parse_sp_disp(const struct avr32_operand *op, char *str, int opindex)
6091 +{
6092 +  char *p, c;
6093 +
6094 +  for (; *str; str++)
6095 +    if (*str == '[')
6096 +      break;
6097 +
6098 +  assert(*str);
6099 +
6100 +  for (p = ++str; *p; p++)
6101 +    if (*p == ']')
6102 +      break;
6103 +
6104 +  c = *p, *p = 0;
6105 +  parse_const(op, str, opindex);
6106 +  *p = c;
6107 +}
6108 +
6109 +static void
6110 +parse_cpno(const struct avr32_operand *op ATTRIBUTE_UNUSED, char *str,
6111 +          int opindex ATTRIBUTE_UNUSED)
6112 +{
6113 +  int slot;
6114 +
6115 +  str += 2;
6116 +  if (*str == '#')
6117 +    str++;
6118 +  if (*str < '0' || *str > '7' || str[1])
6119 +    as_bad(_("invalid coprocessor `%s'"), str);
6120 +
6121 +  slot = current_insn.next_slot++;
6122 +  current_insn.field_value[slot].value = *str - '0';
6123 +}
6124 +
6125 +static void
6126 +parse_cpreg(const struct avr32_operand *op, char *str,
6127 +           int opindex ATTRIBUTE_UNUSED)
6128 +{
6129 +  unsigned int crid;
6130 +  int slot;
6131 +  char *endptr;
6132 +
6133 +  str += 2;
6134 +  crid = strtoul(str, &endptr, 10);
6135 +  if (*endptr || crid > 15 || crid & ((1 << op->align_order) - 1))
6136 +    as_bad(_("invalid coprocessor register `%s'"), str);
6137 +
6138 +  crid >>= op->align_order;
6139 +
6140 +  slot = current_insn.next_slot++;
6141 +  current_insn.field_value[slot].value = crid;
6142 +}
6143 +
6144 +static void
6145 +parse_number(const struct avr32_operand *op, char *str,
6146 +            int opindex ATTRIBUTE_UNUSED)
6147 +{
6148 +  expressionS exp;
6149 +  int slot;
6150 +  char *save;
6151 +
6152 +  save = input_line_pointer;
6153 +  input_line_pointer = str;
6154 +  expression(&exp);
6155 +  input_line_pointer = save;
6156 +
6157 +  slot = current_insn.next_slot++;
6158 +  current_insn.field_value[slot].align_order = op->align_order;
6159 +
6160 +  if (exp.X_op == O_constant)
6161 +      current_insn.field_value[slot].value = exp.X_add_number;
6162 +  else
6163 +      as_bad(_("invalid numeric expression `%s'"), str);
6164 +}
6165 +
6166 +static void
6167 +parse_reglist8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6168 +              char *str, int opindex ATTRIBUTE_UNUSED)
6169 +{
6170 +  unsigned long regmask;
6171 +  unsigned long value = 0;
6172 +  int slot;
6173 +  char *tail;
6174 +
6175 +  regmask = avr32_parse_reglist(str, &tail);
6176 +  if (*tail)
6177 +    as_bad(_("invalid register list `%s'"), str);
6178 +  else
6179 +    {
6180 +      if (avr32_make_regmask8(regmask, &value))
6181 +       as_bad(_("register list `%s' doesn't fit"), str);
6182 +    }
6183 +
6184 +  slot = current_insn.next_slot++;
6185 +  current_insn.field_value[slot].value = value;
6186 +}
6187 +
6188 +static int
6189 +parse_reglist_tail(char *str, unsigned long regmask)
6190 +{
6191 +  expressionS exp;
6192 +  char *save, *p, c;
6193 +  int regid;
6194 +
6195 +  for (p = str + 1; *p; p++)
6196 +    if (*p == '=')
6197 +      break;
6198 +
6199 +  if (!*p)
6200 +    {
6201 +      as_bad(_("invalid register list `%s'"), str);
6202 +      return -2;
6203 +    }
6204 +
6205 +  c = *p, *p = 0;
6206 +  regid = avr32_parse_intreg(str);
6207 +  *p = c;
6208 +
6209 +  if (regid != 12)
6210 +    {
6211 +      as_bad(_("invalid register list `%s'"), str);
6212 +      return -2;
6213 +    }
6214 +
6215 +  /* If we have an assignment, we must pop PC and we must _not_
6216 +     pop LR or R12 */
6217 +  if (!(regmask & (1 << AVR32_REG_PC)))
6218 +    {
6219 +      as_bad(_("return value specified for non-return instruction"));
6220 +      return -2;
6221 +    }
6222 +  else if (regmask & ((1 << AVR32_REG_R12) | (1 << AVR32_REG_LR)))
6223 +    {
6224 +      as_bad(_("can't pop LR or R12 when specifying return value"));
6225 +      return -2;
6226 +    }
6227 +
6228 +  save = input_line_pointer;
6229 +  input_line_pointer = p + 1;
6230 +  expression(&exp);
6231 +  input_line_pointer = save;
6232 +
6233 +  if (exp.X_op != O_constant
6234 +      || exp.X_add_number < -1
6235 +      || exp.X_add_number > 1)
6236 +    {
6237 +      as_bad(_("invalid return value `%s'"), str);
6238 +      return -2;
6239 +    }
6240 +
6241 +  return exp.X_add_number;
6242 +}
6243 +
6244 +static void
6245 +parse_reglist9(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6246 +              char *str, int opindex ATTRIBUTE_UNUSED)
6247 +{
6248 +  unsigned long regmask;
6249 +  unsigned long value = 0, kbit = 0;
6250 +  int slot;
6251 +  char *tail;
6252 +
6253 +  regmask = avr32_parse_reglist(str, &tail);
6254 +  /* printf("parsed reglist16: %04lx, tail: `%s'\n", regmask, tail); */
6255 +  if (*tail)
6256 +    {
6257 +      int retval;
6258 +
6259 +      retval = parse_reglist_tail(tail, regmask);
6260 +
6261 +      switch (retval)
6262 +       {
6263 +       case -1:
6264 +         regmask |= 1 << AVR32_REG_LR;
6265 +         break;
6266 +       case 0:
6267 +         break;
6268 +       case 1:
6269 +         regmask |= 1 << AVR32_REG_R12;
6270 +         break;
6271 +       default:
6272 +         break;
6273 +       }
6274 +
6275 +      kbit = 1;
6276 +    }
6277 +
6278 +  if (avr32_make_regmask8(regmask, &value))
6279 +    as_bad(_("register list `%s' doesn't fit"), str);
6280 +
6281 +
6282 +  slot = current_insn.next_slot++;
6283 +  current_insn.field_value[slot].value = (value << 1) | kbit;
6284 +}
6285 +
6286 +static void
6287 +parse_reglist16(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6288 +               char *str, int opindex ATTRIBUTE_UNUSED)
6289 +{
6290 +  unsigned long regmask;
6291 +  int slot;
6292 +  char *tail;
6293 +
6294 +  regmask = avr32_parse_reglist(str, &tail);
6295 +  if (*tail)
6296 +    as_bad(_("invalid register list `%s'"), str);
6297 +
6298 +  slot = current_insn.next_slot++;
6299 +  current_insn.field_value[slot].value = regmask;
6300 +}
6301 +
6302 +static void
6303 +parse_reglist_ldm(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6304 +                 char *str, int opindex ATTRIBUTE_UNUSED)
6305 +{
6306 +  unsigned long regmask;
6307 +  int slot, rp, w_bit = 0;
6308 +  char *tail, *p, c;
6309 +
6310 +  for (p = str; *p && *p != ','; p++)
6311 +    if (*p == '+')
6312 +      break;
6313 +
6314 +  c = *p, *p = 0;
6315 +  rp = avr32_parse_intreg(str);
6316 +  *p = c;
6317 +  if (rp < 0)
6318 +    {
6319 +      as_bad(_("invalid destination register in `%s'"), str);
6320 +      return;
6321 +    }
6322 +
6323 +  if (p[0] == '+' && p[1] == '+')
6324 +    {
6325 +      w_bit = 1;
6326 +      p += 2;
6327 +    }
6328 +
6329 +  if (*p != ',')
6330 +    {
6331 +      as_bad(_("expected `,' after destination register in `%s'"), str);
6332 +      return;
6333 +    }
6334 +
6335 +  str = p + 1;
6336 +  regmask = avr32_parse_reglist(str, &tail);
6337 +  if (*tail)
6338 +    {
6339 +      int retval;
6340 +
6341 +      if (rp != AVR32_REG_SP)
6342 +       {
6343 +         as_bad(_("junk at end of line: `%s'"), tail);
6344 +         return;
6345 +       }
6346 +
6347 +      rp = AVR32_REG_PC;
6348 +
6349 +      retval = parse_reglist_tail(tail, regmask);
6350 +
6351 +      switch (retval)
6352 +       {
6353 +       case -1:
6354 +         regmask |= 1 << AVR32_REG_LR;
6355 +         break;
6356 +       case 0:
6357 +         break;
6358 +       case 1:
6359 +         regmask |= 1 << AVR32_REG_R12;
6360 +         break;
6361 +       default:
6362 +         return;
6363 +       }
6364 +    }
6365 +
6366 +  slot = current_insn.next_slot++;
6367 +  current_insn.field_value[slot].value = rp;
6368 +  slot = current_insn.next_slot++;
6369 +  current_insn.field_value[slot].value = w_bit;
6370 +  slot = current_insn.next_slot++;
6371 +  current_insn.field_value[slot].value = regmask;
6372 +}
6373 +
6374 +static void
6375 +parse_reglist_cp8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6376 +                 char *str, int opindex ATTRIBUTE_UNUSED)
6377 +{
6378 +  unsigned long regmask;
6379 +  int slot, h_bit = 0;
6380 +  char *tail;
6381 +
6382 +  regmask = avr32_parse_cpreglist(str, &tail);
6383 +  if (*tail)
6384 +    as_bad(_("junk at end of line: `%s'"), tail);
6385 +  else if (regmask & 0xffUL)
6386 +    {
6387 +      if (regmask & 0xff00UL)
6388 +       as_bad(_("register list `%s' doesn't fit"), str);
6389 +      regmask &= 0xff;
6390 +    }
6391 +  else if (regmask & 0xff00UL)
6392 +    {
6393 +      regmask >>= 8;
6394 +      h_bit = 1;
6395 +    }
6396 +  else
6397 +    as_warn(_("register list is empty"));
6398 +
6399 +  slot = current_insn.next_slot++;
6400 +  current_insn.field_value[slot].value = regmask;
6401 +  slot = current_insn.next_slot++;
6402 +  current_insn.field_value[slot].value = h_bit;
6403 +}
6404 +
6405 +static void
6406 +parse_reglist_cpd8(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6407 +                  char *str, int opindex ATTRIBUTE_UNUSED)
6408 +{
6409 +  unsigned long regmask, regmask_d = 0;
6410 +  int slot, i;
6411 +  char *tail;
6412 +
6413 +  regmask = avr32_parse_cpreglist(str, &tail);
6414 +  if (*tail)
6415 +    as_bad(_("junk at end of line: `%s'"), tail);
6416 +
6417 +  for (i = 0; i < 8; i++)
6418 +    {
6419 +      if (regmask & 1)
6420 +       {
6421 +         if (!(regmask & 2))
6422 +           {
6423 +             as_bad(_("register list `%s' doesn't fit"), str);
6424 +             break;
6425 +           }
6426 +         regmask_d |= 1 << i;
6427 +       }
6428 +      else if (regmask & 2)
6429 +       {
6430 +         as_bad(_("register list `%s' doesn't fit"), str);
6431 +         break;
6432 +       }
6433 +
6434 +      regmask >>= 2;
6435 +    }
6436 +
6437 +  slot = current_insn.next_slot++;
6438 +  current_insn.field_value[slot].value = regmask_d;
6439 +}
6440 +
6441 +static void
6442 +parse_retval(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6443 +            char *str, int opindex ATTRIBUTE_UNUSED)
6444 +{
6445 +  int regid, slot;
6446 +
6447 +  regid = avr32_parse_intreg(str);
6448 +  if (regid < 0)
6449 +    {
6450 +      expressionS exp;
6451 +      char *save;
6452 +
6453 +      regid = 0;
6454 +
6455 +      save = input_line_pointer;
6456 +      input_line_pointer = str;
6457 +      expression(&exp);
6458 +      input_line_pointer = save;
6459 +
6460 +      if (exp.X_op != O_constant)
6461 +       as_bad(_("invalid return value `%s'"), str);
6462 +      else
6463 +       switch (exp.X_add_number)
6464 +         {
6465 +         case -1:
6466 +           regid = AVR32_REG_LR;
6467 +           break;
6468 +         case 0:
6469 +           regid = AVR32_REG_SP;
6470 +           break;
6471 +         case 1:
6472 +           regid = AVR32_REG_PC;
6473 +           break;
6474 +         default:
6475 +           as_bad(_("invalid return value `%s'"), str);
6476 +           break;
6477 +         }
6478 +    }
6479 +
6480 +  slot = current_insn.next_slot++;
6481 +  current_insn.field_value[slot].value = regid;
6482 +}
6483 +
6484 +#define parse_mcall parse_intreg_disp
6485 +
6486 +static void
6487 +parse_jospinc(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6488 +             char *str, int opindex ATTRIBUTE_UNUSED)
6489 +{
6490 +  expressionS exp;
6491 +  int slot;
6492 +  char *save;
6493 +
6494 +  save = input_line_pointer;
6495 +  input_line_pointer = str;
6496 +  expression(&exp);
6497 +  input_line_pointer = save;
6498 +
6499 +  slot = current_insn.next_slot++;
6500 +
6501 +  if (exp.X_op == O_constant)
6502 +    {
6503 +      if (exp.X_add_number > 0)
6504 +       exp.X_add_number--;
6505 +      current_insn.field_value[slot].value = exp.X_add_number;
6506 +    }
6507 +  else
6508 +    as_bad(_("invalid numeric expression `%s'"), str);
6509 +}
6510 +
6511 +#define parse_coh              parse_nothing
6512 +#if 0
6513 +static void
6514 +parse_fpreg(const struct avr32_operand *op,
6515 +           char *str, int opindex ATTRIBUTE_UNUSED)
6516 +{
6517 +  unsigned long regid;
6518 +  int slot;
6519 +
6520 +  regid = strtoul(str + 2, NULL, 10);
6521 +
6522 +  if ((regid >= 16) || (regid & ((1 << op->align_order) - 1)))
6523 +    as_bad(_("invalid floating-point register `%s'"), str);
6524 +
6525 +  slot = current_insn.next_slot++;
6526 +  current_insn.field_value[slot].value = regid;
6527 +  current_insn.field_value[slot].align_order = op->align_order;
6528 +}
6529 +#endif
6530 +
6531 +static void
6532 +parse_picoreg(const struct avr32_operand *op,
6533 +             char *str, int opindex ATTRIBUTE_UNUSED)
6534 +{
6535 +  unsigned long regid;
6536 +  int slot;
6537 +
6538 +  regid = avr32_parse_picoreg(str);
6539 +  if (regid & ((1 << op->align_order) - 1))
6540 +    as_bad(_("invalid double-word PiCo register `%s'"), str);
6541 +
6542 +  slot = current_insn.next_slot++;
6543 +  current_insn.field_value[slot].value = regid;
6544 +  current_insn.field_value[slot].align_order = op->align_order;
6545 +}
6546 +
6547 +static void
6548 +parse_pico_reglist_w(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6549 +                    char *str, int opindex ATTRIBUTE_UNUSED)
6550 +{
6551 +  unsigned long regmask;
6552 +  int slot, h_bit = 0;
6553 +  char *tail;
6554 +
6555 +  regmask = avr32_parse_pico_reglist(str, &tail);
6556 +  if (*tail)
6557 +    as_bad(_("junk at end of line: `%s'"), tail);
6558 +
6559 +  if (regmask & 0x00ffUL)
6560 +    {
6561 +      if (regmask & 0xff00UL)
6562 +       as_bad(_("register list `%s' doesn't fit"), str);
6563 +      regmask &= 0x00ffUL;
6564 +    }
6565 +  else if (regmask & 0xff00UL)
6566 +    {
6567 +      regmask >>= 8;
6568 +      h_bit = 1;
6569 +    }
6570 +  else
6571 +    as_warn(_("register list is empty"));
6572 +
6573 +  slot = current_insn.next_slot++;
6574 +  current_insn.field_value[slot].value = regmask;
6575 +  slot = current_insn.next_slot++;
6576 +  current_insn.field_value[slot].value = h_bit;
6577 +}
6578 +
6579 +static void
6580 +parse_pico_reglist_d(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6581 +                    char *str, int opindex ATTRIBUTE_UNUSED)
6582 +{
6583 +  unsigned long regmask, regmask_d = 0;
6584 +  int slot, i;
6585 +  char *tail;
6586 +
6587 +  regmask = avr32_parse_pico_reglist(str, &tail);
6588 +  if (*tail)
6589 +    as_bad(_("junk at end of line: `%s'"), tail);
6590 +
6591 +  for (i = 0; i < 8; i++)
6592 +    {
6593 +      if (regmask & 1)
6594 +       {
6595 +         if (!(regmask & 2))
6596 +           {
6597 +             as_bad(_("register list `%s' doesn't fit"), str);
6598 +             break;
6599 +           }
6600 +         regmask_d |= 1 << i;
6601 +       }
6602 +      else if (regmask & 2)
6603 +       {
6604 +         as_bad(_("register list `%s' doesn't fit"), str);
6605 +         break;
6606 +       }
6607 +
6608 +      regmask >>= 2;
6609 +    }
6610 +
6611 +  slot = current_insn.next_slot++;
6612 +  current_insn.field_value[slot].value = regmask_d;
6613 +}
6614 +
6615 +static void
6616 +parse_pico_in(const struct avr32_operand *op ATTRIBUTE_UNUSED,
6617 +             char *str, int opindex ATTRIBUTE_UNUSED)
6618 +{
6619 +  unsigned long regid;
6620 +  int slot;
6621 +
6622 +  regid = strtoul(str + 2, NULL, 10);
6623 +
6624 +  if (regid >= 12)
6625 +    as_bad(_("invalid PiCo IN register `%s'"), str);
6626 +
6627 +  slot = current_insn.next_slot++;
6628 +  current_insn.field_value[slot].value = regid;
6629 +  current_insn.field_value[slot].align_order = 0;
6630 +}
6631 +
6632 +#define parse_pico_out0                parse_nothing
6633 +#define parse_pico_out1                parse_nothing
6634 +#define parse_pico_out2                parse_nothing
6635 +#define parse_pico_out3                parse_nothing
6636 +
6637 +#define OP(name, sgn, pcrel, align, func) \
6638 +  { AVR32_OPERAND_##name, sgn, pcrel, align, match_##func, parse_##func }
6639 +
6640 +struct avr32_operand avr32_operand_table[] = {
6641 +  OP(INTREG, 0, 0, 0, intreg),
6642 +  OP(INTREG_PREDEC, 0, 0, 0, intreg_predec),
6643 +  OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc),
6644 +  OP(INTREG_LSL, 0, 0, 0, intreg_lsl),
6645 +  OP(INTREG_LSR, 0, 0, 0, intreg_lsr),
6646 +  OP(INTREG_BSEL, 0, 0, 0, intreg_part),
6647 +  OP(INTREG_HSEL, 0, 0, 1, intreg_part),
6648 +  OP(INTREG_SDISP, 1, 0, 0, intreg_disp),
6649 +  OP(INTREG_SDISP_H, 1, 0, 1, intreg_disp),
6650 +  OP(INTREG_SDISP_W, 1, 0, 2, intreg_disp),
6651 +  OP(INTREG_UDISP, 0, 0, 0, intreg_disp),
6652 +  OP(INTREG_UDISP_H, 0, 0, 1, intreg_disp),
6653 +  OP(INTREG_UDISP_W, 0, 0, 2, intreg_disp),
6654 +  OP(INTREG_INDEX, 0, 0, 0, intreg_index),
6655 +  OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex),
6656 +  OP(DWREG, 0, 0, 1, intreg),
6657 +  OP(PC_UDISP_W, 0, 1, 2, pc_disp),
6658 +  OP(SP, 0, 0, 0, sp),
6659 +  OP(SP_UDISP_W, 0, 0, 2, sp_disp),
6660 +  OP(CPNO, 0, 0, 0, cpno),
6661 +  OP(CPREG, 0, 0, 0, cpreg),
6662 +  OP(CPREG_D, 0, 0, 1, cpreg),
6663 +  OP(UNSIGNED_CONST, 0, 0, 0, const),
6664 +  OP(UNSIGNED_CONST_W, 0, 0, 2, const),
6665 +  OP(SIGNED_CONST, 1, 0, 0, const),
6666 +  OP(SIGNED_CONST_W, 1, 0, 2, const),
6667 +  OP(JMPLABEL, 1, 1, 1, jmplabel),
6668 +  OP(UNSIGNED_NUMBER, 0, 0, 0, number),
6669 +  OP(UNSIGNED_NUMBER_W, 0, 0, 2, number),
6670 +  OP(REGLIST8, 0, 0, 0, reglist8),
6671 +  OP(REGLIST9, 0, 0, 0, reglist9),
6672 +  OP(REGLIST16, 0, 0, 0, reglist16),
6673 +  OP(REGLIST_LDM, 0, 0, 0, reglist_ldm),
6674 +  OP(REGLIST_CP8, 0, 0, 0, reglist_cp8),
6675 +  OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8),
6676 +  OP(RETVAL, 0, 0, 0, retval),
6677 +  OP(MCALL, 1, 0, 2, mcall),
6678 +  OP(JOSPINC, 0, 0, 0, jospinc),
6679 +  OP(COH, 0, 0, 0, coh),
6680 +  OP(PICO_REG_W, 0, 0, 0, picoreg),
6681 +  OP(PICO_REG_D, 0, 0, 1, picoreg),
6682 +  OP(PICO_REGLIST_W, 0, 0, 0, pico_reglist_w),
6683 +  OP(PICO_REGLIST_D, 0, 0, 0, pico_reglist_d),
6684 +  OP(PICO_IN, 0, 0, 0, pico_in),
6685 +  OP(PICO_OUT0, 0, 0, 0, pico_out0),
6686 +  OP(PICO_OUT1, 0, 0, 0, pico_out1),
6687 +  OP(PICO_OUT2, 0, 0, 0, pico_out2),
6688 +  OP(PICO_OUT3, 0, 0, 0, pico_out3),
6689 +};
6690 +
6691 +symbolS *
6692 +md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
6693 +{
6694 +  pr_debug("md_undefined_symbol: %s\n", name);
6695 +  return 0;
6696 +}
6697 +
6698 +struct avr32_relax_type
6699 +{
6700 +  long lower_bound;
6701 +  long upper_bound;
6702 +  unsigned char align;
6703 +  unsigned char length;
6704 +  signed short next;
6705 +};
6706 +
6707 +#define EMPTY { 0, 0, 0, 0, -1 }
6708 +#define C(lower, upper, align, next)                   \
6709 +  { (lower), (upper), (align), 2, AVR32_OPC_##next }
6710 +#define E(lower, upper, align)                         \
6711 +  { (lower), (upper), (align), 4, -1 }
6712 +
6713 +static const struct avr32_relax_type avr32_relax_table[] =
6714 +  {
6715 +    /* 0 */
6716 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6717 +    EMPTY, EMPTY, EMPTY,
6718 +    E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0), E(0, 65535, 0),
6719 +    EMPTY,
6720 +    /* 16 */
6721 +    EMPTY, EMPTY, EMPTY, EMPTY,
6722 +
6723 +    C(-256, 254, 1, BREQ2), C(-256, 254, 1, BRNE2),
6724 +    C(-256, 254, 1, BRCC2), C(-256, 254, 1, BRCS2),
6725 +    C(-256, 254, 1, BRGE2), C(-256, 254, 1, BRLT2),
6726 +    C(-256, 254, 1, BRMI2), C(-256, 254, 1, BRPL2),
6727 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6728 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6729 +    /* 32 */
6730 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6731 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6732 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6733 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6734 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6735 +    E(-2097152, 2097150, 1), E(-2097152, 2097150, 1),
6736 +
6737 +    EMPTY, EMPTY, EMPTY, EMPTY,
6738 +    /* 48 */
6739 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6740 +    EMPTY, EMPTY, EMPTY,
6741 +
6742 +    C(-32, 31, 0, CP_W3), E(-1048576, 1048575, 0),
6743 +
6744 +    EMPTY, EMPTY, EMPTY,
6745 +    /* 64: csrfcz */
6746 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6747 +    E(0, 65535, 0), E(0, 65535, 0),
6748 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6749 +    E(-32768, 32767, 0),
6750 +    /* 80: LD_SB2 */
6751 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6752 +
6753 +    C(0, 7, 0, LD_UB4), E(-32768, 32767, 0),
6754 +
6755 +    EMPTY,
6756 +    EMPTY, EMPTY,
6757 +
6758 +    C(0, 14, 1, LD_SH4), E(-32768, 32767, 0),
6759 +
6760 +    EMPTY, EMPTY, EMPTY,
6761 +
6762 +    C(0, 14, 1, LD_UH4),
6763 +
6764 +    /* 96: LD_UH4 */
6765 +    E(-32768, 32767, 0),
6766 +
6767 +    EMPTY, EMPTY, EMPTY, EMPTY,
6768 +
6769 +    C(0, 124, 2, LD_W4), E(-32768, 32767, 0),
6770 +
6771 +    E(0, 1020, 2),     /* LDC_D1 */
6772 +    EMPTY, EMPTY,
6773 +    E(0, 1020, 2),     /* LDC_W1 */
6774 +    EMPTY, EMPTY,
6775 +    E(0, 16380, 2),    /* LDC0_D */
6776 +    E(0, 16380, 2),    /* LDC0_W */
6777 +    EMPTY,
6778 +
6779 +    /* 112: LDCM_D_PU */
6780 +    EMPTY, EMPTY, EMPTY,
6781 +
6782 +    C(0, 508, 2, LDDPC_EXT), E(-32768, 32767, 0),
6783 +
6784 +    EMPTY,EMPTY, EMPTY,
6785 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6786 +
6787 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6788 +    /* 134: MACHH_W */
6789 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6790 +    E(-131072, 131068, 2),     /* MCALL */
6791 +    E(0, 1020, 2),             /* MFDR */
6792 +    E(0, 1020, 2),             /* MFSR */
6793 +    EMPTY, EMPTY,
6794 +
6795 +    C(-128, 127, 0, MOV2), E(-1048576, 1048575, 0),
6796 +
6797 +    EMPTY, EMPTY, EMPTY,
6798 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6799 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6800 +
6801 +    E(-128, 127, 0),           /* MOVEQ2 */
6802 +    E(-128, 127, 0),           /* MOVNE2 */
6803 +    E(-128, 127, 0),           /* MOVCC2 */
6804 +    E(-128, 127, 0),           /* 166: MOVCS2 */
6805 +    E(-128, 127, 0),           /* MOVGE2 */
6806 +    E(-128, 127, 0),           /* MOVLT2 */
6807 +    E(-128, 127, 0),           /* MOVMI2 */
6808 +    E(-128, 127, 0),           /* MOVPL2 */
6809 +    E(-128, 127, 0),           /* MOVLS2 */
6810 +    E(-128, 127, 0),           /* MOVGT2 */
6811 +    E(-128, 127, 0),           /* MOVLE2 */
6812 +    E(-128, 127, 0),           /* MOVHI2 */
6813 +    E(-128, 127, 0),           /* MOVVS2 */
6814 +    E(-128, 127, 0),           /* MOVVC2 */
6815 +    E(-128, 127, 0),           /* MOVQS2 */
6816 +    E(-128, 127, 0),           /* MOVAL2 */
6817 +
6818 +    E(0, 1020, 2),             /* MTDR */
6819 +    E(0, 1020, 2),             /* MTSR */
6820 +    EMPTY,
6821 +    EMPTY,
6822 +    E(-128, 127, 0),           /* MUL3 */
6823 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6824 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6825 +    /* 198: MVCR_W */
6826 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6827 +    E(0, 65535, 0), E(0, 65535, 0),
6828 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6829 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6830 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6831 +    /* 230: PASR_H */
6832 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6833 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6834 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6835 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6836 +    /* 262: PUNPCKSB_H */
6837 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6838 +
6839 +    C(-1024, 1022, 1, RCALL2), E(-2097152, 2097150, 1),
6840 +
6841 +    EMPTY,
6842 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6843 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6844 +    EMPTY, EMPTY, EMPTY,
6845 +
6846 +    C(-1024, 1022, 1, BRAL),
6847 +
6848 +    EMPTY, EMPTY, EMPTY,
6849 +    E(-128, 127, 0),           /* RSUB2 */
6850 +    /* 294: SATADD_H */
6851 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6852 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6853 +    E(0, 255, 0),              /* SLEEP */
6854 +    EMPTY, EMPTY,
6855 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6856 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6857 +    /* 326: ST_B2 */
6858 +    EMPTY, EMPTY,
6859 +    C(0, 7, 0, ST_B4), E(-32768, 32767, 0),
6860 +    EMPTY, EMPTY, EMPTY, EMPTY,
6861 +    E(-32768, 32767, 0),
6862 +    EMPTY, EMPTY, EMPTY,
6863 +    C(0, 14, 1, ST_H4), E(-32768, 32767, 0),
6864 +    EMPTY, EMPTY,
6865 +    EMPTY,
6866 +    C(0, 60, 2, ST_W4), E(-32768, 32767, 0),
6867 +    E(0, 1020, 2),     /* STC_D1 */
6868 +    EMPTY, EMPTY,
6869 +    E(0, 1020, 2),     /* STC_W1 */
6870 +    EMPTY, EMPTY,
6871 +    E(0, 16380, 2),    /* STC0_D */
6872 +    E(0, 16380, 2),    /* STC0_W */
6873 +
6874 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6875 +    /* 358: STDSP */
6876 +    EMPTY, EMPTY,
6877 +    E(0, 1020, 2),     /* STHH_W1 */
6878 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6879 +    EMPTY, EMPTY, EMPTY,
6880 +    E(-32768, 32767, 0),
6881 +    C(-512, 508, 2, SUB4),
6882 +    C(-128, 127, 0, SUB4), E(-1048576, 1048576, 0),
6883 +    /* SUB{cond} */
6884 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6885 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6886 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6887 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6888 +    /* SUBF{cond} */
6889 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6890 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6891 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6892 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6893 +    EMPTY,
6894 +
6895 +    /* 406: SWAP_B */
6896 +    EMPTY, EMPTY, EMPTY,
6897 +    E(0, 255, 0),      /* SYNC */
6898 +    EMPTY, EMPTY, EMPTY, EMPTY,
6899 +    /* 414: TST */
6900 +    EMPTY, EMPTY, E(-65536, 65535, 2), E(-65536, 65535, 2), E(-65536, 65535, 2), EMPTY, EMPTY, EMPTY,
6901 +    /* 422: RSUB{cond} */
6902 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6903 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6904 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6905 +    E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0), E(-128, 127, 0),
6906 +    /* 436: ADD{cond} */
6907 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6908 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6909 +    /* 454: SUB{cond} */
6910 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6911 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6912 +    /* 472: AND{cond} */
6913 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6914 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6915 +    /* 486: OR{cond} */
6916 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6917 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6918 +    /* 502: EOR{cond} */
6919 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6920 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6921 +    /* 518: LD.w{cond} */
6922 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6923 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6924 +    /* 534: LD.sh{cond} */
6925 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6926 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6927 +    /* 550: LD.uh{cond} */
6928 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6929 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6930 +    /* 566: LD.sb{cond} */
6931 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6932 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6933 +    /* 582: LD.ub{cond} */
6934 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6935 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6936 +    /* 596: ST.w{cond} */
6937 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6938 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6939 +    /* 614: ST.h{cond} */
6940 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6941 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6942 +    /* 630: ST.b{cond} */
6943 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6944 +    EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6945 +    /* 646: movh */
6946 +    E(0, 65535, 0), EMPTY, EMPTY,
6947 +  /* 649: fmac.s */
6948 +  EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6949 +  EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, EMPTY,
6950 +  };
6951 +
6952 +#undef E
6953 +#undef C
6954 +#undef EMPTY
6955 +
6956 +#define AVR32_RS_NONE (-1)
6957 +
6958 +#define avr32_rs_size(state) (avr32_relax_table[(state)].length)
6959 +#define avr32_rs_align(state) (avr32_relax_table[(state)].align)
6960 +#define relax_more(state) (avr32_relax_table[(state)].next)
6961 +
6962 +#define opc_initial_substate(opc) ((opc)->id)
6963 +
6964 +static int need_relax(int subtype, offsetT distance)
6965 +{
6966 +  offsetT upper_bound, lower_bound;
6967 +
6968 +  upper_bound = avr32_relax_table[subtype].upper_bound;
6969 +  lower_bound = avr32_relax_table[subtype].lower_bound;
6970 +
6971 +  if (distance & ((1 << avr32_rs_align(subtype)) - 1))
6972 +    return 1;
6973 +  if ((distance > upper_bound) || (distance < lower_bound))
6974 +    return 1;
6975 +
6976 +  return 0;
6977 +}
6978 +
6979 +enum {
6980 +  LDA_SUBTYPE_MOV1,
6981 +  LDA_SUBTYPE_MOV2,
6982 +  LDA_SUBTYPE_SUB,
6983 +  LDA_SUBTYPE_LDDPC,
6984 +  LDA_SUBTYPE_LDW,
6985 +  LDA_SUBTYPE_GOTLOAD,
6986 +  LDA_SUBTYPE_GOTLOAD_LARGE,
6987 +};
6988 +
6989 +enum {
6990 +  CALL_SUBTYPE_RCALL1,
6991 +  CALL_SUBTYPE_RCALL2,
6992 +  CALL_SUBTYPE_MCALL_CP,
6993 +  CALL_SUBTYPE_MCALL_GOT,
6994 +  CALL_SUBTYPE_MCALL_LARGE,
6995 +};
6996 +
6997 +#define LDA_INITIAL_SIZE       (avr32_pic ? 4 : 2)
6998 +#define CALL_INITIAL_SIZE      2
6999 +
7000 +#define need_reloc(sym, seg, pcrel)                                    \
7001 +  (!(S_IS_DEFINED(sym)                                                 \
7002 +     && ((pcrel && S_GET_SEGMENT(sym) == seg)                          \
7003 +        || (!pcrel && S_GET_SEGMENT(sym) == absolute_section)))        \
7004 +   || S_FORCE_RELOC(sym, 1))
7005 +
7006 +/* Return an initial guess of the length by which a fragment must grow to
7007 +   hold a branch to reach its destination.
7008 +   Also updates fr_type/fr_subtype as necessary.
7009 +
7010 +   Called just before doing relaxation.
7011 +   Any symbol that is now undefined will not become defined.
7012 +   The guess for fr_var is ACTUALLY the growth beyond fr_fix.
7013 +   Whatever we do to grow fr_fix or fr_var contributes to our returned value.
7014 +   Although it may not be explicit in the frag, pretend fr_var starts with a
7015 +   0 value.  */
7016 +
7017 +static int
7018 +avr32_default_estimate_size_before_relax (fragS *fragP, segT segment)
7019 +{
7020 +  int growth = 0;
7021 +
7022 +  assert(fragP);
7023 +  assert(fragP->fr_symbol);
7024 +
7025 +  if (fragP->tc_frag_data.force_extended
7026 +      || need_reloc(fragP->fr_symbol, segment, fragP->tc_frag_data.pcrel))
7027 +    {
7028 +      int largest_state = fragP->fr_subtype;
7029 +      while (relax_more(largest_state) != AVR32_RS_NONE)
7030 +       largest_state = relax_more(largest_state);
7031 +      growth = avr32_rs_size(largest_state) - fragP->fr_var;
7032 +    }
7033 +  else
7034 +    {
7035 +      growth = avr32_rs_size(fragP->fr_subtype) - fragP->fr_var;
7036 +    }
7037 +
7038 +  pr_debug("%s:%d: md_estimate_size_before_relax: %d\n",
7039 +          fragP->fr_file, fragP->fr_line, growth);
7040 +
7041 +  return growth;
7042 +}
7043 +
7044 +static int
7045 +avr32_lda_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED)
7046 +{
7047 +  return fragP->fr_var - LDA_INITIAL_SIZE;
7048 +}
7049 +
7050 +static int
7051 +avr32_call_estimate_size_before_relax(fragS *fragP, segT segment ATTRIBUTE_UNUSED)
7052 +{
7053 +  return fragP->fr_var - CALL_INITIAL_SIZE;
7054 +}
7055 +
7056 +static int
7057 +avr32_cpool_estimate_size_before_relax(fragS *fragP,
7058 +                                      segT segment ATTRIBUTE_UNUSED)
7059 +{
7060 +  return fragP->fr_var;
7061 +}
7062 +
7063 +/* This macro may be defined to relax a frag. GAS will call this with the
7064 + * segment, the frag, and the change in size of all previous frags;
7065 + * md_relax_frag should return the change in size of the frag. */
7066 +static long
7067 +avr32_default_relax_frag (segT segment, fragS *fragP, long stretch)
7068 +{
7069 +  int state, next_state;
7070 +  symbolS *symbolP;    /* The target symbol */
7071 +  long growth = 0;
7072 +
7073 +  state = next_state = fragP->fr_subtype;
7074 +
7075 +  symbolP = fragP->fr_symbol;
7076 +
7077 +  if (fragP->tc_frag_data.force_extended
7078 +      || need_reloc(symbolP, segment, fragP->tc_frag_data.pcrel))
7079 +    {
7080 +      /* Symbol must be resolved by the linker. Emit the largest
7081 +        possible opcode. */
7082 +      while (relax_more(next_state) != AVR32_RS_NONE)
7083 +       next_state = relax_more(next_state);
7084 +    }
7085 +  else
7086 +    {
7087 +      addressT address;        /* The address of fragP */
7088 +      addressT target; /* The address of the target symbol */
7089 +      offsetT distance;        /* The distance between the insn and the symbol */
7090 +      fragS *sym_frag;
7091 +
7092 +      address = fragP->fr_address;
7093 +      target = fragP->fr_offset;
7094 +      symbolP = fragP->fr_symbol;
7095 +      sym_frag = symbol_get_frag(symbolP);
7096 +
7097 +      address += fragP->fr_fix - fragP->fr_var;
7098 +      target += S_GET_VALUE(symbolP);
7099 +
7100 +      if (stretch != 0
7101 +         && sym_frag->relax_marker != fragP->relax_marker
7102 +         && S_GET_SEGMENT(symbolP) == segment)
7103 +       /* if it was correctly aligned before, make sure it stays aligned */
7104 +       target += stretch & (~0UL << avr32_rs_align(state));
7105 +
7106 +      if (fragP->tc_frag_data.pcrel)
7107 +       distance = target - (address & (~0UL << avr32_rs_align(state)));
7108 +      else
7109 +       distance = target;
7110 +
7111 +      pr_debug("%s:%d: relax more? 0x%x - 0x%x = 0x%x (%d), align %d\n",
7112 +              fragP->fr_file, fragP->fr_line, target, address,
7113 +              distance, distance, avr32_rs_align(state));
7114 +
7115 +      if (need_relax(state, distance))
7116 +       {
7117 +         if (relax_more(state) != AVR32_RS_NONE)
7118 +           next_state = relax_more(state);
7119 +         pr_debug("%s:%d: relax more %d -> %d (%d - %d, align %d)\n",
7120 +                  fragP->fr_file, fragP->fr_line, state, next_state,
7121 +                  target, address, avr32_rs_align(state));
7122 +       }
7123 +    }
7124 +
7125 +  growth = avr32_rs_size(next_state) - avr32_rs_size(state);
7126 +  fragP->fr_subtype = next_state;
7127 +
7128 +  pr_debug("%s:%d: md_relax_frag: growth=%d, subtype=%d, opc=0x%08lx\n",
7129 +          fragP->fr_file, fragP->fr_line, growth, fragP->fr_subtype,
7130 +          avr32_opc_table[next_state].value);
7131 +
7132 +  return growth;
7133 +}
7134 +
7135 +static long
7136 +avr32_lda_relax_frag(segT segment, fragS *fragP, long stretch)
7137 +{
7138 +  struct cpool *pool= NULL;
7139 +  unsigned int entry = 0;
7140 +  addressT address, target;
7141 +  offsetT distance;
7142 +  symbolS *symbolP;
7143 +  fragS *sym_frag;
7144 +  long old_size, new_size;
7145 +
7146 +  symbolP = fragP->fr_symbol;
7147 +  old_size = fragP->fr_var;
7148 +  if (!avr32_pic)
7149 +    {
7150 +      pool = fragP->tc_frag_data.pool;
7151 +      entry = fragP->tc_frag_data.pool_entry;
7152 +    }
7153 +
7154 +  address = fragP->fr_address;
7155 +  address += fragP->fr_fix - LDA_INITIAL_SIZE;
7156 +
7157 +  if (!S_IS_DEFINED(symbolP) || S_FORCE_RELOC(symbolP, 1))
7158 +    goto relax_max;
7159 +
7160 +  target = fragP->fr_offset;
7161 +  sym_frag = symbol_get_frag(symbolP);
7162 +  target += S_GET_VALUE(symbolP);
7163 +
7164 +  if (sym_frag->relax_marker != fragP->relax_marker
7165 +      && S_GET_SEGMENT(symbolP) == segment)
7166 +    target += stretch;
7167 +
7168 +  distance = target - address;
7169 +
7170 +  pr_debug("lda_relax_frag: target: %d, address: %d, var: %d\n",
7171 +          target, address, fragP->fr_var);
7172 +
7173 +  if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section
7174 +      && target <= 127 && (offsetT)target >= -128)
7175 +    {
7176 +      if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
7177 +         || fragP->fr_subtype == LDA_SUBTYPE_LDW)
7178 +       pool->literals[entry].refcount--;
7179 +      new_size = 2;
7180 +      fragP->fr_subtype = LDA_SUBTYPE_MOV1;
7181 +    }
7182 +  else if (!avr32_pic && S_GET_SEGMENT(symbolP) == absolute_section
7183 +          && target <= 1048575 && (offsetT)target >= -1048576)
7184 +    {
7185 +      if (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
7186 +         || fragP->fr_subtype == LDA_SUBTYPE_LDW)
7187 +       pool->literals[entry].refcount--;
7188 +      new_size = 4;
7189 +      fragP->fr_subtype = LDA_SUBTYPE_MOV2;
7190 +    }
7191 +  else if (!linkrelax && S_GET_SEGMENT(symbolP) == segment
7192 +          /* the field will be negated, so this is really -(-32768)
7193 +             and -(32767) */
7194 +          && distance <= 32768 && distance >= -32767)
7195 +    {
7196 +      if (!avr32_pic
7197 +         && (fragP->fr_subtype == LDA_SUBTYPE_LDDPC
7198 +             || fragP->fr_subtype == LDA_SUBTYPE_LDW))
7199 +       pool->literals[entry].refcount--;
7200 +      new_size = 4;
7201 +      fragP->fr_subtype = LDA_SUBTYPE_SUB;
7202 +    }
7203 +  else
7204 +    {
7205 +    relax_max:
7206 +      if (avr32_pic)
7207 +       {
7208 +         if (linkrelax)
7209 +           {
7210 +             new_size = 8;
7211 +             fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD_LARGE;
7212 +           }
7213 +         else
7214 +           {
7215 +             new_size = 4;
7216 +             fragP->fr_subtype = LDA_SUBTYPE_GOTLOAD;
7217 +           }
7218 +       }
7219 +      else
7220 +       {
7221 +         if (fragP->fr_subtype != LDA_SUBTYPE_LDDPC
7222 +             && fragP->fr_subtype != LDA_SUBTYPE_LDW)
7223 +           pool->literals[entry].refcount++;
7224 +
7225 +         sym_frag = symbol_get_frag(pool->symbol);
7226 +         target = (sym_frag->fr_address + sym_frag->fr_fix
7227 +                   + pool->padding + pool->literals[entry].offset);
7228 +
7229 +         pr_debug("cpool sym address: 0x%lx\n",
7230 +                  sym_frag->fr_address + sym_frag->fr_fix);
7231 +
7232 +         know(pool->section == segment);
7233 +
7234 +         if (sym_frag->relax_marker != fragP->relax_marker)
7235 +           target += stretch;
7236 +
7237 +         distance = target - address;
7238 +         if (distance <= 508 && distance >= 0)
7239 +           {
7240 +             new_size = 2;
7241 +             fragP->fr_subtype = LDA_SUBTYPE_LDDPC;
7242 +           }
7243 +         else
7244 +           {
7245 +             new_size = 4;
7246 +             fragP->fr_subtype = LDA_SUBTYPE_LDW;
7247 +           }
7248 +
7249 +         pr_debug("lda_relax_frag (cpool): target=0x%lx, address=0x%lx, refcount=%d\n",
7250 +                  target, address, pool->literals[entry].refcount);
7251 +       }
7252 +    }
7253 +
7254 +  fragP->fr_var = new_size;
7255 +
7256 +  pr_debug("%s:%d: lda: relax pass done. subtype: %d, growth: %ld\n",
7257 +          fragP->fr_file, fragP->fr_line,
7258 +          fragP->fr_subtype, new_size - old_size);
7259 +
7260 +  return new_size - old_size;
7261 +}
7262 +
7263 +static long
7264 +avr32_call_relax_frag(segT segment, fragS *fragP, long stretch)
7265 +{
7266 +  struct cpool *pool = NULL;
7267 +  unsigned int entry = 0;
7268 +  addressT address, target;
7269 +  offsetT distance;
7270 +  symbolS *symbolP;
7271 +  fragS *sym_frag;
7272 +  long old_size, new_size;
7273 +
7274 +  symbolP = fragP->fr_symbol;
7275 +  old_size = fragP->fr_var;
7276 +  if (!avr32_pic)
7277 +    {
7278 +      pool = fragP->tc_frag_data.pool;
7279 +      entry = fragP->tc_frag_data.pool_entry;
7280 +    }
7281 +
7282 +  address = fragP->fr_address;
7283 +  address += fragP->fr_fix - CALL_INITIAL_SIZE;
7284 +
7285 +  if (need_reloc(symbolP, segment, 1))
7286 +    {
7287 +      pr_debug("call: must emit reloc\n");
7288 +      goto relax_max;
7289 +    }
7290 +
7291 +  target = fragP->fr_offset;
7292 +  sym_frag = symbol_get_frag(symbolP);
7293 +  target += S_GET_VALUE(symbolP);
7294 +
7295 +  if (sym_frag->relax_marker != fragP->relax_marker
7296 +      && S_GET_SEGMENT(symbolP) == segment)
7297 +    target += stretch;
7298 +
7299 +  distance = target - address;
7300 +
7301 +  if (distance <= 1022 && distance >= -1024)
7302 +    {
7303 +      pr_debug("call: distance is %d, emitting short rcall\n", distance);
7304 +      if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP)
7305 +       pool->literals[entry].refcount--;
7306 +      new_size = 2;
7307 +      fragP->fr_subtype = CALL_SUBTYPE_RCALL1;
7308 +    }
7309 +  else if (distance <= 2097150 && distance >= -2097152)
7310 +    {
7311 +      pr_debug("call: distance is %d, emitting long rcall\n", distance);
7312 +      if (!avr32_pic && fragP->fr_subtype == CALL_SUBTYPE_MCALL_CP)
7313 +       pool->literals[entry].refcount--;
7314 +      new_size = 4;
7315 +      fragP->fr_subtype = CALL_SUBTYPE_RCALL2;
7316 +    }
7317 +  else
7318 +    {
7319 +      pr_debug("call: distance %d too far, emitting something big\n", distance);
7320 +
7321 +    relax_max:
7322 +      if (avr32_pic)
7323 +       {
7324 +         if (linkrelax)
7325 +           {
7326 +             new_size = 10;
7327 +             fragP->fr_subtype = CALL_SUBTYPE_MCALL_LARGE;
7328 +           }
7329 +         else
7330 +           {
7331 +             new_size = 4;
7332 +             fragP->fr_subtype = CALL_SUBTYPE_MCALL_GOT;
7333 +           }
7334 +       }
7335 +      else
7336 +       {
7337 +         if (fragP->fr_subtype != CALL_SUBTYPE_MCALL_CP)
7338 +           pool->literals[entry].refcount++;
7339 +
7340 +         new_size = 4;
7341 +         fragP->fr_subtype = CALL_SUBTYPE_MCALL_CP;
7342 +       }
7343 +    }
7344 +
7345 +  fragP->fr_var = new_size;
7346 +
7347 +  pr_debug("%s:%d: call: relax pass done, growth: %d, fr_var: %d\n",
7348 +          fragP->fr_file, fragP->fr_line,
7349 +          new_size - old_size, fragP->fr_var);
7350 +
7351 +  return new_size - old_size;
7352 +}
7353 +
7354 +static long
7355 +avr32_cpool_relax_frag(segT segment ATTRIBUTE_UNUSED,
7356 +                      fragS *fragP,
7357 +                      long stretch ATTRIBUTE_UNUSED)
7358 +{
7359 +  struct cpool *pool;
7360 +  addressT address;
7361 +  long old_size, new_size;
7362 +  unsigned int entry;
7363 +
7364 +  pool = fragP->tc_frag_data.pool;
7365 +  address = fragP->fr_address + fragP->fr_fix;
7366 +  old_size = fragP->fr_var;
7367 +  new_size = 0;
7368 +
7369 +  for (entry = 0; entry < pool->next_free_entry; entry++)
7370 +    {
7371 +      if (pool->literals[entry].refcount > 0)
7372 +       {
7373 +         pool->literals[entry].offset = new_size;
7374 +         new_size += 4;
7375 +       }
7376 +    }
7377 +
7378 +  fragP->fr_var = new_size;
7379 +
7380 +  return new_size - old_size;
7381 +}
7382 +
7383 +/* *fragP has been relaxed to its final size, and now needs to have
7384 +   the bytes inside it modified to conform to the new size.
7385 +
7386 +   Called after relaxation is finished.
7387 +   fragP->fr_type == rs_machine_dependent.
7388 +   fragP->fr_subtype is the subtype of what the address relaxed to.  */
7389 +
7390 +static void
7391 +avr32_default_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
7392 +                           segT segment ATTRIBUTE_UNUSED,
7393 +                           fragS *fragP)
7394 +{
7395 +  const struct avr32_opcode *opc;
7396 +  const struct avr32_ifield *ifield;
7397 +  bfd_reloc_code_real_type r_type;
7398 +  symbolS *symbolP;
7399 +  fixS *fixP;
7400 +  bfd_vma value;
7401 +  int subtype;
7402 +
7403 +  opc = &avr32_opc_table[fragP->fr_subtype];
7404 +  ifield = opc->fields[opc->var_field];
7405 +  symbolP = fragP->fr_symbol;
7406 +  subtype = fragP->fr_subtype;
7407 +  r_type = opc->reloc_type;
7408 +
7409 +  /* Clear the opcode bits and the bits belonging to the relaxed
7410 +     field.  We assume all other fields stay the same.  */
7411 +  value = bfd_getb32(fragP->fr_opcode);
7412 +  value &= ~(opc->mask | ifield->mask);
7413 +
7414 +  /* Insert the new opcode */
7415 +  value |= opc->value;
7416 +  bfd_putb32(value, fragP->fr_opcode);
7417 +
7418 +  fragP->fr_fix += opc->size - fragP->fr_var;
7419 +
7420 +  if (fragP->tc_frag_data.reloc_info != AVR32_OPINFO_NONE)
7421 +    {
7422 +      switch (fragP->tc_frag_data.reloc_info)
7423 +       {
7424 +       case AVR32_OPINFO_HI:
7425 +         r_type = BFD_RELOC_HI16;
7426 +         break;
7427 +       case AVR32_OPINFO_LO:
7428 +         r_type = BFD_RELOC_LO16;
7429 +         break;
7430 +       case AVR32_OPINFO_GOT:
7431 +         switch (r_type)
7432 +           {
7433 +           case BFD_RELOC_AVR32_18W_PCREL:
7434 +             r_type = BFD_RELOC_AVR32_GOT18SW;
7435 +             break;
7436 +           case BFD_RELOC_AVR32_16S:
7437 +             r_type = BFD_RELOC_AVR32_GOT16S;
7438 +             break;
7439 +           default:
7440 +             BAD_CASE(r_type);
7441 +             break;
7442 +           }
7443 +         break;
7444 +       default:
7445 +         BAD_CASE(fragP->tc_frag_data.reloc_info);
7446 +         break;
7447 +       }
7448 +    }
7449 +
7450 +  pr_debug("%s:%d: convert_frag: new %s fixup\n",
7451 +          fragP->fr_file, fragP->fr_line,
7452 +          bfd_get_reloc_code_name(r_type));
7453 +
7454 +#if 1
7455 +  fixP = fix_new_exp(fragP, fragP->fr_fix - opc->size, opc->size,
7456 +                    &fragP->tc_frag_data.exp,
7457 +                    fragP->tc_frag_data.pcrel, r_type);
7458 +#else
7459 +  fixP = fix_new(fragP, fragP->fr_fix - opc->size, opc->size, symbolP,
7460 +                fragP->fr_offset, fragP->tc_frag_data.pcrel, r_type);
7461 +#endif
7462 +
7463 +  /* Revert fix_new brain damage. "dot_value" is the value of PC at
7464 +     the point of the fixup, relative to the frag address.  fix_new()
7465 +     and friends think they are only being called during the assembly
7466 +     pass, not during relaxation or similar, so fx_dot_value, fx_file
7467 +     and fx_line are all initialized to the wrong value.  But we don't
7468 +     know the size of the fixup until now, so we really can't live up
7469 +     to the assumptions these functions make about the target.  What
7470 +     do these functions think the "where" and "frag" argument mean
7471 +     anyway?  */
7472 +  fixP->fx_dot_value = fragP->fr_fix - opc->size;
7473 +  fixP->fx_file = fragP->fr_file;
7474 +  fixP->fx_line = fragP->fr_line;
7475 +
7476 +  fixP->tc_fix_data.ifield = ifield;
7477 +  fixP->tc_fix_data.align = avr32_rs_align(subtype);
7478 +  fixP->tc_fix_data.min = avr32_relax_table[subtype].lower_bound;
7479 +  fixP->tc_fix_data.max = avr32_relax_table[subtype].upper_bound;
7480 +}
7481 +
7482 +static void
7483 +avr32_lda_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7484 +                      segT segment ATTRIBUTE_UNUSED,
7485 +                      fragS *fragP)
7486 +{
7487 +  const struct avr32_opcode *opc;
7488 +  const struct avr32_ifield *ifield;
7489 +  bfd_reloc_code_real_type r_type;
7490 +  expressionS exp;
7491 +  struct cpool *pool;
7492 +  fixS *fixP;
7493 +  bfd_vma value;
7494 +  int regid, pcrel = 0, align = 0;
7495 +  char *p;
7496 +
7497 +  r_type = BFD_RELOC_NONE;
7498 +  regid = fragP->tc_frag_data.reloc_info;
7499 +  p = fragP->fr_opcode;
7500 +  exp.X_add_symbol = fragP->fr_symbol;
7501 +  exp.X_add_number = fragP->fr_offset;
7502 +  exp.X_op = O_symbol;
7503 +
7504 +  pr_debug("%s:%d: lda_convert_frag, subtype: %d, fix: %d, var: %d, regid: %d\n",
7505 +          fragP->fr_file, fragP->fr_line,
7506 +          fragP->fr_subtype, fragP->fr_fix, fragP->fr_var, regid);
7507 +
7508 +  switch (fragP->fr_subtype)
7509 +    {
7510 +    case LDA_SUBTYPE_MOV1:
7511 +      opc = &avr32_opc_table[AVR32_OPC_MOV1];
7512 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7513 +      ifield = opc->fields[1];
7514 +      r_type = opc->reloc_type;
7515 +      break;
7516 +    case LDA_SUBTYPE_MOV2:
7517 +      opc = &avr32_opc_table[AVR32_OPC_MOV2];
7518 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7519 +      ifield = opc->fields[1];
7520 +      r_type = opc->reloc_type;
7521 +      break;
7522 +    case LDA_SUBTYPE_SUB:
7523 +      opc = &avr32_opc_table[AVR32_OPC_SUB5];
7524 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7525 +      opc->fields[1]->insert(opc->fields[1], p, AVR32_REG_PC);
7526 +      ifield = opc->fields[2];
7527 +      r_type = BFD_RELOC_AVR32_16N_PCREL;
7528 +
7529 +      /* Pretend that SUB5 isn't a "negated" pcrel expression for now.
7530 +        We'll have to fix it up later when we know whether to
7531 +        generate a reloc for it (in which case the linker will negate
7532 +        it, so we shouldn't). */
7533 +      pcrel = 1;
7534 +      break;
7535 +    case LDA_SUBTYPE_LDDPC:
7536 +      opc = &avr32_opc_table[AVR32_OPC_LDDPC];
7537 +      align = 2;
7538 +      r_type = BFD_RELOC_AVR32_9W_CP;
7539 +      goto cpool_common;
7540 +    case LDA_SUBTYPE_LDW:
7541 +      opc = &avr32_opc_table[AVR32_OPC_LDDPC_EXT];
7542 +      r_type = BFD_RELOC_AVR32_16_CP;
7543 +    cpool_common:
7544 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7545 +      ifield = opc->fields[1];
7546 +      pool = fragP->tc_frag_data.pool;
7547 +      exp.X_add_symbol = pool->symbol;
7548 +      exp.X_add_number = pool->literals[fragP->tc_frag_data.pool_entry].offset;
7549 +      pcrel = 1;
7550 +      break;
7551 +    case LDA_SUBTYPE_GOTLOAD_LARGE:
7552 +      /* ld.w Rd, r6[Rd << 2] (last) */
7553 +      opc = &avr32_opc_table[AVR32_OPC_LD_W5];
7554 +      bfd_putb32(opc->value, p + 4);
7555 +      opc->fields[0]->insert(opc->fields[0], p + 4, regid);
7556 +      opc->fields[1]->insert(opc->fields[1], p + 4, 6);
7557 +      opc->fields[2]->insert(opc->fields[2], p + 4, regid);
7558 +      opc->fields[3]->insert(opc->fields[3], p + 4, 2);
7559 +
7560 +      /* mov Rd, (got_offset / 4) */
7561 +      opc = &avr32_opc_table[AVR32_OPC_MOV2];
7562 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7563 +      ifield = opc->fields[1];
7564 +      r_type = BFD_RELOC_AVR32_LDA_GOT;
7565 +      break;
7566 +    case LDA_SUBTYPE_GOTLOAD:
7567 +      opc = &avr32_opc_table[AVR32_OPC_LD_W4];
7568 +      opc->fields[0]->insert(opc->fields[0], p, regid);
7569 +      opc->fields[1]->insert(opc->fields[1], p, 6);
7570 +      ifield = opc->fields[2];
7571 +      if (r_type == BFD_RELOC_NONE)
7572 +       r_type = BFD_RELOC_AVR32_GOT16S;
7573 +      break;
7574 +    default:
7575 +      BAD_CASE(fragP->fr_subtype);
7576 +    }
7577 +
7578 +  value = bfd_getb32(p);
7579 +  value &= ~(opc->mask | ifield->mask);
7580 +  value |= opc->value;
7581 +  bfd_putb32(value, p);
7582 +
7583 +  fragP->fr_fix += fragP->fr_var - LDA_INITIAL_SIZE;
7584 +
7585 +  if (fragP->fr_next
7586 +      && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address)
7587 +         != fragP->fr_fix))
7588 +    {
7589 +      fprintf(stderr, "LDA frag: fr_fix is wrong! fragP->fr_var = %ld, r_type = %s\n",
7590 +             fragP->fr_var, bfd_get_reloc_code_name(r_type));
7591 +      abort();
7592 +    }
7593 +
7594 +  fixP = fix_new_exp(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var,
7595 +                    &exp, pcrel, r_type);
7596 +
7597 +  /* Revert fix_new brain damage. "dot_value" is the value of PC at
7598 +     the point of the fixup, relative to the frag address.  fix_new()
7599 +     and friends think they are only being called during the assembly
7600 +     pass, not during relaxation or similar, so fx_dot_value, fx_file
7601 +     and fx_line are all initialized to the wrong value.  But we don't
7602 +     know the size of the fixup until now, so we really can't live up
7603 +     to the assumptions these functions make about the target.  What
7604 +     do these functions think the "where" and "frag" argument mean
7605 +     anyway?  */
7606 +  fixP->fx_dot_value = fragP->fr_fix - opc->size;
7607 +  fixP->fx_file = fragP->fr_file;
7608 +  fixP->fx_line = fragP->fr_line;
7609 +
7610 +  fixP->tc_fix_data.ifield = ifield;
7611 +  fixP->tc_fix_data.align = align;
7612 +  /* these are only used if the fixup can actually be resolved */
7613 +  fixP->tc_fix_data.min = -32768;
7614 +  fixP->tc_fix_data.max = 32767;
7615 +}
7616 +
7617 +static void
7618 +avr32_call_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7619 +                      segT segment ATTRIBUTE_UNUSED,
7620 +                      fragS *fragP)
7621 +{
7622 +  const struct avr32_opcode *opc = NULL;
7623 +  const struct avr32_ifield *ifield;
7624 +  bfd_reloc_code_real_type r_type;
7625 +  symbolS *symbol;
7626 +  offsetT offset;
7627 +  fixS *fixP;
7628 +  bfd_vma value;
7629 +  int pcrel = 0, align = 0;
7630 +  char *p;
7631 +
7632 +  symbol = fragP->fr_symbol;
7633 +  offset = fragP->fr_offset;
7634 +  r_type = BFD_RELOC_NONE;
7635 +  p = fragP->fr_opcode;
7636 +
7637 +  pr_debug("%s:%d: call_convert_frag, subtype: %d, fix: %d, var: %d\n",
7638 +          fragP->fr_file, fragP->fr_line,
7639 +          fragP->fr_subtype, fragP->fr_fix, fragP->fr_var);
7640 +
7641 +  switch (fragP->fr_subtype)
7642 +    {
7643 +    case CALL_SUBTYPE_RCALL1:
7644 +      opc = &avr32_opc_table[AVR32_OPC_RCALL1];
7645 +      /* fall through */
7646 +    case CALL_SUBTYPE_RCALL2:
7647 +      if (!opc)
7648 +       opc = &avr32_opc_table[AVR32_OPC_RCALL2];
7649 +      ifield = opc->fields[0];
7650 +      r_type = opc->reloc_type;
7651 +      pcrel = 1;
7652 +      align = 1;
7653 +      break;
7654 +    case CALL_SUBTYPE_MCALL_CP:
7655 +      opc = &avr32_opc_table[AVR32_OPC_MCALL];
7656 +      opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_PC);
7657 +      ifield = opc->fields[1];
7658 +      r_type = BFD_RELOC_AVR32_CPCALL;
7659 +      symbol = fragP->tc_frag_data.pool->symbol;
7660 +      offset = fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].offset;
7661 +      assert(fragP->tc_frag_data.pool->literals[fragP->tc_frag_data.pool_entry].refcount > 0);
7662 +      pcrel = 1;
7663 +      align = 2;
7664 +      break;
7665 +    case CALL_SUBTYPE_MCALL_GOT:
7666 +      opc = &avr32_opc_table[AVR32_OPC_MCALL];
7667 +      opc->fields[0]->insert(opc->fields[0], p, 6);
7668 +      ifield = opc->fields[1];
7669 +      r_type = BFD_RELOC_AVR32_GOT18SW;
7670 +      break;
7671 +    case CALL_SUBTYPE_MCALL_LARGE:
7672 +      assert(fragP->fr_var == 10);
7673 +      /* ld.w lr, r6[lr << 2] */
7674 +      opc = &avr32_opc_table[AVR32_OPC_LD_W5];
7675 +      bfd_putb32(opc->value, p + 4);
7676 +      opc->fields[0]->insert(opc->fields[0], p + 4, AVR32_REG_LR);
7677 +      opc->fields[1]->insert(opc->fields[1], p + 4, 6);
7678 +      opc->fields[2]->insert(opc->fields[2], p + 4, AVR32_REG_LR);
7679 +      opc->fields[3]->insert(opc->fields[3], p + 4, 2);
7680 +
7681 +      /* icall lr */
7682 +      opc = &avr32_opc_table[AVR32_OPC_ICALL];
7683 +      bfd_putb16(opc->value >> 16, p + 8);
7684 +      opc->fields[0]->insert(opc->fields[0], p + 8, AVR32_REG_LR);
7685 +
7686 +      /* mov lr, (got_offset / 4) */
7687 +      opc = &avr32_opc_table[AVR32_OPC_MOV2];
7688 +      opc->fields[0]->insert(opc->fields[0], p, AVR32_REG_LR);
7689 +      ifield = opc->fields[1];
7690 +      r_type = BFD_RELOC_AVR32_GOTCALL;
7691 +      break;
7692 +    default:
7693 +      BAD_CASE(fragP->fr_subtype);
7694 +    }
7695 +
7696 +  /* Insert the opcode and clear the variable ifield */
7697 +  value = bfd_getb32(p);
7698 +  value &= ~(opc->mask | ifield->mask);
7699 +  value |= opc->value;
7700 +  bfd_putb32(value, p);
7701 +
7702 +  fragP->fr_fix += fragP->fr_var - CALL_INITIAL_SIZE;
7703 +
7704 +  if (fragP->fr_next
7705 +      && ((offsetT)(fragP->fr_next->fr_address - fragP->fr_address)
7706 +         != fragP->fr_fix))
7707 +    {
7708 +      fprintf(stderr, "%s:%d: fr_fix %lu is wrong! fr_var=%lu, r_type=%s\n",
7709 +             fragP->fr_file, fragP->fr_line,
7710 +             fragP->fr_fix, fragP->fr_var, bfd_get_reloc_code_name(r_type));
7711 +      fprintf(stderr, "fr_fix should be %ld. next frag is %s:%d\n",
7712 +             (offsetT)(fragP->fr_next->fr_address - fragP->fr_address),
7713 +             fragP->fr_next->fr_file, fragP->fr_next->fr_line);
7714 +    }
7715 +
7716 +  fixP = fix_new(fragP, fragP->fr_fix - fragP->fr_var, fragP->fr_var,
7717 +                symbol, offset, pcrel, r_type);
7718 +
7719 +  /* Revert fix_new brain damage. "dot_value" is the value of PC at
7720 +     the point of the fixup, relative to the frag address.  fix_new()
7721 +     and friends think they are only being called during the assembly
7722 +     pass, not during relaxation or similar, so fx_dot_value, fx_file
7723 +     and fx_line are all initialized to the wrong value.  But we don't
7724 +     know the size of the fixup until now, so we really can't live up
7725 +     to the assumptions these functions make about the target.  What
7726 +     do these functions think the "where" and "frag" argument mean
7727 +     anyway?  */
7728 +  fixP->fx_dot_value = fragP->fr_fix - opc->size;
7729 +  fixP->fx_file = fragP->fr_file;
7730 +  fixP->fx_line = fragP->fr_line;
7731 +
7732 +  fixP->tc_fix_data.ifield = ifield;
7733 +  fixP->tc_fix_data.align = align;
7734 +  /* these are only used if the fixup can actually be resolved */
7735 +  fixP->tc_fix_data.min = -2097152;
7736 +  fixP->tc_fix_data.max = 2097150;
7737 +}
7738 +
7739 +static void
7740 +avr32_cpool_convert_frag(bfd *abfd ATTRIBUTE_UNUSED,
7741 +                        segT segment ATTRIBUTE_UNUSED,
7742 +                        fragS *fragP)
7743 +{
7744 +  struct cpool *pool;
7745 +  addressT address;
7746 +  unsigned int entry;
7747 +  char *p;
7748 +  char sym_name[20];
7749 +
7750 +  /* Did we get rid of the frag altogether? */
7751 +  if (!fragP->fr_var)
7752 +    return;
7753 +
7754 +  pool = fragP->tc_frag_data.pool;
7755 +  address = fragP->fr_address + fragP->fr_fix;
7756 +  p = fragP->fr_literal + fragP->fr_fix;
7757 +
7758 +  sprintf(sym_name, "$$cp_\002%x", pool->id);
7759 +  symbol_locate(pool->symbol, sym_name, pool->section, fragP->fr_fix, fragP);
7760 +  symbol_table_insert(pool->symbol);
7761 +
7762 +  for (entry = 0; entry < pool->next_free_entry; entry++)
7763 +    {
7764 +      if (pool->literals[entry].refcount > 0)
7765 +       {
7766 +         fix_new_exp(fragP, fragP->fr_fix, 4, &pool->literals[entry].exp,
7767 +                     FALSE, BFD_RELOC_AVR32_32_CPENT);
7768 +         fragP->fr_fix += 4;
7769 +       }
7770 +    }
7771 +}
7772 +
7773 +static struct avr32_relaxer avr32_default_relaxer = {
7774 +  .estimate_size       = avr32_default_estimate_size_before_relax,
7775 +  .relax_frag          = avr32_default_relax_frag,
7776 +  .convert_frag                = avr32_default_convert_frag,
7777 +};
7778 +static struct avr32_relaxer avr32_lda_relaxer = {
7779 +  .estimate_size       = avr32_lda_estimate_size_before_relax,
7780 +  .relax_frag          = avr32_lda_relax_frag,
7781 +  .convert_frag                = avr32_lda_convert_frag,
7782 +};
7783 +static struct avr32_relaxer avr32_call_relaxer = {
7784 +  .estimate_size       = avr32_call_estimate_size_before_relax,
7785 +  .relax_frag          = avr32_call_relax_frag,
7786 +  .convert_frag                = avr32_call_convert_frag,
7787 +};
7788 +static struct avr32_relaxer avr32_cpool_relaxer = {
7789 +  .estimate_size       = avr32_cpool_estimate_size_before_relax,
7790 +  .relax_frag          = avr32_cpool_relax_frag,
7791 +  .convert_frag                = avr32_cpool_convert_frag,
7792 +};
7793 +
7794 +static void s_cpool(int arg ATTRIBUTE_UNUSED)
7795 +{
7796 +  struct cpool *pool;
7797 +  unsigned int max_size;
7798 +  char *buf;
7799 +
7800 +  pool = find_cpool(now_seg, now_subseg);
7801 +  if (!pool || !pool->symbol || pool->next_free_entry == 0)
7802 +    return;
7803 +
7804 +  /* Make sure the constant pool is properly aligned */
7805 +  frag_align_code(2, 0);
7806 +  if (bfd_get_section_alignment(stdoutput, pool->section) < 2)
7807 +    bfd_set_section_alignment(stdoutput, pool->section, 2);
7808 +
7809 +  /* Assume none of the entries are discarded, and that we need the
7810 +     maximum amount of alignment.  But we're not going to allocate
7811 +     anything up front. */
7812 +  max_size = pool->next_free_entry * 4 + 2;
7813 +  frag_grow(max_size);
7814 +  buf = frag_more(0);
7815 +
7816 +  frag_now->tc_frag_data.relaxer = &avr32_cpool_relaxer;
7817 +  frag_now->tc_frag_data.pool = pool;
7818 +
7819 +  symbol_set_frag(pool->symbol, frag_now);
7820 +
7821 +  /* Assume zero initial size, allowing other relaxers to be
7822 +     optimistic about things.  */
7823 +  frag_var(rs_machine_dependent, max_size, 0,
7824 +          0, pool->symbol, 0, NULL);
7825 +
7826 +  /* Mark the pool as empty.  */
7827 +  pool->used = 1;
7828 +}
7829 +
7830 +/* The location from which a PC relative jump should be calculated,
7831 +   given a PC relative reloc.  */
7832 +
7833 +long
7834 +md_pcrel_from_section (fixS *fixP, segT sec)
7835 +{
7836 +  pr_debug("pcrel_from_section, fx_offset = %d\n", fixP->fx_offset);
7837 +
7838 +  if (fixP->fx_addsy != NULL
7839 +      && (! S_IS_DEFINED (fixP->fx_addsy)
7840 +          || S_GET_SEGMENT (fixP->fx_addsy) != sec
7841 +         || S_FORCE_RELOC(fixP->fx_addsy, 1)))
7842 +    {
7843 +      pr_debug("Unknown pcrel symbol: %s\n", S_GET_NAME(fixP->fx_addsy));
7844 +
7845 +      /* The symbol is undefined (or is defined but not in this section).
7846 +        Let the linker figure it out.  */
7847 +      return 0;
7848 +    }
7849 +
7850 +  pr_debug("pcrel from %x + %x, symbol: %s (%x)\n",
7851 +          fixP->fx_frag->fr_address, fixP->fx_where,
7852 +          fixP->fx_addsy?S_GET_NAME(fixP->fx_addsy):"(null)",
7853 +          fixP->fx_addsy?S_GET_VALUE(fixP->fx_addsy):0);
7854 +
7855 +  return ((fixP->fx_frag->fr_address + fixP->fx_where)
7856 +         & (~0UL << fixP->tc_fix_data.align));
7857 +}
7858 +
7859 +valueT
7860 +md_section_align (segT segment, valueT size)
7861 +{
7862 +  int align = bfd_get_section_alignment (stdoutput, segment);
7863 +  return ((size + (1 << align) - 1) & (-1 << align));
7864 +}
7865 +
7866 +static int syntax_matches(const struct avr32_syntax *syntax,
7867 +                         char *str)
7868 +{
7869 +  int i;
7870 +
7871 +  pr_debug("syntax %d matches `%s'?\n", syntax->id, str);
7872 +
7873 +  if (syntax->nr_operands < 0)
7874 +    {
7875 +      struct avr32_operand *op;
7876 +      int optype;
7877 +
7878 +      for (i = 0; i < (-syntax->nr_operands - 1); i++)
7879 +       {
7880 +         char *p;
7881 +         char c;
7882 +
7883 +         optype = syntax->operand[i];
7884 +         assert(optype < AVR32_NR_OPERANDS);
7885 +         op = &avr32_operand_table[optype];
7886 +
7887 +         for (p = str; *p; p++)
7888 +           if (*p == ',')
7889 +             break;
7890 +
7891 +         if (p == str)
7892 +           return 0;
7893 +
7894 +         c = *p;
7895 +         *p = 0;
7896 +
7897 +         if (!op->match(str))
7898 +           {
7899 +             *p = c;
7900 +             return 0;
7901 +           }
7902 +
7903 +         str = p;
7904 +         *p = c;
7905 +         if (c)
7906 +           str++;
7907 +       }
7908 +
7909 +      optype = syntax->operand[i];
7910 +      assert(optype < AVR32_NR_OPERANDS);
7911 +      op = &avr32_operand_table[optype];
7912 +
7913 +      if (!op->match(str))
7914 +       return 0;
7915 +      return 1;
7916 +    }
7917 +
7918 +  for (i = 0; i < syntax->nr_operands; i++)
7919 +    {
7920 +      struct avr32_operand *op;
7921 +      int optype = syntax->operand[i];
7922 +      char *p;
7923 +      char c;
7924 +
7925 +      assert(optype < AVR32_NR_OPERANDS);
7926 +      op = &avr32_operand_table[optype];
7927 +
7928 +      for (p = str; *p; p++)
7929 +       if (*p == ',')
7930 +         break;
7931 +
7932 +      if (p == str)
7933 +       return 0;
7934 +
7935 +      c = *p;
7936 +      *p = 0;
7937 +
7938 +      if (!op->match(str))
7939 +       {
7940 +         *p = c;
7941 +         return 0;
7942 +       }
7943 +
7944 +      str = p;
7945 +      *p = c;
7946 +      if (c)
7947 +       str++;
7948 +    }
7949 +
7950 +  if (*str == '\0')
7951 +    return 1;
7952 +
7953 +  if ((*str == 'e' || *str == 'E') && !str[1])
7954 +    return 1;
7955 +
7956 +  return 0;
7957 +}
7958 +
7959 +static int parse_operands(char *str)
7960 +{
7961 +  int i;
7962 +
7963 +  if (current_insn.syntax->nr_operands < 0)
7964 +    {
7965 +      int optype;
7966 +      struct avr32_operand *op;
7967 +
7968 +      for (i = 0; i < (-current_insn.syntax->nr_operands - 1); i++)
7969 +       {
7970 +         char *p;
7971 +         char c;
7972 +
7973 +         optype = current_insn.syntax->operand[i];
7974 +         op = &avr32_operand_table[optype];
7975 +
7976 +         for (p = str; *p; p++)
7977 +           if (*p == ',')
7978 +             break;
7979 +
7980 +         assert(p != str);
7981 +
7982 +         c = *p, *p = 0;
7983 +         op->parse(op, str, i);
7984 +         *p = c;
7985 +
7986 +         str = p;
7987 +         if (c) str++;
7988 +       }
7989 +
7990 +      /* give the rest of the line to the last operand */
7991 +      optype = current_insn.syntax->operand[i];
7992 +      op = &avr32_operand_table[optype];
7993 +      op->parse(op, str, i);
7994 +    }
7995 +  else
7996 +    {
7997 +      for (i = 0; i < current_insn.syntax->nr_operands; i++)
7998 +       {
7999 +         int optype = current_insn.syntax->operand[i];
8000 +         struct avr32_operand *op = &avr32_operand_table[optype];
8001 +         char *p;
8002 +         char c;
8003 +
8004 +         skip_whitespace(str);
8005 +
8006 +         for (p = str; *p; p++)
8007 +           if (*p == ',')
8008 +             break;
8009 +
8010 +         assert(p != str);
8011 +
8012 +         c = *p, *p = 0;
8013 +         op->parse(op, str, i);
8014 +         *p = c;
8015 +
8016 +         str = p;
8017 +         if (c) str++;
8018 +       }
8019 +
8020 +      if (*str == 'E' || *str == 'e')
8021 +       current_insn.force_extended = 1;
8022 +    }
8023 +
8024 +  return 0;
8025 +}
8026 +
8027 +static const char *
8028 +finish_insn(const struct avr32_opcode *opc)
8029 +{
8030 +  expressionS *exp = &current_insn.immediate;
8031 +  unsigned int i;
8032 +  int will_relax = 0;
8033 +  char *buf;
8034 +
8035 +  assert(current_insn.next_slot == opc->nr_fields);
8036 +
8037 +  pr_debug("%s:%d: finish_insn: trying opcode %d\n",
8038 +          frag_now->fr_file, frag_now->fr_line, opc->id);
8039 +
8040 +  /* Go through the relaxation stage for all instructions that can
8041 +     possibly take a symbolic immediate.  The relax code will take
8042 +     care of range checking and alignment.  */
8043 +  if (opc->var_field != -1)
8044 +    {
8045 +      int substate, largest_substate;
8046 +      symbolS *sym;
8047 +      offsetT off;
8048 +
8049 +      will_relax = 1;
8050 +      substate = largest_substate = opc_initial_substate(opc);
8051 +
8052 +      while (relax_more(largest_substate) != AVR32_RS_NONE)
8053 +       largest_substate = relax_more(largest_substate);
8054 +
8055 +      pr_debug("will relax. initial substate: %d (size %d), largest substate: %d (size %d)\n",
8056 +              substate, avr32_rs_size(substate),
8057 +              largest_substate, avr32_rs_size(largest_substate));
8058 +
8059 +      /* make sure we have enough room for the largest possible opcode */
8060 +      frag_grow(avr32_rs_size(largest_substate));
8061 +      buf = frag_more(opc->size);
8062 +
8063 +      dwarf2_emit_insn(opc->size);
8064 +
8065 +      frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_NONE;
8066 +      frag_now->tc_frag_data.pcrel = current_insn.pcrel;
8067 +      frag_now->tc_frag_data.force_extended = current_insn.force_extended;
8068 +      frag_now->tc_frag_data.relaxer = &avr32_default_relaxer;
8069 +
8070 +      if (exp->X_op == O_hi)
8071 +       {
8072 +         frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_HI;
8073 +         exp->X_op = exp->X_md;
8074 +       }
8075 +      else if (exp->X_op == O_lo)
8076 +       {
8077 +         frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_LO;
8078 +         exp->X_op = exp->X_md;
8079 +       }
8080 +      else if (exp->X_op == O_got)
8081 +       {
8082 +         frag_now->tc_frag_data.reloc_info = AVR32_OPINFO_GOT;
8083 +         exp->X_op = O_symbol;
8084 +       }
8085 +
8086 +#if 0
8087 +      if ((opc->reloc_type == BFD_RELOC_AVR32_SUB5)
8088 +         && exp->X_op == O_subtract)
8089 +       {
8090 +         symbolS *tmp;
8091 +         tmp = exp->X_add_symbol;
8092 +         exp->X_add_symbol = exp->X_op_symbol;
8093 +         exp->X_op_symbol = tmp;
8094 +       }
8095 +#endif
8096 +
8097 +      frag_now->tc_frag_data.exp = current_insn.immediate;
8098 +
8099 +      sym = exp->X_add_symbol;
8100 +      off = exp->X_add_number;
8101 +      if (exp->X_op != O_symbol)
8102 +       {
8103 +         sym = make_expr_symbol(exp);
8104 +         off = 0;
8105 +       }
8106 +
8107 +      frag_var(rs_machine_dependent,
8108 +              avr32_rs_size(largest_substate) - opc->size,
8109 +              opc->size,
8110 +              substate, sym, off, buf);
8111 +    }
8112 +  else
8113 +    {
8114 +      assert(avr32_rs_size(opc_initial_substate(opc)) == 0);
8115 +
8116 +      /* Make sure we always have room for another whole word, as the ifield
8117 +        inserters can only write words. */
8118 +      frag_grow(4);
8119 +      buf = frag_more(opc->size);
8120 +      dwarf2_emit_insn(opc->size);
8121 +    }
8122 +
8123 +  assert(!(opc->value & ~opc->mask));
8124 +
8125 +  pr_debug("inserting opcode: 0x%lx\n", opc->value);
8126 +  bfd_putb32(opc->value, buf);
8127 +
8128 +  for (i = 0; i < opc->nr_fields; i++)
8129 +    {
8130 +      const struct avr32_ifield *f = opc->fields[i];
8131 +      const struct avr32_ifield_data *fd = &current_insn.field_value[i];
8132 +
8133 +      pr_debug("inserting field: 0x%lx & 0x%lx\n",
8134 +              fd->value >> fd->align_order, f->mask);
8135 +
8136 +      f->insert(f, buf, fd->value >> fd->align_order);
8137 +    }
8138 +
8139 +  assert(will_relax || !current_insn.immediate.X_add_symbol);
8140 +  return NULL;
8141 +}
8142 +
8143 +static const char *
8144 +finish_alias(const struct avr32_alias *alias)
8145 +{
8146 +  const struct avr32_opcode *opc;
8147 +  struct {
8148 +    unsigned long value;
8149 +    unsigned long align;
8150 +  } mapped_operand[AVR32_MAX_OPERANDS];
8151 +  unsigned int i;
8152 +
8153 +  opc = alias->opc;
8154 +
8155 +  /* Remap the operands from the alias to the real opcode */
8156 +  for (i = 0; i < opc->nr_fields; i++)
8157 +    {
8158 +      if (alias->operand_map[i].is_opindex)
8159 +       {
8160 +         struct avr32_ifield_data *fd;
8161 +         fd = &current_insn.field_value[alias->operand_map[i].value];
8162 +         mapped_operand[i].value = fd->value;
8163 +         mapped_operand[i].align = fd->align_order;
8164 +       }
8165 +      else
8166 +       {
8167 +         mapped_operand[i].value = alias->operand_map[i].value;
8168 +         mapped_operand[i].align = 0;
8169 +       }
8170 +    }
8171 +
8172 +  for (i = 0; i < opc->nr_fields; i++)
8173 +    {
8174 +      current_insn.field_value[i].value = mapped_operand[i].value;
8175 +      if (opc->id == AVR32_OPC_COP)
8176 +       current_insn.field_value[i].align_order = 0;
8177 +      else
8178 +       current_insn.field_value[i].align_order
8179 +         = mapped_operand[i].align;
8180 +    }
8181 +
8182 +  current_insn.next_slot = opc->nr_fields;
8183 +
8184 +  return finish_insn(opc);
8185 +}
8186 +
8187 +static const char *
8188 +finish_lda(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED)
8189 +{
8190 +  expressionS *exp = &current_insn.immediate;
8191 +  relax_substateT initial_subtype;
8192 +  symbolS *sym;
8193 +  offsetT off;
8194 +  int initial_size, max_size;
8195 +  char *buf;
8196 +
8197 +  initial_size = LDA_INITIAL_SIZE;
8198 +
8199 +  if (avr32_pic)
8200 +    {
8201 +      initial_subtype = LDA_SUBTYPE_SUB;
8202 +      if (linkrelax)
8203 +       max_size = 8;
8204 +      else
8205 +       max_size = 4;
8206 +    }
8207 +  else
8208 +    {
8209 +      initial_subtype = LDA_SUBTYPE_MOV1;
8210 +      max_size = 4;
8211 +    }
8212 +
8213 +  frag_grow(max_size);
8214 +  buf = frag_more(initial_size);
8215 +  dwarf2_emit_insn(initial_size);
8216 +
8217 +  if (exp->X_op == O_symbol)
8218 +    {
8219 +      sym = exp->X_add_symbol;
8220 +      off = exp->X_add_number;
8221 +    }
8222 +  else
8223 +    {
8224 +      sym = make_expr_symbol(exp);
8225 +      off = 0;
8226 +    }
8227 +
8228 +  frag_now->tc_frag_data.reloc_info = current_insn.field_value[0].value;
8229 +  frag_now->tc_frag_data.relaxer = &avr32_lda_relaxer;
8230 +
8231 +  if (!avr32_pic)
8232 +    {
8233 +      /* The relaxer will bump the refcount if necessary */
8234 +      frag_now->tc_frag_data.pool
8235 +       = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0);
8236 +    }
8237 +
8238 +  frag_var(rs_machine_dependent, max_size - initial_size,
8239 +          initial_size, initial_subtype, sym, off, buf);
8240 +
8241 +  return NULL;
8242 +}
8243 +
8244 +static const char *
8245 +finish_call(const struct avr32_syntax *syntax ATTRIBUTE_UNUSED)
8246 +{
8247 +  expressionS *exp = &current_insn.immediate;
8248 +  symbolS *sym;
8249 +  offsetT off;
8250 +  int initial_size, max_size;
8251 +  char *buf;
8252 +
8253 +  initial_size = CALL_INITIAL_SIZE;
8254 +
8255 +  if (avr32_pic)
8256 +    {
8257 +      if (linkrelax)
8258 +       max_size = 10;
8259 +      else
8260 +       max_size = 4;
8261 +    }
8262 +  else
8263 +    max_size = 4;
8264 +
8265 +  frag_grow(max_size);
8266 +  buf = frag_more(initial_size);
8267 +  dwarf2_emit_insn(initial_size);
8268 +
8269 +  frag_now->tc_frag_data.relaxer = &avr32_call_relaxer;
8270 +
8271 +  if (exp->X_op == O_symbol)
8272 +    {
8273 +      sym = exp->X_add_symbol;
8274 +      off = exp->X_add_number;
8275 +    }
8276 +  else
8277 +    {
8278 +      sym = make_expr_symbol(exp);
8279 +      off = 0;
8280 +    }
8281 +
8282 +  if (!avr32_pic)
8283 +    {
8284 +      /* The relaxer will bump the refcount if necessary */
8285 +      frag_now->tc_frag_data.pool
8286 +       = add_to_cpool(exp, &frag_now->tc_frag_data.pool_entry, 0);
8287 +    }
8288 +
8289 +  frag_var(rs_machine_dependent, max_size - initial_size,
8290 +          initial_size, CALL_SUBTYPE_RCALL1, sym, off, buf);
8291 +
8292 +  return NULL;
8293 +}
8294 +
8295 +void
8296 +md_begin (void)
8297 +{
8298 +  unsigned long flags = 0;
8299 +  int i;
8300 +
8301 +  avr32_mnemonic_htab = hash_new();
8302 +
8303 +  if (!avr32_mnemonic_htab)
8304 +    as_fatal(_("virtual memory exhausted"));
8305 +
8306 +  for (i = 0; i < AVR32_NR_MNEMONICS; i++)
8307 +    {
8308 +      hash_insert(avr32_mnemonic_htab, avr32_mnemonic_table[i].name,
8309 +                 (void *)&avr32_mnemonic_table[i]);
8310 +    }
8311 +
8312 +  if (linkrelax)
8313 +    flags |= EF_AVR32_LINKRELAX;
8314 +  if (avr32_pic)
8315 +    flags |= EF_AVR32_PIC;
8316 +
8317 +  bfd_set_private_flags(stdoutput, flags);
8318 +
8319 +#ifdef OPC_CONSISTENCY_CHECK
8320 +  if (sizeof(avr32_operand_table)/sizeof(avr32_operand_table[0])
8321 +      < AVR32_NR_OPERANDS)
8322 +    as_fatal(_("operand table is incomplete"));
8323 +
8324 +  for (i = 0; i < AVR32_NR_OPERANDS; i++)
8325 +    if (avr32_operand_table[i].id != i)
8326 +      as_fatal(_("operand table inconsistency found at index %d\n"), i);
8327 +  pr_debug("%d operands verified\n", AVR32_NR_OPERANDS);
8328 +
8329 +  for (i = 0; i < AVR32_NR_IFIELDS; i++)
8330 +    if (avr32_ifield_table[i].id != i)
8331 +      as_fatal(_("ifield table inconsistency found at index %d\n"), i);
8332 +  pr_debug("%d instruction fields verified\n", AVR32_NR_IFIELDS);
8333 +
8334 +  for (i = 0; i < AVR32_NR_OPCODES; i++)
8335 +    {
8336 +      if (avr32_opc_table[i].id != i)
8337 +       as_fatal(_("opcode table inconsistency found at index %d\n"), i);
8338 +      if ((avr32_opc_table[i].var_field == -1
8339 +          && avr32_relax_table[i].length != 0)
8340 +         || (avr32_opc_table[i].var_field != -1
8341 +             && avr32_relax_table[i].length == 0))
8342 +       as_fatal(_("relax table inconsistency found at index %d\n"), i);
8343 +    }
8344 +  pr_debug("%d opcodes verified\n", AVR32_NR_OPCODES);
8345 +
8346 +  for (i = 0; i < AVR32_NR_SYNTAX; i++)
8347 +    if (avr32_syntax_table[i].id != i)
8348 +      as_fatal(_("syntax table inconsistency found at index %d\n"), i);
8349 +  pr_debug("%d syntax variants verified\n", AVR32_NR_SYNTAX);
8350 +
8351 +  for (i = 0; i < AVR32_NR_ALIAS; i++)
8352 +    if (avr32_alias_table[i].id != i)
8353 +      as_fatal(_("alias table inconsistency found at index %d\n"), i);
8354 +  pr_debug("%d aliases verified\n", AVR32_NR_ALIAS);
8355 +
8356 +  for (i = 0; i < AVR32_NR_MNEMONICS; i++)
8357 +    if (avr32_mnemonic_table[i].id != i)
8358 +      as_fatal(_("mnemonic table inconsistency found at index %d\n"), i);
8359 +  pr_debug("%d mnemonics verified\n", AVR32_NR_MNEMONICS);
8360 +#endif
8361 +}
8362 +
8363 +void
8364 +md_assemble (char *str)
8365 +{
8366 +  struct avr32_mnemonic *mnemonic;
8367 +  char *p, c;
8368 +
8369 +  memset(&current_insn, 0, sizeof(current_insn));
8370 +  current_insn.immediate.X_op = O_constant;
8371 +
8372 +  skip_whitespace(str);
8373 +  for (p = str; *p; p++)
8374 +    if (*p == ' ')
8375 +      break;
8376 +  c = *p;
8377 +  *p = 0;
8378 +
8379 +  mnemonic = hash_find(avr32_mnemonic_htab, str);
8380 +  *p = c;
8381 +  if (c) p++;
8382 +
8383 +  if (mnemonic)
8384 +    {
8385 +      const struct avr32_syntax *syntax;
8386 +
8387 +      for (syntax = mnemonic->syntax; syntax; syntax = syntax->next)
8388 +       {
8389 +         const char *errmsg = NULL;
8390 +
8391 +         if (syntax_matches(syntax, p))
8392 +           {
8393 +             if (!(syntax->isa_flags & avr32_arch->isa_flags))
8394 +               {
8395 +                 as_bad(_("Selected architecture `%s'  does not support `%s'"),
8396 +                        avr32_arch->name, str);
8397 +                 return;
8398 +               }
8399 +
8400 +             current_insn.syntax = syntax;
8401 +             parse_operands(p);
8402 +
8403 +             switch (syntax->type)
8404 +               {
8405 +               case AVR32_PARSER_NORMAL:
8406 +                 errmsg = finish_insn(syntax->u.opc);
8407 +                 break;
8408 +               case AVR32_PARSER_ALIAS:
8409 +                 errmsg = finish_alias(syntax->u.alias);
8410 +                 break;
8411 +               case AVR32_PARSER_LDA:
8412 +                 errmsg = finish_lda(syntax);
8413 +                 break;
8414 +               case AVR32_PARSER_CALL:
8415 +                 errmsg = finish_call(syntax);
8416 +                 break;
8417 +               default:
8418 +                 BAD_CASE(syntax->type);
8419 +                 break;
8420 +               }
8421 +
8422 +             if (errmsg)
8423 +               as_bad("%s in `%s'", errmsg, str);
8424 +
8425 +             return;
8426 +           }
8427 +       }
8428 +
8429 +      as_bad(_("unrecognized form of instruction: `%s'"), str);
8430 +    }
8431 +  else
8432 +    as_bad(_("unrecognized instruction `%s'"), str);
8433 +}
8434 +
8435 +void avr32_cleanup(void)
8436 +{
8437 +  struct cpool *pool;
8438 +
8439 +  /* Emit any constant pools that haven't been explicitly flushed with
8440 +     a .cpool directive. */
8441 +  for (pool = cpool_list; pool; pool = pool->next)
8442 +    {
8443 +      subseg_set(pool->section, pool->sub_section);
8444 +      s_cpool(0);
8445 +    }
8446 +}
8447 +
8448 +/* Handle any PIC-related operands in data allocation pseudo-ops */
8449 +void
8450 +avr32_cons_fix_new (fragS *frag, int off, int size, expressionS *exp)
8451 +{
8452 +  bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
8453 +  int pcrel = 0;
8454 +
8455 +  pr_debug("%s:%u: cons_fix_new, add_sym: %s, op_sym: %s, op: %d, add_num: %d\n",
8456 +          frag->fr_file, frag->fr_line,
8457 +          exp->X_add_symbol?S_GET_NAME(exp->X_add_symbol):"(none)",
8458 +          exp->X_op_symbol?S_GET_NAME(exp->X_op_symbol):"(none)",
8459 +          exp->X_op, exp->X_add_number);
8460 +
8461 +  if (exp->X_op == O_subtract && exp->X_op_symbol)
8462 +    {
8463 +      if (exp->X_op_symbol == GOT_symbol)
8464 +       {
8465 +         if (size != 4)
8466 +           goto bad_size;
8467 +         r_type = BFD_RELOC_AVR32_GOTPC;
8468 +         exp->X_op = O_symbol;
8469 +         exp->X_op_symbol = NULL;
8470 +       }
8471 +    }
8472 +  else if (exp->X_op == O_got)
8473 +    {
8474 +      switch (size)
8475 +       {
8476 +       case 1:
8477 +         r_type = BFD_RELOC_AVR32_GOT8;
8478 +         break;
8479 +       case 2:
8480 +         r_type = BFD_RELOC_AVR32_GOT16;
8481 +         break;
8482 +       case 4:
8483 +         r_type = BFD_RELOC_AVR32_GOT32;
8484 +         break;
8485 +       default:
8486 +         goto bad_size;
8487 +       }
8488 +
8489 +      exp->X_op = O_symbol;
8490 +    }
8491 +
8492 +  if (r_type == BFD_RELOC_UNUSED)
8493 +    switch (size)
8494 +      {
8495 +      case 1:
8496 +       r_type = BFD_RELOC_8;
8497 +       break;
8498 +      case 2:
8499 +       r_type = BFD_RELOC_16;
8500 +       break;
8501 +      case 4:
8502 +       r_type = BFD_RELOC_32;
8503 +       break;
8504 +      default:
8505 +       goto bad_size;
8506 +      }
8507 +  else if (size != 4)
8508 +    {
8509 +    bad_size:
8510 +      as_bad(_("unsupported BFD relocation size %u"), size);
8511 +      r_type = BFD_RELOC_UNUSED;
8512 +    }
8513 +
8514 +  fix_new_exp (frag, off, size, exp, pcrel, r_type);
8515 +}
8516 +
8517 +static void
8518 +avr32_frob_section(bfd *abfd ATTRIBUTE_UNUSED, segT sec,
8519 +                  void *ignore ATTRIBUTE_UNUSED)
8520 +{
8521 +  segment_info_type *seginfo;
8522 +  fixS *fix;
8523 +
8524 +  seginfo = seg_info(sec);
8525 +  if (!seginfo)
8526 +    return;
8527 +
8528 +  for (fix = seginfo->fix_root; fix; fix = fix->fx_next)
8529 +    {
8530 +      if (fix->fx_done)
8531 +       continue;
8532 +
8533 +      if (fix->fx_r_type == BFD_RELOC_AVR32_SUB5
8534 +         && fix->fx_addsy && fix->fx_subsy)
8535 +       {
8536 +         if (S_GET_SEGMENT(fix->fx_addsy) != S_GET_SEGMENT(fix->fx_subsy)
8537 +             || linkrelax)
8538 +           {
8539 +             symbolS *tmp;
8540 +#ifdef DEBUG
8541 +             fprintf(stderr, "Swapping symbols in fixup:\n");
8542 +             print_fixup(fix);
8543 +#endif
8544 +             tmp = fix->fx_addsy;
8545 +             fix->fx_addsy = fix->fx_subsy;
8546 +             fix->fx_subsy = tmp;
8547 +             fix->fx_offset = -fix->fx_offset;
8548 +           }
8549 +       }
8550 +    }
8551 +}
8552 +
8553 +/* We need to look for SUB5 instructions with expressions that will be
8554 +   made PC-relative and switch fx_addsy with fx_subsy.  This has to be
8555 +   done before adjustment or the wrong symbol might be adjusted.
8556 +
8557 +   This applies to fixups that are a result of expressions like -(sym
8558 +   - .) and that will make it all the way to md_apply_fix3().  LDA
8559 +   does the right thing in convert_frag, so we must not convert
8560 +   those. */
8561 +void
8562 +avr32_frob_file(void)
8563 +{
8564 +  /* if (1 || !linkrelax)
8565 +     return; */
8566 +
8567 +  bfd_map_over_sections(stdoutput, avr32_frob_section, NULL);
8568 +}
8569 +
8570 +static bfd_boolean
8571 +convert_to_diff_reloc(fixS *fixP)
8572 +{
8573 +  switch (fixP->fx_r_type)
8574 +    {
8575 +    case BFD_RELOC_32:
8576 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32;
8577 +      break;
8578 +    case BFD_RELOC_16:
8579 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF16;
8580 +      break;
8581 +    case BFD_RELOC_8:
8582 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF8;
8583 +      break;
8584 +    default:
8585 +      return FALSE;
8586 +    }
8587 +
8588 +  return TRUE;
8589 +}
8590 +
8591 +/* Simplify a fixup.  If possible, the fixup is reduced to a single
8592 +   constant which is written to the output file.  Otherwise, a
8593 +   relocation is generated so that the linker can take care of the
8594 +   rest.
8595 +
8596 +   ELF relocations have certain constraints: They can only take a
8597 +   single symbol and a single addend.  This means that for difference
8598 +   expressions, we _must_ get rid of the fx_subsy symbol somehow.
8599 +
8600 +   The difference between two labels in the same section can be
8601 +   calculated directly unless 'linkrelax' is set, or a relocation is
8602 +   forced.  If so, we must emit a R_AVR32_DIFFxx relocation.  If there
8603 +   are addends involved at this point, we must be especially careful
8604 +   as the relocation must point exactly to the symbol being
8605 +   subtracted.
8606 +
8607 +   When subtracting a symbol defined in the same section as the fixup,
8608 +   we might be able to convert it to a PC-relative expression, unless
8609 +   linkrelax is set. If this is the case, there's no way we can make
8610 +   sure that the difference between the fixup and fx_subsy stays
8611 +   constant.  So for now, we're just going to disallow that.
8612 +   */
8613 +void
8614 +avr32_process_fixup(fixS *fixP, segT this_segment)
8615 +{
8616 +  segT add_symbol_segment = absolute_section;
8617 +  segT sub_symbol_segment = absolute_section;
8618 +  symbolS *fx_addsy, *fx_subsy;
8619 +  offsetT value = 0, fx_offset;
8620 +  bfd_boolean apply = FALSE;
8621 +
8622 +  assert(this_segment != absolute_section);
8623 +
8624 +  if (fixP->fx_r_type >= BFD_RELOC_UNUSED)
8625 +    {
8626 +      as_bad_where(fixP->fx_file, fixP->fx_line,
8627 +                  _("Bad relocation type %d\n"), fixP->fx_r_type);
8628 +      return;
8629 +    }
8630 +
8631 +  /* BFD_RELOC_AVR32_SUB5 fixups have been swapped by avr32_frob_section() */
8632 +  fx_addsy = fixP->fx_addsy;
8633 +  fx_subsy = fixP->fx_subsy;
8634 +  fx_offset = fixP->fx_offset;
8635 +
8636 +  if (fx_addsy)
8637 +    add_symbol_segment = S_GET_SEGMENT(fx_addsy);
8638 +
8639 +  if (fx_subsy)
8640 +    {
8641 +      resolve_symbol_value(fx_subsy);
8642 +      sub_symbol_segment = S_GET_SEGMENT(fx_subsy);
8643 +
8644 +      if (sub_symbol_segment == this_segment
8645 +         && (!linkrelax
8646 +             || S_GET_VALUE(fx_subsy) == (fixP->fx_frag->fr_address
8647 +                                          + fixP->fx_where)))
8648 +       {
8649 +         fixP->fx_pcrel = TRUE;
8650 +         fx_offset += (fixP->fx_frag->fr_address + fixP->fx_where
8651 +                       - S_GET_VALUE(fx_subsy));
8652 +         fx_subsy = NULL;
8653 +       }
8654 +      else if (sub_symbol_segment == absolute_section)
8655 +       {
8656 +         /* The symbol is really a constant.  */
8657 +         fx_offset -= S_GET_VALUE(fx_subsy);
8658 +         fx_subsy = NULL;
8659 +       }
8660 +      else if (SEG_NORMAL(add_symbol_segment)
8661 +              && sub_symbol_segment == add_symbol_segment
8662 +              && (!linkrelax || convert_to_diff_reloc(fixP)))
8663 +       {
8664 +         /* Difference between two labels in the same section.  */
8665 +         if (linkrelax)
8666 +           {
8667 +             /* convert_to_diff() has ensured that the reloc type is
8668 +                either DIFF32, DIFF16 or DIFF8.  */
8669 +             value = (S_GET_VALUE(fx_addsy) + fixP->fx_offset
8670 +                      - S_GET_VALUE(fx_subsy));
8671 +
8672 +             /* Try to convert it to a section symbol if possible  */
8673 +             if (!S_FORCE_RELOC(fx_addsy, 1)
8674 +                 && !(sub_symbol_segment->flags & SEC_THREAD_LOCAL))
8675 +               {
8676 +                 fx_offset = S_GET_VALUE(fx_subsy);
8677 +                 fx_addsy = section_symbol(sub_symbol_segment);
8678 +               }
8679 +             else
8680 +               {
8681 +                 fx_addsy = fx_subsy;
8682 +                 fx_offset = 0;
8683 +               }
8684 +
8685 +             fx_subsy = NULL;
8686 +             apply = TRUE;
8687 +           }
8688 +         else
8689 +           {
8690 +             fx_offset += S_GET_VALUE(fx_addsy);
8691 +             fx_offset -= S_GET_VALUE(fx_subsy);
8692 +             fx_addsy = NULL;
8693 +             fx_subsy = NULL;
8694 +           }
8695 +       }
8696 +      else
8697 +       {
8698 +         as_bad_where(fixP->fx_file, fixP->fx_line,
8699 +                      _("can't resolve `%s' {%s section} - `%s' {%s section}"),
8700 +                      fx_addsy ? S_GET_NAME (fx_addsy) : "0",
8701 +                      segment_name (add_symbol_segment),
8702 +                      S_GET_NAME (fx_subsy),
8703 +                      segment_name (sub_symbol_segment));
8704 +         return;
8705 +       }
8706 +    }
8707 +
8708 +  if (fx_addsy && !TC_FORCE_RELOCATION(fixP))
8709 +    {
8710 +      if (add_symbol_segment == this_segment
8711 +         && fixP->fx_pcrel)
8712 +       {
8713 +         value += S_GET_VALUE(fx_addsy);
8714 +         value -= md_pcrel_from_section(fixP, this_segment);
8715 +         fx_addsy = NULL;
8716 +         fixP->fx_pcrel = FALSE;
8717 +       }
8718 +      else if (add_symbol_segment == absolute_section)
8719 +       {
8720 +         fx_offset += S_GET_VALUE(fixP->fx_addsy);
8721 +         fx_addsy = NULL;
8722 +       }
8723 +    }
8724 +
8725 +  if (!fx_addsy)
8726 +    fixP->fx_done = TRUE;
8727 +
8728 +  if (fixP->fx_pcrel)
8729 +    {
8730 +      if (fx_addsy != NULL
8731 +         && S_IS_DEFINED(fx_addsy)
8732 +         && S_GET_SEGMENT(fx_addsy) != this_segment)
8733 +       value += md_pcrel_from_section(fixP, this_segment);
8734 +
8735 +      switch (fixP->fx_r_type)
8736 +       {
8737 +       case BFD_RELOC_32:
8738 +         fixP->fx_r_type = BFD_RELOC_32_PCREL;
8739 +         break;
8740 +       case BFD_RELOC_16:
8741 +         fixP->fx_r_type = BFD_RELOC_16_PCREL;
8742 +         break;
8743 +       case BFD_RELOC_8:
8744 +         fixP->fx_r_type = BFD_RELOC_8_PCREL;
8745 +         break;
8746 +       case BFD_RELOC_AVR32_SUB5:
8747 +         fixP->fx_r_type = BFD_RELOC_AVR32_16N_PCREL;
8748 +         break;
8749 +       case BFD_RELOC_AVR32_16S:
8750 +         fixP->fx_r_type = BFD_RELOC_AVR32_16B_PCREL;
8751 +         break;
8752 +       case BFD_RELOC_AVR32_14UW:
8753 +         fixP->fx_r_type = BFD_RELOC_AVR32_14UW_PCREL;
8754 +         break;
8755 +       case BFD_RELOC_AVR32_10UW:
8756 +         fixP->fx_r_type = BFD_RELOC_AVR32_10UW_PCREL;
8757 +         break;
8758 +       default:
8759 +         /* Should have been taken care of already */
8760 +         break;
8761 +       }
8762 +    }
8763 +
8764 +  if (fixP->fx_done || apply)
8765 +    {
8766 +      const struct avr32_ifield *ifield;
8767 +      char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
8768 +
8769 +      if (fixP->fx_done)
8770 +       value += fx_offset;
8771 +
8772 +      /* For hosts with longs bigger than 32-bits make sure that the top
8773 +         bits of a 32-bit negative value read in by the parser are set,
8774 +         so that the correct comparisons are made.  */
8775 +      if (value & 0x80000000)
8776 +        value |= (-1L << 31);
8777 +
8778 +      switch (fixP->fx_r_type)
8779 +       {
8780 +       case BFD_RELOC_32:
8781 +       case BFD_RELOC_16:
8782 +       case BFD_RELOC_8:
8783 +       case BFD_RELOC_AVR32_DIFF32:
8784 +       case BFD_RELOC_AVR32_DIFF16:
8785 +       case BFD_RELOC_AVR32_DIFF8:
8786 +         md_number_to_chars(buf, value, fixP->fx_size);
8787 +         break;
8788 +       case BFD_RELOC_HI16:
8789 +         value >>= 16;
8790 +       case BFD_RELOC_LO16:
8791 +         value &= 0xffff;
8792 +         md_number_to_chars(buf + 2, value, 2);
8793 +         break;
8794 +       case BFD_RELOC_AVR32_16N_PCREL:
8795 +         value = -value;
8796 +         /* fall through */
8797 +       case BFD_RELOC_AVR32_22H_PCREL:
8798 +       case BFD_RELOC_AVR32_18W_PCREL:
8799 +       case BFD_RELOC_AVR32_16B_PCREL:
8800 +       case BFD_RELOC_AVR32_11H_PCREL:
8801 +       case BFD_RELOC_AVR32_9H_PCREL:
8802 +       case BFD_RELOC_AVR32_9UW_PCREL:
8803 +       case BFD_RELOC_AVR32_3U:
8804 +       case BFD_RELOC_AVR32_4UH:
8805 +       case BFD_RELOC_AVR32_6UW:
8806 +       case BFD_RELOC_AVR32_6S:
8807 +       case BFD_RELOC_AVR32_7UW:
8808 +       case BFD_RELOC_AVR32_8S_EXT:
8809 +       case BFD_RELOC_AVR32_8S:
8810 +       case BFD_RELOC_AVR32_10UW:
8811 +       case BFD_RELOC_AVR32_10SW:
8812 +       case BFD_RELOC_AVR32_STHH_W:
8813 +       case BFD_RELOC_AVR32_14UW:
8814 +       case BFD_RELOC_AVR32_16S:
8815 +       case BFD_RELOC_AVR32_16U:
8816 +       case BFD_RELOC_AVR32_21S:
8817 +       case BFD_RELOC_AVR32_SUB5:
8818 +       case BFD_RELOC_AVR32_CPCALL:
8819 +       case BFD_RELOC_AVR32_16_CP:
8820 +       case BFD_RELOC_AVR32_9W_CP:
8821 +       case BFD_RELOC_AVR32_15S:
8822 +         ifield = fixP->tc_fix_data.ifield;
8823 +         pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n",
8824 +                  fixP->tc_fix_data.min, value, fixP->tc_fix_data.max,
8825 +                  fixP->tc_fix_data.align);
8826 +         if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max)
8827 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8828 +                        _("operand out of range (%ld not between %ld and %ld)"),
8829 +                        value, fixP->tc_fix_data.min, fixP->tc_fix_data.max);
8830 +         if (value & ((1 << fixP->tc_fix_data.align) - 1))
8831 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8832 +                        _("misaligned operand (required alignment: %d)"),
8833 +                        1 << fixP->tc_fix_data.align);
8834 +         ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align);
8835 +         break;
8836 +       case BFD_RELOC_AVR32_ALIGN:
8837 +         /* Nothing to do */
8838 +         fixP->fx_done = FALSE;
8839 +         break;
8840 +       default:
8841 +         as_fatal("reloc type %s not handled\n",
8842 +                  bfd_get_reloc_code_name(fixP->fx_r_type));
8843 +       }
8844 +    }
8845 +
8846 +  fixP->fx_addsy = fx_addsy;
8847 +  fixP->fx_subsy = fx_subsy;
8848 +  fixP->fx_offset = fx_offset;
8849 +
8850 +  if (!fixP->fx_done)
8851 +    {
8852 +      if (!fixP->fx_addsy)
8853 +       fixP->fx_addsy = abs_section_sym;
8854 +
8855 +      symbol_mark_used_in_reloc(fixP->fx_addsy);
8856 +      if (fixP->fx_subsy)
8857 +       abort();
8858 +    }
8859 +}
8860 +
8861 +#if 0
8862 +void
8863 +md_apply_fix3 (fixS *fixP, valueT *valP, segT seg)
8864 +{
8865 +  const struct avr32_ifield *ifield;
8866 +  offsetT      value = *valP;
8867 +  char         *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
8868 +  bfd_boolean  apply;
8869 +
8870 +  pr_debug("%s:%u: apply_fix3: r_type=%d value=%lx offset=%lx\n",
8871 +          fixP->fx_file, fixP->fx_line, fixP->fx_r_type, *valP,
8872 +          fixP->fx_offset);
8873 +
8874 +  if (fixP->fx_r_type >= BFD_RELOC_UNUSED)
8875 +    {
8876 +      as_bad_where(fixP->fx_file, fixP->fx_line,
8877 +                  _("Bad relocation type %d\n"), fixP->fx_r_type);
8878 +      return;
8879 +    }
8880 +
8881 +  if (!fixP->fx_addsy && !fixP->fx_subsy)
8882 +    fixP->fx_done = 1;
8883 +
8884 +  if (fixP->fx_pcrel)
8885 +    {
8886 +      if (fixP->fx_addsy != NULL
8887 +         && S_IS_DEFINED(fixP->fx_addsy)
8888 +         && S_GET_SEGMENT(fixP->fx_addsy) != seg)
8889 +       value += md_pcrel_from_section(fixP, seg);
8890 +
8891 +      switch (fixP->fx_r_type)
8892 +       {
8893 +       case BFD_RELOC_32:
8894 +         fixP->fx_r_type = BFD_RELOC_32_PCREL;
8895 +         break;
8896 +       case BFD_RELOC_16:
8897 +       case BFD_RELOC_8:
8898 +         as_bad_where (fixP->fx_file, fixP->fx_line,
8899 +                       _("8- and 16-bit PC-relative relocations not supported"));
8900 +         break;
8901 +       case BFD_RELOC_AVR32_SUB5:
8902 +         fixP->fx_r_type = BFD_RELOC_AVR32_PCREL_SUB5;
8903 +         break;
8904 +       case BFD_RELOC_AVR32_16S:
8905 +         fixP->fx_r_type = BFD_RELOC_AVR32_16_PCREL;
8906 +         break;
8907 +       default:
8908 +         /* Should have been taken care of already */
8909 +         break;
8910 +       }
8911 +    }
8912 +
8913 +  if (fixP->fx_r_type == BFD_RELOC_32
8914 +      && fixP->fx_subsy)
8915 +    {
8916 +      fixP->fx_r_type = BFD_RELOC_AVR32_DIFF32;
8917 +
8918 +      /* Offsets are only allowed if it's a result of adjusting a
8919 +        local symbol into a section-relative offset.
8920 +        tc_fix_adjustable() should prevent any adjustment if there
8921 +        was an offset involved before.  */
8922 +      if (fixP->fx_offset && !symbol_section_p(fixP->fx_addsy))
8923 +       as_bad_where(fixP->fx_file, fixP->fx_line,
8924 +                    _("cannot represent symbol difference with an offset"));
8925 +
8926 +      value = (S_GET_VALUE(fixP->fx_addsy) + fixP->fx_offset
8927 +              - S_GET_VALUE(fixP->fx_subsy));
8928 +
8929 +      /* The difference before any relaxing takes place is written
8930 +        out, and the DIFF32 reloc identifies the address of the first
8931 +        symbol (i.e. the on that's subtracted.)  */
8932 +      *valP = value;
8933 +      fixP->fx_offset -= value;
8934 +      fixP->fx_subsy = NULL;
8935 +
8936 +      md_number_to_chars(buf, value, fixP->fx_size);
8937 +    }
8938 +
8939 +  if (fixP->fx_done)
8940 +    {
8941 +      switch (fixP->fx_r_type)
8942 +       {
8943 +       case BFD_RELOC_8:
8944 +       case BFD_RELOC_16:
8945 +       case BFD_RELOC_32:
8946 +         md_number_to_chars(buf, value, fixP->fx_size);
8947 +         break;
8948 +       case BFD_RELOC_HI16:
8949 +         value >>= 16;
8950 +       case BFD_RELOC_LO16:
8951 +         value &= 0xffff;
8952 +         *valP = value;
8953 +         md_number_to_chars(buf + 2, value, 2);
8954 +         break;
8955 +       case BFD_RELOC_AVR32_PCREL_SUB5:
8956 +         value = -value;
8957 +         /* fall through */
8958 +       case BFD_RELOC_AVR32_9_PCREL:
8959 +       case BFD_RELOC_AVR32_11_PCREL:
8960 +       case BFD_RELOC_AVR32_16_PCREL:
8961 +       case BFD_RELOC_AVR32_18_PCREL:
8962 +       case BFD_RELOC_AVR32_22_PCREL:
8963 +       case BFD_RELOC_AVR32_3U:
8964 +       case BFD_RELOC_AVR32_4UH:
8965 +       case BFD_RELOC_AVR32_6UW:
8966 +       case BFD_RELOC_AVR32_6S:
8967 +       case BFD_RELOC_AVR32_7UW:
8968 +       case BFD_RELOC_AVR32_8S:
8969 +       case BFD_RELOC_AVR32_10UW:
8970 +       case BFD_RELOC_AVR32_10SW:
8971 +       case BFD_RELOC_AVR32_14UW:
8972 +       case BFD_RELOC_AVR32_16S:
8973 +       case BFD_RELOC_AVR32_16U:
8974 +       case BFD_RELOC_AVR32_21S:
8975 +       case BFD_RELOC_AVR32_BRC1:
8976 +       case BFD_RELOC_AVR32_SUB5:
8977 +       case BFD_RELOC_AVR32_CPCALL:
8978 +       case BFD_RELOC_AVR32_16_CP:
8979 +       case BFD_RELOC_AVR32_9_CP:
8980 +       case BFD_RELOC_AVR32_15S:
8981 +         ifield = fixP->tc_fix_data.ifield;
8982 +         pr_debug("insert field: %ld <= %ld <= %ld (align %u)\n",
8983 +                  fixP->tc_fix_data.min, value, fixP->tc_fix_data.max,
8984 +                  fixP->tc_fix_data.align);
8985 +         if (value < fixP->tc_fix_data.min || value > fixP->tc_fix_data.max)
8986 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8987 +                        _("operand out of range (%ld not between %ld and %ld)"),
8988 +                        value, fixP->tc_fix_data.min, fixP->tc_fix_data.max);
8989 +         if (value & ((1 << fixP->tc_fix_data.align) - 1))
8990 +           as_bad_where(fixP->fx_file, fixP->fx_line,
8991 +                        _("misaligned operand (required alignment: %d)"),
8992 +                        1 << fixP->tc_fix_data.align);
8993 +         ifield->insert(ifield, buf, value >> fixP->tc_fix_data.align);
8994 +         break;
8995 +       case BFD_RELOC_AVR32_ALIGN:
8996 +         /* Nothing to do */
8997 +         fixP->fx_done = FALSE;
8998 +         break;
8999 +       default:
9000 +         as_fatal("reloc type %s not handled\n",
9001 +                  bfd_get_reloc_code_name(fixP->fx_r_type));
9002 +       }
9003 +    }
9004 +}
9005 +#endif
9006 +
9007 +arelent *
9008 +tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
9009 +             fixS *fixp)
9010 +{
9011 +  arelent *reloc;
9012 +  bfd_reloc_code_real_type code;
9013 +
9014 +  reloc = xmalloc (sizeof (arelent));
9015 +
9016 +  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
9017 +  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
9018 +  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
9019 +  reloc->addend = fixp->fx_offset;
9020 +  code = fixp->fx_r_type;
9021 +
9022 +  reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
9023 +
9024 +  if (reloc->howto == NULL)
9025 +    {
9026 +      as_bad_where (fixp->fx_file, fixp->fx_line,
9027 +                   _("cannot represent relocation %s in this object file format"),
9028 +                   bfd_get_reloc_code_name (code));
9029 +      return NULL;
9030 +    }
9031 +
9032 +  return reloc;
9033 +}
9034 +
9035 +bfd_boolean
9036 +avr32_force_reloc(fixS *fixP)
9037 +{
9038 +  if (linkrelax && fixP->fx_addsy
9039 +      && !(S_GET_SEGMENT(fixP->fx_addsy)->flags & SEC_DEBUGGING)
9040 +      && S_GET_SEGMENT(fixP->fx_addsy) != absolute_section)
9041 +    {
9042 +      pr_debug(stderr, "force reloc: addsy=%p, r_type=%d, sec=%s\n",
9043 +              fixP->fx_addsy, fixP->fx_r_type, S_GET_SEGMENT(fixP->fx_addsy)->name);
9044 +      return 1;
9045 +    }
9046 +
9047 +  return generic_force_reloc(fixP);
9048 +}
9049 +
9050 +bfd_boolean
9051 +avr32_fix_adjustable(fixS *fixP)
9052 +{
9053 +  switch (fixP->fx_r_type)
9054 +    {
9055 +      /* GOT relocations can't have addends since BFD treats all
9056 +        references to a given symbol the same. This means that we
9057 +        must avoid section-relative references to local symbols when
9058 +        dealing with these kinds of relocs */
9059 +    case BFD_RELOC_AVR32_GOT32:
9060 +    case BFD_RELOC_AVR32_GOT16:
9061 +    case BFD_RELOC_AVR32_GOT8:
9062 +    case BFD_RELOC_AVR32_GOT21S:
9063 +    case BFD_RELOC_AVR32_GOT18SW:
9064 +    case BFD_RELOC_AVR32_GOT16S:
9065 +    case BFD_RELOC_AVR32_LDA_GOT:
9066 +    case BFD_RELOC_AVR32_GOTCALL:
9067 +      pr_debug("fix not adjustable\n");
9068 +      return 0;
9069 +
9070 +    default:
9071 +      break;
9072 +    }
9073 +
9074 +  return 1;
9075 +}
9076 +
9077 +/* When we want the linker to be able to relax the code, we need to
9078 +   output a reloc for every .align directive requesting an alignment
9079 +   to a four byte boundary or larger.  If we don't do this, the linker
9080 +   can't guarantee that the alignment is actually maintained in the
9081 +   linker output.
9082 +
9083 +   TODO: Might as well insert proper NOPs while we're at it... */
9084 +void
9085 +avr32_handle_align(fragS *frag)
9086 +{
9087 +  if (linkrelax
9088 +      && frag->fr_type == rs_align_code
9089 +      && frag->fr_address + frag->fr_fix > 0
9090 +      && frag->fr_offset > 0)
9091 +    {
9092 +      /* The alignment order (fr_offset) is stored in the addend. */
9093 +      fix_new(frag, frag->fr_fix, 2, &abs_symbol, frag->fr_offset,
9094 +             FALSE, BFD_RELOC_AVR32_ALIGN);
9095 +    }
9096 +}
9097 +
9098 +/* Relax_align. Advance location counter to next address that has 'alignment'
9099 +   lowest order bits all 0s, return size of adjustment made.  */
9100 +relax_addressT
9101 +avr32_relax_align(segT segment ATTRIBUTE_UNUSED,
9102 +                 fragS *fragP,
9103 +                 relax_addressT address)
9104 +{
9105 +  relax_addressT mask;
9106 +  relax_addressT new_address;
9107 +  int alignment;
9108 +
9109 +  alignment = fragP->fr_offset;
9110 +  mask = ~((~0) << alignment);
9111 +  new_address = (address + mask) & (~mask);
9112 +
9113 +  return new_address - address;
9114 +}
9115 +
9116 +/* Turn a string in input_line_pointer into a floating point constant
9117 +   of type type, and store the appropriate bytes in *litP.  The number
9118 +   of LITTLENUMS emitted is stored in *sizeP .  An error message is
9119 +   returned, or NULL on OK. */
9120 +
9121 +/* Equal to MAX_PRECISION in atof-ieee.c */
9122 +#define MAX_LITTLENUMS 6
9123 +
9124 +char *
9125 +md_atof (type, litP, sizeP)
9126 +char   type;
9127 +char * litP;
9128 +int *  sizeP;
9129 +{
9130 +  int              i;
9131 +  int              prec;
9132 +  LITTLENUM_TYPE   words [MAX_LITTLENUMS];
9133 +  char *           t;
9134 +
9135 +  switch (type)
9136 +  {
9137 +    case 'f':
9138 +    case 'F':
9139 +    case 's':
9140 +    case 'S':
9141 +      prec = 2;
9142 +      break;
9143 +
9144 +    case 'd':
9145 +    case 'D':
9146 +    case 'r':
9147 +    case 'R':
9148 +      prec = 4;
9149 +      break;
9150 +
9151 +      /* FIXME: Some targets allow other format chars for bigger sizes here.  */
9152 +
9153 +    default:
9154 +      * sizeP = 0;
9155 +      return _("Bad call to md_atof()");
9156 +  }
9157 +
9158 +  t = atof_ieee (input_line_pointer, type, words);
9159 +  if (t)
9160 +    input_line_pointer = t;
9161 +  * sizeP = prec * sizeof (LITTLENUM_TYPE);
9162 +
9163 +  for (i = 0; i < prec; i++)
9164 +  {
9165 +    md_number_to_chars (litP, (valueT) words[i],
9166 +                        sizeof (LITTLENUM_TYPE));
9167 +    litP += sizeof (LITTLENUM_TYPE);
9168 +  }
9169 +
9170 +  return 0;
9171 +}
9172 +
9173 +static char *avr32_end_of_match(char *cont, char *what)
9174 +{
9175 +  int len = strlen (what);
9176 +
9177 +  if (! is_part_of_name (cont[len])
9178 +      && strncasecmp (cont, what, len) == 0)
9179 +    return cont + len;
9180 +
9181 +  return NULL;
9182 +}
9183 +
9184 +int
9185 +avr32_parse_name (char const *name, expressionS *exp, char *nextchar)
9186 +{
9187 +  char *next = input_line_pointer;
9188 +  char *next_end;
9189 +
9190 +  pr_debug("parse_name: %s, nextchar=%c (%02x)\n", name, *nextchar, *nextchar);
9191 +
9192 +  if (*nextchar == '(')
9193 +    {
9194 +      if (strcasecmp(name, "hi") == 0)
9195 +       {
9196 +         *next = *nextchar;
9197 +
9198 +         expression(exp);
9199 +
9200 +         if (exp->X_op == O_constant)
9201 +           {
9202 +             pr_debug("  -> constant hi(0x%08lx) -> 0x%04lx\n",
9203 +                      exp->X_add_number, exp->X_add_number >> 16);
9204 +             exp->X_add_number = (exp->X_add_number >> 16) & 0xffff;
9205 +           }
9206 +         else
9207 +           {
9208 +             exp->X_md = exp->X_op;
9209 +             exp->X_op = O_hi;
9210 +           }
9211 +
9212 +         return 1;
9213 +       }
9214 +      else if (strcasecmp(name, "lo") == 0)
9215 +       {
9216 +         *next = *nextchar;
9217 +
9218 +         expression(exp);
9219 +
9220 +         if (exp->X_op == O_constant)
9221 +           exp->X_add_number &= 0xffff;
9222 +         else
9223 +           {
9224 +             exp->X_md = exp->X_op;
9225 +             exp->X_op = O_lo;
9226 +           }
9227 +
9228 +         return 1;
9229 +       }
9230 +    }
9231 +  else if (*nextchar == '@')
9232 +    {
9233 +      exp->X_md = exp->X_op;
9234 +
9235 +      if ((next_end = avr32_end_of_match (next + 1, "got")))
9236 +       exp->X_op = O_got;
9237 +      else if ((next_end = avr32_end_of_match (next + 1, "tlsgd")))
9238 +       exp->X_op = O_tlsgd;
9239 +      /* Add more as needed */
9240 +      else
9241 +       {
9242 +         char c;
9243 +         input_line_pointer++;
9244 +         c = get_symbol_end();
9245 +         as_bad (_("unknown relocation override `%s'"), next + 1);
9246 +         *input_line_pointer = c;
9247 +         input_line_pointer = next;
9248 +         return 0;
9249 +       }
9250 +
9251 +      exp->X_op_symbol = NULL;
9252 +      exp->X_add_symbol = symbol_find_or_make (name);
9253 +      exp->X_add_number = 0;
9254 +
9255 +      *input_line_pointer = *nextchar;
9256 +      input_line_pointer = next_end;
9257 +      *nextchar = *input_line_pointer;
9258 +      *input_line_pointer = '\0';
9259 +      return 1;
9260 +    }
9261 +  else if (strcmp (name, "_GLOBAL_OFFSET_TABLE_") == 0)
9262 +    {
9263 +      if (!GOT_symbol)
9264 +       GOT_symbol = symbol_find_or_make(name);
9265 +
9266 +      exp->X_add_symbol = GOT_symbol;
9267 +      exp->X_op = O_symbol;
9268 +      exp->X_add_number = 0;
9269 +      return 1;
9270 +    }
9271 +
9272 +  return 0;
9273 +}
9274 +
9275 +static void
9276 +s_rseg (int value ATTRIBUTE_UNUSED)
9277 +{
9278 +  /* Syntax: RSEG segment_name [:type] [NOROOT|ROOT] [(align)]
9279 +   * Defaults:
9280 +   *  - type: undocumented ("typically CODE or DATA")
9281 +   *  - ROOT
9282 +   *  - align: 1 for code, 0 for others
9283 +   *
9284 +   * TODO: NOROOT is ignored. If gas supports discardable segments, it should
9285 +   * be implemented.
9286 +   */
9287 +  char *name, *end;
9288 +  int length, type, attr;
9289 +  int align = 0;
9290 +
9291 +  SKIP_WHITESPACE();
9292 +
9293 +  end = input_line_pointer;
9294 +  while (0 == strchr ("\n\t;:( ", *end))
9295 +    end++;
9296 +  if (end == input_line_pointer)
9297 +    {
9298 +      as_warn (_("missing name"));
9299 +      ignore_rest_of_line();
9300 +      return;
9301 +    }
9302 +
9303 +  name = xmalloc (end - input_line_pointer + 1);
9304 +  memcpy (name, input_line_pointer, end - input_line_pointer);
9305 +  name[end - input_line_pointer] = '\0';
9306 +  input_line_pointer = end;
9307 +
9308 +  SKIP_WHITESPACE();
9309 +
9310 +  type = SHT_NULL;
9311 +  attr = 0;
9312 +
9313 +  if (*input_line_pointer == ':')
9314 +    {
9315 +      /* Skip the colon */
9316 +      ++input_line_pointer;
9317 +      SKIP_WHITESPACE();
9318 +
9319 +      /* Possible options at this point:
9320 +       *   - flag (ROOT or NOROOT)
9321 +       *   - a segment type
9322 +       */
9323 +      end = input_line_pointer;
9324 +      while (0 == strchr ("\n\t;:( ", *end))
9325 +       end++;
9326 +      length = end - input_line_pointer;
9327 +      if (((length == 4) && (0 == strncasecmp( input_line_pointer, "ROOT", 4))) ||
9328 +         ((length == 6) && (0 == strncasecmp( input_line_pointer, "NOROOT", 6))))
9329 +       {
9330 +         /* Ignore ROOT/NOROOT */
9331 +         input_line_pointer = end;
9332 +       }
9333 +      else
9334 +       {
9335 +         /* Must be a segment type */
9336 +         switch (*input_line_pointer)
9337 +           {
9338 +           case 'C':
9339 +           case 'c':
9340 +             if ((length == 4) &&
9341 +                 (0 == strncasecmp (input_line_pointer, "CODE", 4)))
9342 +               {
9343 +                 attr |= SHF_ALLOC | SHF_EXECINSTR;
9344 +                 type = SHT_PROGBITS;
9345 +                 align = 1;
9346 +                 break;
9347 +               }
9348 +             if ((length == 5) &&
9349 +                 (0 == strncasecmp (input_line_pointer, "CONST", 5)))
9350 +               {
9351 +                 attr |= SHF_ALLOC;
9352 +                 type = SHT_PROGBITS;
9353 +                 break;
9354 +               }
9355 +             goto de_fault;
9356 +
9357 +           case 'D':
9358 +           case 'd':
9359 +             if ((length == 4) &&
9360 +                 (0 == strncasecmp (input_line_pointer, "DATA", 4)))
9361 +               {
9362 +                 attr |= SHF_ALLOC | SHF_WRITE;
9363 +                 type = SHT_PROGBITS;
9364 +                 break;
9365 +               }
9366 +             goto de_fault;
9367 +
9368 +             /* TODO: Add FAR*, HUGE*, IDATA and NEAR* if necessary */
9369 +
9370 +           case 'U':
9371 +           case 'u':
9372 +             if ((length == 7) &&
9373 +                 (0 == strncasecmp (input_line_pointer, "UNTYPED", 7)))
9374 +               break;
9375 +             goto de_fault;
9376 +
9377 +             /* TODO: Add XDATA and ZPAGE if necessary */
9378 +
9379 +           de_fault:
9380 +           default:
9381 +             as_warn (_("unrecognized segment type"));
9382 +           }
9383 +
9384 +         input_line_pointer = end;
9385 +         SKIP_WHITESPACE();
9386 +
9387 +         if (*input_line_pointer == ':')
9388 +           {
9389 +             /*  ROOT/NOROOT */
9390 +             ++input_line_pointer;
9391 +             SKIP_WHITESPACE();
9392 +
9393 +             end = input_line_pointer;
9394 +             while (0 == strchr ("\n\t;:( ", *end))
9395 +               end++;
9396 +             length = end - input_line_pointer;
9397 +             if (! ((length == 4) &&
9398 +                    (0 == strncasecmp( input_line_pointer, "ROOT", 4))) &&
9399 +                 ! ((length == 6) &&
9400 +                    (0 == strncasecmp( input_line_pointer, "NOROOT", 6))))
9401 +               {
9402 +                 as_warn (_("unrecognized segment flag"));
9403 +               }
9404 +
9405 +             input_line_pointer = end;
9406 +             SKIP_WHITESPACE();
9407 +           }
9408 +       }
9409 +    }
9410 +
9411 +  if (*input_line_pointer == '(')
9412 +    {
9413 +      align = get_absolute_expression ();
9414 +    }
9415 +
9416 +  demand_empty_rest_of_line();
9417 +
9418 +  obj_elf_change_section (name, type, attr, 0, NULL, 0, 0);
9419 +#ifdef AVR32_DEBUG
9420 +  fprintf( stderr, "RSEG: Changed section to %s, type: 0x%x, attr: 0x%x\n",
9421 +      name, type, attr );
9422 +  fprintf( stderr, "RSEG: Aligning to 2**%d\n", align );
9423 +#endif
9424 +
9425 +  if (align > 15)
9426 +    {
9427 +      align = 15;
9428 +      as_warn (_("alignment too large: %u assumed"), align);
9429 +    }
9430 +
9431 +  /* Hope not, that is */
9432 +  assert (now_seg != absolute_section);
9433 +
9434 +  /* Only make a frag if we HAVE to... */
9435 +  if (align != 0 && !need_pass_2)
9436 +    {
9437 +      if (subseg_text_p (now_seg))
9438 +       frag_align_code (align, 0);
9439 +      else
9440 +       frag_align (align, 0, 0);
9441 +    }
9442 +
9443 +  record_alignment (now_seg, align - OCTETS_PER_BYTE_POWER);
9444 +}
9445 +
9446 +/* vim: syntax=c sw=2
9447 + */
9448 --- /dev/null
9449 +++ b/gas/config/tc-avr32.h
9450 @@ -0,0 +1,325 @@
9451 +/* Assembler definitions for AVR32.
9452 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
9453 +
9454 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
9455 +
9456 +   This file is part of GAS, the GNU Assembler.
9457 +
9458 +   GAS is free software; you can redistribute it and/or modify it
9459 +   under the terms of the GNU General Public License as published by
9460 +   the Free Software Foundation; either version 2, or (at your option)
9461 +   any later version.
9462 +
9463 +   GAS is distributed in the hope that it will be useful, but WITHOUT
9464 +   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
9465 +   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
9466 +   License for more details.
9467 +
9468 +   You should have received a copy of the GNU General Public License
9469 +   along with GAS; see the file COPYING.  If not, write to the Free
9470 +   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
9471 +   02111-1307, USA.  */
9472 +
9473 +#if 0
9474 +#define DEBUG
9475 +#define DEBUG1
9476 +#define DEBUG2
9477 +#define DEBUG3
9478 +#define DEBUG4
9479 +#define DEBUG5
9480 +#endif
9481 +
9482 +/* Are we trying to be compatible with the IAR assembler? (--iar) */
9483 +extern int avr32_iarcompat;
9484 +
9485 +/* By convention, you should define this macro in the `.h' file.  For
9486 +   example, `tc-m68k.h' defines `TC_M68K'.  You might have to use this
9487 +   if it is necessary to add CPU specific code to the object format
9488 +   file.  */
9489 +#define TC_AVR32
9490 +
9491 +/* This macro is the BFD target name to use when creating the output
9492 +   file.  This will normally depend upon the `OBJ_FMT' macro.  */
9493 +#define TARGET_FORMAT "elf32-avr32"
9494 +
9495 +/* This macro is the BFD architecture to pass to `bfd_set_arch_mach'.  */
9496 +#define TARGET_ARCH bfd_arch_avr32
9497 +
9498 +/* This macro is the BFD machine number to pass to
9499 +   `bfd_set_arch_mach'.  If it is not defined, GAS will use 0.  */
9500 +#define TARGET_MACH 0
9501 +
9502 +/* UNDOCUMENTED: Allow //-style comments */
9503 +#define DOUBLESLASH_LINE_COMMENTS
9504 +
9505 +/* You should define this macro to be non-zero if the target is big
9506 +   endian, and zero if the target is little endian.  */
9507 +#define TARGET_BYTES_BIG_ENDIAN 1
9508 +
9509 +/* FIXME: It seems that GAS only expects a one-byte opcode...
9510 +   #define NOP_OPCODE 0xd703 */
9511 +
9512 +/* If you define this macro, GAS will warn about the use of
9513 +   nonstandard escape sequences in a string.  */
9514 +#undef ONLY_STANDARD_ESCAPES
9515 +
9516 +#define DWARF2_FORMAT(SEC) dwarf2_format_32bit
9517 +
9518 +/* Instructions are either 2 or 4 bytes long */
9519 +/* #define DWARF2_LINE_MIN_INSN_LENGTH 2 */
9520 +
9521 +/* GAS will call this function for any expression that can not be
9522 +   recognized.  When the function is called, `input_line_pointer'
9523 +   will point to the start of the expression.  */
9524 +#define md_operand(x)
9525 +
9526 +#define md_parse_name(name, expr, mode, c) avr32_parse_name(name, expr, c)
9527 +extern int avr32_parse_name(const char *, struct expressionS *, char *);
9528 +
9529 +/* You may define this macro to generate a fixup for a data
9530 +   allocation pseudo-op.  */
9531 +#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP)   \
9532 +  avr32_cons_fix_new(FRAG, OFF, LEN, EXP)
9533 +void avr32_cons_fix_new (fragS *, int, int, expressionS *);
9534 +
9535 +/* `extsym - .' expressions can be emitted using PC-relative relocs */
9536 +#define DIFF_EXPR_OK
9537 +
9538 +/* This is used to construct expressions out of @gotoff, etc. The
9539 +   relocation type is stored in X_md */
9540 +#define O_got          O_md1
9541 +#define O_hi           O_md2
9542 +#define O_lo           O_md3
9543 +#define O_tlsgd                O_md4
9544 +
9545 +/* You may define this macro to parse an expression used in a data
9546 +   allocation pseudo-op such as `.word'.  You can use this to
9547 +   recognize relocation directives that may appear in such directives.  */
9548 +/* #define TC_PARSE_CONS_EXPRESSION(EXPR,N) avr_parse_cons_expression (EXPR,N)
9549 +   void avr_parse_cons_expression (expressionS *exp, int nbytes); */
9550 +
9551 +/* This should just call either `number_to_chars_bigendian' or
9552 +   `number_to_chars_littleendian', whichever is appropriate.  On
9553 +   targets like the MIPS which support options to change the
9554 +   endianness, which function to call is a runtime decision.  On
9555 +   other targets, `md_number_to_chars' can be a simple macro.  */
9556 +#define md_number_to_chars number_to_chars_bigendian
9557 +
9558 +/* `md_short_jump_size'
9559 +   `md_long_jump_size'
9560 +   `md_create_short_jump'
9561 +   `md_create_long_jump'
9562 +   If `WORKING_DOT_WORD' is defined, GAS will not do broken word
9563 +   processing (*note Broken words::.).  Otherwise, you should set
9564 +   `md_short_jump_size' to the size of a short jump (a jump that is
9565 +   just long enough to jump around a long jmp) and
9566 +   `md_long_jump_size' to the size of a long jump (a jump that can go
9567 +   anywhere in the function), You should define
9568 +   `md_create_short_jump' to create a short jump around a long jump,
9569 +   and define `md_create_long_jump' to create a long jump.  */
9570 +#define WORKING_DOT_WORD
9571 +
9572 +/* If you define this macro, it means that `tc_gen_reloc' may return
9573 +   multiple relocation entries for a single fixup.  In this case, the
9574 +   return value of `tc_gen_reloc' is a pointer to a null terminated
9575 +   array.  */
9576 +#undef RELOC_EXPANSION_POSSIBLE
9577 +
9578 +/* If you define this macro, GAS will not require pseudo-ops to start with a .
9579 +   character. */
9580 +#define NO_PSEUDO_DOT (avr32_iarcompat)
9581 +
9582 +/* The IAR assembler uses $ as the location counter. Unfortunately, we
9583 +   can't make this dependent on avr32_iarcompat... */
9584 +#define DOLLAR_DOT
9585 +
9586 +/* Values passed to md_apply_fix3 don't include the symbol value.  */
9587 +#define MD_APPLY_SYM_VALUE(FIX) 0
9588 +
9589 +/* The number of bytes to put into a word in a listing.  This affects
9590 +   the way the bytes are clumped together in the listing.  For
9591 +   example, a value of 2 might print `1234 5678' where a value of 1
9592 +   would print `12 34 56 78'.  The default value is 4.  */
9593 +#define LISTING_WORD_SIZE 4
9594 +
9595 +/* extern const struct relax_type md_relax_table[];
9596 +#define TC_GENERIC_RELAX_TABLE md_relax_table */
9597 +
9598 +/*
9599 +  An `.lcomm' directive with no explicit alignment parameter will use
9600 +  this macro to set P2VAR to the alignment that a request for SIZE
9601 +  bytes will have.  The alignment is expressed as a power of two.  If
9602 +  no alignment should take place, the macro definition should do
9603 +  nothing.  Some targets define a `.bss' directive that is also
9604 +  affected by this macro.  The default definition will set P2VAR to
9605 +  the truncated power of two of sizes up to eight bytes.
9606 +
9607 +  We want doublewords to be word-aligned, so we're going to modify the
9608 +  default definition a tiny bit.
9609 +*/
9610 +#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR)       \
9611 +  do                                                   \
9612 +    {                                                  \
9613 +      if ((SIZE) >= 4)                                 \
9614 +       (P2VAR) = 2;                                    \
9615 +      else if ((SIZE) >= 2)                            \
9616 +       (P2VAR) = 1;                                    \
9617 +      else                                             \
9618 +       (P2VAR) = 0;                                    \
9619 +    }                                                  \
9620 +  while (0)
9621 +
9622 +/* When relaxing, we need to generate relocations for alignment
9623 +   directives.  */
9624 +#define HANDLE_ALIGN(frag) avr32_handle_align(frag)
9625 +extern void avr32_handle_align(fragS *);
9626 +
9627 +/* See internals doc for explanation. Oh wait...
9628 +   Now, can you guess where "alignment" comes from? ;-) */
9629 +#define MAX_MEM_FOR_RS_ALIGN_CODE ((1 << alignment) - 1)
9630 +
9631 +/* We need to stop gas from reducing certain expressions (e.g. GOT
9632 +   references) */
9633 +#define tc_fix_adjustable(fix) avr32_fix_adjustable(fix)
9634 +extern bfd_boolean avr32_fix_adjustable(struct fix *);
9635 +
9636 +/* The linker needs to be passed a little more information when relaxing. */
9637 +#define TC_FORCE_RELOCATION(fix) avr32_force_reloc(fix)
9638 +extern bfd_boolean avr32_force_reloc(struct fix *);
9639 +
9640 +/* I'm tired of working around all the madness in fixup_segment().
9641 +   This hook will do basically the same things as the generic code,
9642 +   and then it will "goto" right past it.  */
9643 +#define TC_VALIDATE_FIX(FIX, SEG, SKIP)                \
9644 +  do                                           \
9645 +    {                                          \
9646 +      avr32_process_fixup(FIX, SEG);           \
9647 +      if (!(FIX)->fx_done)                     \
9648 +       ++seg_reloc_count;                      \
9649 +      goto SKIP;                               \
9650 +    }                                          \
9651 +  while (0)
9652 +extern void avr32_process_fixup(struct fix *fixP, segT this_segment);
9653 +
9654 +/* Positive values of TC_FX_SIZE_SLACK allow a target to define
9655 +   fixups that far past the end of a frag.  Having such fixups
9656 +   is of course most most likely a bug in setting fx_size correctly.
9657 +   A negative value disables the fixup check entirely, which is
9658 +   appropriate for something like the Renesas / SuperH SH_COUNT
9659 +   reloc.  */
9660 +/* This target is buggy, and sets fix size too large.  */
9661 +#define TC_FX_SIZE_SLACK(FIX) -1
9662 +
9663 +/* We don't want the gas core to make any assumptions about our way of
9664 +   doing linkrelaxing.  */
9665 +#define TC_LINKRELAX_FIXUP(SEG)                        0
9666 +
9667 +/* ... but we do want it to insert lots of padding. */
9668 +#define LINKER_RELAXING_SHRINKS_ONLY
9669 +
9670 +/* Better do it ourselves, really... */
9671 +#define TC_RELAX_ALIGN(SEG, FRAG, ADDR)        avr32_relax_align(SEG, FRAG, ADDR)
9672 +extern relax_addressT
9673 +avr32_relax_align(segT segment, fragS *fragP, relax_addressT address);
9674 +
9675 +/* Use line number format that is amenable to linker relaxation.  */
9676 +#define DWARF2_USE_FIXED_ADVANCE_PC (linkrelax != 0)
9677 +
9678 +/* This is called by write_object_file() just before symbols are
9679 +   attempted converted into section symbols.  */
9680 +#define tc_frob_file_before_adjust()   avr32_frob_file()
9681 +extern void avr32_frob_file(void);
9682 +
9683 +/* If you define this macro, GAS will call it at the end of each input
9684 +   file.  */
9685 +#define md_cleanup() avr32_cleanup()
9686 +extern void avr32_cleanup(void);
9687 +
9688 +/* There's an AVR32-specific hack in operand() which creates O_md
9689 +   expressions when encountering HWRD or LWRD. We need to generate
9690 +   proper relocs for them */
9691 +/* #define md_cgen_record_fixup_exp avr32_cgen_record_fixup_exp */
9692 +
9693 +/* I needed to add an extra hook in gas_cgen_finish_insn() for
9694 +   conversion of O_md* operands because md_cgen_record_fixup_exp()
9695 +   isn't called for relaxable insns */
9696 +/* #define md_cgen_convert_expr(exp, opinfo) avr32_cgen_convert_expr(exp, opinfo)
9697 +   int avr32_cgen_convert_expr(expressionS *, int); */
9698 +
9699 +/* #define tc_gen_reloc gas_cgen_tc_gen_reloc */
9700 +
9701 +/* If you define this macro, it should return the position from which
9702 +   the PC relative adjustment for a PC relative fixup should be
9703 +   made. On many processors, the base of a PC relative instruction is
9704 +   the next instruction, so this macro would return the length of an
9705 +   instruction, plus the address of the PC relative fixup. The latter
9706 +   can be calculated as fixp->fx_where + fixp->fx_frag->fr_address. */
9707 +extern long md_pcrel_from_section (struct fix *, segT);
9708 +#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
9709 +
9710 +#define LOCAL_LABEL(name) (name[0] == '.' && (name[1] == 'L'))
9711 +#define LOCAL_LABELS_FB                1
9712 +
9713 +struct avr32_relaxer
9714 +{
9715 +  int (*estimate_size)(fragS *, segT);
9716 +  long (*relax_frag)(segT, fragS *, long);
9717 +  void (*convert_frag)(bfd *, segT, fragS *);
9718 +};
9719 +
9720 +/* AVR32 has quite complex instruction coding, which means we need
9721 + * lots of information in order to do the right thing during relaxing
9722 + * (basically, we need to be able to reconstruct a whole new opcode if
9723 + * necessary) */
9724 +#define TC_FRAG_TYPE struct avr32_frag_data
9725 +
9726 +struct cpool;
9727 +
9728 +struct avr32_frag_data
9729 +{
9730 +  /* TODO: Maybe add an expression object here so that we can use
9731 +     fix_new_exp() in md_convert_frag?  We may have to decide
9732 +     pcrel-ness in md_estimate_size_before_relax() as well...or we
9733 +     might do it when parsing.  Doing it while parsing may fail
9734 +     because the sub_symbol is undefined then... */
9735 +  int pcrel;
9736 +  int force_extended;
9737 +  int reloc_info;
9738 +  struct avr32_relaxer *relaxer;
9739 +  expressionS exp;
9740 +
9741 +  /* Points to associated constant pool, for use by LDA and CALL in
9742 +     non-pic mode, and when relaxing the .cpool directive */
9743 +  struct cpool *pool;
9744 +  unsigned int pool_entry;
9745 +};
9746 +
9747 +/* We will have to initialize the fields explicitly when needed */
9748 +#define TC_FRAG_INIT(fragP)
9749 +
9750 +#define md_estimate_size_before_relax(fragP, segT)                     \
9751 +  ((fragP)->tc_frag_data.relaxer->estimate_size(fragP, segT))
9752 +#define md_relax_frag(segment, fragP, stretch)                         \
9753 +  ((fragP)->tc_frag_data.relaxer->relax_frag(segment, fragP, stretch))
9754 +#define md_convert_frag(abfd, segment, fragP)                          \
9755 +  ((fragP)->tc_frag_data.relaxer->convert_frag(abfd, segment, fragP))
9756 +
9757 +#define TC_FIX_TYPE struct avr32_fix_data
9758 +
9759 +struct avr32_fix_data
9760 +{
9761 +  const struct avr32_ifield *ifield;
9762 +  unsigned int align;
9763 +  long min;
9764 +  long max;
9765 +};
9766 +
9767 +#define TC_INIT_FIX_DATA(fixP)                 \
9768 +  do                                           \
9769 +    {                                          \
9770 +      (fixP)->tc_fix_data.ifield = NULL;       \
9771 +      (fixP)->tc_fix_data.align = 0;           \
9772 +      (fixP)->tc_fix_data.min = 0;             \
9773 +      (fixP)->tc_fix_data.max = 0;             \
9774 +    }                                          \
9775 +  while (0)
9776 --- a/gas/configure.tgt
9777 +++ b/gas/configure.tgt
9778 @@ -33,6 +33,7 @@ case ${cpu} in
9779    am33_2.0)            cpu_type=mn10300 endian=little ;;
9780    arm*be|arm*b)                cpu_type=arm endian=big ;;
9781    arm*)                        cpu_type=arm endian=little ;;
9782 +  avr32*)              cpu_type=avr32 endian=big ;;
9783    bfin*)               cpu_type=bfin endian=little ;;
9784    c4x*)                        cpu_type=tic4x ;;
9785    cr16*)               cpu_type=cr16 endian=little ;;
9786 @@ -136,6 +137,9 @@ case ${generic_target} in
9787
9788    cr16-*-elf*)                         fmt=elf ;;
9789
9790 +  avr32-*-linux*)                      fmt=elf  em=linux bfd_gas=yes ;;
9791 +  avr32*)                              fmt=elf  bfd_gas=yes ;;
9792 +
9793    cris-*-linux-* | crisv32-*-linux-*)
9794                                         fmt=multi em=linux ;;
9795    cris-*-* | crisv32-*-*)              fmt=multi ;;
9796 --- a/gas/doc/all.texi
9797 +++ b/gas/doc/all.texi
9798 @@ -30,6 +30,7 @@
9799  @set ARC
9800  @set ARM
9801  @set AVR
9802 +@set AVR32
9803  @set Blackfin
9804  @set CR16
9805  @set CRIS
9806 --- a/gas/doc/asconfig.texi
9807 +++ b/gas/doc/asconfig.texi
9808 @@ -30,6 +30,7 @@
9809  @set ARC
9810  @set ARM
9811  @set AVR
9812 +@set AVR32
9813  @set Blackfin
9814  @set CR16
9815  @set CRIS
9816 --- a/gas/doc/as.texinfo
9817 +++ b/gas/doc/as.texinfo
9818 @@ -6877,6 +6877,9 @@ subject, see the hardware manufacturer's
9819  @ifset AVR
9820  * AVR-Dependent::               AVR Dependent Features
9821  @end ifset
9822 +@ifset AVR32
9823 +* AVR32-Dependent::               AVR32 Dependent Features
9824 +@end ifset
9825  @ifset Blackfin
9826  * Blackfin-Dependent::         Blackfin Dependent Features
9827  @end ifset
9828 @@ -7018,6 +7021,10 @@ subject, see the hardware manufacturer's
9829  @include c-avr.texi
9830  @end ifset
9831
9832 +@ifset AVR32
9833 +@include c-avr32.texi
9834 +@end ifset
9835 +
9836  @ifset Blackfin
9837  @include c-bfin.texi
9838  @end ifset
9839 --- /dev/null
9840 +++ b/gas/doc/c-avr32.texi
9841 @@ -0,0 +1,244 @@
9842 +@c Copyright 2005, 2006, 2007, 2008, 2009
9843 +@c Atmel Corporation
9844 +@c This is part of the GAS manual.
9845 +@c For copying conditions, see the file as.texinfo.
9846 +
9847 +@ifset GENERIC
9848 +@page
9849 +@node AVR32-Dependent
9850 +@chapter AVR32 Dependent Features
9851 +@end ifset
9852 +
9853 +@ifclear GENERIC
9854 +@node Machine Dependencies
9855 +@chapter AVR32 Dependent Features
9856 +@end ifclear
9857 +
9858 +@cindex AVR32 support
9859 +@menu
9860 +* AVR32 Options::               Options
9861 +* AVR32 Syntax::                Syntax
9862 +* AVR32 Directives::            Directives
9863 +* AVR32 Opcodes::               Opcodes
9864 +@end menu
9865 +
9866 +@node AVR32 Options
9867 +@section Options
9868 +@cindex AVR32 options
9869 +@cindex options for AVR32
9870 +
9871 +@table @code
9872 +
9873 +@cindex @code{--pic} command line option, AVR32
9874 +@cindex PIC code generation for AVR32
9875 +@item --pic
9876 +This option specifies that the output of the assembler should be marked
9877 +as position-independent code (PIC).  It will also ensure that
9878 +pseudo-instructions that deal with address calculation are output as
9879 +PIC, and that all absolute address references in the code are marked as
9880 +such.
9881 +
9882 +@cindex @code{--linkrelax} command line option, AVR32
9883 +@item --linkrelax
9884 +This option specifies that the output of the assembler should be marked
9885 +as linker-relaxable.  It will also ensure that all PC-relative operands
9886 +that may change during linker relaxation get appropriate relocations.
9887 +
9888 +@end table
9889 +
9890 +
9891 +@node AVR32 Syntax
9892 +@section Syntax
9893 +@menu
9894 +* AVR32-Chars::              Special Characters
9895 +* AVR32-Symrefs::            Symbol references
9896 +@end menu
9897 +
9898 +@node AVR32-Chars
9899 +@subsection Special Characters
9900 +
9901 +@cindex line comment character, AVR32
9902 +@cindex AVR32 line comment character
9903 +The presence of a @samp{//} on a line indicates the start of a comment
9904 +that extends to the end of the current line.  If a @samp{#} appears as
9905 +the first character of a line, the whole line is treated as a comment.
9906 +
9907 +@cindex line separator, AVR32
9908 +@cindex statement separator, AVR32
9909 +@cindex AVR32 line separator
9910 +The @samp{;} character can be used instead of a newline to separate
9911 +statements.
9912 +
9913 +@node AVR32-Symrefs
9914 +@subsection Symbol references
9915 +
9916 +The absolute value of a symbol can be obtained by simply naming the
9917 +symbol.  However, as AVR32 symbols have 32-bit values, most symbols have
9918 +values that are outside the range of any instructions.
9919 +
9920 +Instructions that take a PC-relative offset, e.g. @code{lddpc} or
9921 +@code{rcall}, can also reference a symbol by simply naming the symbol
9922 +(no explicit calculations necessary).  In this case, the assembler or
9923 +linker subtracts the address of the instruction from the symbol's value
9924 +and inserts the result into the instruction.  Note that even though an
9925 +overflow is less likely to happen for a relative reference than for an
9926 +absolute reference, the assembler or linker will generate an error if
9927 +the referenced symbol is too far away from the current location.
9928 +
9929 +Relative references can be used for data as well.  For example:
9930 +
9931 +@smallexample
9932 +        lddpc   r0, 2f
9933 +1:      add     r0, pc
9934 +        ...
9935 +        .align  2
9936 +2:      .int    @var{some_symbol} - 1b
9937 +@end smallexample
9938 +
9939 +Here, r0 will end up with the run-time address of @var{some_symbol} even
9940 +if the program was loaded at a different address than it was linked
9941 +(position-independent code).
9942 +
9943 +@subsubsection Symbol modifiers
9944 +
9945 +@table @code
9946 +
9947 +@item @code{hi(@var{symbol})}
9948 +Evaluates to the value of the symbol shifted right 16 bits.  This will
9949 +work even if @var{symbol} is defined in a different module.
9950 +
9951 +@item @code{lo(@var{symbol})}
9952 +Evaluates to the low 16 bits of the symbol's value.  This will work even
9953 +if @var{symbol} is defined in a different module.
9954 +
9955 +@item @code{@var{symbol}@@got}
9956 +Create a GOT entry for @var{symbol} and return the offset of that entry
9957 +relative to the GOT base.
9958 +
9959 +@end table
9960 +
9961 +
9962 +@node AVR32 Directives
9963 +@section Directives
9964 +@cindex machine directives, AVR32
9965 +@cindex AVR32 directives
9966 +
9967 +@table @code
9968 +
9969 +@cindex @code{.cpool} directive, AVR32
9970 +@item .cpool
9971 +This directive causes the current contents of the constant pool to be
9972 +dumped into the current section at the current location (aligned to a
9973 +word boundary).  @code{GAS} maintains a separate constant pool for each
9974 +section and each sub-section.  The @code{.cpool} directive will only
9975 +affect the constant pool of the current section and sub-section.  At the
9976 +end of assembly, all remaining, non-empty constant pools will
9977 +automatically be dumped.
9978 +
9979 +@end table
9980 +
9981 +
9982 +@node AVR32 Opcodes
9983 +@section Opcodes
9984 +@cindex AVR32 opcodes
9985 +@cindex opcodes for AVR32
9986 +
9987 +@code{@value{AS}} implements all the standard AVR32 opcodes.  It also
9988 +implements several pseudo-opcodes, which are recommended to use wherever
9989 +possible because they give the tool chain better freedom to generate
9990 +optimal code.
9991 +
9992 +@table @code
9993 +
9994 +@cindex @code{LDA.W reg, symbol} pseudo op, AVR32
9995 +@item LDA.W
9996 +@smallexample
9997 +        lda.w   @var{reg}, @var{symbol}
9998 +@end smallexample
9999 +
10000 +This instruction will load the address of @var{symbol} into
10001 +@var{reg}. The instruction will evaluate to one of the following,
10002 +depending on the relative distance to the symbol, the relative distance
10003 +to the constant pool and whether the @code{--pic} option has been
10004 +specified. If the @code{--pic} option has not been specified, the
10005 +alternatives are as follows:
10006 +@smallexample
10007 +        /* @var{symbol} evaluates to a small enough value */
10008 +        mov     @var{reg}, @var{symbol}
10009 +
10010 +        /* (. - @var{symbol}) evaluates to a small enough value */
10011 +        sub     @var{reg}, pc, . - @var{symbol}
10012 +
10013 +        /* Constant pool is close enough */
10014 +        lddpc   @var{reg}, @var{cpent}
10015 +        ...
10016 +@var{cpent}:
10017 +        .long   @var{symbol}
10018 +
10019 +        /* Otherwise (not implemented yet, probably not necessary) */
10020 +        mov     @var{reg}, lo(@var{symbol})
10021 +        orh     @var{reg}, hi(@var{symbol})
10022 +@end smallexample
10023 +
10024 +If the @code{--pic} option has been specified, the alternatives are as
10025 +follows:
10026 +@smallexample
10027 +        /* (. - @var{symbol}) evaluates to a small enough value */
10028 +        sub     @var{reg}, pc, . - @var{symbol}
10029 +
10030 +        /* If @code{--linkrelax} not specified */
10031 +        ld.w    @var{reg}, r6[@var{symbol}@@got]
10032 +
10033 +        /* Otherwise */
10034 +        mov     @var{reg}, @var{symbol}@@got / 4
10035 +        ld.w    @var{reg}, r6[@var{reg} << 2]
10036 +@end smallexample
10037 +
10038 +If @var{symbol} is not defined in the same file and section as the
10039 +@code{LDA.W} instruction, the most pessimistic alternative of the
10040 +above is selected. The linker may convert it back into the most
10041 +optimal alternative when the final value of all symbols is known.
10042 +
10043 +@cindex @code{CALL symbol} pseudo op, AVR32
10044 +@item CALL
10045 +@smallexample
10046 +        call    @var{symbol}
10047 +@end smallexample
10048 +
10049 +This instruction will insert code to call the subroutine identified by
10050 +@var{symbol}. It will evaluate to one of the following, depending on
10051 +the relative distance to the symbol as well as the @code{--linkrelax}
10052 +and @code{--pic} command-line options.
10053 +
10054 +If @var{symbol} is defined in the same section and input file, and the
10055 +distance is small enough, an @code{rcall} instruction is inserted:
10056 +@smallexample
10057 +        rcall   @var{symbol}
10058 +@end smallexample
10059 +
10060 +Otherwise, if the @code{--pic} option has not been specified:
10061 +@smallexample
10062 +        mcall   @var{cpent}
10063 +        ...
10064 +@var{cpent}:
10065 +        .long   @var{symbol}
10066 +@end smallexample
10067 +
10068 +Finally, if nothing else fits and the @code{--pic} option has been
10069 +specified, the assembler will indirect the call through the Global
10070 +Offset Table:
10071 +@smallexample
10072 +        /* If @code{--linkrelax} not specified */
10073 +        mcall   r6[@var{symbol}@@got]
10074 +
10075 +        /* If @code{--linkrelax} specified */
10076 +        mov     lr, @var{symbol}@@got / 4
10077 +        ld.w    lr, r6[lr << 2]
10078 +        icall   lr
10079 +@end smallexample
10080 +
10081 +The linker, after determining the final value of @var{symbol}, may
10082 +convert any of these into more optimal alternatives. This includes
10083 +deleting any superfluous constant pool- and GOT-entries.
10084 +
10085 +@end table
10086 --- a/gas/doc/Makefile.am
10087 +++ b/gas/doc/Makefile.am
10088 @@ -33,6 +33,7 @@ CPU_DOCS = \
10089         c-arc.texi \
10090         c-arm.texi \
10091         c-avr.texi \
10092 +       c-avr32.texi \
10093         c-bfin.texi \
10094         c-cr16.texi \
10095         c-d10v.texi \
10096 --- a/gas/Makefile.am
10097 +++ b/gas/Makefile.am
10098 @@ -111,6 +111,7 @@ TARGET_CPU_CFILES = \
10099         config/tc-arc.c \
10100         config/tc-arm.c \
10101         config/tc-avr.c \
10102 +       config/tc-avr32.c \
10103         config/tc-bfin.c \
10104         config/tc-cr16.c \
10105         config/tc-cris.c \
10106 @@ -175,6 +176,7 @@ TARGET_CPU_HFILES = \
10107         config/tc-arc.h \
10108         config/tc-arm.h \
10109         config/tc-avr.h \
10110 +       config/tc-avr32.h \
10111         config/tc-bfin.h \
10112         config/tc-cr16.h \
10113         config/tc-cris.h \
10114 --- a/gas/Makefile.in
10115 +++ b/gas/Makefile.in
10116 @@ -378,6 +378,7 @@ TARGET_CPU_CFILES = \
10117         config/tc-arc.c \
10118         config/tc-arm.c \
10119         config/tc-avr.c \
10120 +       config/tc-avr32.c \
10121         config/tc-bfin.c \
10122         config/tc-cr16.c \
10123         config/tc-cris.c \
10124 @@ -442,6 +443,7 @@ TARGET_CPU_HFILES = \
10125         config/tc-arc.h \
10126         config/tc-arm.h \
10127         config/tc-avr.h \
10128 +       config/tc-avr32.h \
10129         config/tc-bfin.h \
10130         config/tc-cr16.h \
10131         config/tc-cris.h \
10132 @@ -785,6 +787,7 @@ distclean-compile:
10133  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arc.Po@am__quote@
10134  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-arm.Po@am__quote@
10135  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-avr.Po@am__quote@
10136 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-avr32.Po@am__quote@
10137  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-bfin.Po@am__quote@
10138  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-cr16.Po@am__quote@
10139  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-cris.Po@am__quote@
10140 @@ -923,6 +926,20 @@ tc-avr.obj: config/tc-avr.c
10141  @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
10142  @am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr.obj `if test -f 'config/tc-avr.c'; then $(CYGPATH_W) 'config/tc-avr.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr.c'; fi`
10143
10144 +tc-avr32.o: config/tc-avr32.c
10145 +@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-avr32.o -MD -MP -MF $(DEPDIR)/tc-avr32.Tpo -c -o tc-avr32.o `test -f 'config/tc-avr32.c' || echo '$(srcdir)/'`config/tc-avr32.c
10146 +@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/tc-avr32.Tpo $(DEPDIR)/tc-avr32.Po
10147 +@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='config/tc-avr32.c' object='tc-avr32.o' libtool=no @AMDEPBACKSLASH@
10148 +@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
10149 +@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr32.o `test -f 'config/tc-avr32.c' || echo '$(srcdir)/'`config/tc-avr32.c
10150 +
10151 +tc-avr32.obj: config/tc-avr32.c
10152 +@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-avr32.obj -MD -MP -MF $(DEPDIR)/tc-avr32.Tpo -c -o tc-avr32.obj `if test -f 'config/tc-avr32.c'; then $(CYGPATH_W) 'config/tc-avr32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr32.c'; fi`
10153 +@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/tc-avr32.Tpo $(DEPDIR)/tc-avr32.Po
10154 +@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='config/tc-avr32.c' object='tc-avr32.obj' libtool=no @AMDEPBACKSLASH@
10155 +@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
10156 +@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-avr32.obj `if test -f 'config/tc-avr32.c'; then $(CYGPATH_W) 'config/tc-avr32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-avr32.c'; fi`
10157 +
10158  tc-bfin.o: config/tc-bfin.c
10159  @am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-bfin.o -MD -MP -MF $(DEPDIR)/tc-bfin.Tpo -c -o tc-bfin.o `test -f 'config/tc-bfin.c' || echo '$(srcdir)/'`config/tc-bfin.c
10160  @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/tc-bfin.Tpo $(DEPDIR)/tc-bfin.Po
10161 --- /dev/null
10162 +++ b/gas/testsuite/gas/avr32/aliases.d
10163 @@ -0,0 +1,19 @@
10164 +#as:
10165 +#objdump: -dr
10166 +#name: aliases
10167 +
10168 +.*: +file format .*
10169 +
10170 +Disassembly of section \.text:
10171 +
10172 +00000000 <ld_nodisp>:
10173 +   0:  19 80      [ \t]+ld\.ub r0,r12\[0x0\]
10174 +   2:  f9 20 00 00[ \t]+ld\.sb r0,r12\[0\]
10175 +   6:  98 80      [ \t]+ld\.uh r0,r12\[0x0\]
10176 +   8:  98 00      [ \t]+ld\.sh r0,r12\[0x0\]
10177 +   a:  78 00      [ \t]+ld\.w r0,r12\[0x0\]
10178 +
10179 +0000000c <st_nodisp>:
10180 +   c:  b8 80      [ \t]+st\.b r12\[0x0\],r0
10181 +   e:  b8 00      [ \t]+st\.h r12\[0x0\],r0
10182 +  10:  99 00      [ \t]+st\.w r12\[0x0\],r0
10183 --- /dev/null
10184 +++ b/gas/testsuite/gas/avr32/aliases.s
10185 @@ -0,0 +1,14 @@
10186 +       .text
10187 +       .global ld_nodisp
10188 +ld_nodisp:
10189 +       ld.ub   r0, r12
10190 +       ld.sb   r0, r12
10191 +       ld.uh   r0, r12
10192 +       ld.sh   r0, r12
10193 +       ld.w    r0, r12
10194 +
10195 +       .global st_nodisp
10196 +st_nodisp:
10197 +       st.b    r12, r0
10198 +       st.h    r12, r0
10199 +       st.w    r12, r0
10200 --- /dev/null
10201 +++ b/gas/testsuite/gas/avr32/allinsn.d
10202 @@ -0,0 +1,2987 @@
10203 +#as:
10204 +#objdump: -dr
10205 +#name: allinsn
10206 +
10207 +.*: +file format .*
10208 +
10209 +Disassembly of section \.text:
10210 +
10211 +[0-9a-f]* <ld_d5>:
10212 + *[0-9a-f]*:   fe 0f 02 3e     ld\.d lr,pc\[pc<<0x3\]
10213 + *[0-9a-f]*:   e0 00 02 00     ld\.d r0,r0\[r0\]
10214 + *[0-9a-f]*:   ea 05 02 26     ld\.d r6,r5\[r5<<0x2\]
10215 + *[0-9a-f]*:   e8 04 02 14     ld\.d r4,r4\[r4<<0x1\]
10216 + *[0-9a-f]*:   fc 0e 02 1e     ld\.d lr,lr\[lr<<0x1\]
10217 + *[0-9a-f]*:   e6 0d 02 2a     ld\.d r10,r3\[sp<<0x2\]
10218 + *[0-9a-f]*:   f4 06 02 28     ld\.d r8,r10\[r6<<0x2\]
10219 + *[0-9a-f]*:   ee 09 02 02     ld\.d r2,r7\[r9\]
10220 +
10221 +[0-9a-f]* <ld_w5>:
10222 + *[0-9a-f]*:   fe 0f 03 0f     ld\.w pc,pc\[pc\]
10223 + *[0-9a-f]*:   f8 0c 03 3c     ld\.w r12,r12\[r12<<0x3\]
10224 + *[0-9a-f]*:   ea 05 03 25     ld\.w r5,r5\[r5<<0x2\]
10225 + *[0-9a-f]*:   e8 04 03 14     ld\.w r4,r4\[r4<<0x1\]
10226 + *[0-9a-f]*:   fc 0e 03 1e     ld\.w lr,lr\[lr<<0x1\]
10227 + *[0-9a-f]*:   f2 09 03 02     ld\.w r2,r9\[r9\]
10228 + *[0-9a-f]*:   e4 06 03 0b     ld\.w r11,r2\[r6\]
10229 + *[0-9a-f]*:   e4 0d 03 30     ld\.w r0,r2\[sp<<0x3\]
10230 +
10231 +[0-9a-f]* <ld_sh5>:
10232 + *[0-9a-f]*:   fe 0f 04 0f     ld\.sh pc,pc\[pc\]
10233 + *[0-9a-f]*:   f8 0c 04 3c     ld\.sh r12,r12\[r12<<0x3\]
10234 + *[0-9a-f]*:   ea 05 04 25     ld\.sh r5,r5\[r5<<0x2\]
10235 + *[0-9a-f]*:   e8 04 04 14     ld\.sh r4,r4\[r4<<0x1\]
10236 + *[0-9a-f]*:   fc 0e 04 1e     ld\.sh lr,lr\[lr<<0x1\]
10237 + *[0-9a-f]*:   e0 0f 04 2b     ld\.sh r11,r0\[pc<<0x2\]
10238 + *[0-9a-f]*:   fa 06 04 2a     ld\.sh r10,sp\[r6<<0x2\]
10239 + *[0-9a-f]*:   e4 02 04 0c     ld\.sh r12,r2\[r2\]
10240 +
10241 +[0-9a-f]* <ld_uh5>:
10242 + *[0-9a-f]*:   fe 0f 05 0f     ld\.uh pc,pc\[pc\]
10243 + *[0-9a-f]*:   f8 0c 05 3c     ld\.uh r12,r12\[r12<<0x3\]
10244 + *[0-9a-f]*:   ea 05 05 25     ld\.uh r5,r5\[r5<<0x2\]
10245 + *[0-9a-f]*:   e8 04 05 14     ld\.uh r4,r4\[r4<<0x1\]
10246 + *[0-9a-f]*:   fc 0e 05 1e     ld\.uh lr,lr\[lr<<0x1\]
10247 + *[0-9a-f]*:   fe 0e 05 38     ld\.uh r8,pc\[lr<<0x3\]
10248 + *[0-9a-f]*:   e2 0f 05 16     ld\.uh r6,r1\[pc<<0x1\]
10249 + *[0-9a-f]*:   fc 0d 05 16     ld\.uh r6,lr\[sp<<0x1\]
10250 +
10251 +[0-9a-f]* <ld_sb2>:
10252 + *[0-9a-f]*:   fe 0f 06 0f     ld\.sb pc,pc\[pc\]
10253 + *[0-9a-f]*:   f8 0c 06 3c     ld\.sb r12,r12\[r12<<0x3\]
10254 + *[0-9a-f]*:   ea 05 06 25     ld\.sb r5,r5\[r5<<0x2\]
10255 + *[0-9a-f]*:   e8 04 06 14     ld\.sb r4,r4\[r4<<0x1\]
10256 + *[0-9a-f]*:   fc 0e 06 1e     ld\.sb lr,lr\[lr<<0x1\]
10257 + *[0-9a-f]*:   e2 0f 06 39     ld\.sb r9,r1\[pc<<0x3\]
10258 + *[0-9a-f]*:   e6 0b 06 10     ld\.sb r0,r3\[r11<<0x1\]
10259 + *[0-9a-f]*:   ea 05 06 1a     ld\.sb r10,r5\[r5<<0x1\]
10260 +
10261 +[0-9a-f]* <ld_ub5>:
10262 + *[0-9a-f]*:   fe 0f 07 0f     ld\.ub pc,pc\[pc\]
10263 + *[0-9a-f]*:   f8 0c 07 3c     ld\.ub r12,r12\[r12<<0x3\]
10264 + *[0-9a-f]*:   ea 05 07 25     ld\.ub r5,r5\[r5<<0x2\]
10265 + *[0-9a-f]*:   e8 04 07 14     ld\.ub r4,r4\[r4<<0x1\]
10266 + *[0-9a-f]*:   fc 0e 07 1e     ld\.ub lr,lr\[lr<<0x1\]
10267 + *[0-9a-f]*:   f8 07 07 36     ld\.ub r6,r12\[r7<<0x3\]
10268 + *[0-9a-f]*:   ec 0c 07 02     ld\.ub r2,r6\[r12\]
10269 + *[0-9a-f]*:   ee 0b 07 10     ld\.ub r0,r7\[r11<<0x1\]
10270 +
10271 +[0-9a-f]* <st_d5>:
10272 + *[0-9a-f]*:   fe 0f 08 0e     st\.d pc\[pc\],lr
10273 + *[0-9a-f]*:   f8 0c 08 3c     st\.d r12\[r12<<0x3\],r12
10274 + *[0-9a-f]*:   ea 05 08 26     st\.d r5\[r5<<0x2\],r6
10275 + *[0-9a-f]*:   e8 04 08 14     st\.d r4\[r4<<0x1\],r4
10276 + *[0-9a-f]*:   fc 0e 08 1e     st\.d lr\[lr<<0x1\],lr
10277 + *[0-9a-f]*:   e2 09 08 14     st\.d r1\[r9<<0x1\],r4
10278 + *[0-9a-f]*:   f4 02 08 14     st\.d r10\[r2<<0x1\],r4
10279 + *[0-9a-f]*:   f8 06 08 0e     st\.d r12\[r6\],lr
10280 +
10281 +[0-9a-f]* <st_w5>:
10282 + *[0-9a-f]*:   fe 0f 09 0f     st\.w pc\[pc\],pc
10283 + *[0-9a-f]*:   f8 0c 09 3c     st\.w r12\[r12<<0x3\],r12
10284 + *[0-9a-f]*:   ea 05 09 25     st\.w r5\[r5<<0x2\],r5
10285 + *[0-9a-f]*:   e8 04 09 14     st\.w r4\[r4<<0x1\],r4
10286 + *[0-9a-f]*:   fc 0e 09 1e     st\.w lr\[lr<<0x1\],lr
10287 + *[0-9a-f]*:   e2 0a 09 03     st\.w r1\[r10\],r3
10288 + *[0-9a-f]*:   e0 0a 09 19     st\.w r0\[r10<<0x1\],r9
10289 + *[0-9a-f]*:   e8 05 09 3f     st\.w r4\[r5<<0x3\],pc
10290 +
10291 +[0-9a-f]* <st_h5>:
10292 + *[0-9a-f]*:   fe 0f 0a 0f     st\.h pc\[pc\],pc
10293 + *[0-9a-f]*:   f8 0c 0a 3c     st\.h r12\[r12<<0x3\],r12
10294 + *[0-9a-f]*:   ea 05 0a 25     st\.h r5\[r5<<0x2\],r5
10295 + *[0-9a-f]*:   e8 04 0a 14     st\.h r4\[r4<<0x1\],r4
10296 + *[0-9a-f]*:   fc 0e 0a 1e     st\.h lr\[lr<<0x1\],lr
10297 + *[0-9a-f]*:   e4 09 0a 0b     st\.h r2\[r9\],r11
10298 + *[0-9a-f]*:   ea 01 0a 2c     st\.h r5\[r1<<0x2\],r12
10299 + *[0-9a-f]*:   fe 08 0a 23     st\.h pc\[r8<<0x2\],r3
10300 +
10301 +[0-9a-f]* <st_b5>:
10302 + *[0-9a-f]*:   fe 0f 0b 0f     st\.b pc\[pc\],pc
10303 + *[0-9a-f]*:   f8 0c 0b 3c     st\.b r12\[r12<<0x3\],r12
10304 + *[0-9a-f]*:   ea 05 0b 25     st\.b r5\[r5<<0x2\],r5
10305 + *[0-9a-f]*:   e8 04 0b 14     st\.b r4\[r4<<0x1\],r4
10306 + *[0-9a-f]*:   fc 0e 0b 1e     st\.b lr\[lr<<0x1\],lr
10307 + *[0-9a-f]*:   e2 08 0b 16     st\.b r1\[r8<<0x1\],r6
10308 + *[0-9a-f]*:   fc 0e 0b 31     st\.b lr\[lr<<0x3\],r1
10309 + *[0-9a-f]*:   ea 00 0b 2f     st\.b r5\[r0<<0x2\],pc
10310 +
10311 +[0-9a-f]* <divs>:
10312 + *[0-9a-f]*:   fe 0f 0c 0f     divs pc,pc,pc
10313 + *[0-9a-f]*:   f8 0c 0c 0c     divs r12,r12,r12
10314 + *[0-9a-f]*:   ea 05 0c 05     divs r5,r5,r5
10315 + *[0-9a-f]*:   e8 04 0c 04     divs r4,r4,r4
10316 + *[0-9a-f]*:   fc 0e 0c 0e     divs lr,lr,lr
10317 + *[0-9a-f]*:   fe 0f 0c 03     divs r3,pc,pc
10318 + *[0-9a-f]*:   f8 02 0c 09     divs r9,r12,r2
10319 + *[0-9a-f]*:   e8 01 0c 07     divs r7,r4,r1
10320 +
10321 +[0-9a-f]* <add1>:
10322 + *[0-9a-f]*:   1e 0f           add pc,pc
10323 + *[0-9a-f]*:   18 0c           add r12,r12
10324 + *[0-9a-f]*:   0a 05           add r5,r5
10325 + *[0-9a-f]*:   08 04           add r4,r4
10326 + *[0-9a-f]*:   1c 0e           add lr,lr
10327 + *[0-9a-f]*:   12 0c           add r12,r9
10328 + *[0-9a-f]*:   06 06           add r6,r3
10329 + *[0-9a-f]*:   18 0a           add r10,r12
10330 +
10331 +[0-9a-f]* <sub1>:
10332 + *[0-9a-f]*:   1e 1f           sub pc,pc
10333 + *[0-9a-f]*:   18 1c           sub r12,r12
10334 + *[0-9a-f]*:   0a 15           sub r5,r5
10335 + *[0-9a-f]*:   08 14           sub r4,r4
10336 + *[0-9a-f]*:   1c 1e           sub lr,lr
10337 + *[0-9a-f]*:   0c 1e           sub lr,r6
10338 + *[0-9a-f]*:   1a 10           sub r0,sp
10339 + *[0-9a-f]*:   18 16           sub r6,r12
10340 +
10341 +[0-9a-f]* <rsub1>:
10342 + *[0-9a-f]*:   1e 2f           rsub pc,pc
10343 + *[0-9a-f]*:   18 2c           rsub r12,r12
10344 + *[0-9a-f]*:   0a 25           rsub r5,r5
10345 + *[0-9a-f]*:   08 24           rsub r4,r4
10346 + *[0-9a-f]*:   1c 2e           rsub lr,lr
10347 + *[0-9a-f]*:   1a 2b           rsub r11,sp
10348 + *[0-9a-f]*:   08 27           rsub r7,r4
10349 + *[0-9a-f]*:   02 29           rsub r9,r1
10350 +
10351 +[0-9a-f]* <cp1>:
10352 + *[0-9a-f]*:   1e 3f           cp\.w pc,pc
10353 + *[0-9a-f]*:   18 3c           cp\.w r12,r12
10354 + *[0-9a-f]*:   0a 35           cp\.w r5,r5
10355 + *[0-9a-f]*:   08 34           cp\.w r4,r4
10356 + *[0-9a-f]*:   1c 3e           cp\.w lr,lr
10357 + *[0-9a-f]*:   04 36           cp\.w r6,r2
10358 + *[0-9a-f]*:   12 30           cp\.w r0,r9
10359 + *[0-9a-f]*:   1a 33           cp\.w r3,sp
10360 +
10361 +[0-9a-f]* <or1>:
10362 + *[0-9a-f]*:   1e 4f           or pc,pc
10363 + *[0-9a-f]*:   18 4c           or r12,r12
10364 + *[0-9a-f]*:   0a 45           or r5,r5
10365 + *[0-9a-f]*:   08 44           or r4,r4
10366 + *[0-9a-f]*:   1c 4e           or lr,lr
10367 + *[0-9a-f]*:   12 44           or r4,r9
10368 + *[0-9a-f]*:   08 4b           or r11,r4
10369 + *[0-9a-f]*:   00 44           or r4,r0
10370 +
10371 +[0-9a-f]* <eor1>:
10372 + *[0-9a-f]*:   1e 5f           eor pc,pc
10373 + *[0-9a-f]*:   18 5c           eor r12,r12
10374 + *[0-9a-f]*:   0a 55           eor r5,r5
10375 + *[0-9a-f]*:   08 54           eor r4,r4
10376 + *[0-9a-f]*:   1c 5e           eor lr,lr
10377 + *[0-9a-f]*:   16 5c           eor r12,r11
10378 + *[0-9a-f]*:   02 50           eor r0,r1
10379 + *[0-9a-f]*:   1e 55           eor r5,pc
10380 +
10381 +[0-9a-f]* <and1>:
10382 + *[0-9a-f]*:   1e 6f           and pc,pc
10383 + *[0-9a-f]*:   18 6c           and r12,r12
10384 + *[0-9a-f]*:   0a 65           and r5,r5
10385 + *[0-9a-f]*:   08 64           and r4,r4
10386 + *[0-9a-f]*:   1c 6e           and lr,lr
10387 + *[0-9a-f]*:   02 68           and r8,r1
10388 + *[0-9a-f]*:   1a 60           and r0,sp
10389 + *[0-9a-f]*:   0a 6a           and r10,r5
10390 +
10391 +[0-9a-f]* <tst>:
10392 + *[0-9a-f]*:   1e 7f           tst pc,pc
10393 + *[0-9a-f]*:   18 7c           tst r12,r12
10394 + *[0-9a-f]*:   0a 75           tst r5,r5
10395 + *[0-9a-f]*:   08 74           tst r4,r4
10396 + *[0-9a-f]*:   1c 7e           tst lr,lr
10397 + *[0-9a-f]*:   18 70           tst r0,r12
10398 + *[0-9a-f]*:   0c 7a           tst r10,r6
10399 + *[0-9a-f]*:   08 7d           tst sp,r4
10400 +
10401 +[0-9a-f]* <andn>:
10402 + *[0-9a-f]*:   1e 8f           andn pc,pc
10403 + *[0-9a-f]*:   18 8c           andn r12,r12
10404 + *[0-9a-f]*:   0a 85           andn r5,r5
10405 + *[0-9a-f]*:   08 84           andn r4,r4
10406 + *[0-9a-f]*:   1c 8e           andn lr,lr
10407 + *[0-9a-f]*:   18 89           andn r9,r12
10408 + *[0-9a-f]*:   1a 8b           andn r11,sp
10409 + *[0-9a-f]*:   0a 8c           andn r12,r5
10410 +
10411 +[0-9a-f]* <mov3>:
10412 + *[0-9a-f]*:   1e 9f           mov pc,pc
10413 + *[0-9a-f]*:   18 9c           mov r12,r12
10414 + *[0-9a-f]*:   0a 95           mov r5,r5
10415 + *[0-9a-f]*:   08 94           mov r4,r4
10416 + *[0-9a-f]*:   1c 9e           mov lr,lr
10417 + *[0-9a-f]*:   12 95           mov r5,r9
10418 + *[0-9a-f]*:   16 9b           mov r11,r11
10419 + *[0-9a-f]*:   1c 92           mov r2,lr
10420 +
10421 +[0-9a-f]* <st_w1>:
10422 + *[0-9a-f]*:   1e af           st\.w pc\+\+,pc
10423 + *[0-9a-f]*:   18 ac           st\.w r12\+\+,r12
10424 + *[0-9a-f]*:   0a a5           st\.w r5\+\+,r5
10425 + *[0-9a-f]*:   08 a4           st\.w r4\+\+,r4
10426 + *[0-9a-f]*:   1c ae           st\.w lr\+\+,lr
10427 + *[0-9a-f]*:   02 ab           st\.w r1\+\+,r11
10428 + *[0-9a-f]*:   1a a0           st\.w sp\+\+,r0
10429 + *[0-9a-f]*:   1a a1           st\.w sp\+\+,r1
10430 +
10431 +[0-9a-f]* <st_h1>:
10432 + *[0-9a-f]*:   1e bf           st\.h pc\+\+,pc
10433 + *[0-9a-f]*:   18 bc           st\.h r12\+\+,r12
10434 + *[0-9a-f]*:   0a b5           st\.h r5\+\+,r5
10435 + *[0-9a-f]*:   08 b4           st\.h r4\+\+,r4
10436 + *[0-9a-f]*:   1c be           st\.h lr\+\+,lr
10437 + *[0-9a-f]*:   18 bd           st\.h r12\+\+,sp
10438 + *[0-9a-f]*:   0e be           st\.h r7\+\+,lr
10439 + *[0-9a-f]*:   0e b4           st\.h r7\+\+,r4
10440 +
10441 +[0-9a-f]* <st_b1>:
10442 + *[0-9a-f]*:   1e cf           st\.b pc\+\+,pc
10443 + *[0-9a-f]*:   18 cc           st\.b r12\+\+,r12
10444 + *[0-9a-f]*:   0a c5           st\.b r5\+\+,r5
10445 + *[0-9a-f]*:   08 c4           st\.b r4\+\+,r4
10446 + *[0-9a-f]*:   1c ce           st\.b lr\+\+,lr
10447 + *[0-9a-f]*:   12 cd           st\.b r9\+\+,sp
10448 + *[0-9a-f]*:   02 cd           st\.b r1\+\+,sp
10449 + *[0-9a-f]*:   00 c4           st\.b r0\+\+,r4
10450 +
10451 +[0-9a-f]* <st_w2>:
10452 + *[0-9a-f]*:   1e df           st\.w --pc,pc
10453 + *[0-9a-f]*:   18 dc           st\.w --r12,r12
10454 + *[0-9a-f]*:   0a d5           st\.w --r5,r5
10455 + *[0-9a-f]*:   08 d4           st\.w --r4,r4
10456 + *[0-9a-f]*:   1c de           st\.w --lr,lr
10457 + *[0-9a-f]*:   02 d7           st\.w --r1,r7
10458 + *[0-9a-f]*:   06 d9           st\.w --r3,r9
10459 + *[0-9a-f]*:   0a d5           st\.w --r5,r5
10460 +
10461 +[0-9a-f]* <st_h2>:
10462 + *[0-9a-f]*:   1e ef           st\.h --pc,pc
10463 + *[0-9a-f]*:   18 ec           st\.h --r12,r12
10464 + *[0-9a-f]*:   0a e5           st\.h --r5,r5
10465 + *[0-9a-f]*:   08 e4           st\.h --r4,r4
10466 + *[0-9a-f]*:   1c ee           st\.h --lr,lr
10467 + *[0-9a-f]*:   0a e7           st\.h --r5,r7
10468 + *[0-9a-f]*:   10 e8           st\.h --r8,r8
10469 + *[0-9a-f]*:   0e e2           st\.h --r7,r2
10470 +
10471 +[0-9a-f]* <st_b2>:
10472 + *[0-9a-f]*:   1e ff           st\.b --pc,pc
10473 + *[0-9a-f]*:   18 fc           st\.b --r12,r12
10474 + *[0-9a-f]*:   0a f5           st\.b --r5,r5
10475 + *[0-9a-f]*:   08 f4           st\.b --r4,r4
10476 + *[0-9a-f]*:   1c fe           st\.b --lr,lr
10477 + *[0-9a-f]*:   1a fd           st\.b --sp,sp
10478 + *[0-9a-f]*:   1a fb           st\.b --sp,r11
10479 + *[0-9a-f]*:   08 f5           st\.b --r4,r5
10480 +
10481 +[0-9a-f]* <ld_w1>:
10482 + *[0-9a-f]*:   1f 0f           ld\.w pc,pc\+\+
10483 + *[0-9a-f]*:   19 0c           ld\.w r12,r12\+\+
10484 + *[0-9a-f]*:   0b 05           ld\.w r5,r5\+\+
10485 + *[0-9a-f]*:   09 04           ld\.w r4,r4\+\+
10486 + *[0-9a-f]*:   1d 0e           ld\.w lr,lr\+\+
10487 + *[0-9a-f]*:   0f 03           ld\.w r3,r7\+\+
10488 + *[0-9a-f]*:   1d 03           ld\.w r3,lr\+\+
10489 + *[0-9a-f]*:   0b 0c           ld\.w r12,r5\+\+
10490 +
10491 +[0-9a-f]* <ld_sh1>:
10492 + *[0-9a-f]*:   1f 1f           ld\.sh pc,pc\+\+
10493 + *[0-9a-f]*:   19 1c           ld\.sh r12,r12\+\+
10494 + *[0-9a-f]*:   0b 15           ld\.sh r5,r5\+\+
10495 + *[0-9a-f]*:   09 14           ld\.sh r4,r4\+\+
10496 + *[0-9a-f]*:   1d 1e           ld\.sh lr,lr\+\+
10497 + *[0-9a-f]*:   05 1b           ld\.sh r11,r2\+\+
10498 + *[0-9a-f]*:   11 12           ld\.sh r2,r8\+\+
10499 + *[0-9a-f]*:   0d 17           ld\.sh r7,r6\+\+
10500 +
10501 +[0-9a-f]* <ld_uh1>:
10502 + *[0-9a-f]*:   1f 2f           ld\.uh pc,pc\+\+
10503 + *[0-9a-f]*:   19 2c           ld\.uh r12,r12\+\+
10504 + *[0-9a-f]*:   0b 25           ld\.uh r5,r5\+\+
10505 + *[0-9a-f]*:   09 24           ld\.uh r4,r4\+\+
10506 + *[0-9a-f]*:   1d 2e           ld\.uh lr,lr\+\+
10507 + *[0-9a-f]*:   0f 26           ld\.uh r6,r7\+\+
10508 + *[0-9a-f]*:   17 2a           ld\.uh r10,r11\+\+
10509 + *[0-9a-f]*:   09 2e           ld\.uh lr,r4\+\+
10510 +
10511 +[0-9a-f]* <ld_ub1>:
10512 + *[0-9a-f]*:   1f 3f           ld\.ub pc,pc\+\+
10513 + *[0-9a-f]*:   19 3c           ld\.ub r12,r12\+\+
10514 + *[0-9a-f]*:   0b 35           ld\.ub r5,r5\+\+
10515 + *[0-9a-f]*:   09 34           ld\.ub r4,r4\+\+
10516 + *[0-9a-f]*:   1d 3e           ld\.ub lr,lr\+\+
10517 + *[0-9a-f]*:   1d 38           ld\.ub r8,lr\+\+
10518 + *[0-9a-f]*:   19 3c           ld\.ub r12,r12\+\+
10519 + *[0-9a-f]*:   15 3b           ld\.ub r11,r10\+\+
10520 +
10521 +[0-9a-f]* <ld_w2>:
10522 + *[0-9a-f]*:   1f 4f           ld\.w pc,--pc
10523 + *[0-9a-f]*:   19 4c           ld\.w r12,--r12
10524 + *[0-9a-f]*:   0b 45           ld\.w r5,--r5
10525 + *[0-9a-f]*:   09 44           ld\.w r4,--r4
10526 + *[0-9a-f]*:   1d 4e           ld\.w lr,--lr
10527 + *[0-9a-f]*:   1d 4a           ld\.w r10,--lr
10528 + *[0-9a-f]*:   13 4c           ld\.w r12,--r9
10529 + *[0-9a-f]*:   0b 46           ld\.w r6,--r5
10530 +
10531 +[0-9a-f]* <ld_sh2>:
10532 + *[0-9a-f]*:   1f 5f           ld\.sh pc,--pc
10533 + *[0-9a-f]*:   19 5c           ld\.sh r12,--r12
10534 + *[0-9a-f]*:   0b 55           ld\.sh r5,--r5
10535 + *[0-9a-f]*:   09 54           ld\.sh r4,--r4
10536 + *[0-9a-f]*:   1d 5e           ld\.sh lr,--lr
10537 + *[0-9a-f]*:   15 5f           ld\.sh pc,--r10
10538 + *[0-9a-f]*:   07 56           ld\.sh r6,--r3
10539 + *[0-9a-f]*:   0d 54           ld\.sh r4,--r6
10540 +
10541 +[0-9a-f]* <ld_uh2>:
10542 + *[0-9a-f]*:   1f 6f           ld\.uh pc,--pc
10543 + *[0-9a-f]*:   19 6c           ld\.uh r12,--r12
10544 + *[0-9a-f]*:   0b 65           ld\.uh r5,--r5
10545 + *[0-9a-f]*:   09 64           ld\.uh r4,--r4
10546 + *[0-9a-f]*:   1d 6e           ld\.uh lr,--lr
10547 + *[0-9a-f]*:   05 63           ld\.uh r3,--r2
10548 + *[0-9a-f]*:   01 61           ld\.uh r1,--r0
10549 + *[0-9a-f]*:   13 62           ld\.uh r2,--r9
10550 +
10551 +[0-9a-f]* <ld_ub2>:
10552 + *[0-9a-f]*:   1f 7f           ld\.ub pc,--pc
10553 + *[0-9a-f]*:   19 7c           ld\.ub r12,--r12
10554 + *[0-9a-f]*:   0b 75           ld\.ub r5,--r5
10555 + *[0-9a-f]*:   09 74           ld\.ub r4,--r4
10556 + *[0-9a-f]*:   1d 7e           ld\.ub lr,--lr
10557 + *[0-9a-f]*:   03 71           ld\.ub r1,--r1
10558 + *[0-9a-f]*:   0d 70           ld\.ub r0,--r6
10559 + *[0-9a-f]*:   0f 72           ld\.ub r2,--r7
10560 +
10561 +[0-9a-f]* <ld_ub3>:
10562 + *[0-9a-f]*:   1f 8f           ld\.ub pc,pc\[0x0\]
10563 + *[0-9a-f]*:   19 fc           ld\.ub r12,r12\[0x7\]
10564 + *[0-9a-f]*:   0b c5           ld\.ub r5,r5\[0x4\]
10565 + *[0-9a-f]*:   09 b4           ld\.ub r4,r4\[0x3\]
10566 + *[0-9a-f]*:   1d 9e           ld\.ub lr,lr\[0x1\]
10567 + *[0-9a-f]*:   13 e6           ld\.ub r6,r9\[0x6\]
10568 + *[0-9a-f]*:   1d c2           ld\.ub r2,lr\[0x4\]
10569 + *[0-9a-f]*:   11 81           ld\.ub r1,r8\[0x0\]
10570 +
10571 +[0-9a-f]* <sub3_sp>:
10572 + *[0-9a-f]*:   20 0d           sub sp,0
10573 + *[0-9a-f]*:   2f fd           sub sp,-4
10574 + *[0-9a-f]*:   28 0d           sub sp,-512
10575 + *[0-9a-f]*:   27 fd           sub sp,508
10576 + *[0-9a-f]*:   20 1d           sub sp,4
10577 + *[0-9a-f]*:   20 bd           sub sp,44
10578 + *[0-9a-f]*:   20 2d           sub sp,8
10579 + *[0-9a-f]*:   25 7d           sub sp,348
10580 +
10581 +[0-9a-f]* <sub3>:
10582 + *[0-9a-f]*:   20 0f           sub pc,0
10583 + *[0-9a-f]*:   2f fc           sub r12,-1
10584 + *[0-9a-f]*:   28 05           sub r5,-128
10585 + *[0-9a-f]*:   27 f4           sub r4,127
10586 + *[0-9a-f]*:   20 1e           sub lr,1
10587 + *[0-9a-f]*:   2d 76           sub r6,-41
10588 + *[0-9a-f]*:   22 54           sub r4,37
10589 + *[0-9a-f]*:   23 8c           sub r12,56
10590 +
10591 +[0-9a-f]* <mov1>:
10592 + *[0-9a-f]*:   30 0f           mov pc,0
10593 + *[0-9a-f]*:   3f fc           mov r12,-1
10594 + *[0-9a-f]*:   38 05           mov r5,-128
10595 + *[0-9a-f]*:   37 f4           mov r4,127
10596 + *[0-9a-f]*:   30 1e           mov lr,1
10597 + *[0-9a-f]*:   30 ef           mov pc,14
10598 + *[0-9a-f]*:   39 c6           mov r6,-100
10599 + *[0-9a-f]*:   38 6e           mov lr,-122
10600 +
10601 +[0-9a-f]* <lddsp>:
10602 + *[0-9a-f]*:   40 0f           lddsp pc,sp\[0x0\]
10603 + *[0-9a-f]*:   47 fc           lddsp r12,sp\[0x1fc\]
10604 + *[0-9a-f]*:   44 05           lddsp r5,sp\[0x100\]
10605 + *[0-9a-f]*:   43 f4           lddsp r4,sp\[0xfc\]
10606 + *[0-9a-f]*:   40 1e           lddsp lr,sp\[0x4\]
10607 + *[0-9a-f]*:   44 0e           lddsp lr,sp\[0x100\]
10608 + *[0-9a-f]*:   40 5c           lddsp r12,sp\[0x14\]
10609 + *[0-9a-f]*:   47 69           lddsp r9,sp\[0x1d8\]
10610 +
10611 +[0-9a-f]* <lddpc>:
10612 + *[0-9a-f]*:   48 0f           lddpc pc,[0-9a-f]* <.*>
10613 + *[0-9a-f]*:   4f f0           lddpc r0,[0-9a-f]* <.*>
10614 + *[0-9a-f]*:   4c 08           lddpc r8,[0-9a-f]* <.*>
10615 + *[0-9a-f]*:   4b f7           lddpc r7,[0-9a-f]* <.*>
10616 + *[0-9a-f]*:   48 1e           lddpc lr,[0-9a-f]* <.*>
10617 + *[0-9a-f]*:   4f 6d           lddpc sp,[0-9a-f]* <.*>
10618 + *[0-9a-f]*:   49 e6           lddpc r6,[0-9a-f]* <.*>
10619 + *[0-9a-f]*:   48 7b           lddpc r11,[0-9a-f]* <.*>
10620 +
10621 +[0-9a-f]* <stdsp>:
10622 + *[0-9a-f]*:   50 0f           stdsp sp\[0x0\],pc
10623 + *[0-9a-f]*:   57 fc           stdsp sp\[0x1fc\],r12
10624 + *[0-9a-f]*:   54 05           stdsp sp\[0x100\],r5
10625 + *[0-9a-f]*:   53 f4           stdsp sp\[0xfc\],r4
10626 + *[0-9a-f]*:   50 1e           stdsp sp\[0x4\],lr
10627 + *[0-9a-f]*:   54 cf           stdsp sp\[0x130\],pc
10628 + *[0-9a-f]*:   54 00           stdsp sp\[0x100\],r0
10629 + *[0-9a-f]*:   55 45           stdsp sp\[0x150\],r5
10630 +
10631 +[0-9a-f]* <cp2>:
10632 + *[0-9a-f]*:   58 0f           cp.w pc,0
10633 + *[0-9a-f]*:   5b fc           cp.w r12,-1
10634 + *[0-9a-f]*:   5a 05           cp.w r5,-32
10635 + *[0-9a-f]*:   59 f4           cp.w r4,31
10636 + *[0-9a-f]*:   58 1e           cp.w lr,1
10637 + *[0-9a-f]*:   58 38           cp.w r8,3
10638 + *[0-9a-f]*:   59 0e           cp.w lr,16
10639 + *[0-9a-f]*:   5a 67           cp.w r7,-26
10640 +
10641 +[0-9a-f]* <acr>:
10642 + *[0-9a-f]*:   5c 0f           acr pc
10643 + *[0-9a-f]*:   5c 0c           acr r12
10644 + *[0-9a-f]*:   5c 05           acr r5
10645 + *[0-9a-f]*:   5c 04           acr r4
10646 + *[0-9a-f]*:   5c 0e           acr lr
10647 + *[0-9a-f]*:   5c 02           acr r2
10648 + *[0-9a-f]*:   5c 0c           acr r12
10649 + *[0-9a-f]*:   5c 0f           acr pc
10650 +
10651 +[0-9a-f]* <scr>:
10652 + *[0-9a-f]*:   5c 1f           scr pc
10653 + *[0-9a-f]*:   5c 1c           scr r12
10654 + *[0-9a-f]*:   5c 15           scr r5
10655 + *[0-9a-f]*:   5c 14           scr r4
10656 + *[0-9a-f]*:   5c 1e           scr lr
10657 + *[0-9a-f]*:   5c 1f           scr pc
10658 + *[0-9a-f]*:   5c 16           scr r6
10659 + *[0-9a-f]*:   5c 11           scr r1
10660 +
10661 +[0-9a-f]* <cpc0>:
10662 + *[0-9a-f]*:   5c 2f           cpc pc
10663 + *[0-9a-f]*:   5c 2c           cpc r12
10664 + *[0-9a-f]*:   5c 25           cpc r5
10665 + *[0-9a-f]*:   5c 24           cpc r4
10666 + *[0-9a-f]*:   5c 2e           cpc lr
10667 + *[0-9a-f]*:   5c 2f           cpc pc
10668 + *[0-9a-f]*:   5c 24           cpc r4
10669 + *[0-9a-f]*:   5c 29           cpc r9
10670 +
10671 +[0-9a-f]* <neg>:
10672 + *[0-9a-f]*:   5c 3f           neg pc
10673 + *[0-9a-f]*:   5c 3c           neg r12
10674 + *[0-9a-f]*:   5c 35           neg r5
10675 + *[0-9a-f]*:   5c 34           neg r4
10676 + *[0-9a-f]*:   5c 3e           neg lr
10677 + *[0-9a-f]*:   5c 37           neg r7
10678 + *[0-9a-f]*:   5c 31           neg r1
10679 + *[0-9a-f]*:   5c 39           neg r9
10680 +
10681 +[0-9a-f]* <abs>:
10682 + *[0-9a-f]*:   5c 4f           abs pc
10683 + *[0-9a-f]*:   5c 4c           abs r12
10684 + *[0-9a-f]*:   5c 45           abs r5
10685 + *[0-9a-f]*:   5c 44           abs r4
10686 + *[0-9a-f]*:   5c 4e           abs lr
10687 + *[0-9a-f]*:   5c 46           abs r6
10688 + *[0-9a-f]*:   5c 46           abs r6
10689 + *[0-9a-f]*:   5c 44           abs r4
10690 +
10691 +[0-9a-f]* <castu_b>:
10692 + *[0-9a-f]*:   5c 5f           castu\.b pc
10693 + *[0-9a-f]*:   5c 5c           castu\.b r12
10694 + *[0-9a-f]*:   5c 55           castu\.b r5
10695 + *[0-9a-f]*:   5c 54           castu\.b r4
10696 + *[0-9a-f]*:   5c 5e           castu\.b lr
10697 + *[0-9a-f]*:   5c 57           castu\.b r7
10698 + *[0-9a-f]*:   5c 5d           castu\.b sp
10699 + *[0-9a-f]*:   5c 59           castu\.b r9
10700 +
10701 +[0-9a-f]* <casts_b>:
10702 + *[0-9a-f]*:   5c 6f           casts\.b pc
10703 + *[0-9a-f]*:   5c 6c           casts\.b r12
10704 + *[0-9a-f]*:   5c 65           casts\.b r5
10705 + *[0-9a-f]*:   5c 64           casts\.b r4
10706 + *[0-9a-f]*:   5c 6e           casts\.b lr
10707 + *[0-9a-f]*:   5c 6b           casts\.b r11
10708 + *[0-9a-f]*:   5c 61           casts\.b r1
10709 + *[0-9a-f]*:   5c 6a           casts\.b r10
10710 +
10711 +[0-9a-f]* <castu_h>:
10712 + *[0-9a-f]*:   5c 7f           castu\.h pc
10713 + *[0-9a-f]*:   5c 7c           castu\.h r12
10714 + *[0-9a-f]*:   5c 75           castu\.h r5
10715 + *[0-9a-f]*:   5c 74           castu\.h r4
10716 + *[0-9a-f]*:   5c 7e           castu\.h lr
10717 + *[0-9a-f]*:   5c 7a           castu\.h r10
10718 + *[0-9a-f]*:   5c 7b           castu\.h r11
10719 + *[0-9a-f]*:   5c 71           castu\.h r1
10720 +
10721 +[0-9a-f]* <casts_h>:
10722 + *[0-9a-f]*:   5c 8f           casts\.h pc
10723 + *[0-9a-f]*:   5c 8c           casts\.h r12
10724 + *[0-9a-f]*:   5c 85           casts\.h r5
10725 + *[0-9a-f]*:   5c 84           casts\.h r4
10726 + *[0-9a-f]*:   5c 8e           casts\.h lr
10727 + *[0-9a-f]*:   5c 80           casts\.h r0
10728 + *[0-9a-f]*:   5c 85           casts\.h r5
10729 + *[0-9a-f]*:   5c 89           casts\.h r9
10730 +
10731 +[0-9a-f]* <brev>:
10732 + *[0-9a-f]*:   5c 9f           brev pc
10733 + *[0-9a-f]*:   5c 9c           brev r12
10734 + *[0-9a-f]*:   5c 95           brev r5
10735 + *[0-9a-f]*:   5c 94           brev r4
10736 + *[0-9a-f]*:   5c 9e           brev lr
10737 + *[0-9a-f]*:   5c 95           brev r5
10738 + *[0-9a-f]*:   5c 9a           brev r10
10739 + *[0-9a-f]*:   5c 98           brev r8
10740 +
10741 +[0-9a-f]* <swap_h>:
10742 + *[0-9a-f]*:   5c af           swap\.h pc
10743 + *[0-9a-f]*:   5c ac           swap\.h r12
10744 + *[0-9a-f]*:   5c a5           swap\.h r5
10745 + *[0-9a-f]*:   5c a4           swap\.h r4
10746 + *[0-9a-f]*:   5c ae           swap\.h lr
10747 + *[0-9a-f]*:   5c a7           swap\.h r7
10748 + *[0-9a-f]*:   5c a0           swap\.h r0
10749 + *[0-9a-f]*:   5c a8           swap\.h r8
10750 +
10751 +[0-9a-f]* <swap_b>:
10752 + *[0-9a-f]*:   5c bf           swap\.b pc
10753 + *[0-9a-f]*:   5c bc           swap\.b r12
10754 + *[0-9a-f]*:   5c b5           swap\.b r5
10755 + *[0-9a-f]*:   5c b4           swap\.b r4
10756 + *[0-9a-f]*:   5c be           swap\.b lr
10757 + *[0-9a-f]*:   5c ba           swap\.b r10
10758 + *[0-9a-f]*:   5c bc           swap\.b r12
10759 + *[0-9a-f]*:   5c b1           swap\.b r1
10760 +
10761 +[0-9a-f]* <swap_bh>:
10762 + *[0-9a-f]*:   5c cf           swap\.bh pc
10763 + *[0-9a-f]*:   5c cc           swap\.bh r12
10764 + *[0-9a-f]*:   5c c5           swap\.bh r5
10765 + *[0-9a-f]*:   5c c4           swap\.bh r4
10766 + *[0-9a-f]*:   5c ce           swap\.bh lr
10767 + *[0-9a-f]*:   5c c9           swap\.bh r9
10768 + *[0-9a-f]*:   5c c4           swap\.bh r4
10769 + *[0-9a-f]*:   5c c1           swap\.bh r1
10770 +
10771 +[0-9a-f]* <One_s_compliment>:
10772 + *[0-9a-f]*:   5c df           com pc
10773 + *[0-9a-f]*:   5c dc           com r12
10774 + *[0-9a-f]*:   5c d5           com r5
10775 + *[0-9a-f]*:   5c d4           com r4
10776 + *[0-9a-f]*:   5c de           com lr
10777 + *[0-9a-f]*:   5c d2           com r2
10778 + *[0-9a-f]*:   5c d2           com r2
10779 + *[0-9a-f]*:   5c d7           com r7
10780 +
10781 +[0-9a-f]* <tnbz>:
10782 + *[0-9a-f]*:   5c ef           tnbz pc
10783 + *[0-9a-f]*:   5c ec           tnbz r12
10784 + *[0-9a-f]*:   5c e5           tnbz r5
10785 + *[0-9a-f]*:   5c e4           tnbz r4
10786 + *[0-9a-f]*:   5c ee           tnbz lr
10787 + *[0-9a-f]*:   5c e8           tnbz r8
10788 + *[0-9a-f]*:   5c ec           tnbz r12
10789 + *[0-9a-f]*:   5c ef           tnbz pc
10790 +
10791 +[0-9a-f]* <rol>:
10792 + *[0-9a-f]*:   5c ff           rol pc
10793 + *[0-9a-f]*:   5c fc           rol r12
10794 + *[0-9a-f]*:   5c f5           rol r5
10795 + *[0-9a-f]*:   5c f4           rol r4
10796 + *[0-9a-f]*:   5c fe           rol lr
10797 + *[0-9a-f]*:   5c fa           rol r10
10798 + *[0-9a-f]*:   5c f9           rol r9
10799 + *[0-9a-f]*:   5c f5           rol r5
10800 +
10801 +[0-9a-f]* <ror>:
10802 + *[0-9a-f]*:   5d 0f           ror pc
10803 + *[0-9a-f]*:   5d 0c           ror r12
10804 + *[0-9a-f]*:   5d 05           ror r5
10805 + *[0-9a-f]*:   5d 04           ror r4
10806 + *[0-9a-f]*:   5d 0e           ror lr
10807 + *[0-9a-f]*:   5d 08           ror r8
10808 + *[0-9a-f]*:   5d 04           ror r4
10809 + *[0-9a-f]*:   5d 07           ror r7
10810 +
10811 +[0-9a-f]* <icall>:
10812 + *[0-9a-f]*:   5d 1f           icall pc
10813 + *[0-9a-f]*:   5d 1c           icall r12
10814 + *[0-9a-f]*:   5d 15           icall r5
10815 + *[0-9a-f]*:   5d 14           icall r4
10816 + *[0-9a-f]*:   5d 1e           icall lr
10817 + *[0-9a-f]*:   5d 13           icall r3
10818 + *[0-9a-f]*:   5d 11           icall r1
10819 + *[0-9a-f]*:   5d 13           icall r3
10820 +
10821 +[0-9a-f]* <mustr>:
10822 + *[0-9a-f]*:   5d 2f           mustr pc
10823 + *[0-9a-f]*:   5d 2c           mustr r12
10824 + *[0-9a-f]*:   5d 25           mustr r5
10825 + *[0-9a-f]*:   5d 24           mustr r4
10826 + *[0-9a-f]*:   5d 2e           mustr lr
10827 + *[0-9a-f]*:   5d 21           mustr r1
10828 + *[0-9a-f]*:   5d 24           mustr r4
10829 + *[0-9a-f]*:   5d 2c           mustr r12
10830 +
10831 +[0-9a-f]* <musfr>:
10832 + *[0-9a-f]*:   5d 3f           musfr pc
10833 + *[0-9a-f]*:   5d 3c           musfr r12
10834 + *[0-9a-f]*:   5d 35           musfr r5
10835 + *[0-9a-f]*:   5d 34           musfr r4
10836 + *[0-9a-f]*:   5d 3e           musfr lr
10837 + *[0-9a-f]*:   5d 3b           musfr r11
10838 + *[0-9a-f]*:   5d 3c           musfr r12
10839 + *[0-9a-f]*:   5d 32           musfr r2
10840 +
10841 +[0-9a-f]* <ret_cond>:
10842 + *[0-9a-f]*:   5e 0f           reteq 1
10843 + *[0-9a-f]*:   5e fc           retal r12
10844 + *[0-9a-f]*:   5e 85           retls r5
10845 + *[0-9a-f]*:   5e 74           retpl r4
10846 + *[0-9a-f]*:   5e 1e           retne -1
10847 + *[0-9a-f]*:   5e 90           retgt r0
10848 + *[0-9a-f]*:   5e 9c           retgt r12
10849 + *[0-9a-f]*:   5e 4a           retge r10
10850 +
10851 +[0-9a-f]* <sr_cond>:
10852 + *[0-9a-f]*:   5f 0f           sreq pc
10853 + *[0-9a-f]*:   5f fc           sral r12
10854 + *[0-9a-f]*:   5f 85           srls r5
10855 + *[0-9a-f]*:   5f 74           srpl r4
10856 + *[0-9a-f]*:   5f 1e           srne lr
10857 + *[0-9a-f]*:   5f 50           srlt r0
10858 + *[0-9a-f]*:   5f fd           sral sp
10859 + *[0-9a-f]*:   5f 49           srge r9
10860 +
10861 +[0-9a-f]* <ld_w3>:
10862 + *[0-9a-f]*:   7e 0f           ld\.w pc,pc\[0x0\]
10863 + *[0-9a-f]*:   79 fc           ld\.w r12,r12\[0x7c\]
10864 + *[0-9a-f]*:   6b 05           ld\.w r5,r5\[0x40\]
10865 + *[0-9a-f]*:   68 f4           ld\.w r4,r4\[0x3c\]
10866 + *[0-9a-f]*:   7c 1e           ld\.w lr,lr\[0x4\]
10867 + *[0-9a-f]*:   64 dd           ld\.w sp,r2\[0x34\]
10868 + *[0-9a-f]*:   62 29           ld\.w r9,r1\[0x8\]
10869 + *[0-9a-f]*:   7a f5           ld\.w r5,sp\[0x3c\]
10870 +
10871 +[0-9a-f]* <ld_sh3>:
10872 + *[0-9a-f]*:   9e 0f           ld\.sh pc,pc\[0x0\]
10873 + *[0-9a-f]*:   98 7c           ld\.sh r12,r12\[0xe\]
10874 + *[0-9a-f]*:   8a 45           ld\.sh r5,r5\[0x8\]
10875 + *[0-9a-f]*:   88 34           ld\.sh r4,r4\[0x6\]
10876 + *[0-9a-f]*:   9c 1e           ld\.sh lr,lr\[0x2\]
10877 + *[0-9a-f]*:   84 44           ld\.sh r4,r2\[0x8\]
10878 + *[0-9a-f]*:   9c 5d           ld\.sh sp,lr\[0xa\]
10879 + *[0-9a-f]*:   96 12           ld\.sh r2,r11\[0x2\]
10880 +
10881 +[0-9a-f]* <ld_uh3>:
10882 + *[0-9a-f]*:   9e 8f           ld\.uh pc,pc\[0x0\]
10883 + *[0-9a-f]*:   98 fc           ld\.uh r12,r12\[0xe\]
10884 + *[0-9a-f]*:   8a c5           ld\.uh r5,r5\[0x8\]
10885 + *[0-9a-f]*:   88 b4           ld\.uh r4,r4\[0x6\]
10886 + *[0-9a-f]*:   9c 9e           ld\.uh lr,lr\[0x2\]
10887 + *[0-9a-f]*:   80 da           ld\.uh r10,r0\[0xa\]
10888 + *[0-9a-f]*:   96 c8           ld\.uh r8,r11\[0x8\]
10889 + *[0-9a-f]*:   84 ea           ld\.uh r10,r2\[0xc\]
10890 +
10891 +[0-9a-f]* <st_w3>:
10892 + *[0-9a-f]*:   9f 0f           st\.w pc\[0x0\],pc
10893 + *[0-9a-f]*:   99 fc           st\.w r12\[0x3c\],r12
10894 + *[0-9a-f]*:   8b 85           st\.w r5\[0x20\],r5
10895 + *[0-9a-f]*:   89 74           st\.w r4\[0x1c\],r4
10896 + *[0-9a-f]*:   9d 1e           st\.w lr\[0x4\],lr
10897 + *[0-9a-f]*:   8f bb           st\.w r7\[0x2c\],r11
10898 + *[0-9a-f]*:   85 66           st\.w r2\[0x18\],r6
10899 + *[0-9a-f]*:   89 39           st\.w r4\[0xc\],r9
10900 +
10901 +[0-9a-f]* <st_h3>:
10902 + *[0-9a-f]*:   be 0f           st\.h pc\[0x0\],pc
10903 + *[0-9a-f]*:   b8 7c           st\.h r12\[0xe\],r12
10904 + *[0-9a-f]*:   aa 45           st\.h r5\[0x8\],r5
10905 + *[0-9a-f]*:   a8 34           st\.h r4\[0x6\],r4
10906 + *[0-9a-f]*:   bc 1e           st\.h lr\[0x2\],lr
10907 + *[0-9a-f]*:   bc 5c           st\.h lr\[0xa\],r12
10908 + *[0-9a-f]*:   ac 20           st\.h r6\[0x4\],r0
10909 + *[0-9a-f]*:   aa 6d           st\.h r5\[0xc\],sp
10910 +
10911 +[0-9a-f]* <st_b3>:
10912 + *[0-9a-f]*:   be 8f           st\.b pc\[0x0\],pc
10913 + *[0-9a-f]*:   b8 fc           st\.b r12\[0x7\],r12
10914 + *[0-9a-f]*:   aa c5           st\.b r5\[0x4\],r5
10915 + *[0-9a-f]*:   a8 b4           st\.b r4\[0x3\],r4
10916 + *[0-9a-f]*:   bc 9e           st\.b lr\[0x1\],lr
10917 + *[0-9a-f]*:   b8 e9           st\.b r12\[0x6\],r9
10918 + *[0-9a-f]*:   a4 be           st\.b r2\[0x3\],lr
10919 + *[0-9a-f]*:   a2 bb           st\.b r1\[0x3\],r11
10920 +
10921 +[0-9a-f]* <ldd>:
10922 + *[0-9a-f]*:   bf 00           ld\.d r0,pc
10923 + *[0-9a-f]*:   b9 0e           ld\.d lr,r12
10924 + *[0-9a-f]*:   ab 08           ld\.d r8,r5
10925 + *[0-9a-f]*:   a9 06           ld\.d r6,r4
10926 + *[0-9a-f]*:   bd 02           ld\.d r2,lr
10927 + *[0-9a-f]*:   af 0e           ld\.d lr,r7
10928 + *[0-9a-f]*:   a9 04           ld\.d r4,r4
10929 + *[0-9a-f]*:   bf 0e           ld\.d lr,pc
10930 +
10931 +[0-9a-f]* <ldd_postinc>:
10932 + *[0-9a-f]*:   bf 01           ld\.d r0,pc\+\+
10933 + *[0-9a-f]*:   b9 0f           ld\.d lr,r12\+\+
10934 + *[0-9a-f]*:   ab 09           ld\.d r8,r5\+\+
10935 + *[0-9a-f]*:   a9 07           ld\.d r6,r4\+\+
10936 + *[0-9a-f]*:   bd 03           ld\.d r2,lr\+\+
10937 + *[0-9a-f]*:   ab 0f           ld\.d lr,r5\+\+
10938 + *[0-9a-f]*:   b7 0d           ld\.d r12,r11\+\+
10939 + *[0-9a-f]*:   b9 03           ld\.d r2,r12\+\+
10940 +
10941 +[0-9a-f]* <ldd_predec>:
10942 + *[0-9a-f]*:   bf 10           ld\.d r0,--pc
10943 + *[0-9a-f]*:   b9 1e           ld\.d lr,--r12
10944 + *[0-9a-f]*:   ab 18           ld\.d r8,--r5
10945 + *[0-9a-f]*:   a9 16           ld\.d r6,--r4
10946 + *[0-9a-f]*:   bd 12           ld\.d r2,--lr
10947 + *[0-9a-f]*:   a1 18           ld\.d r8,--r0
10948 + *[0-9a-f]*:   bf 1a           ld\.d r10,--pc
10949 + *[0-9a-f]*:   a9 12           ld\.d r2,--r4
10950 +
10951 +[0-9a-f]* <std>:
10952 + *[0-9a-f]*:   bf 11           st\.d pc,r0
10953 + *[0-9a-f]*:   b9 1f           st\.d r12,lr
10954 + *[0-9a-f]*:   ab 19           st\.d r5,r8
10955 + *[0-9a-f]*:   a9 17           st\.d r4,r6
10956 + *[0-9a-f]*:   bd 13           st\.d lr,r2
10957 + *[0-9a-f]*:   a1 1d           st\.d r0,r12
10958 + *[0-9a-f]*:   bb 15           st\.d sp,r4
10959 + *[0-9a-f]*:   b9 1d           st\.d r12,r12
10960 +
10961 +[0-9a-f]* <std_postinc>:
10962 + *[0-9a-f]*:   bf 20           st\.d pc\+\+,r0
10963 + *[0-9a-f]*:   b9 2e           st\.d r12\+\+,lr
10964 + *[0-9a-f]*:   ab 28           st\.d r5\+\+,r8
10965 + *[0-9a-f]*:   a9 26           st\.d r4\+\+,r6
10966 + *[0-9a-f]*:   bd 22           st\.d lr\+\+,r2
10967 + *[0-9a-f]*:   bb 26           st\.d sp\+\+,r6
10968 + *[0-9a-f]*:   b5 26           st\.d r10\+\+,r6
10969 + *[0-9a-f]*:   af 22           st\.d r7\+\+,r2
10970 +
10971 +[0-9a-f]* <std_predec>:
10972 + *[0-9a-f]*:   bf 21           st\.d --pc,r0
10973 + *[0-9a-f]*:   b9 2f           st\.d --r12,lr
10974 + *[0-9a-f]*:   ab 29           st\.d --r5,r8
10975 + *[0-9a-f]*:   a9 27           st\.d --r4,r6
10976 + *[0-9a-f]*:   bd 23           st\.d --lr,r2
10977 + *[0-9a-f]*:   a7 27           st\.d --r3,r6
10978 + *[0-9a-f]*:   bd 23           st\.d --lr,r2
10979 + *[0-9a-f]*:   a1 25           st\.d --r0,r4
10980 +
10981 +[0-9a-f]* <mul>:
10982 + *[0-9a-f]*:   bf 3f           mul pc,pc
10983 + *[0-9a-f]*:   b9 3c           mul r12,r12
10984 + *[0-9a-f]*:   ab 35           mul r5,r5
10985 + *[0-9a-f]*:   a9 34           mul r4,r4
10986 + *[0-9a-f]*:   bd 3e           mul lr,lr
10987 + *[0-9a-f]*:   bd 3a           mul r10,lr
10988 + *[0-9a-f]*:   b1 30           mul r0,r8
10989 + *[0-9a-f]*:   ab 38           mul r8,r5
10990 +
10991 +[0-9a-f]* <asr_imm5>:
10992 + *[0-9a-f]*:   a1 4f           asr pc,0x0
10993 + *[0-9a-f]*:   bf 5c           asr r12,0x1f
10994 + *[0-9a-f]*:   b1 45           asr r5,0x10
10995 + *[0-9a-f]*:   af 54           asr r4,0xf
10996 + *[0-9a-f]*:   a1 5e           asr lr,0x1
10997 + *[0-9a-f]*:   b7 56           asr r6,0x17
10998 + *[0-9a-f]*:   b3 46           asr r6,0x12
10999 + *[0-9a-f]*:   a9 45           asr r5,0x8
11000 +
11001 +[0-9a-f]* <lsl_imm5>:
11002 + *[0-9a-f]*:   a1 6f           lsl pc,0x0
11003 + *[0-9a-f]*:   bf 7c           lsl r12,0x1f
11004 + *[0-9a-f]*:   b1 65           lsl r5,0x10
11005 + *[0-9a-f]*:   af 74           lsl r4,0xf
11006 + *[0-9a-f]*:   a1 7e           lsl lr,0x1
11007 + *[0-9a-f]*:   ad 7c           lsl r12,0xd
11008 + *[0-9a-f]*:   b1 66           lsl r6,0x10
11009 + *[0-9a-f]*:   b9 71           lsl r1,0x19
11010 +
11011 +[0-9a-f]* <lsr_imm5>:
11012 + *[0-9a-f]*:   a1 8f           lsr pc,0x0
11013 + *[0-9a-f]*:   bf 9c           lsr r12,0x1f
11014 + *[0-9a-f]*:   b1 85           lsr r5,0x10
11015 + *[0-9a-f]*:   af 94           lsr r4,0xf
11016 + *[0-9a-f]*:   a1 9e           lsr lr,0x1
11017 + *[0-9a-f]*:   a1 90           lsr r0,0x1
11018 + *[0-9a-f]*:   ab 88           lsr r8,0xa
11019 + *[0-9a-f]*:   bb 87           lsr r7,0x1a
11020 +
11021 +[0-9a-f]* <sbr>:
11022 + *[0-9a-f]*:   a1 af           sbr pc,0x0
11023 + *[0-9a-f]*:   bf bc           sbr r12,0x1f
11024 + *[0-9a-f]*:   b1 a5           sbr r5,0x10
11025 + *[0-9a-f]*:   af b4           sbr r4,0xf
11026 + *[0-9a-f]*:   a1 be           sbr lr,0x1
11027 + *[0-9a-f]*:   bf b8           sbr r8,0x1f
11028 + *[0-9a-f]*:   b7 a6           sbr r6,0x16
11029 + *[0-9a-f]*:   b7 b1           sbr r1,0x17
11030 +
11031 +[0-9a-f]* <cbr>:
11032 + *[0-9a-f]*:   a1 cf           cbr pc,0x0
11033 + *[0-9a-f]*:   bf dc           cbr r12,0x1f
11034 + *[0-9a-f]*:   b1 c5           cbr r5,0x10
11035 + *[0-9a-f]*:   af d4           cbr r4,0xf
11036 + *[0-9a-f]*:   a1 de           cbr lr,0x1
11037 + *[0-9a-f]*:   ab cc           cbr r12,0xa
11038 + *[0-9a-f]*:   b7 c7           cbr r7,0x16
11039 + *[0-9a-f]*:   a9 d8           cbr r8,0x9
11040 +
11041 +[0-9a-f]* <brc1>:
11042 + *[0-9a-f]*:   c0 00           breq [0-9a-f]* <.*>
11043 + *[0-9a-f]*:   cf f7           brpl [0-9a-f]* <.*>
11044 + *[0-9a-f]*:   c8 04           brge [0-9a-f]* <.*>
11045 + *[0-9a-f]*:   c7 f3           brcs [0-9a-f]* <.*>
11046 + *[0-9a-f]*:   c0 11           brne [0-9a-f]* <.*>
11047 + *[0-9a-f]*:   c7 33           brcs [0-9a-f]* <.*>
11048 + *[0-9a-f]*:   cf 70           breq [0-9a-f]* <.*>
11049 + *[0-9a-f]*:   c0 60           breq [0-9a-f]* <.*>
11050 +
11051 +[0-9a-f]* <rjmp>:
11052 + *[0-9a-f]*:   c0 08           rjmp [0-9a-f]* <.*>
11053 + *[0-9a-f]*:   cf fb           rjmp [0-9a-f]* <.*>
11054 + *[0-9a-f]*:   c0 0a           rjmp [0-9a-f]* <.*>
11055 + *[0-9a-f]*:   cf f9           rjmp [0-9a-f]* <.*>
11056 + *[0-9a-f]*:   c0 18           rjmp [0-9a-f]* <.*>
11057 + *[0-9a-f]*:   c1 fa           rjmp [0-9a-f]* <.*>
11058 + *[0-9a-f]*:   c0 78           rjmp [0-9a-f]* <.*>
11059 + *[0-9a-f]*:   cf ea           rjmp [0-9a-f]* <.*>
11060 +
11061 +[0-9a-f]* <rcall1>:
11062 + *[0-9a-f]*:   c0 0c           rcall [0-9a-f]* <.*>
11063 + *[0-9a-f]*:   cf ff           rcall [0-9a-f]* <.*>
11064 + *[0-9a-f]*:   c0 0e           rcall [0-9a-f]* <.*>
11065 + *[0-9a-f]*:   cf fd           rcall [0-9a-f]* <.*>
11066 + *[0-9a-f]*:   c0 1c           rcall [0-9a-f]* <.*>
11067 + *[0-9a-f]*:   c6 cc           rcall [0-9a-f]* <.*>
11068 + *[0-9a-f]*:   cf 7e           rcall [0-9a-f]* <.*>
11069 + *[0-9a-f]*:   c1 ae           rcall [0-9a-f]* <.*>
11070 +
11071 +[0-9a-f]* <acall>:
11072 + *[0-9a-f]*:   d0 00           acall 0x0
11073 + *[0-9a-f]*:   df f0           acall 0x3fc
11074 + *[0-9a-f]*:   d8 00           acall 0x200
11075 + *[0-9a-f]*:   d7 f0           acall 0x1fc
11076 + *[0-9a-f]*:   d0 10           acall 0x4
11077 + *[0-9a-f]*:   d5 90           acall 0x164
11078 + *[0-9a-f]*:   d4 c0           acall 0x130
11079 + *[0-9a-f]*:   d2 b0           acall 0xac
11080 +
11081 +[0-9a-f]* <scall>:
11082 + *[0-9a-f]*:   d7 33           scall
11083 + *[0-9a-f]*:   d7 33           scall
11084 + *[0-9a-f]*:   d7 33           scall
11085 + *[0-9a-f]*:   d7 33           scall
11086 + *[0-9a-f]*:   d7 33           scall
11087 + *[0-9a-f]*:   d7 33           scall
11088 + *[0-9a-f]*:   d7 33           scall
11089 + *[0-9a-f]*:   d7 33           scall
11090 +
11091 +[0-9a-f]* <popm>:
11092 + *[0-9a-f]*:   d8 02           popm pc
11093 + *[0-9a-f]*:   dd fa           popm r0-r11,pc,r12=-1
11094 + *[0-9a-f]*:   d4 02           popm lr
11095 + *[0-9a-f]*:   db fa           popm r0-r11,pc,r12=1
11096 + *[0-9a-f]*:   d0 12           popm r0-r3
11097 + *[0-9a-f]*:   d8 e2           popm r4-r10,pc
11098 + *[0-9a-f]*:   d9 1a           popm r0-r3,r11,pc,r12=0
11099 + *[0-9a-f]*:   d7 b2           popm r0-r7,r10-r12,lr
11100 +
11101 +[0-9a-f]* <pushm>:
11102 + *[0-9a-f]*:   d8 01           pushm pc
11103 + *[0-9a-f]*:   df f1           pushm r0-r12,lr-pc
11104 + *[0-9a-f]*:   d8 01           pushm pc
11105 + *[0-9a-f]*:   d7 f1           pushm r0-r12,lr
11106 + *[0-9a-f]*:   d0 11           pushm r0-r3
11107 + *[0-9a-f]*:   dc c1           pushm r8-r10,lr-pc
11108 + *[0-9a-f]*:   d0 91           pushm r0-r3,r10
11109 + *[0-9a-f]*:   d2 41           pushm r8-r9,r12
11110 +
11111 +[0-9a-f]* <popm_n>:
11112 +.*
11113 +.*
11114 +.*
11115 +.*
11116 +.*
11117 +.*
11118 +.*
11119 +.*
11120 +
11121 +[0-9a-f]* <pushm_n>:
11122 +.*
11123 +.*
11124 +.*
11125 +.*
11126 +.*
11127 +.*
11128 +.*
11129 +.*
11130 +
11131 +[0-9a-f]* <csrfcz>:
11132 + *[0-9a-f]*:   d0 03           csrfcz 0x0
11133 + *[0-9a-f]*:   d1 f3           csrfcz 0x1f
11134 + *[0-9a-f]*:   d1 03           csrfcz 0x10
11135 + *[0-9a-f]*:   d0 f3           csrfcz 0xf
11136 + *[0-9a-f]*:   d0 13           csrfcz 0x1
11137 + *[0-9a-f]*:   d0 53           csrfcz 0x5
11138 + *[0-9a-f]*:   d0 d3           csrfcz 0xd
11139 + *[0-9a-f]*:   d1 73           csrfcz 0x17
11140 +
11141 +[0-9a-f]* <ssrf>:
11142 + *[0-9a-f]*:   d2 03           ssrf 0x0
11143 + *[0-9a-f]*:   d3 f3           ssrf 0x1f
11144 + *[0-9a-f]*:   d3 03           ssrf 0x10
11145 + *[0-9a-f]*:   d2 f3           ssrf 0xf
11146 + *[0-9a-f]*:   d2 13           ssrf 0x1
11147 + *[0-9a-f]*:   d3 d3           ssrf 0x1d
11148 + *[0-9a-f]*:   d2 d3           ssrf 0xd
11149 + *[0-9a-f]*:   d2 d3           ssrf 0xd
11150 +
11151 +[0-9a-f]* <csrf>:
11152 + *[0-9a-f]*:   d4 03           csrf 0x0
11153 + *[0-9a-f]*:   d5 f3           csrf 0x1f
11154 + *[0-9a-f]*:   d5 03           csrf 0x10
11155 + *[0-9a-f]*:   d4 f3           csrf 0xf
11156 + *[0-9a-f]*:   d4 13           csrf 0x1
11157 + *[0-9a-f]*:   d4 a3           csrf 0xa
11158 + *[0-9a-f]*:   d4 f3           csrf 0xf
11159 + *[0-9a-f]*:   d4 b3           csrf 0xb
11160 +
11161 +[0-9a-f]* <rete>:
11162 + *[0-9a-f]*:   d6 03           rete
11163 +
11164 +[0-9a-f]* <rets>:
11165 + *[0-9a-f]*:   d6 13           rets
11166 +
11167 +[0-9a-f]* <retd>:
11168 + *[0-9a-f]*:   d6 23           retd
11169 +
11170 +[0-9a-f]* <retj>:
11171 + *[0-9a-f]*:   d6 33           retj
11172 +
11173 +[0-9a-f]* <tlbr>:
11174 + *[0-9a-f]*:   d6 43           tlbr
11175 +
11176 +[0-9a-f]* <tlbs>:
11177 + *[0-9a-f]*:   d6 53           tlbs
11178 +
11179 +[0-9a-f]* <tlbw>:
11180 + *[0-9a-f]*:   d6 63           tlbw
11181 +
11182 +[0-9a-f]* <breakpoint>:
11183 + *[0-9a-f]*:   d6 73           breakpoint
11184 +
11185 +[0-9a-f]* <incjosp>:
11186 + *[0-9a-f]*:   d6 83           incjosp 1
11187 + *[0-9a-f]*:   d6 93           incjosp 2
11188 + *[0-9a-f]*:   d6 a3           incjosp 3
11189 + *[0-9a-f]*:   d6 b3           incjosp 4
11190 + *[0-9a-f]*:   d6 c3           incjosp -4
11191 + *[0-9a-f]*:   d6 d3           incjosp -3
11192 + *[0-9a-f]*:   d6 e3           incjosp -2
11193 + *[0-9a-f]*:   d6 f3           incjosp -1
11194 +
11195 +[0-9a-f]* <nop>:
11196 + *[0-9a-f]*:   d7 03           nop
11197 +
11198 +[0-9a-f]* <popjc>:
11199 + *[0-9a-f]*:   d7 13           popjc
11200 +
11201 +[0-9a-f]* <pushjc>:
11202 + *[0-9a-f]*:   d7 23           pushjc
11203 +
11204 +[0-9a-f]* <add2>:
11205 + *[0-9a-f]*:   fe 0f 00 0f     add pc,pc,pc
11206 + *[0-9a-f]*:   f8 0c 00 3c     add r12,r12,r12<<0x3
11207 + *[0-9a-f]*:   ea 05 00 25     add r5,r5,r5<<0x2
11208 + *[0-9a-f]*:   e8 04 00 14     add r4,r4,r4<<0x1
11209 + *[0-9a-f]*:   fc 0e 00 1e     add lr,lr,lr<<0x1
11210 + *[0-9a-f]*:   f8 00 00 10     add r0,r12,r0<<0x1
11211 + *[0-9a-f]*:   f8 04 00 09     add r9,r12,r4
11212 + *[0-9a-f]*:   f8 07 00 2c     add r12,r12,r7<<0x2
11213 +
11214 +[0-9a-f]* <sub2>:
11215 + *[0-9a-f]*:   fe 0f 01 0f     sub pc,pc,pc
11216 + *[0-9a-f]*:   f8 0c 01 3c     sub r12,r12,r12<<0x3
11217 + *[0-9a-f]*:   ea 05 01 25     sub r5,r5,r5<<0x2
11218 + *[0-9a-f]*:   e8 04 01 14     sub r4,r4,r4<<0x1
11219 + *[0-9a-f]*:   fc 0e 01 1e     sub lr,lr,lr<<0x1
11220 + *[0-9a-f]*:   e6 04 01 0d     sub sp,r3,r4
11221 + *[0-9a-f]*:   ee 03 01 03     sub r3,r7,r3
11222 + *[0-9a-f]*:   f4 0d 01 1d     sub sp,r10,sp<<0x1
11223 +
11224 +[0-9a-f]* <divu>:
11225 + *[0-9a-f]*:   fe 0f 0d 0f     divu pc,pc,pc
11226 + *[0-9a-f]*:   f8 0c 0d 0c     divu r12,r12,r12
11227 + *[0-9a-f]*:   ea 05 0d 05     divu r5,r5,r5
11228 + *[0-9a-f]*:   e8 04 0d 04     divu r4,r4,r4
11229 + *[0-9a-f]*:   fc 0e 0d 0e     divu lr,lr,lr
11230 + *[0-9a-f]*:   e8 0f 0d 0d     divu sp,r4,pc
11231 + *[0-9a-f]*:   ea 0d 0d 05     divu r5,r5,sp
11232 + *[0-9a-f]*:   fa 00 0d 0a     divu r10,sp,r0
11233 +
11234 +[0-9a-f]* <addhh_w>:
11235 + *[0-9a-f]*:   fe 0f 0e 0f     addhh\.w pc,pc:b,pc:b
11236 + *[0-9a-f]*:   f8 0c 0e 3c     addhh\.w r12,r12:t,r12:t
11237 + *[0-9a-f]*:   ea 05 0e 35     addhh\.w r5,r5:t,r5:t
11238 + *[0-9a-f]*:   e8 04 0e 04     addhh\.w r4,r4:b,r4:b
11239 + *[0-9a-f]*:   fc 0e 0e 3e     addhh\.w lr,lr:t,lr:t
11240 + *[0-9a-f]*:   e0 03 0e 00     addhh\.w r0,r0:b,r3:b
11241 + *[0-9a-f]*:   f8 07 0e 2e     addhh\.w lr,r12:t,r7:b
11242 + *[0-9a-f]*:   f4 02 0e 23     addhh\.w r3,r10:t,r2:b
11243 +
11244 +[0-9a-f]* <subhh_w>:
11245 + *[0-9a-f]*:   fe 0f 0f 0f     subhh\.w pc,pc:b,pc:b
11246 + *[0-9a-f]*:   f8 0c 0f 3c     subhh\.w r12,r12:t,r12:t
11247 + *[0-9a-f]*:   ea 05 0f 35     subhh\.w r5,r5:t,r5:t
11248 + *[0-9a-f]*:   e8 04 0f 04     subhh\.w r4,r4:b,r4:b
11249 + *[0-9a-f]*:   fc 0e 0f 3e     subhh\.w lr,lr:t,lr:t
11250 + *[0-9a-f]*:   e2 07 0f 2a     subhh\.w r10,r1:t,r7:b
11251 + *[0-9a-f]*:   f4 0e 0f 3f     subhh\.w pc,r10:t,lr:t
11252 + *[0-9a-f]*:   e0 0c 0f 23     subhh\.w r3,r0:t,r12:b
11253 +
11254 +[0-9a-f]* <adc>:
11255 + *[0-9a-f]*:   fe 0f 00 4f     adc pc,pc,pc
11256 + *[0-9a-f]*:   f8 0c 00 4c     adc r12,r12,r12
11257 + *[0-9a-f]*:   ea 05 00 45     adc r5,r5,r5
11258 + *[0-9a-f]*:   e8 04 00 44     adc r4,r4,r4
11259 + *[0-9a-f]*:   fc 0e 00 4e     adc lr,lr,lr
11260 + *[0-9a-f]*:   e0 07 00 44     adc r4,r0,r7
11261 + *[0-9a-f]*:   e8 03 00 4d     adc sp,r4,r3
11262 + *[0-9a-f]*:   f8 00 00 42     adc r2,r12,r0
11263 +
11264 +[0-9a-f]* <sbc>:
11265 + *[0-9a-f]*:   fe 0f 01 4f     sbc pc,pc,pc
11266 + *[0-9a-f]*:   f8 0c 01 4c     sbc r12,r12,r12
11267 + *[0-9a-f]*:   ea 05 01 45     sbc r5,r5,r5
11268 + *[0-9a-f]*:   e8 04 01 44     sbc r4,r4,r4
11269 + *[0-9a-f]*:   fc 0e 01 4e     sbc lr,lr,lr
11270 + *[0-9a-f]*:   ee 09 01 46     sbc r6,r7,r9
11271 + *[0-9a-f]*:   f0 05 01 40     sbc r0,r8,r5
11272 + *[0-9a-f]*:   e0 04 01 41     sbc r1,r0,r4
11273 +
11274 +[0-9a-f]* <mul_2>:
11275 + *[0-9a-f]*:   fe 0f 02 4f     mul pc,pc,pc
11276 + *[0-9a-f]*:   f8 0c 02 4c     mul r12,r12,r12
11277 + *[0-9a-f]*:   ea 05 02 45     mul r5,r5,r5
11278 + *[0-9a-f]*:   e8 04 02 44     mul r4,r4,r4
11279 + *[0-9a-f]*:   fc 0e 02 4e     mul lr,lr,lr
11280 + *[0-9a-f]*:   e0 00 02 4f     mul pc,r0,r0
11281 + *[0-9a-f]*:   fe 0e 02 48     mul r8,pc,lr
11282 + *[0-9a-f]*:   f8 0f 02 44     mul r4,r12,pc
11283 +
11284 +[0-9a-f]* <mac>:
11285 + *[0-9a-f]*:   fe 0f 03 4f     mac pc,pc,pc
11286 + *[0-9a-f]*:   f8 0c 03 4c     mac r12,r12,r12
11287 + *[0-9a-f]*:   ea 05 03 45     mac r5,r5,r5
11288 + *[0-9a-f]*:   e8 04 03 44     mac r4,r4,r4
11289 + *[0-9a-f]*:   fc 0e 03 4e     mac lr,lr,lr
11290 + *[0-9a-f]*:   e8 00 03 4a     mac r10,r4,r0
11291 + *[0-9a-f]*:   fc 00 03 47     mac r7,lr,r0
11292 + *[0-9a-f]*:   f2 0c 03 42     mac r2,r9,r12
11293 +
11294 +[0-9a-f]* <mulsd>:
11295 + *[0-9a-f]*:   fe 0f 04 4f     muls\.d pc,pc,pc
11296 + *[0-9a-f]*:   f8 0c 04 4c     muls\.d r12,r12,r12
11297 + *[0-9a-f]*:   ea 05 04 45     muls\.d r5,r5,r5
11298 + *[0-9a-f]*:   e8 04 04 44     muls\.d r4,r4,r4
11299 + *[0-9a-f]*:   fc 0e 04 4e     muls\.d lr,lr,lr
11300 + *[0-9a-f]*:   f0 0e 04 42     muls\.d r2,r8,lr
11301 + *[0-9a-f]*:   e0 0b 04 44     muls\.d r4,r0,r11
11302 + *[0-9a-f]*:   fc 06 04 45     muls\.d r5,lr,r6
11303 +
11304 +[0-9a-f]* <macsd>:
11305 + *[0-9a-f]*:   fe 0f 05 40     macs\.d r0,pc,pc
11306 + *[0-9a-f]*:   f8 0c 05 4e     macs\.d lr,r12,r12
11307 + *[0-9a-f]*:   ea 05 05 48     macs\.d r8,r5,r5
11308 + *[0-9a-f]*:   e8 04 05 46     macs\.d r6,r4,r4
11309 + *[0-9a-f]*:   fc 0e 05 42     macs\.d r2,lr,lr
11310 + *[0-9a-f]*:   e2 09 05 48     macs\.d r8,r1,r9
11311 + *[0-9a-f]*:   f0 08 05 4e     macs\.d lr,r8,r8
11312 + *[0-9a-f]*:   e6 0c 05 44     macs\.d r4,r3,r12
11313 +
11314 +[0-9a-f]* <mulud>:
11315 + *[0-9a-f]*:   fe 0f 06 40     mulu\.d r0,pc,pc
11316 + *[0-9a-f]*:   f8 0c 06 4e     mulu\.d lr,r12,r12
11317 + *[0-9a-f]*:   ea 05 06 48     mulu\.d r8,r5,r5
11318 + *[0-9a-f]*:   e8 04 06 46     mulu\.d r6,r4,r4
11319 + *[0-9a-f]*:   fc 0e 06 42     mulu\.d r2,lr,lr
11320 + *[0-9a-f]*:   ea 00 06 46     mulu\.d r6,r5,r0
11321 + *[0-9a-f]*:   ec 01 06 44     mulu\.d r4,r6,r1
11322 + *[0-9a-f]*:   f0 02 06 48     mulu\.d r8,r8,r2
11323 +
11324 +[0-9a-f]* <macud>:
11325 + *[0-9a-f]*:   fe 0f 07 40     macu\.d r0,pc,pc
11326 + *[0-9a-f]*:   f8 0c 07 4e     macu\.d lr,r12,r12
11327 + *[0-9a-f]*:   ea 05 07 48     macu\.d r8,r5,r5
11328 + *[0-9a-f]*:   e8 04 07 46     macu\.d r6,r4,r4
11329 + *[0-9a-f]*:   fc 0e 07 42     macu\.d r2,lr,lr
11330 + *[0-9a-f]*:   fa 0b 07 46     macu\.d r6,sp,r11
11331 + *[0-9a-f]*:   e8 08 07 42     macu\.d r2,r4,r8
11332 + *[0-9a-f]*:   f4 09 07 46     macu\.d r6,r10,r9
11333 +
11334 +[0-9a-f]* <asr_1>:
11335 + *[0-9a-f]*:   fe 0f 08 4f     asr pc,pc,pc
11336 + *[0-9a-f]*:   f8 0c 08 4c     asr r12,r12,r12
11337 + *[0-9a-f]*:   ea 05 08 45     asr r5,r5,r5
11338 + *[0-9a-f]*:   e8 04 08 44     asr r4,r4,r4
11339 + *[0-9a-f]*:   fc 0e 08 4e     asr lr,lr,lr
11340 + *[0-9a-f]*:   ec 0f 08 4f     asr pc,r6,pc
11341 + *[0-9a-f]*:   ec 0c 08 40     asr r0,r6,r12
11342 + *[0-9a-f]*:   fa 00 08 44     asr r4,sp,r0
11343 +
11344 +[0-9a-f]* <lsl_1>:
11345 + *[0-9a-f]*:   fe 0f 09 4f     lsl pc,pc,pc
11346 + *[0-9a-f]*:   f8 0c 09 4c     lsl r12,r12,r12
11347 + *[0-9a-f]*:   ea 05 09 45     lsl r5,r5,r5
11348 + *[0-9a-f]*:   e8 04 09 44     lsl r4,r4,r4
11349 + *[0-9a-f]*:   fc 0e 09 4e     lsl lr,lr,lr
11350 + *[0-9a-f]*:   ea 0e 09 4e     lsl lr,r5,lr
11351 + *[0-9a-f]*:   fe 03 09 45     lsl r5,pc,r3
11352 + *[0-9a-f]*:   fe 09 09 41     lsl r1,pc,r9
11353 +
11354 +[0-9a-f]* <lsr_1>:
11355 + *[0-9a-f]*:   fe 0f 0a 4f     lsr pc,pc,pc
11356 + *[0-9a-f]*:   f8 0c 0a 4c     lsr r12,r12,r12
11357 + *[0-9a-f]*:   ea 05 0a 45     lsr r5,r5,r5
11358 + *[0-9a-f]*:   e8 04 0a 44     lsr r4,r4,r4
11359 + *[0-9a-f]*:   fc 0e 0a 4e     lsr lr,lr,lr
11360 + *[0-9a-f]*:   e8 01 0a 42     lsr r2,r4,r1
11361 + *[0-9a-f]*:   e2 06 0a 45     lsr r5,r1,r6
11362 + *[0-9a-f]*:   ec 07 0a 4d     lsr sp,r6,r7
11363 +
11364 +[0-9a-f]* <xchg>:
11365 + *[0-9a-f]*:   fe 0f 0b 4f     xchg pc,pc,pc
11366 + *[0-9a-f]*:   f8 0c 0b 4c     xchg r12,r12,r12
11367 + *[0-9a-f]*:   ea 05 0b 45     xchg r5,r5,r5
11368 + *[0-9a-f]*:   e8 04 0b 44     xchg r4,r4,r4
11369 + *[0-9a-f]*:   fc 0e 0b 4e     xchg lr,lr,lr
11370 + *[0-9a-f]*:   e8 0d 0b 4e     xchg lr,r4,sp
11371 + *[0-9a-f]*:   ea 0c 0b 41     xchg r1,r5,r12
11372 + *[0-9a-f]*:   f8 00 0b 4e     xchg lr,r12,r0
11373 +
11374 +[0-9a-f]* <max>:
11375 + *[0-9a-f]*:   fe 0f 0c 4f     max pc,pc,pc
11376 + *[0-9a-f]*:   f8 0c 0c 4c     max r12,r12,r12
11377 + *[0-9a-f]*:   ea 05 0c 45     max r5,r5,r5
11378 + *[0-9a-f]*:   e8 04 0c 44     max r4,r4,r4
11379 + *[0-9a-f]*:   fc 0e 0c 4e     max lr,lr,lr
11380 + *[0-9a-f]*:   e4 0d 0c 4e     max lr,r2,sp
11381 + *[0-9a-f]*:   f4 09 0c 44     max r4,r10,r9
11382 + *[0-9a-f]*:   f2 0e 0c 4e     max lr,r9,lr
11383 +
11384 +[0-9a-f]* <min>:
11385 + *[0-9a-f]*:   fe 0f 0d 4f     min pc,pc,pc
11386 + *[0-9a-f]*:   f8 0c 0d 4c     min r12,r12,r12
11387 + *[0-9a-f]*:   ea 05 0d 45     min r5,r5,r5
11388 + *[0-9a-f]*:   e8 04 0d 44     min r4,r4,r4
11389 + *[0-9a-f]*:   fc 0e 0d 4e     min lr,lr,lr
11390 + *[0-9a-f]*:   ee 08 0d 49     min r9,r7,r8
11391 + *[0-9a-f]*:   ea 05 0d 4d     min sp,r5,r5
11392 + *[0-9a-f]*:   e2 04 0d 44     min r4,r1,r4
11393 +
11394 +[0-9a-f]* <addabs>:
11395 + *[0-9a-f]*:   fe 0f 0e 4f     addabs pc,pc,pc
11396 + *[0-9a-f]*:   f8 0c 0e 4c     addabs r12,r12,r12
11397 + *[0-9a-f]*:   ea 05 0e 45     addabs r5,r5,r5
11398 + *[0-9a-f]*:   e8 04 0e 44     addabs r4,r4,r4
11399 + *[0-9a-f]*:   fc 0e 0e 4e     addabs lr,lr,lr
11400 + *[0-9a-f]*:   f4 00 0e 47     addabs r7,r10,r0
11401 + *[0-9a-f]*:   f2 07 0e 49     addabs r9,r9,r7
11402 + *[0-9a-f]*:   f0 0c 0e 42     addabs r2,r8,r12
11403 +
11404 +[0-9a-f]* <mulnhh_w>:
11405 + *[0-9a-f]*:   fe 0f 01 8f     mulnhh\.w pc,pc:b,pc:b
11406 + *[0-9a-f]*:   f8 0c 01 bc     mulnhh\.w r12,r12:t,r12:t
11407 + *[0-9a-f]*:   ea 05 01 b5     mulnhh\.w r5,r5:t,r5:t
11408 + *[0-9a-f]*:   e8 04 01 84     mulnhh\.w r4,r4:b,r4:b
11409 + *[0-9a-f]*:   fc 0e 01 be     mulnhh\.w lr,lr:t,lr:t
11410 + *[0-9a-f]*:   fa 09 01 ab     mulnhh\.w r11,sp:t,r9:b
11411 + *[0-9a-f]*:   e8 0e 01 9d     mulnhh\.w sp,r4:b,lr:t
11412 + *[0-9a-f]*:   e4 0b 01 ac     mulnhh\.w r12,r2:t,r11:b
11413 +
11414 +[0-9a-f]* <mulnwh_d>:
11415 + *[0-9a-f]*:   fe 0f 02 80     mulnwh\.d r0,pc,pc:b
11416 + *[0-9a-f]*:   f8 0c 02 9e     mulnwh\.d lr,r12,r12:t
11417 + *[0-9a-f]*:   ea 05 02 98     mulnwh\.d r8,r5,r5:t
11418 + *[0-9a-f]*:   e8 04 02 86     mulnwh\.d r6,r4,r4:b
11419 + *[0-9a-f]*:   fc 0e 02 92     mulnwh\.d r2,lr,lr:t
11420 + *[0-9a-f]*:   e6 02 02 9e     mulnwh\.d lr,r3,r2:t
11421 + *[0-9a-f]*:   ea 09 02 84     mulnwh\.d r4,r5,r9:b
11422 + *[0-9a-f]*:   e8 04 02 9c     mulnwh\.d r12,r4,r4:t
11423 +
11424 +[0-9a-f]* <machh_w>:
11425 + *[0-9a-f]*:   fe 0f 04 8f     machh\.w pc,pc:b,pc:b
11426 + *[0-9a-f]*:   f8 0c 04 bc     machh\.w r12,r12:t,r12:t
11427 + *[0-9a-f]*:   ea 05 04 b5     machh\.w r5,r5:t,r5:t
11428 + *[0-9a-f]*:   e8 04 04 84     machh\.w r4,r4:b,r4:b
11429 + *[0-9a-f]*:   fc 0e 04 be     machh\.w lr,lr:t,lr:t
11430 + *[0-9a-f]*:   ea 01 04 9e     machh\.w lr,r5:b,r1:t
11431 + *[0-9a-f]*:   ec 07 04 89     machh\.w r9,r6:b,r7:b
11432 + *[0-9a-f]*:   fc 0c 04 a5     machh\.w r5,lr:t,r12:b
11433 +
11434 +[0-9a-f]* <machh_d>:
11435 + *[0-9a-f]*:   fe 0f 05 80     machh\.d r0,pc:b,pc:b
11436 + *[0-9a-f]*:   f8 0c 05 be     machh\.d lr,r12:t,r12:t
11437 + *[0-9a-f]*:   ea 05 05 b8     machh\.d r8,r5:t,r5:t
11438 + *[0-9a-f]*:   e8 04 05 86     machh\.d r6,r4:b,r4:b
11439 + *[0-9a-f]*:   fc 0e 05 b2     machh\.d r2,lr:t,lr:t
11440 + *[0-9a-f]*:   e0 08 05 8a     machh\.d r10,r0:b,r8:b
11441 + *[0-9a-f]*:   e8 05 05 9e     machh\.d lr,r4:b,r5:t
11442 + *[0-9a-f]*:   e0 04 05 98     machh\.d r8,r0:b,r4:t
11443 +
11444 +[0-9a-f]* <macsathh_w>:
11445 + *[0-9a-f]*:   fe 0f 06 8f     macsathh\.w pc,pc:b,pc:b
11446 + *[0-9a-f]*:   f8 0c 06 bc     macsathh\.w r12,r12:t,r12:t
11447 + *[0-9a-f]*:   ea 05 06 b5     macsathh\.w r5,r5:t,r5:t
11448 + *[0-9a-f]*:   e8 04 06 84     macsathh\.w r4,r4:b,r4:b
11449 + *[0-9a-f]*:   fc 0e 06 be     macsathh\.w lr,lr:t,lr:t
11450 + *[0-9a-f]*:   ee 0f 06 b7     macsathh\.w r7,r7:t,pc:t
11451 + *[0-9a-f]*:   e4 04 06 a4     macsathh\.w r4,r2:t,r4:b
11452 + *[0-9a-f]*:   f0 03 06 b4     macsathh\.w r4,r8:t,r3:t
11453 +
11454 +[0-9a-f]* <mulhh_w>:
11455 + *[0-9a-f]*:   fe 0f 07 8f     mulhh\.w pc,pc:b,pc:b
11456 + *[0-9a-f]*:   f8 0c 07 bc     mulhh\.w r12,r12:t,r12:t
11457 + *[0-9a-f]*:   ea 05 07 b5     mulhh\.w r5,r5:t,r5:t
11458 + *[0-9a-f]*:   e8 04 07 84     mulhh\.w r4,r4:b,r4:b
11459 + *[0-9a-f]*:   fc 0e 07 be     mulhh\.w lr,lr:t,lr:t
11460 + *[0-9a-f]*:   e8 09 07 a7     mulhh\.w r7,r4:t,r9:b
11461 + *[0-9a-f]*:   e6 07 07 bf     mulhh\.w pc,r3:t,r7:t
11462 + *[0-9a-f]*:   e8 09 07 9f     mulhh\.w pc,r4:b,r9:t
11463 +
11464 +[0-9a-f]* <mulsathh_h>:
11465 + *[0-9a-f]*:   fe 0f 08 8f     mulsathh\.h pc,pc:b,pc:b
11466 + *[0-9a-f]*:   f8 0c 08 bc     mulsathh\.h r12,r12:t,r12:t
11467 + *[0-9a-f]*:   ea 05 08 b5     mulsathh\.h r5,r5:t,r5:t
11468 + *[0-9a-f]*:   e8 04 08 84     mulsathh\.h r4,r4:b,r4:b
11469 + *[0-9a-f]*:   fc 0e 08 be     mulsathh\.h lr,lr:t,lr:t
11470 + *[0-9a-f]*:   e2 0d 08 83     mulsathh\.h r3,r1:b,sp:b
11471 + *[0-9a-f]*:   fc 0b 08 ab     mulsathh\.h r11,lr:t,r11:b
11472 + *[0-9a-f]*:   f0 0b 08 98     mulsathh\.h r8,r8:b,r11:t
11473 +
11474 +[0-9a-f]* <mulsathh_w>:
11475 + *[0-9a-f]*:   fe 0f 09 8f     mulsathh\.w pc,pc:b,pc:b
11476 + *[0-9a-f]*:   f8 0c 09 bc     mulsathh\.w r12,r12:t,r12:t
11477 + *[0-9a-f]*:   ea 05 09 b5     mulsathh\.w r5,r5:t,r5:t
11478 + *[0-9a-f]*:   e8 04 09 84     mulsathh\.w r4,r4:b,r4:b
11479 + *[0-9a-f]*:   fc 0e 09 be     mulsathh\.w lr,lr:t,lr:t
11480 + *[0-9a-f]*:   f6 06 09 ae     mulsathh\.w lr,r11:t,r6:b
11481 + *[0-9a-f]*:   ec 07 09 96     mulsathh\.w r6,r6:b,r7:t
11482 + *[0-9a-f]*:   e4 03 09 8a     mulsathh\.w r10,r2:b,r3:b
11483 +
11484 +[0-9a-f]* <mulsatrndhh_h>:
11485 + *[0-9a-f]*:   fe 0f 0a 8f     mulsatrndhh\.h pc,pc:b,pc:b
11486 + *[0-9a-f]*:   f8 0c 0a bc     mulsatrndhh\.h r12,r12:t,r12:t
11487 + *[0-9a-f]*:   ea 05 0a b5     mulsatrndhh\.h r5,r5:t,r5:t
11488 + *[0-9a-f]*:   e8 04 0a 84     mulsatrndhh\.h r4,r4:b,r4:b
11489 + *[0-9a-f]*:   fc 0e 0a be     mulsatrndhh\.h lr,lr:t,lr:t
11490 + *[0-9a-f]*:   ec 09 0a 8b     mulsatrndhh\.h r11,r6:b,r9:b
11491 + *[0-9a-f]*:   e6 08 0a 9b     mulsatrndhh\.h r11,r3:b,r8:t
11492 + *[0-9a-f]*:   fa 07 0a b5     mulsatrndhh\.h r5,sp:t,r7:t
11493 +
11494 +[0-9a-f]* <mulsatrndwh_w>:
11495 + *[0-9a-f]*:   fe 0f 0b 8f     mulsatrndwh\.w pc,pc,pc:b
11496 + *[0-9a-f]*:   f8 0c 0b 9c     mulsatrndwh\.w r12,r12,r12:t
11497 + *[0-9a-f]*:   ea 05 0b 95     mulsatrndwh\.w r5,r5,r5:t
11498 + *[0-9a-f]*:   e8 04 0b 84     mulsatrndwh\.w r4,r4,r4:b
11499 + *[0-9a-f]*:   fc 0e 0b 9e     mulsatrndwh\.w lr,lr,lr:t
11500 + *[0-9a-f]*:   f8 00 0b 85     mulsatrndwh\.w r5,r12,r0:b
11501 + *[0-9a-f]*:   f4 0f 0b 87     mulsatrndwh\.w r7,r10,pc:b
11502 + *[0-9a-f]*:   f0 05 0b 9a     mulsatrndwh\.w r10,r8,r5:t
11503 +
11504 +[0-9a-f]* <macwh_d>:
11505 + *[0-9a-f]*:   fe 0f 0c 80     macwh\.d r0,pc,pc:b
11506 + *[0-9a-f]*:   f8 0c 0c 9e     macwh\.d lr,r12,r12:t
11507 + *[0-9a-f]*:   ea 05 0c 98     macwh\.d r8,r5,r5:t
11508 + *[0-9a-f]*:   e8 04 0c 86     macwh\.d r6,r4,r4:b
11509 + *[0-9a-f]*:   fc 0e 0c 92     macwh\.d r2,lr,lr:t
11510 + *[0-9a-f]*:   f4 0c 0c 94     macwh\.d r4,r10,r12:t
11511 + *[0-9a-f]*:   ee 0d 0c 84     macwh\.d r4,r7,sp:b
11512 + *[0-9a-f]*:   f2 0b 0c 8e     macwh\.d lr,r9,r11:b
11513 +
11514 +[0-9a-f]* <mulwh_d>:
11515 + *[0-9a-f]*:   fe 0f 0d 80     mulwh\.d r0,pc,pc:b
11516 + *[0-9a-f]*:   f8 0c 0d 9e     mulwh\.d lr,r12,r12:t
11517 + *[0-9a-f]*:   ea 05 0d 98     mulwh\.d r8,r5,r5:t
11518 + *[0-9a-f]*:   e8 04 0d 86     mulwh\.d r6,r4,r4:b
11519 + *[0-9a-f]*:   fc 0e 0d 92     mulwh\.d r2,lr,lr:t
11520 + *[0-9a-f]*:   ea 01 0d 8c     mulwh\.d r12,r5,r1:b
11521 + *[0-9a-f]*:   e2 03 0d 90     mulwh\.d r0,r1,r3:t
11522 + *[0-9a-f]*:   f2 02 0d 80     mulwh\.d r0,r9,r2:b
11523 +
11524 +[0-9a-f]* <mulsatwh_w>:
11525 + *[0-9a-f]*:   fe 0f 0e 8f     mulsatwh\.w pc,pc,pc:b
11526 + *[0-9a-f]*:   f8 0c 0e 9c     mulsatwh\.w r12,r12,r12:t
11527 + *[0-9a-f]*:   ea 05 0e 95     mulsatwh\.w r5,r5,r5:t
11528 + *[0-9a-f]*:   e8 04 0e 84     mulsatwh\.w r4,r4,r4:b
11529 + *[0-9a-f]*:   fc 0e 0e 9e     mulsatwh\.w lr,lr,lr:t
11530 + *[0-9a-f]*:   fe 0a 0e 9b     mulsatwh\.w r11,pc,r10:t
11531 + *[0-9a-f]*:   f8 09 0e 9d     mulsatwh\.w sp,r12,r9:t
11532 + *[0-9a-f]*:   e6 02 0e 90     mulsatwh\.w r0,r3,r2:t
11533 +
11534 +[0-9a-f]* <ldw7>:
11535 + *[0-9a-f]*:   fe 0f 0f 8f     ld\.w pc,pc\[pc:b<<2\]
11536 + *[0-9a-f]*:   f8 0c 0f bc     ld\.w r12,r12\[r12:t<<2\]
11537 + *[0-9a-f]*:   ea 05 0f a5     ld\.w r5,r5\[r5:u<<2\]
11538 + *[0-9a-f]*:   e8 04 0f 94     ld\.w r4,r4\[r4:l<<2\]
11539 + *[0-9a-f]*:   fc 0e 0f 9e     ld\.w lr,lr\[lr:l<<2\]
11540 + *[0-9a-f]*:   f4 06 0f 99     ld\.w r9,r10\[r6:l<<2\]
11541 + *[0-9a-f]*:   f4 0a 0f 82     ld\.w r2,r10\[r10:b<<2\]
11542 + *[0-9a-f]*:   ea 0f 0f 8b     ld\.w r11,r5\[pc:b<<2\]
11543 +
11544 +[0-9a-f]* <satadd_w>:
11545 + *[0-9a-f]*:   fe 0f 00 cf     satadd\.w pc,pc,pc
11546 + *[0-9a-f]*:   f8 0c 00 cc     satadd\.w r12,r12,r12
11547 + *[0-9a-f]*:   ea 05 00 c5     satadd\.w r5,r5,r5
11548 + *[0-9a-f]*:   e8 04 00 c4     satadd\.w r4,r4,r4
11549 + *[0-9a-f]*:   fc 0e 00 ce     satadd\.w lr,lr,lr
11550 + *[0-9a-f]*:   f0 0b 00 c4     satadd\.w r4,r8,r11
11551 + *[0-9a-f]*:   f8 06 00 c3     satadd\.w r3,r12,r6
11552 + *[0-9a-f]*:   fc 09 00 c3     satadd\.w r3,lr,r9
11553 +
11554 +[0-9a-f]* <satsub_w1>:
11555 + *[0-9a-f]*:   fe 0f 01 cf     satsub\.w pc,pc,pc
11556 + *[0-9a-f]*:   f8 0c 01 cc     satsub\.w r12,r12,r12
11557 + *[0-9a-f]*:   ea 05 01 c5     satsub\.w r5,r5,r5
11558 + *[0-9a-f]*:   e8 04 01 c4     satsub\.w r4,r4,r4
11559 + *[0-9a-f]*:   fc 0e 01 ce     satsub\.w lr,lr,lr
11560 + *[0-9a-f]*:   fa 00 01 c8     satsub\.w r8,sp,r0
11561 + *[0-9a-f]*:   f0 04 01 c9     satsub\.w r9,r8,r4
11562 + *[0-9a-f]*:   fc 02 01 cf     satsub\.w pc,lr,r2
11563 +
11564 +[0-9a-f]* <satadd_h>:
11565 + *[0-9a-f]*:   fe 0f 02 cf     satadd\.h pc,pc,pc
11566 + *[0-9a-f]*:   f8 0c 02 cc     satadd\.h r12,r12,r12
11567 + *[0-9a-f]*:   ea 05 02 c5     satadd\.h r5,r5,r5
11568 + *[0-9a-f]*:   e8 04 02 c4     satadd\.h r4,r4,r4
11569 + *[0-9a-f]*:   fc 0e 02 ce     satadd\.h lr,lr,lr
11570 + *[0-9a-f]*:   e6 09 02 c7     satadd\.h r7,r3,r9
11571 + *[0-9a-f]*:   e0 02 02 c1     satadd\.h r1,r0,r2
11572 + *[0-9a-f]*:   e8 0e 02 c1     satadd\.h r1,r4,lr
11573 +
11574 +[0-9a-f]* <satsub_h>:
11575 + *[0-9a-f]*:   fe 0f 03 cf     satsub\.h pc,pc,pc
11576 + *[0-9a-f]*:   f8 0c 03 cc     satsub\.h r12,r12,r12
11577 + *[0-9a-f]*:   ea 05 03 c5     satsub\.h r5,r5,r5
11578 + *[0-9a-f]*:   e8 04 03 c4     satsub\.h r4,r4,r4
11579 + *[0-9a-f]*:   fc 0e 03 ce     satsub\.h lr,lr,lr
11580 + *[0-9a-f]*:   fc 03 03 ce     satsub\.h lr,lr,r3
11581 + *[0-9a-f]*:   ec 05 03 cb     satsub\.h r11,r6,r5
11582 + *[0-9a-f]*:   fa 00 03 c3     satsub\.h r3,sp,r0
11583 +
11584 +[0-9a-f]* <mul3>:
11585 + *[0-9a-f]*:   fe 0f 10 00     mul pc,pc,0
11586 + *[0-9a-f]*:   f8 0c 10 ff     mul r12,r12,-1
11587 + *[0-9a-f]*:   ea 05 10 80     mul r5,r5,-128
11588 + *[0-9a-f]*:   e8 04 10 7f     mul r4,r4,127
11589 + *[0-9a-f]*:   fc 0e 10 01     mul lr,lr,1
11590 + *[0-9a-f]*:   e4 0c 10 f9     mul r12,r2,-7
11591 + *[0-9a-f]*:   fe 01 10 5f     mul r1,pc,95
11592 + *[0-9a-f]*:   ec 04 10 13     mul r4,r6,19
11593 +
11594 +[0-9a-f]* <rsub2>:
11595 + *[0-9a-f]*:   fe 0f 11 00     rsub pc,pc,0
11596 + *[0-9a-f]*:   f8 0c 11 ff     rsub r12,r12,-1
11597 + *[0-9a-f]*:   ea 05 11 80     rsub r5,r5,-128
11598 + *[0-9a-f]*:   e8 04 11 7f     rsub r4,r4,127
11599 + *[0-9a-f]*:   fc 0e 11 01     rsub lr,lr,1
11600 + *[0-9a-f]*:   fc 09 11 60     rsub r9,lr,96
11601 + *[0-9a-f]*:   e2 0b 11 38     rsub r11,r1,56
11602 + *[0-9a-f]*:   ee 00 11 a9     rsub r0,r7,-87
11603 +
11604 +[0-9a-f]* <clz>:
11605 + *[0-9a-f]*:   fe 0f 12 00     clz pc,pc
11606 + *[0-9a-f]*:   f8 0c 12 00     clz r12,r12
11607 + *[0-9a-f]*:   ea 05 12 00     clz r5,r5
11608 + *[0-9a-f]*:   e8 04 12 00     clz r4,r4
11609 + *[0-9a-f]*:   fc 0e 12 00     clz lr,lr
11610 + *[0-9a-f]*:   e6 02 12 00     clz r2,r3
11611 + *[0-9a-f]*:   f6 05 12 00     clz r5,r11
11612 + *[0-9a-f]*:   e6 0f 12 00     clz pc,r3
11613 +
11614 +[0-9a-f]* <cpc1>:
11615 + *[0-9a-f]*:   fe 0f 13 00     cpc pc,pc
11616 + *[0-9a-f]*:   f8 0c 13 00     cpc r12,r12
11617 + *[0-9a-f]*:   ea 05 13 00     cpc r5,r5
11618 + *[0-9a-f]*:   e8 04 13 00     cpc r4,r4
11619 + *[0-9a-f]*:   fc 0e 13 00     cpc lr,lr
11620 + *[0-9a-f]*:   e8 0f 13 00     cpc pc,r4
11621 + *[0-9a-f]*:   f2 05 13 00     cpc r5,r9
11622 + *[0-9a-f]*:   ee 06 13 00     cpc r6,r7
11623 +
11624 +[0-9a-f]* <asr3>:
11625 + *[0-9a-f]*:   fe 0f 14 00     asr pc,pc,0x0
11626 + *[0-9a-f]*:   f8 0c 14 1f     asr r12,r12,0x1f
11627 + *[0-9a-f]*:   ea 05 14 10     asr r5,r5,0x10
11628 + *[0-9a-f]*:   e8 04 14 0f     asr r4,r4,0xf
11629 + *[0-9a-f]*:   fc 0e 14 01     asr lr,lr,0x1
11630 + *[0-9a-f]*:   f6 04 14 13     asr r4,r11,0x13
11631 + *[0-9a-f]*:   fe 0d 14 1a     asr sp,pc,0x1a
11632 + *[0-9a-f]*:   fa 0b 14 08     asr r11,sp,0x8
11633 +
11634 +[0-9a-f]* <lsl3>:
11635 + *[0-9a-f]*:   fe 0f 15 00     lsl pc,pc,0x0
11636 + *[0-9a-f]*:   f8 0c 15 1f     lsl r12,r12,0x1f
11637 + *[0-9a-f]*:   ea 05 15 10     lsl r5,r5,0x10
11638 + *[0-9a-f]*:   e8 04 15 0f     lsl r4,r4,0xf
11639 + *[0-9a-f]*:   fc 0e 15 01     lsl lr,lr,0x1
11640 + *[0-9a-f]*:   f4 08 15 11     lsl r8,r10,0x11
11641 + *[0-9a-f]*:   fc 02 15 03     lsl r2,lr,0x3
11642 + *[0-9a-f]*:   f6 0e 15 0e     lsl lr,r11,0xe
11643 +
11644 +[0-9a-f]* <lsr3>:
11645 + *[0-9a-f]*:   fe 0f 16 00     lsr pc,pc,0x0
11646 + *[0-9a-f]*:   f8 0c 16 1f     lsr r12,r12,0x1f
11647 + *[0-9a-f]*:   ea 05 16 10     lsr r5,r5,0x10
11648 + *[0-9a-f]*:   e8 04 16 0f     lsr r4,r4,0xf
11649 + *[0-9a-f]*:   fc 0e 16 01     lsr lr,lr,0x1
11650 + *[0-9a-f]*:   e6 04 16 1f     lsr r4,r3,0x1f
11651 + *[0-9a-f]*:   f2 0f 16 0e     lsr pc,r9,0xe
11652 + *[0-9a-f]*:   e0 03 16 06     lsr r3,r0,0x6
11653 +
11654 +[0-9a-f]* <movc1>:
11655 + *[0-9a-f]*:   fe 0f 17 00     moveq pc,pc
11656 + *[0-9a-f]*:   f8 0c 17 f0     moval r12,r12
11657 + *[0-9a-f]*:   ea 05 17 80     movls r5,r5
11658 + *[0-9a-f]*:   e8 04 17 70     movpl r4,r4
11659 + *[0-9a-f]*:   fc 0e 17 10     movne lr,lr
11660 + *[0-9a-f]*:   f6 0f 17 10     movne pc,r11
11661 + *[0-9a-f]*:   e4 0a 17 60     movmi r10,r2
11662 + *[0-9a-f]*:   f8 08 17 80     movls r8,r12
11663 +
11664 +[0-9a-f]* <padd_h>:
11665 + *[0-9a-f]*:   fe 0f 20 0f     padd\.h pc,pc,pc
11666 + *[0-9a-f]*:   f8 0c 20 0c     padd\.h r12,r12,r12
11667 + *[0-9a-f]*:   ea 05 20 05     padd\.h r5,r5,r5
11668 + *[0-9a-f]*:   e8 04 20 04     padd\.h r4,r4,r4
11669 + *[0-9a-f]*:   fc 0e 20 0e     padd\.h lr,lr,lr
11670 + *[0-9a-f]*:   e4 07 20 08     padd\.h r8,r2,r7
11671 + *[0-9a-f]*:   e0 03 20 00     padd\.h r0,r0,r3
11672 + *[0-9a-f]*:   f6 06 20 0d     padd\.h sp,r11,r6
11673 +
11674 +[0-9a-f]* <psub_h>:
11675 + *[0-9a-f]*:   fe 0f 20 1f     psub\.h pc,pc,pc
11676 + *[0-9a-f]*:   f8 0c 20 1c     psub\.h r12,r12,r12
11677 + *[0-9a-f]*:   ea 05 20 15     psub\.h r5,r5,r5
11678 + *[0-9a-f]*:   e8 04 20 14     psub\.h r4,r4,r4
11679 + *[0-9a-f]*:   fc 0e 20 1e     psub\.h lr,lr,lr
11680 + *[0-9a-f]*:   ec 08 20 1e     psub\.h lr,r6,r8
11681 + *[0-9a-f]*:   e2 0d 20 10     psub\.h r0,r1,sp
11682 + *[0-9a-f]*:   fe 0d 20 1f     psub\.h pc,pc,sp
11683 +
11684 +[0-9a-f]* <paddx_h>:
11685 + *[0-9a-f]*:   fe 0f 20 2f     paddx\.h pc,pc,pc
11686 + *[0-9a-f]*:   f8 0c 20 2c     paddx\.h r12,r12,r12
11687 + *[0-9a-f]*:   ea 05 20 25     paddx\.h r5,r5,r5
11688 + *[0-9a-f]*:   e8 04 20 24     paddx\.h r4,r4,r4
11689 + *[0-9a-f]*:   fc 0e 20 2e     paddx\.h lr,lr,lr
11690 + *[0-9a-f]*:   fe 01 20 2f     paddx\.h pc,pc,r1
11691 + *[0-9a-f]*:   e8 05 20 2a     paddx\.h r10,r4,r5
11692 + *[0-9a-f]*:   fe 02 20 25     paddx\.h r5,pc,r2
11693 +
11694 +[0-9a-f]* <psubx_h>:
11695 + *[0-9a-f]*:   fe 0f 20 3f     psubx\.h pc,pc,pc
11696 + *[0-9a-f]*:   f8 0c 20 3c     psubx\.h r12,r12,r12
11697 + *[0-9a-f]*:   ea 05 20 35     psubx\.h r5,r5,r5
11698 + *[0-9a-f]*:   e8 04 20 34     psubx\.h r4,r4,r4
11699 + *[0-9a-f]*:   fc 0e 20 3e     psubx\.h lr,lr,lr
11700 + *[0-9a-f]*:   f8 05 20 35     psubx\.h r5,r12,r5
11701 + *[0-9a-f]*:   f0 03 20 33     psubx\.h r3,r8,r3
11702 + *[0-9a-f]*:   e4 03 20 35     psubx\.h r5,r2,r3
11703 +
11704 +[0-9a-f]* <padds_sh>:
11705 + *[0-9a-f]*:   fe 0f 20 4f     padds\.sh pc,pc,pc
11706 + *[0-9a-f]*:   f8 0c 20 4c     padds\.sh r12,r12,r12
11707 + *[0-9a-f]*:   ea 05 20 45     padds\.sh r5,r5,r5
11708 + *[0-9a-f]*:   e8 04 20 44     padds\.sh r4,r4,r4
11709 + *[0-9a-f]*:   fc 0e 20 4e     padds\.sh lr,lr,lr
11710 + *[0-9a-f]*:   fc 02 20 49     padds\.sh r9,lr,r2
11711 + *[0-9a-f]*:   f0 01 20 46     padds\.sh r6,r8,r1
11712 + *[0-9a-f]*:   e8 0a 20 46     padds\.sh r6,r4,r10
11713 +
11714 +[0-9a-f]* <psubs_sh>:
11715 + *[0-9a-f]*:   fe 0f 20 5f     psubs\.sh pc,pc,pc
11716 + *[0-9a-f]*:   f8 0c 20 5c     psubs\.sh r12,r12,r12
11717 + *[0-9a-f]*:   ea 05 20 55     psubs\.sh r5,r5,r5
11718 + *[0-9a-f]*:   e8 04 20 54     psubs\.sh r4,r4,r4
11719 + *[0-9a-f]*:   fc 0e 20 5e     psubs\.sh lr,lr,lr
11720 + *[0-9a-f]*:   fc 0b 20 56     psubs\.sh r6,lr,r11
11721 + *[0-9a-f]*:   f8 04 20 52     psubs\.sh r2,r12,r4
11722 + *[0-9a-f]*:   f2 00 20 50     psubs\.sh r0,r9,r0
11723 +
11724 +[0-9a-f]* <paddxs_sh>:
11725 + *[0-9a-f]*:   fe 0f 20 6f     paddxs\.sh pc,pc,pc
11726 + *[0-9a-f]*:   f8 0c 20 6c     paddxs\.sh r12,r12,r12
11727 + *[0-9a-f]*:   ea 05 20 65     paddxs\.sh r5,r5,r5
11728 + *[0-9a-f]*:   e8 04 20 64     paddxs\.sh r4,r4,r4
11729 + *[0-9a-f]*:   fc 0e 20 6e     paddxs\.sh lr,lr,lr
11730 + *[0-9a-f]*:   e6 09 20 60     paddxs\.sh r0,r3,r9
11731 + *[0-9a-f]*:   f4 0b 20 6f     paddxs\.sh pc,r10,r11
11732 + *[0-9a-f]*:   f4 0f 20 6f     paddxs\.sh pc,r10,pc
11733 +
11734 +[0-9a-f]* <psubxs_sh>:
11735 + *[0-9a-f]*:   fe 0f 20 7f     psubxs\.sh pc,pc,pc
11736 + *[0-9a-f]*:   f8 0c 20 7c     psubxs\.sh r12,r12,r12
11737 + *[0-9a-f]*:   ea 05 20 75     psubxs\.sh r5,r5,r5
11738 + *[0-9a-f]*:   e8 04 20 74     psubxs\.sh r4,r4,r4
11739 + *[0-9a-f]*:   fc 0e 20 7e     psubxs\.sh lr,lr,lr
11740 + *[0-9a-f]*:   e8 04 20 77     psubxs\.sh r7,r4,r4
11741 + *[0-9a-f]*:   f0 03 20 77     psubxs\.sh r7,r8,r3
11742 + *[0-9a-f]*:   ec 05 20 7f     psubxs\.sh pc,r6,r5
11743 +
11744 +[0-9a-f]* <padds_uh>:
11745 + *[0-9a-f]*:   fe 0f 20 8f     padds\.uh pc,pc,pc
11746 + *[0-9a-f]*:   f8 0c 20 8c     padds\.uh r12,r12,r12
11747 + *[0-9a-f]*:   ea 05 20 85     padds\.uh r5,r5,r5
11748 + *[0-9a-f]*:   e8 04 20 84     padds\.uh r4,r4,r4
11749 + *[0-9a-f]*:   fc 0e 20 8e     padds\.uh lr,lr,lr
11750 + *[0-9a-f]*:   f6 07 20 8c     padds\.uh r12,r11,r7
11751 + *[0-9a-f]*:   f0 0e 20 87     padds\.uh r7,r8,lr
11752 + *[0-9a-f]*:   f2 07 20 86     padds\.uh r6,r9,r7
11753 +
11754 +[0-9a-f]* <psubs_uh>:
11755 + *[0-9a-f]*:   fe 0f 20 9f     psubs\.uh pc,pc,pc
11756 + *[0-9a-f]*:   f8 0c 20 9c     psubs\.uh r12,r12,r12
11757 + *[0-9a-f]*:   ea 05 20 95     psubs\.uh r5,r5,r5
11758 + *[0-9a-f]*:   e8 04 20 94     psubs\.uh r4,r4,r4
11759 + *[0-9a-f]*:   fc 0e 20 9e     psubs\.uh lr,lr,lr
11760 + *[0-9a-f]*:   f4 06 20 9e     psubs\.uh lr,r10,r6
11761 + *[0-9a-f]*:   e4 0f 20 9d     psubs\.uh sp,r2,pc
11762 + *[0-9a-f]*:   f2 02 20 92     psubs\.uh r2,r9,r2
11763 +
11764 +[0-9a-f]* <paddxs_uh>:
11765 + *[0-9a-f]*:   fe 0f 20 af     paddxs\.uh pc,pc,pc
11766 + *[0-9a-f]*:   f8 0c 20 ac     paddxs\.uh r12,r12,r12
11767 + *[0-9a-f]*:   ea 05 20 a5     paddxs\.uh r5,r5,r5
11768 + *[0-9a-f]*:   e8 04 20 a4     paddxs\.uh r4,r4,r4
11769 + *[0-9a-f]*:   fc 0e 20 ae     paddxs\.uh lr,lr,lr
11770 + *[0-9a-f]*:   f2 05 20 a7     paddxs\.uh r7,r9,r5
11771 + *[0-9a-f]*:   e2 04 20 a9     paddxs\.uh r9,r1,r4
11772 + *[0-9a-f]*:   e4 03 20 a5     paddxs\.uh r5,r2,r3
11773 +
11774 +[0-9a-f]* <psubxs_uh>:
11775 + *[0-9a-f]*:   fe 0f 20 bf     psubxs\.uh pc,pc,pc
11776 + *[0-9a-f]*:   f8 0c 20 bc     psubxs\.uh r12,r12,r12
11777 + *[0-9a-f]*:   ea 05 20 b5     psubxs\.uh r5,r5,r5
11778 + *[0-9a-f]*:   e8 04 20 b4     psubxs\.uh r4,r4,r4
11779 + *[0-9a-f]*:   fc 0e 20 be     psubxs\.uh lr,lr,lr
11780 + *[0-9a-f]*:   ea 0d 20 bd     psubxs\.uh sp,r5,sp
11781 + *[0-9a-f]*:   ec 06 20 bd     psubxs\.uh sp,r6,r6
11782 + *[0-9a-f]*:   f6 08 20 b3     psubxs\.uh r3,r11,r8
11783 +
11784 +[0-9a-f]* <paddh_sh>:
11785 + *[0-9a-f]*:   fe 0f 20 cf     paddh\.sh pc,pc,pc
11786 + *[0-9a-f]*:   f8 0c 20 cc     paddh\.sh r12,r12,r12
11787 + *[0-9a-f]*:   ea 05 20 c5     paddh\.sh r5,r5,r5
11788 + *[0-9a-f]*:   e8 04 20 c4     paddh\.sh r4,r4,r4
11789 + *[0-9a-f]*:   fc 0e 20 ce     paddh\.sh lr,lr,lr
11790 + *[0-9a-f]*:   fa 03 20 cc     paddh\.sh r12,sp,r3
11791 + *[0-9a-f]*:   ea 03 20 cf     paddh\.sh pc,r5,r3
11792 + *[0-9a-f]*:   f0 0d 20 c8     paddh\.sh r8,r8,sp
11793 +
11794 +[0-9a-f]* <psubh_sh>:
11795 + *[0-9a-f]*:   fe 0f 20 df     psubh\.sh pc,pc,pc
11796 + *[0-9a-f]*:   f8 0c 20 dc     psubh\.sh r12,r12,r12
11797 + *[0-9a-f]*:   ea 05 20 d5     psubh\.sh r5,r5,r5
11798 + *[0-9a-f]*:   e8 04 20 d4     psubh\.sh r4,r4,r4
11799 + *[0-9a-f]*:   fc 0e 20 de     psubh\.sh lr,lr,lr
11800 + *[0-9a-f]*:   ea 08 20 d1     psubh\.sh r1,r5,r8
11801 + *[0-9a-f]*:   e6 06 20 d7     psubh\.sh r7,r3,r6
11802 + *[0-9a-f]*:   e6 03 20 d4     psubh\.sh r4,r3,r3
11803 +
11804 +[0-9a-f]* <paddxh_sh>:
11805 + *[0-9a-f]*:   fe 0f 20 ef     paddxh\.sh pc,pc,pc
11806 + *[0-9a-f]*:   f8 0c 20 ec     paddxh\.sh r12,r12,r12
11807 + *[0-9a-f]*:   ea 05 20 e5     paddxh\.sh r5,r5,r5
11808 + *[0-9a-f]*:   e8 04 20 e4     paddxh\.sh r4,r4,r4
11809 + *[0-9a-f]*:   fc 0e 20 ee     paddxh\.sh lr,lr,lr
11810 + *[0-9a-f]*:   e0 04 20 e6     paddxh\.sh r6,r0,r4
11811 + *[0-9a-f]*:   f0 09 20 e9     paddxh\.sh r9,r8,r9
11812 + *[0-9a-f]*:   e0 0d 20 e3     paddxh\.sh r3,r0,sp
11813 +
11814 +[0-9a-f]* <psubxh_sh>:
11815 + *[0-9a-f]*:   fe 0f 20 ff     psubxh\.sh pc,pc,pc
11816 + *[0-9a-f]*:   f8 0c 20 fc     psubxh\.sh r12,r12,r12
11817 + *[0-9a-f]*:   ea 05 20 f5     psubxh\.sh r5,r5,r5
11818 + *[0-9a-f]*:   e8 04 20 f4     psubxh\.sh r4,r4,r4
11819 + *[0-9a-f]*:   fc 0e 20 fe     psubxh\.sh lr,lr,lr
11820 + *[0-9a-f]*:   fe 0c 20 f4     psubxh\.sh r4,pc,r12
11821 + *[0-9a-f]*:   e8 06 20 f8     psubxh\.sh r8,r4,r6
11822 + *[0-9a-f]*:   f2 04 20 fc     psubxh\.sh r12,r9,r4
11823 +
11824 +[0-9a-f]* <paddsub_h>:
11825 + *[0-9a-f]*:   fe 0f 21 0f     paddsub\.h pc,pc:b,pc:b
11826 + *[0-9a-f]*:   f8 0c 21 3c     paddsub\.h r12,r12:t,r12:t
11827 + *[0-9a-f]*:   ea 05 21 35     paddsub\.h r5,r5:t,r5:t
11828 + *[0-9a-f]*:   e8 04 21 04     paddsub\.h r4,r4:b,r4:b
11829 + *[0-9a-f]*:   fc 0e 21 3e     paddsub\.h lr,lr:t,lr:t
11830 + *[0-9a-f]*:   e4 0e 21 25     paddsub\.h r5,r2:t,lr:b
11831 + *[0-9a-f]*:   e2 08 21 07     paddsub\.h r7,r1:b,r8:b
11832 + *[0-9a-f]*:   f4 05 21 36     paddsub\.h r6,r10:t,r5:t
11833 +
11834 +[0-9a-f]* <psubadd_h>:
11835 + *[0-9a-f]*:   fe 0f 21 4f     psubadd\.h pc,pc:b,pc:b
11836 + *[0-9a-f]*:   f8 0c 21 7c     psubadd\.h r12,r12:t,r12:t
11837 + *[0-9a-f]*:   ea 05 21 75     psubadd\.h r5,r5:t,r5:t
11838 + *[0-9a-f]*:   e8 04 21 44     psubadd\.h r4,r4:b,r4:b
11839 + *[0-9a-f]*:   fc 0e 21 7e     psubadd\.h lr,lr:t,lr:t
11840 + *[0-9a-f]*:   f6 08 21 79     psubadd\.h r9,r11:t,r8:t
11841 + *[0-9a-f]*:   ee 0e 21 7a     psubadd\.h r10,r7:t,lr:t
11842 + *[0-9a-f]*:   fe 0f 21 66     psubadd\.h r6,pc:t,pc:b
11843 +
11844 +[0-9a-f]* <paddsubs_sh>:
11845 + *[0-9a-f]*:   fe 0f 21 8f     paddsubs\.sh pc,pc:b,pc:b
11846 + *[0-9a-f]*:   f8 0c 21 bc     paddsubs\.sh r12,r12:t,r12:t
11847 + *[0-9a-f]*:   ea 05 21 b5     paddsubs\.sh r5,r5:t,r5:t
11848 + *[0-9a-f]*:   e8 04 21 84     paddsubs\.sh r4,r4:b,r4:b
11849 + *[0-9a-f]*:   fc 0e 21 be     paddsubs\.sh lr,lr:t,lr:t
11850 + *[0-9a-f]*:   fc 00 21 a0     paddsubs\.sh r0,lr:t,r0:b
11851 + *[0-9a-f]*:   e4 04 21 b9     paddsubs\.sh r9,r2:t,r4:t
11852 + *[0-9a-f]*:   f2 0d 21 bc     paddsubs\.sh r12,r9:t,sp:t
11853 +
11854 +[0-9a-f]* <psubadds_sh>:
11855 + *[0-9a-f]*:   fe 0f 21 cf     psubadds\.sh pc,pc:b,pc:b
11856 + *[0-9a-f]*:   f8 0c 21 fc     psubadds\.sh r12,r12:t,r12:t
11857 + *[0-9a-f]*:   ea 05 21 f5     psubadds\.sh r5,r5:t,r5:t
11858 + *[0-9a-f]*:   e8 04 21 c4     psubadds\.sh r4,r4:b,r4:b
11859 + *[0-9a-f]*:   fc 0e 21 fe     psubadds\.sh lr,lr:t,lr:t
11860 + *[0-9a-f]*:   fc 01 21 df     psubadds\.sh pc,lr:b,r1:t
11861 + *[0-9a-f]*:   e6 0c 21 cb     psubadds\.sh r11,r3:b,r12:b
11862 + *[0-9a-f]*:   e4 08 21 fa     psubadds\.sh r10,r2:t,r8:t
11863 +
11864 +[0-9a-f]* <paddsubs_uh>:
11865 + *[0-9a-f]*:   fe 0f 22 0f     paddsubs\.uh pc,pc:b,pc:b
11866 + *[0-9a-f]*:   f8 0c 22 3c     paddsubs\.uh r12,r12:t,r12:t
11867 + *[0-9a-f]*:   ea 05 22 35     paddsubs\.uh r5,r5:t,r5:t
11868 + *[0-9a-f]*:   e8 04 22 04     paddsubs\.uh r4,r4:b,r4:b
11869 + *[0-9a-f]*:   fc 0e 22 3e     paddsubs\.uh lr,lr:t,lr:t
11870 + *[0-9a-f]*:   e4 03 22 09     paddsubs\.uh r9,r2:b,r3:b
11871 + *[0-9a-f]*:   fa 07 22 1d     paddsubs\.uh sp,sp:b,r7:t
11872 + *[0-9a-f]*:   e0 0a 22 1e     paddsubs\.uh lr,r0:b,r10:t
11873 +
11874 +[0-9a-f]* <psubadds_uh>:
11875 + *[0-9a-f]*:   fe 0f 22 4f     psubadds\.uh pc,pc:b,pc:b
11876 + *[0-9a-f]*:   f8 0c 22 7c     psubadds\.uh r12,r12:t,r12:t
11877 + *[0-9a-f]*:   ea 05 22 75     psubadds\.uh r5,r5:t,r5:t
11878 + *[0-9a-f]*:   e8 04 22 44     psubadds\.uh r4,r4:b,r4:b
11879 + *[0-9a-f]*:   fc 0e 22 7e     psubadds\.uh lr,lr:t,lr:t
11880 + *[0-9a-f]*:   f2 0f 22 7c     psubadds\.uh r12,r9:t,pc:t
11881 + *[0-9a-f]*:   ec 08 22 48     psubadds\.uh r8,r6:b,r8:b
11882 + *[0-9a-f]*:   f0 04 22 48     psubadds\.uh r8,r8:b,r4:b
11883 +
11884 +[0-9a-f]* <paddsubh_sh>:
11885 + *[0-9a-f]*:   fe 0f 22 8f     paddsubh\.sh pc,pc:b,pc:b
11886 + *[0-9a-f]*:   f8 0c 22 bc     paddsubh\.sh r12,r12:t,r12:t
11887 + *[0-9a-f]*:   ea 05 22 b5     paddsubh\.sh r5,r5:t,r5:t
11888 + *[0-9a-f]*:   e8 04 22 84     paddsubh\.sh r4,r4:b,r4:b
11889 + *[0-9a-f]*:   fc 0e 22 be     paddsubh\.sh lr,lr:t,lr:t
11890 + *[0-9a-f]*:   f2 09 22 a8     paddsubh\.sh r8,r9:t,r9:b
11891 + *[0-9a-f]*:   fa 01 22 b0     paddsubh\.sh r0,sp:t,r1:t
11892 + *[0-9a-f]*:   e2 00 22 93     paddsubh\.sh r3,r1:b,r0:t
11893 +
11894 +[0-9a-f]* <psubaddh_sh>:
11895 + *[0-9a-f]*:   fe 0f 22 cf     psubaddh\.sh pc,pc:b,pc:b
11896 + *[0-9a-f]*:   f8 0c 22 fc     psubaddh\.sh r12,r12:t,r12:t
11897 + *[0-9a-f]*:   ea 05 22 f5     psubaddh\.sh r5,r5:t,r5:t
11898 + *[0-9a-f]*:   e8 04 22 c4     psubaddh\.sh r4,r4:b,r4:b
11899 + *[0-9a-f]*:   fc 0e 22 fe     psubaddh\.sh lr,lr:t,lr:t
11900 + *[0-9a-f]*:   e6 0a 22 e7     psubaddh\.sh r7,r3:t,r10:b
11901 + *[0-9a-f]*:   e4 01 22 f7     psubaddh\.sh r7,r2:t,r1:t
11902 + *[0-9a-f]*:   e6 06 22 cb     psubaddh\.sh r11,r3:b,r6:b
11903 +
11904 +[0-9a-f]* <padd_b>:
11905 + *[0-9a-f]*:   fe 0f 23 0f     padd\.b pc,pc,pc
11906 + *[0-9a-f]*:   f8 0c 23 0c     padd\.b r12,r12,r12
11907 + *[0-9a-f]*:   ea 05 23 05     padd\.b r5,r5,r5
11908 + *[0-9a-f]*:   e8 04 23 04     padd\.b r4,r4,r4
11909 + *[0-9a-f]*:   fc 0e 23 0e     padd\.b lr,lr,lr
11910 + *[0-9a-f]*:   ec 0f 23 02     padd\.b r2,r6,pc
11911 + *[0-9a-f]*:   f2 0c 23 08     padd\.b r8,r9,r12
11912 + *[0-9a-f]*:   f8 03 23 05     padd\.b r5,r12,r3
11913 +
11914 +[0-9a-f]* <psub_b>:
11915 + *[0-9a-f]*:   fe 0f 23 1f     psub\.b pc,pc,pc
11916 + *[0-9a-f]*:   f8 0c 23 1c     psub\.b r12,r12,r12
11917 + *[0-9a-f]*:   ea 05 23 15     psub\.b r5,r5,r5
11918 + *[0-9a-f]*:   e8 04 23 14     psub\.b r4,r4,r4
11919 + *[0-9a-f]*:   fc 0e 23 1e     psub\.b lr,lr,lr
11920 + *[0-9a-f]*:   f8 0f 23 10     psub\.b r0,r12,pc
11921 + *[0-9a-f]*:   fa 0a 23 17     psub\.b r7,sp,r10
11922 + *[0-9a-f]*:   fa 0c 23 15     psub\.b r5,sp,r12
11923 +
11924 +[0-9a-f]* <padds_sb>:
11925 + *[0-9a-f]*:   fe 0f 23 2f     padds\.sb pc,pc,pc
11926 + *[0-9a-f]*:   f8 0c 23 2c     padds\.sb r12,r12,r12
11927 + *[0-9a-f]*:   ea 05 23 25     padds\.sb r5,r5,r5
11928 + *[0-9a-f]*:   e8 04 23 24     padds\.sb r4,r4,r4
11929 + *[0-9a-f]*:   fc 0e 23 2e     padds\.sb lr,lr,lr
11930 + *[0-9a-f]*:   f6 04 23 2d     padds\.sb sp,r11,r4
11931 + *[0-9a-f]*:   f4 0b 23 2b     padds\.sb r11,r10,r11
11932 + *[0-9a-f]*:   f8 06 23 25     padds\.sb r5,r12,r6
11933 +
11934 +[0-9a-f]* <psubs_sb>:
11935 + *[0-9a-f]*:   fe 0f 23 3f     psubs\.sb pc,pc,pc
11936 + *[0-9a-f]*:   f8 0c 23 3c     psubs\.sb r12,r12,r12
11937 + *[0-9a-f]*:   ea 05 23 35     psubs\.sb r5,r5,r5
11938 + *[0-9a-f]*:   e8 04 23 34     psubs\.sb r4,r4,r4
11939 + *[0-9a-f]*:   fc 0e 23 3e     psubs\.sb lr,lr,lr
11940 + *[0-9a-f]*:   ec 08 23 37     psubs\.sb r7,r6,r8
11941 + *[0-9a-f]*:   f4 09 23 3c     psubs\.sb r12,r10,r9
11942 + *[0-9a-f]*:   f6 00 23 3f     psubs\.sb pc,r11,r0
11943 +
11944 +[0-9a-f]* <padds_ub>:
11945 + *[0-9a-f]*:   fe 0f 23 4f     padds\.ub pc,pc,pc
11946 + *[0-9a-f]*:   f8 0c 23 4c     padds\.ub r12,r12,r12
11947 + *[0-9a-f]*:   ea 05 23 45     padds\.ub r5,r5,r5
11948 + *[0-9a-f]*:   e8 04 23 44     padds\.ub r4,r4,r4
11949 + *[0-9a-f]*:   fc 0e 23 4e     padds\.ub lr,lr,lr
11950 + *[0-9a-f]*:   e4 0b 23 43     padds\.ub r3,r2,r11
11951 + *[0-9a-f]*:   f0 01 23 4a     padds\.ub r10,r8,r1
11952 + *[0-9a-f]*:   f0 0a 23 4b     padds\.ub r11,r8,r10
11953 +
11954 +[0-9a-f]* <psubs_ub>:
11955 + *[0-9a-f]*:   fe 0f 23 5f     psubs\.ub pc,pc,pc
11956 + *[0-9a-f]*:   f8 0c 23 5c     psubs\.ub r12,r12,r12
11957 + *[0-9a-f]*:   ea 05 23 55     psubs\.ub r5,r5,r5
11958 + *[0-9a-f]*:   e8 04 23 54     psubs\.ub r4,r4,r4
11959 + *[0-9a-f]*:   fc 0e 23 5e     psubs\.ub lr,lr,lr
11960 + *[0-9a-f]*:   e4 07 23 50     psubs\.ub r0,r2,r7
11961 + *[0-9a-f]*:   ea 03 23 5e     psubs\.ub lr,r5,r3
11962 + *[0-9a-f]*:   ee 09 23 56     psubs\.ub r6,r7,r9
11963 +
11964 +[0-9a-f]* <paddh_ub>:
11965 + *[0-9a-f]*:   fe 0f 23 6f     paddh\.ub pc,pc,pc
11966 + *[0-9a-f]*:   f8 0c 23 6c     paddh\.ub r12,r12,r12
11967 + *[0-9a-f]*:   ea 05 23 65     paddh\.ub r5,r5,r5
11968 + *[0-9a-f]*:   e8 04 23 64     paddh\.ub r4,r4,r4
11969 + *[0-9a-f]*:   fc 0e 23 6e     paddh\.ub lr,lr,lr
11970 + *[0-9a-f]*:   e2 00 23 6e     paddh\.ub lr,r1,r0
11971 + *[0-9a-f]*:   ee 07 23 62     paddh\.ub r2,r7,r7
11972 + *[0-9a-f]*:   e2 02 23 62     paddh\.ub r2,r1,r2
11973 +
11974 +[0-9a-f]* <psubh_ub>:
11975 + *[0-9a-f]*:   fe 0f 23 7f     psubh\.ub pc,pc,pc
11976 + *[0-9a-f]*:   f8 0c 23 7c     psubh\.ub r12,r12,r12
11977 + *[0-9a-f]*:   ea 05 23 75     psubh\.ub r5,r5,r5
11978 + *[0-9a-f]*:   e8 04 23 74     psubh\.ub r4,r4,r4
11979 + *[0-9a-f]*:   fc 0e 23 7e     psubh\.ub lr,lr,lr
11980 + *[0-9a-f]*:   e2 06 23 70     psubh\.ub r0,r1,r6
11981 + *[0-9a-f]*:   fc 0a 23 74     psubh\.ub r4,lr,r10
11982 + *[0-9a-f]*:   f0 01 23 79     psubh\.ub r9,r8,r1
11983 +
11984 +[0-9a-f]* <pmax_ub>:
11985 + *[0-9a-f]*:   fe 0f 23 8f     pmax\.ub pc,pc,pc
11986 + *[0-9a-f]*:   f8 0c 23 8c     pmax\.ub r12,r12,r12
11987 + *[0-9a-f]*:   ea 05 23 85     pmax\.ub r5,r5,r5
11988 + *[0-9a-f]*:   e8 04 23 84     pmax\.ub r4,r4,r4
11989 + *[0-9a-f]*:   fc 0e 23 8e     pmax\.ub lr,lr,lr
11990 + *[0-9a-f]*:   e4 0b 23 8f     pmax\.ub pc,r2,r11
11991 + *[0-9a-f]*:   e2 01 23 8c     pmax\.ub r12,r1,r1
11992 + *[0-9a-f]*:   e4 00 23 85     pmax\.ub r5,r2,r0
11993 +
11994 +[0-9a-f]* <pmax_sh>:
11995 + *[0-9a-f]*:   fe 0f 23 9f     pmax\.sh pc,pc,pc
11996 + *[0-9a-f]*:   f8 0c 23 9c     pmax\.sh r12,r12,r12
11997 + *[0-9a-f]*:   ea 05 23 95     pmax\.sh r5,r5,r5
11998 + *[0-9a-f]*:   e8 04 23 94     pmax\.sh r4,r4,r4
11999 + *[0-9a-f]*:   fc 0e 23 9e     pmax\.sh lr,lr,lr
12000 + *[0-9a-f]*:   ec 0c 23 9e     pmax\.sh lr,r6,r12
12001 + *[0-9a-f]*:   fe 05 23 92     pmax\.sh r2,pc,r5
12002 + *[0-9a-f]*:   e4 07 23 9f     pmax\.sh pc,r2,r7
12003 +
12004 +[0-9a-f]* <pmin_ub>:
12005 + *[0-9a-f]*:   fe 0f 23 af     pmin\.ub pc,pc,pc
12006 + *[0-9a-f]*:   f8 0c 23 ac     pmin\.ub r12,r12,r12
12007 + *[0-9a-f]*:   ea 05 23 a5     pmin\.ub r5,r5,r5
12008 + *[0-9a-f]*:   e8 04 23 a4     pmin\.ub r4,r4,r4
12009 + *[0-9a-f]*:   fc 0e 23 ae     pmin\.ub lr,lr,lr
12010 + *[0-9a-f]*:   e2 05 23 a8     pmin\.ub r8,r1,r5
12011 + *[0-9a-f]*:   f0 03 23 a1     pmin\.ub r1,r8,r3
12012 + *[0-9a-f]*:   e4 07 23 a0     pmin\.ub r0,r2,r7
12013 +
12014 +[0-9a-f]* <pmin_sh>:
12015 + *[0-9a-f]*:   fe 0f 23 bf     pmin\.sh pc,pc,pc
12016 + *[0-9a-f]*:   f8 0c 23 bc     pmin\.sh r12,r12,r12
12017 + *[0-9a-f]*:   ea 05 23 b5     pmin\.sh r5,r5,r5
12018 + *[0-9a-f]*:   e8 04 23 b4     pmin\.sh r4,r4,r4
12019 + *[0-9a-f]*:   fc 0e 23 be     pmin\.sh lr,lr,lr
12020 + *[0-9a-f]*:   e8 0a 23 b8     pmin\.sh r8,r4,r10
12021 + *[0-9a-f]*:   f4 0c 23 be     pmin\.sh lr,r10,r12
12022 + *[0-9a-f]*:   ec 02 23 b2     pmin\.sh r2,r6,r2
12023 +
12024 +[0-9a-f]* <pavg_ub>:
12025 + *[0-9a-f]*:   fe 0f 23 cf     pavg\.ub pc,pc,pc
12026 + *[0-9a-f]*:   f8 0c 23 cc     pavg\.ub r12,r12,r12
12027 + *[0-9a-f]*:   ea 05 23 c5     pavg\.ub r5,r5,r5
12028 + *[0-9a-f]*:   e8 04 23 c4     pavg\.ub r4,r4,r4
12029 + *[0-9a-f]*:   fc 0e 23 ce     pavg\.ub lr,lr,lr
12030 + *[0-9a-f]*:   e2 06 23 c0     pavg\.ub r0,r1,r6
12031 + *[0-9a-f]*:   e6 06 23 c8     pavg\.ub r8,r3,r6
12032 + *[0-9a-f]*:   f8 0a 23 cf     pavg\.ub pc,r12,r10
12033 +
12034 +[0-9a-f]* <pavg_sh>:
12035 + *[0-9a-f]*:   fe 0f 23 df     pavg\.sh pc,pc,pc
12036 + *[0-9a-f]*:   f8 0c 23 dc     pavg\.sh r12,r12,r12
12037 + *[0-9a-f]*:   ea 05 23 d5     pavg\.sh r5,r5,r5
12038 + *[0-9a-f]*:   e8 04 23 d4     pavg\.sh r4,r4,r4
12039 + *[0-9a-f]*:   fc 0e 23 de     pavg\.sh lr,lr,lr
12040 + *[0-9a-f]*:   fe 0d 23 d9     pavg\.sh r9,pc,sp
12041 + *[0-9a-f]*:   fa 03 23 df     pavg\.sh pc,sp,r3
12042 + *[0-9a-f]*:   e2 09 23 d6     pavg\.sh r6,r1,r9
12043 +
12044 +[0-9a-f]* <pabs_sb>:
12045 + *[0-9a-f]*:   e0 0f 23 ef     pabs\.sb pc,pc
12046 + *[0-9a-f]*:   e0 0c 23 ec     pabs\.sb r12,r12
12047 + *[0-9a-f]*:   e0 05 23 e5     pabs\.sb r5,r5
12048 + *[0-9a-f]*:   e0 04 23 e4     pabs\.sb r4,r4
12049 + *[0-9a-f]*:   e0 0e 23 ee     pabs\.sb lr,lr
12050 + *[0-9a-f]*:   e0 06 23 eb     pabs\.sb r11,r6
12051 + *[0-9a-f]*:   e0 09 23 ee     pabs\.sb lr,r9
12052 + *[0-9a-f]*:   e0 07 23 ed     pabs\.sb sp,r7
12053 +
12054 +[0-9a-f]* <pabs_sh>:
12055 + *[0-9a-f]*:   e0 0f 23 ff     pabs\.sh pc,pc
12056 + *[0-9a-f]*:   e0 0c 23 fc     pabs\.sh r12,r12
12057 + *[0-9a-f]*:   e0 05 23 f5     pabs\.sh r5,r5
12058 + *[0-9a-f]*:   e0 04 23 f4     pabs\.sh r4,r4
12059 + *[0-9a-f]*:   e0 0e 23 fe     pabs\.sh lr,lr
12060 + *[0-9a-f]*:   e0 03 23 ff     pabs\.sh pc,r3
12061 + *[0-9a-f]*:   e0 07 23 f5     pabs\.sh r5,r7
12062 + *[0-9a-f]*:   e0 00 23 f4     pabs\.sh r4,r0
12063 +
12064 +[0-9a-f]* <psad>:
12065 + *[0-9a-f]*:   fe 0f 24 0f     psad pc,pc,pc
12066 + *[0-9a-f]*:   f8 0c 24 0c     psad r12,r12,r12
12067 + *[0-9a-f]*:   ea 05 24 05     psad r5,r5,r5
12068 + *[0-9a-f]*:   e8 04 24 04     psad r4,r4,r4
12069 + *[0-9a-f]*:   fc 0e 24 0e     psad lr,lr,lr
12070 + *[0-9a-f]*:   f6 0b 24 09     psad r9,r11,r11
12071 + *[0-9a-f]*:   e8 0d 24 0e     psad lr,r4,sp
12072 + *[0-9a-f]*:   e8 05 24 0e     psad lr,r4,r5
12073 +
12074 +[0-9a-f]* <pasr_b>:
12075 + *[0-9a-f]*:   fe 00 24 1f     pasr\.b pc,pc,0x0
12076 + *[0-9a-f]*:   f8 07 24 1c     pasr\.b r12,r12,0x7
12077 + *[0-9a-f]*:   ea 04 24 15     pasr\.b r5,r5,0x4
12078 + *[0-9a-f]*:   e8 03 24 14     pasr\.b r4,r4,0x3
12079 + *[0-9a-f]*:   fc 01 24 1e     pasr\.b lr,lr,0x1
12080 + *[0-9a-f]*:   ee 01 24 1f     pasr\.b pc,r7,0x1
12081 + *[0-9a-f]*:   fc 06 24 1d     pasr\.b sp,lr,0x6
12082 + *[0-9a-f]*:   e6 02 24 1d     pasr\.b sp,r3,0x2
12083 +
12084 +[0-9a-f]* <plsl_b>:
12085 + *[0-9a-f]*:   fe 00 24 2f     plsl\.b pc,pc,0x0
12086 + *[0-9a-f]*:   f8 07 24 2c     plsl\.b r12,r12,0x7
12087 + *[0-9a-f]*:   ea 04 24 25     plsl\.b r5,r5,0x4
12088 + *[0-9a-f]*:   e8 03 24 24     plsl\.b r4,r4,0x3
12089 + *[0-9a-f]*:   fc 01 24 2e     plsl\.b lr,lr,0x1
12090 + *[0-9a-f]*:   f6 04 24 22     plsl\.b r2,r11,0x4
12091 + *[0-9a-f]*:   ea 07 24 28     plsl\.b r8,r5,0x7
12092 + *[0-9a-f]*:   e0 02 24 2f     plsl\.b pc,r0,0x2
12093 +
12094 +[0-9a-f]* <plsr_b>:
12095 + *[0-9a-f]*:   fe 00 24 3f     plsr\.b pc,pc,0x0
12096 + *[0-9a-f]*:   f8 07 24 3c     plsr\.b r12,r12,0x7
12097 + *[0-9a-f]*:   ea 04 24 35     plsr\.b r5,r5,0x4
12098 + *[0-9a-f]*:   e8 03 24 34     plsr\.b r4,r4,0x3
12099 + *[0-9a-f]*:   fc 01 24 3e     plsr\.b lr,lr,0x1
12100 + *[0-9a-f]*:   e2 02 24 3c     plsr\.b r12,r1,0x2
12101 + *[0-9a-f]*:   fe 07 24 36     plsr\.b r6,pc,0x7
12102 + *[0-9a-f]*:   f6 02 24 3c     plsr\.b r12,r11,0x2
12103 +
12104 +[0-9a-f]* <pasr_h>:
12105 + *[0-9a-f]*:   fe 00 24 4f     pasr\.h pc,pc,0x0
12106 + *[0-9a-f]*:   f8 0f 24 4c     pasr\.h r12,r12,0xf
12107 + *[0-9a-f]*:   ea 08 24 45     pasr\.h r5,r5,0x8
12108 + *[0-9a-f]*:   e8 07 24 44     pasr\.h r4,r4,0x7
12109 + *[0-9a-f]*:   fc 01 24 4e     pasr\.h lr,lr,0x1
12110 + *[0-9a-f]*:   f6 0a 24 40     pasr\.h r0,r11,0xa
12111 + *[0-9a-f]*:   ec 08 24 44     pasr\.h r4,r6,0x8
12112 + *[0-9a-f]*:   e4 04 24 46     pasr\.h r6,r2,0x4
12113 +
12114 +[0-9a-f]* <plsl_h>:
12115 + *[0-9a-f]*:   fe 00 24 5f     plsl\.h pc,pc,0x0
12116 + *[0-9a-f]*:   f8 0f 24 5c     plsl\.h r12,r12,0xf
12117 + *[0-9a-f]*:   ea 08 24 55     plsl\.h r5,r5,0x8
12118 + *[0-9a-f]*:   e8 07 24 54     plsl\.h r4,r4,0x7
12119 + *[0-9a-f]*:   fc 01 24 5e     plsl\.h lr,lr,0x1
12120 + *[0-9a-f]*:   f4 09 24 55     plsl\.h r5,r10,0x9
12121 + *[0-9a-f]*:   fc 08 24 5d     plsl\.h sp,lr,0x8
12122 + *[0-9a-f]*:   fc 07 24 50     plsl\.h r0,lr,0x7
12123 +
12124 +[0-9a-f]* <plsr_h>:
12125 + *[0-9a-f]*:   fe 00 24 6f     plsr\.h pc,pc,0x0
12126 + *[0-9a-f]*:   f8 0f 24 6c     plsr\.h r12,r12,0xf
12127 + *[0-9a-f]*:   ea 08 24 65     plsr\.h r5,r5,0x8
12128 + *[0-9a-f]*:   e8 07 24 64     plsr\.h r4,r4,0x7
12129 + *[0-9a-f]*:   fc 01 24 6e     plsr\.h lr,lr,0x1
12130 + *[0-9a-f]*:   e0 0f 24 6b     plsr\.h r11,r0,0xf
12131 + *[0-9a-f]*:   e6 03 24 6e     plsr\.h lr,r3,0x3
12132 + *[0-9a-f]*:   fc 0a 24 68     plsr\.h r8,lr,0xa
12133 +
12134 +[0-9a-f]* <packw_sh>:
12135 + *[0-9a-f]*:   fe 0f 24 7f     packw\.sh pc,pc,pc
12136 + *[0-9a-f]*:   f8 0c 24 7c     packw\.sh r12,r12,r12
12137 + *[0-9a-f]*:   ea 05 24 75     packw\.sh r5,r5,r5
12138 + *[0-9a-f]*:   e8 04 24 74     packw\.sh r4,r4,r4
12139 + *[0-9a-f]*:   fc 0e 24 7e     packw\.sh lr,lr,lr
12140 + *[0-9a-f]*:   f6 0a 24 7d     packw\.sh sp,r11,r10
12141 + *[0-9a-f]*:   e4 0c 24 78     packw\.sh r8,r2,r12
12142 + *[0-9a-f]*:   e2 05 24 78     packw\.sh r8,r1,r5
12143 +
12144 +[0-9a-f]* <punpckub_h>:
12145 + *[0-9a-f]*:   fe 00 24 8f     punpckub\.h pc,pc:b
12146 + *[0-9a-f]*:   f8 00 24 9c     punpckub\.h r12,r12:t
12147 + *[0-9a-f]*:   ea 00 24 95     punpckub\.h r5,r5:t
12148 + *[0-9a-f]*:   e8 00 24 84     punpckub\.h r4,r4:b
12149 + *[0-9a-f]*:   fc 00 24 9e     punpckub\.h lr,lr:t
12150 + *[0-9a-f]*:   e2 00 24 96     punpckub\.h r6,r1:t
12151 + *[0-9a-f]*:   ea 00 24 8e     punpckub\.h lr,r5:b
12152 + *[0-9a-f]*:   e4 00 24 9e     punpckub\.h lr,r2:t
12153 +
12154 +[0-9a-f]* <punpcksb_h>:
12155 + *[0-9a-f]*:   fe 00 24 af     punpcksb\.h pc,pc:b
12156 + *[0-9a-f]*:   f8 00 24 bc     punpcksb\.h r12,r12:t
12157 + *[0-9a-f]*:   ea 00 24 b5     punpcksb\.h r5,r5:t
12158 + *[0-9a-f]*:   e8 00 24 a4     punpcksb\.h r4,r4:b
12159 + *[0-9a-f]*:   fc 00 24 be     punpcksb\.h lr,lr:t
12160 + *[0-9a-f]*:   ee 00 24 b4     punpcksb\.h r4,r7:t
12161 + *[0-9a-f]*:   fc 00 24 a6     punpcksb\.h r6,lr:b
12162 + *[0-9a-f]*:   f8 00 24 bc     punpcksb\.h r12,r12:t
12163 +
12164 +[0-9a-f]* <packsh_ub>:
12165 + *[0-9a-f]*:   fe 0f 24 cf     packsh\.ub pc,pc,pc
12166 + *[0-9a-f]*:   f8 0c 24 cc     packsh\.ub r12,r12,r12
12167 + *[0-9a-f]*:   ea 05 24 c5     packsh\.ub r5,r5,r5
12168 + *[0-9a-f]*:   e8 04 24 c4     packsh\.ub r4,r4,r4
12169 + *[0-9a-f]*:   fc 0e 24 ce     packsh\.ub lr,lr,lr
12170 + *[0-9a-f]*:   ec 03 24 c3     packsh\.ub r3,r6,r3
12171 + *[0-9a-f]*:   e0 03 24 c8     packsh\.ub r8,r0,r3
12172 + *[0-9a-f]*:   e6 0e 24 c9     packsh\.ub r9,r3,lr
12173 +
12174 +[0-9a-f]* <packsh_sb>:
12175 + *[0-9a-f]*:   fe 0f 24 df     packsh\.sb pc,pc,pc
12176 + *[0-9a-f]*:   f8 0c 24 dc     packsh\.sb r12,r12,r12
12177 + *[0-9a-f]*:   ea 05 24 d5     packsh\.sb r5,r5,r5
12178 + *[0-9a-f]*:   e8 04 24 d4     packsh\.sb r4,r4,r4
12179 + *[0-9a-f]*:   fc 0e 24 de     packsh\.sb lr,lr,lr
12180 + *[0-9a-f]*:   f0 01 24 d6     packsh\.sb r6,r8,r1
12181 + *[0-9a-f]*:   f2 08 24 de     packsh\.sb lr,r9,r8
12182 + *[0-9a-f]*:   ec 06 24 dd     packsh\.sb sp,r6,r6
12183 +
12184 +[0-9a-f]* <andl>:
12185 + *[0-9a-f]*:   e0 1f 00 00     andl pc,0x0
12186 + *[0-9a-f]*:   e0 1c ff ff     andl r12,0xffff
12187 + *[0-9a-f]*:   e0 15 80 00     andl r5,0x8000
12188 + *[0-9a-f]*:   e0 14 7f ff     andl r4,0x7fff
12189 + *[0-9a-f]*:   e0 1e 00 01     andl lr,0x1
12190 + *[0-9a-f]*:   e0 1f 5a 58     andl pc,0x5a58
12191 + *[0-9a-f]*:   e0 18 b8 9e     andl r8,0xb89e
12192 + *[0-9a-f]*:   e0 17 35 97     andl r7,0x3597
12193 +
12194 +[0-9a-f]* <andl_coh>:
12195 + *[0-9a-f]*:   e2 1f 00 00     andl pc,0x0,COH
12196 + *[0-9a-f]*:   e2 1c ff ff     andl r12,0xffff,COH
12197 + *[0-9a-f]*:   e2 15 80 00     andl r5,0x8000,COH
12198 + *[0-9a-f]*:   e2 14 7f ff     andl r4,0x7fff,COH
12199 + *[0-9a-f]*:   e2 1e 00 01     andl lr,0x1,COH
12200 + *[0-9a-f]*:   e2 16 58 e1     andl r6,0x58e1,COH
12201 + *[0-9a-f]*:   e2 10 9e cd     andl r0,0x9ecd,COH
12202 + *[0-9a-f]*:   e2 14 bd c4     andl r4,0xbdc4,COH
12203 +
12204 +[0-9a-f]* <andh>:
12205 + *[0-9a-f]*:   e4 1f 00 00     andh pc,0x0
12206 + *[0-9a-f]*:   e4 1c ff ff     andh r12,0xffff
12207 + *[0-9a-f]*:   e4 15 80 00     andh r5,0x8000
12208 + *[0-9a-f]*:   e4 14 7f ff     andh r4,0x7fff
12209 + *[0-9a-f]*:   e4 1e 00 01     andh lr,0x1
12210 + *[0-9a-f]*:   e4 1c cc 58     andh r12,0xcc58
12211 + *[0-9a-f]*:   e4 13 21 e3     andh r3,0x21e3
12212 + *[0-9a-f]*:   e4 12 a7 eb     andh r2,0xa7eb
12213 +
12214 +[0-9a-f]* <andh_coh>:
12215 + *[0-9a-f]*:   e6 1f 00 00     andh pc,0x0,COH
12216 + *[0-9a-f]*:   e6 1c ff ff     andh r12,0xffff,COH
12217 + *[0-9a-f]*:   e6 15 80 00     andh r5,0x8000,COH
12218 + *[0-9a-f]*:   e6 14 7f ff     andh r4,0x7fff,COH
12219 + *[0-9a-f]*:   e6 1e 00 01     andh lr,0x1,COH
12220 + *[0-9a-f]*:   e6 1b 86 0d     andh r11,0x860d,COH
12221 + *[0-9a-f]*:   e6 18 ce f6     andh r8,0xcef6,COH
12222 + *[0-9a-f]*:   e6 1a 5c 83     andh r10,0x5c83,COH
12223 +
12224 +[0-9a-f]* <orl>:
12225 + *[0-9a-f]*:   e8 1f 00 00     orl pc,0x0
12226 + *[0-9a-f]*:   e8 1c ff ff     orl r12,0xffff
12227 + *[0-9a-f]*:   e8 15 80 00     orl r5,0x8000
12228 + *[0-9a-f]*:   e8 14 7f ff     orl r4,0x7fff
12229 + *[0-9a-f]*:   e8 1e 00 01     orl lr,0x1
12230 + *[0-9a-f]*:   e8 1d 41 7e     orl sp,0x417e
12231 + *[0-9a-f]*:   e8 10 52 bd     orl r0,0x52bd
12232 + *[0-9a-f]*:   e8 1f ac 47     orl pc,0xac47
12233 +
12234 +[0-9a-f]* <orh>:
12235 + *[0-9a-f]*:   ea 1f 00 00     orh pc,0x0
12236 + *[0-9a-f]*:   ea 1c ff ff     orh r12,0xffff
12237 + *[0-9a-f]*:   ea 15 80 00     orh r5,0x8000
12238 + *[0-9a-f]*:   ea 14 7f ff     orh r4,0x7fff
12239 + *[0-9a-f]*:   ea 1e 00 01     orh lr,0x1
12240 + *[0-9a-f]*:   ea 18 6e 7d     orh r8,0x6e7d
12241 + *[0-9a-f]*:   ea 1c 77 1c     orh r12,0x771c
12242 + *[0-9a-f]*:   ea 11 ea 1a     orh r1,0xea1a
12243 +
12244 +[0-9a-f]* <eorl>:
12245 + *[0-9a-f]*:   ec 1f 00 00     eorl pc,0x0
12246 + *[0-9a-f]*:   ec 1c ff ff     eorl r12,0xffff
12247 + *[0-9a-f]*:   ec 15 80 00     eorl r5,0x8000
12248 + *[0-9a-f]*:   ec 14 7f ff     eorl r4,0x7fff
12249 + *[0-9a-f]*:   ec 1e 00 01     eorl lr,0x1
12250 + *[0-9a-f]*:   ec 14 c7 b9     eorl r4,0xc7b9
12251 + *[0-9a-f]*:   ec 16 fb dd     eorl r6,0xfbdd
12252 + *[0-9a-f]*:   ec 11 51 b1     eorl r1,0x51b1
12253 +
12254 +[0-9a-f]* <eorh>:
12255 + *[0-9a-f]*:   ee 1f 00 00     eorh pc,0x0
12256 + *[0-9a-f]*:   ee 1c ff ff     eorh r12,0xffff
12257 + *[0-9a-f]*:   ee 15 80 00     eorh r5,0x8000
12258 + *[0-9a-f]*:   ee 14 7f ff     eorh r4,0x7fff
12259 + *[0-9a-f]*:   ee 1e 00 01     eorh lr,0x1
12260 + *[0-9a-f]*:   ee 10 2d d4     eorh r0,0x2dd4
12261 + *[0-9a-f]*:   ee 1a 94 b5     eorh r10,0x94b5
12262 + *[0-9a-f]*:   ee 19 df 2a     eorh r9,0xdf2a
12263 +
12264 +[0-9a-f]* <mcall>:
12265 + *[0-9a-f]*:   f0 1f 00 00     mcall [0-9a-f]* <.*>
12266 + *[0-9a-f]*:   f0 1c ff ff     mcall r12\[-4\]
12267 + *[0-9a-f]*:   f0 15 80 00     mcall r5\[-131072\]
12268 + *[0-9a-f]*:   f0 14 7f ff     mcall r4\[131068\]
12269 + *[0-9a-f]*:   f0 1e 00 01     mcall lr\[4\]
12270 + *[0-9a-f]*:   f0 1d 3b bf     mcall sp\[61180\]
12271 + *[0-9a-f]*:   f0 14 dd d2     mcall r4\[-35000\]
12272 + *[0-9a-f]*:   f0 10 09 b1     mcall r0\[9924\]
12273 +
12274 +[0-9a-f]* <pref>:
12275 + *[0-9a-f]*:   f2 1f 00 00     pref pc\[0\]
12276 + *[0-9a-f]*:   f2 1c ff ff     pref r12\[-1\]
12277 + *[0-9a-f]*:   f2 15 80 00     pref r5\[-32768\]
12278 + *[0-9a-f]*:   f2 14 7f ff     pref r4\[32767\]
12279 + *[0-9a-f]*:   f2 1e 00 01     pref lr\[1\]
12280 + *[0-9a-f]*:   f2 17 1e 44     pref r7\[7748\]
12281 + *[0-9a-f]*:   f2 17 e1 ed     pref r7\[-7699\]
12282 + *[0-9a-f]*:   f2 12 9a dc     pref r2\[-25892\]
12283 +
12284 +[0-9a-f]* <cache>:
12285 + *[0-9a-f]*:   f4 1f 00 00     cache pc\[0\],0x0
12286 + *[0-9a-f]*:   f4 1c ff ff     cache r12\[-1\],0x1f
12287 + *[0-9a-f]*:   f4 15 84 00     cache r5\[-1024\],0x10
12288 + *[0-9a-f]*:   f4 14 7b ff     cache r4\[1023\],0xf
12289 + *[0-9a-f]*:   f4 1e 08 01     cache lr\[1\],0x1
12290 + *[0-9a-f]*:   f4 13 8c 3c     cache r3\[-964\],0x11
12291 + *[0-9a-f]*:   f4 14 b6 89     cache r4\[-375\],0x16
12292 + *[0-9a-f]*:   f4 13 8c 88     cache r3\[-888\],0x11
12293 +
12294 +[0-9a-f]* <sub4>:
12295 + *[0-9a-f]*:   20 0f           sub pc,0
12296 + *[0-9a-f]*:   2f fc           sub r12,-1
12297 + *[0-9a-f]*:   f0 25 00 00     sub r5,-1048576
12298 + *[0-9a-f]*:   ee 34 ff ff     sub r4,1048575
12299 + *[0-9a-f]*:   20 1e           sub lr,1
12300 + *[0-9a-f]*:   f6 22 8d 6c     sub r2,-619156
12301 + *[0-9a-f]*:   e6 3e 0a cd     sub lr,461517
12302 + *[0-9a-f]*:   fc 38 2d 25     sub r8,-185051
12303 +
12304 +[0-9a-f]* <cp3>:
12305 + *[0-9a-f]*:   58 0f           cp.w pc,0
12306 + *[0-9a-f]*:   5b fc           cp.w r12,-1
12307 + *[0-9a-f]*:   f0 45 00 00     cp.w r5,-1048576
12308 + *[0-9a-f]*:   ee 54 ff ff     cp.w r4,1048575
12309 + *[0-9a-f]*:   58 1e           cp.w lr,1
12310 + *[0-9a-f]*:   e0 51 e4 ae     cp.w r1,124078
12311 + *[0-9a-f]*:   fa 40 37 e3     cp.w r0,-378909
12312 + *[0-9a-f]*:   fc 44 4a 14     cp.w r4,-243180
12313 +
12314 +[0-9a-f]* <mov2>:
12315 + *[0-9a-f]*:   30 0f           mov pc,0
12316 + *[0-9a-f]*:   3f fc           mov r12,-1
12317 + *[0-9a-f]*:   f0 65 00 00     mov r5,-1048576
12318 + *[0-9a-f]*:   ee 74 ff ff     mov r4,1048575
12319 + *[0-9a-f]*:   30 1e           mov lr,1
12320 + *[0-9a-f]*:   fa 75 29 a3     mov r5,-317021
12321 + *[0-9a-f]*:   f4 6d 91 94     mov sp,-749164
12322 + *[0-9a-f]*:   ee 65 58 93     mov r5,940179
12323 +
12324 +[0-9a-f]* <brc2>:
12325 + *[0-9a-f]*:   c0 00           breq [0-9a-f]* <.*>
12326 + *[0-9a-f]*:   fe 9f ff ff     bral [0-9a-f]* <.*>
12327 + *[0-9a-f]*:   f0 88 00 00     brls [0-9a-f]* <.*>
12328 + *[0-9a-f]*:   ee 97 ff ff     brpl [0-9a-f]* <.*>
12329 + *[0-9a-f]*:   c0 11           brne [0-9a-f]* <.*>
12330 + *[0-9a-f]*:   f2 8b 4a 4d     brhi [0-9a-f]* <.*>
12331 + *[0-9a-f]*:   ea 8e 14 cc     brqs [0-9a-f]* <.*>
12332 + *[0-9a-f]*:   fa 98 98 33     brls [0-9a-f]* <.*>
12333 +
12334 +[0-9a-f]* <rcall2>:
12335 + *[0-9a-f]*:   c0 0c           rcall [0-9a-f]* <.*>
12336 + *[0-9a-f]*:   cf ff           rcall [0-9a-f]* <.*>
12337 + *[0-9a-f]*:   f0 a0 00 00     rcall [0-9a-f]* <.*>
12338 + *[0-9a-f]*:   ee b0 ff ff     rcall [0-9a-f]* <.*>
12339 + *[0-9a-f]*:   c0 1c           rcall [0-9a-f]* <.*>
12340 + *[0-9a-f]*:   e2 b0 ca 5a     rcall [0-9a-f]* <.*>
12341 + *[0-9a-f]*:   e8 a0 47 52     rcall [0-9a-f]* <.*>
12342 + *[0-9a-f]*:   fe b0 fd ef     rcall [0-9a-f]* <.*>
12343 +
12344 +[0-9a-f]* <sub5>:
12345 + *[0-9a-f]*:   fe cf 00 00     sub pc,pc,0
12346 + *[0-9a-f]*:   f8 cc ff ff     sub r12,r12,-1
12347 + *[0-9a-f]*:   ea c5 80 00     sub r5,r5,-32768
12348 + *[0-9a-f]*:   e8 c4 7f ff     sub r4,r4,32767
12349 + *[0-9a-f]*:   fc ce 00 01     sub lr,lr,1
12350 + *[0-9a-f]*:   fe cf ce 38     sub pc,pc,-12744
12351 + *[0-9a-f]*:   ee c7 95 1b     sub r7,r7,-27365
12352 + *[0-9a-f]*:   f2 c2 bc 32     sub r2,r9,-17358
12353 +
12354 +[0-9a-f]* <satsub_w2>:
12355 + *[0-9a-f]*:   fe df 00 00     satsub\.w pc,pc,0
12356 + *[0-9a-f]*:   f8 dc ff ff     satsub\.w r12,r12,-1
12357 + *[0-9a-f]*:   ea d5 80 00     satsub\.w r5,r5,-32768
12358 + *[0-9a-f]*:   e8 d4 7f ff     satsub\.w r4,r4,32767
12359 + *[0-9a-f]*:   fc de 00 01     satsub\.w lr,lr,1
12360 + *[0-9a-f]*:   fc d2 f8 29     satsub\.w r2,lr,-2007
12361 + *[0-9a-f]*:   f8 d7 fc f0     satsub\.w r7,r12,-784
12362 + *[0-9a-f]*:   ee d4 5a 8c     satsub\.w r4,r7,23180
12363 +
12364 +[0-9a-f]* <ld_d4>:
12365 + *[0-9a-f]*:   fe e0 00 00     ld\.d r0,pc\[0\]
12366 + *[0-9a-f]*:   f8 ee ff ff     ld\.d lr,r12\[-1\]
12367 + *[0-9a-f]*:   ea e8 80 00     ld\.d r8,r5\[-32768\]
12368 + *[0-9a-f]*:   e8 e6 7f ff     ld\.d r6,r4\[32767\]
12369 + *[0-9a-f]*:   fc e2 00 01     ld\.d r2,lr\[1\]
12370 + *[0-9a-f]*:   f6 ee 39 c0     ld\.d lr,r11\[14784\]
12371 + *[0-9a-f]*:   f2 e6 b6 27     ld\.d r6,r9\[-18905\]
12372 + *[0-9a-f]*:   e6 e2 e7 2d     ld\.d r2,r3\[-6355\]
12373 +
12374 +[0-9a-f]* <ld_w4>:
12375 + *[0-9a-f]*:   7e 0f           ld\.w pc,pc\[0x0\]
12376 + *[0-9a-f]*:   f8 fc ff ff     ld\.w r12,r12\[-1\]
12377 + *[0-9a-f]*:   ea f5 80 00     ld\.w r5,r5\[-32768\]
12378 + *[0-9a-f]*:   e8 f4 7f ff     ld\.w r4,r4\[32767\]
12379 + *[0-9a-f]*:   fc fe 00 01     ld\.w lr,lr\[1\]
12380 + *[0-9a-f]*:   f8 f0 a9 8b     ld\.w r0,r12\[-22133\]
12381 + *[0-9a-f]*:   fe fd af d7     ld\.w sp,pc\[-20521\]
12382 + *[0-9a-f]*:   d7 03           nop
12383 +
12384 +[0-9a-f]* <ld_sh4>:
12385 + *[0-9a-f]*:   9e 0f           ld\.sh pc,pc\[0x0\]
12386 + *[0-9a-f]*:   f9 0c ff ff     ld\.sh r12,r12\[-1\]
12387 + *[0-9a-f]*:   eb 05 80 00     ld\.sh r5,r5\[-32768\]
12388 + *[0-9a-f]*:   e9 04 7f ff     ld\.sh r4,r4\[32767\]
12389 + *[0-9a-f]*:   fd 0e 00 01     ld\.sh lr,lr\[1\]
12390 + *[0-9a-f]*:   f5 06 78 d2     ld\.sh r6,r10\[30930\]
12391 + *[0-9a-f]*:   f5 06 55 d5     ld\.sh r6,r10\[21973\]
12392 + *[0-9a-f]*:   d7 03           nop
12393 +
12394 +[0-9a-f]* <ld_uh4>:
12395 + *[0-9a-f]*:   9e 8f           ld\.uh pc,pc\[0x0\]
12396 + *[0-9a-f]*:   f9 1c ff ff     ld\.uh r12,r12\[-1\]
12397 + *[0-9a-f]*:   eb 15 80 00     ld\.uh r5,r5\[-32768\]
12398 + *[0-9a-f]*:   e9 14 7f ff     ld\.uh r4,r4\[32767\]
12399 + *[0-9a-f]*:   fd 1e 00 01     ld\.uh lr,lr\[1\]
12400 + *[0-9a-f]*:   f3 11 cb d6     ld\.uh r1,r9\[-13354\]
12401 + *[0-9a-f]*:   f7 1e 53 59     ld\.uh lr,r11\[21337\]
12402 + *[0-9a-f]*:   d7 03           nop
12403 +
12404 +[0-9a-f]* <ld_sb1>:
12405 + *[0-9a-f]*:   ff 2f 00 00     ld\.sb pc,pc\[0\]
12406 + *[0-9a-f]*:   f9 2c ff ff     ld\.sb r12,r12\[-1\]
12407 + *[0-9a-f]*:   eb 25 80 00     ld\.sb r5,r5\[-32768\]
12408 + *[0-9a-f]*:   e9 24 7f ff     ld\.sb r4,r4\[32767\]
12409 + *[0-9a-f]*:   fd 2e 00 01     ld\.sb lr,lr\[1\]
12410 + *[0-9a-f]*:   fb 27 90 09     ld\.sb r7,sp\[-28663\]
12411 + *[0-9a-f]*:   e3 22 e9 09     ld\.sb r2,r1\[-5879\]
12412 + *[0-9a-f]*:   e7 2c 49 2e     ld\.sb r12,r3\[18734\]
12413 +
12414 +[0-9a-f]* <ld_ub4>:
12415 + *[0-9a-f]*:   1f 8f           ld\.ub pc,pc\[0x0\]
12416 + *[0-9a-f]*:   f9 3c ff ff     ld\.ub r12,r12\[-1\]
12417 + *[0-9a-f]*:   eb 35 80 00     ld\.ub r5,r5\[-32768\]
12418 + *[0-9a-f]*:   e9 34 7f ff     ld\.ub r4,r4\[32767\]
12419 + *[0-9a-f]*:   1d 9e           ld\.ub lr,lr\[0x1\]
12420 + *[0-9a-f]*:   e9 3f 20 55     ld\.ub pc,r4\[8277\]
12421 + *[0-9a-f]*:   f9 35 4a e4     ld\.ub r5,r12\[19172\]
12422 + *[0-9a-f]*:   fd 3a 66 eb     ld\.ub r10,lr\[26347\]
12423 +
12424 +[0-9a-f]* <st_d4>:
12425 + *[0-9a-f]*:   fe e1 00 00     st\.d pc\[0\],r0
12426 + *[0-9a-f]*:   f8 ef ff ff     st\.d r12\[-1\],lr
12427 + *[0-9a-f]*:   ea e9 80 00     st\.d r5\[-32768\],r8
12428 + *[0-9a-f]*:   e8 e7 7f ff     st\.d r4\[32767\],r6
12429 + *[0-9a-f]*:   fc e3 00 01     st\.d lr\[1\],r2
12430 + *[0-9a-f]*:   ea eb 33 90     st\.d r5\[13200\],r10
12431 + *[0-9a-f]*:   ea eb 24 88     st\.d r5\[9352\],r10
12432 + *[0-9a-f]*:   ea e5 7e 75     st\.d r5\[32373\],r4
12433 +
12434 +[0-9a-f]* <st_w4>:
12435 + *[0-9a-f]*:   9f 0f           st\.w pc\[0x0\],pc
12436 + *[0-9a-f]*:   f9 4c ff ff     st\.w r12\[-1\],r12
12437 + *[0-9a-f]*:   eb 45 80 00     st\.w r5\[-32768\],r5
12438 + *[0-9a-f]*:   e9 44 7f ff     st\.w r4\[32767\],r4
12439 + *[0-9a-f]*:   fd 4e 00 01     st\.w lr\[1\],lr
12440 + *[0-9a-f]*:   fb 47 17 f8     st\.w sp\[6136\],r7
12441 + *[0-9a-f]*:   ed 4c 69 cf     st\.w r6\[27087\],r12
12442 + *[0-9a-f]*:   d7 03           nop
12443 +
12444 +[0-9a-f]* <st_h4>:
12445 + *[0-9a-f]*:   be 0f           st\.h pc\[0x0\],pc
12446 + *[0-9a-f]*:   f9 5c ff ff     st\.h r12\[-1\],r12
12447 + *[0-9a-f]*:   eb 55 80 00     st\.h r5\[-32768\],r5
12448 + *[0-9a-f]*:   e9 54 7f ff     st\.h r4\[32767\],r4
12449 + *[0-9a-f]*:   fd 5e 00 01     st\.h lr\[1\],lr
12450 + *[0-9a-f]*:   e9 57 d9 16     st\.h r4\[-9962\],r7
12451 + *[0-9a-f]*:   f3 53 c0 86     st\.h r9\[-16250\],r3
12452 + *[0-9a-f]*:   d7 03           nop
12453 +
12454 +[0-9a-f]* <st_b4>:
12455 + *[0-9a-f]*:   be 8f           st\.b pc\[0x0\],pc
12456 + *[0-9a-f]*:   f9 6c ff ff     st\.b r12\[-1\],r12
12457 + *[0-9a-f]*:   eb 65 80 00     st\.b r5\[-32768\],r5
12458 + *[0-9a-f]*:   e9 64 7f ff     st\.b r4\[32767\],r4
12459 + *[0-9a-f]*:   bc 9e           st\.b lr\[0x1\],lr
12460 + *[0-9a-f]*:   f9 66 75 96     st\.b r12\[30102\],r6
12461 + *[0-9a-f]*:   eb 61 71 31     st\.b r5\[28977\],r1
12462 + *[0-9a-f]*:   e1 61 15 5e     st\.b r0\[5470\],r1
12463 +
12464 +[0-9a-f]* <mfsr>:
12465 + *[0-9a-f]*:   e1 bf 00 00     mfsr pc,0x0
12466 + *[0-9a-f]*:   e1 bc 00 ff     mfsr r12,0x3fc
12467 + *[0-9a-f]*:   e1 b5 00 80     mfsr r5,0x200
12468 + *[0-9a-f]*:   e1 b4 00 7f     mfsr r4,0x1fc
12469 + *[0-9a-f]*:   e1 be 00 01     mfsr lr,0x4
12470 + *[0-9a-f]*:   e1 b2 00 ae     mfsr r2,0x2b8
12471 + *[0-9a-f]*:   e1 b4 00 41     mfsr r4,0x104
12472 + *[0-9a-f]*:   e1 ba 00 fe     mfsr r10,0x3f8
12473 +
12474 +[0-9a-f]* <mtsr>:
12475 + *[0-9a-f]*:   e3 bf 00 00     mtsr 0x0,pc
12476 + *[0-9a-f]*:   e3 bc 00 ff     mtsr 0x3fc,r12
12477 + *[0-9a-f]*:   e3 b5 00 80     mtsr 0x200,r5
12478 + *[0-9a-f]*:   e3 b4 00 7f     mtsr 0x1fc,r4
12479 + *[0-9a-f]*:   e3 be 00 01     mtsr 0x4,lr
12480 + *[0-9a-f]*:   e3 ba 00 38     mtsr 0xe0,r10
12481 + *[0-9a-f]*:   e3 bc 00 d1     mtsr 0x344,r12
12482 + *[0-9a-f]*:   e3 b9 00 4c     mtsr 0x130,r9
12483 +
12484 +[0-9a-f]* <mfdr>:
12485 + *[0-9a-f]*:   e5 bf 00 00     mfdr pc,0x0
12486 + *[0-9a-f]*:   e5 bc 00 ff     mfdr r12,0x3fc
12487 + *[0-9a-f]*:   e5 b5 00 80     mfdr r5,0x200
12488 + *[0-9a-f]*:   e5 b4 00 7f     mfdr r4,0x1fc
12489 + *[0-9a-f]*:   e5 be 00 01     mfdr lr,0x4
12490 + *[0-9a-f]*:   e5 b6 00 e9     mfdr r6,0x3a4
12491 + *[0-9a-f]*:   e5 b5 00 09     mfdr r5,0x24
12492 + *[0-9a-f]*:   e5 b9 00 4b     mfdr r9,0x12c
12493 +
12494 +[0-9a-f]* <mtdr>:
12495 + *[0-9a-f]*:   e7 bf 00 00     mtdr 0x0,pc
12496 + *[0-9a-f]*:   e7 bc 00 ff     mtdr 0x3fc,r12
12497 + *[0-9a-f]*:   e7 b5 00 80     mtdr 0x200,r5
12498 + *[0-9a-f]*:   e7 b4 00 7f     mtdr 0x1fc,r4
12499 + *[0-9a-f]*:   e7 be 00 01     mtdr 0x4,lr
12500 + *[0-9a-f]*:   e7 b8 00 2d     mtdr 0xb4,r8
12501 + *[0-9a-f]*:   e7 ba 00 b4     mtdr 0x2d0,r10
12502 + *[0-9a-f]*:   e7 be 00 66     mtdr 0x198,lr
12503 +
12504 +[0-9a-f]* <sleep>:
12505 + *[0-9a-f]*:   e9 b0 00 00     sleep 0x0
12506 + *[0-9a-f]*:   e9 b0 00 ff     sleep 0xff
12507 + *[0-9a-f]*:   e9 b0 00 80     sleep 0x80
12508 + *[0-9a-f]*:   e9 b0 00 7f     sleep 0x7f
12509 + *[0-9a-f]*:   e9 b0 00 01     sleep 0x1
12510 + *[0-9a-f]*:   e9 b0 00 fe     sleep 0xfe
12511 + *[0-9a-f]*:   e9 b0 00 0f     sleep 0xf
12512 + *[0-9a-f]*:   e9 b0 00 2b     sleep 0x2b
12513 +
12514 +[0-9a-f]* <sync>:
12515 + *[0-9a-f]*:   eb b0 00 00     sync 0x0
12516 + *[0-9a-f]*:   eb b0 00 ff     sync 0xff
12517 + *[0-9a-f]*:   eb b0 00 80     sync 0x80
12518 + *[0-9a-f]*:   eb b0 00 7f     sync 0x7f
12519 + *[0-9a-f]*:   eb b0 00 01     sync 0x1
12520 + *[0-9a-f]*:   eb b0 00 a6     sync 0xa6
12521 + *[0-9a-f]*:   eb b0 00 e6     sync 0xe6
12522 + *[0-9a-f]*:   eb b0 00 b4     sync 0xb4
12523 +
12524 +[0-9a-f]* <bld>:
12525 + *[0-9a-f]*:   ed bf 00 00     bld pc,0x0
12526 + *[0-9a-f]*:   ed bc 00 1f     bld r12,0x1f
12527 + *[0-9a-f]*:   ed b5 00 10     bld r5,0x10
12528 + *[0-9a-f]*:   ed b4 00 0f     bld r4,0xf
12529 + *[0-9a-f]*:   ed be 00 01     bld lr,0x1
12530 + *[0-9a-f]*:   ed b9 00 0f     bld r9,0xf
12531 + *[0-9a-f]*:   ed b0 00 04     bld r0,0x4
12532 + *[0-9a-f]*:   ed be 00 1a     bld lr,0x1a
12533 +
12534 +[0-9a-f]* <bst>:
12535 + *[0-9a-f]*:   ef bf 00 00     bst pc,0x0
12536 + *[0-9a-f]*:   ef bc 00 1f     bst r12,0x1f
12537 + *[0-9a-f]*:   ef b5 00 10     bst r5,0x10
12538 + *[0-9a-f]*:   ef b4 00 0f     bst r4,0xf
12539 + *[0-9a-f]*:   ef be 00 01     bst lr,0x1
12540 + *[0-9a-f]*:   ef ba 00 1c     bst r10,0x1c
12541 + *[0-9a-f]*:   ef b0 00 03     bst r0,0x3
12542 + *[0-9a-f]*:   ef bd 00 02     bst sp,0x2
12543 +
12544 +[0-9a-f]* <sats>:
12545 + *[0-9a-f]*:   f1 bf 00 00     sats pc,0x0
12546 + *[0-9a-f]*:   f1 bc 03 ff     sats r12>>0x1f,0x1f
12547 + *[0-9a-f]*:   f1 b5 02 10     sats r5>>0x10,0x10
12548 + *[0-9a-f]*:   f1 b4 01 ef     sats r4>>0xf,0xf
12549 + *[0-9a-f]*:   f1 be 00 21     sats lr>>0x1,0x1
12550 + *[0-9a-f]*:   f1 ba 02 63     sats r10>>0x3,0x13
12551 + *[0-9a-f]*:   f1 ba 03 42     sats r10>>0x2,0x1a
12552 + *[0-9a-f]*:   f1 b1 00 34     sats r1>>0x14,0x1
12553 +
12554 +[0-9a-f]* <satu>:
12555 + *[0-9a-f]*:   f1 bf 04 00     satu pc,0x0
12556 + *[0-9a-f]*:   f1 bc 07 ff     satu r12>>0x1f,0x1f
12557 + *[0-9a-f]*:   f1 b5 06 10     satu r5>>0x10,0x10
12558 + *[0-9a-f]*:   f1 b4 05 ef     satu r4>>0xf,0xf
12559 + *[0-9a-f]*:   f1 be 04 21     satu lr>>0x1,0x1
12560 + *[0-9a-f]*:   f1 bf 04 e5     satu pc>>0x5,0x7
12561 + *[0-9a-f]*:   f1 b7 04 a5     satu r7>>0x5,0x5
12562 + *[0-9a-f]*:   f1 b2 06 7a     satu r2>>0x1a,0x13
12563 +
12564 +[0-9a-f]* <satrnds>:
12565 + *[0-9a-f]*:   f3 bf 00 00     satrnds pc,0x0
12566 + *[0-9a-f]*:   f3 bc 03 ff     satrnds r12>>0x1f,0x1f
12567 + *[0-9a-f]*:   f3 b5 02 10     satrnds r5>>0x10,0x10
12568 + *[0-9a-f]*:   f3 b4 01 ef     satrnds r4>>0xf,0xf
12569 + *[0-9a-f]*:   f3 be 00 21     satrnds lr>>0x1,0x1
12570 + *[0-9a-f]*:   f3 b0 02 75     satrnds r0>>0x15,0x13
12571 + *[0-9a-f]*:   f3 bd 00 40     satrnds sp,0x2
12572 + *[0-9a-f]*:   f3 b7 03 a6     satrnds r7>>0x6,0x1d
12573 +
12574 +[0-9a-f]* <satrndu>:
12575 + *[0-9a-f]*:   f3 bf 04 00     satrndu pc,0x0
12576 + *[0-9a-f]*:   f3 bc 07 ff     satrndu r12>>0x1f,0x1f
12577 + *[0-9a-f]*:   f3 b5 06 10     satrndu r5>>0x10,0x10
12578 + *[0-9a-f]*:   f3 b4 05 ef     satrndu r4>>0xf,0xf
12579 + *[0-9a-f]*:   f3 be 04 21     satrndu lr>>0x1,0x1
12580 + *[0-9a-f]*:   f3 bc 07 40     satrndu r12,0x1a
12581 + *[0-9a-f]*:   f3 b4 04 75     satrndu r4>>0x15,0x3
12582 + *[0-9a-f]*:   f3 ba 06 03     satrndu r10>>0x3,0x10
12583 +
12584 +[0-9a-f]* <subfc>:
12585 + *[0-9a-f]*:   f5 bf 00 00     subfeq pc,0
12586 + *[0-9a-f]*:   f5 bc 0f ff     subfal r12,-1
12587 + *[0-9a-f]*:   f5 b5 08 80     subfls r5,-128
12588 + *[0-9a-f]*:   f5 b4 07 7f     subfpl r4,127
12589 + *[0-9a-f]*:   f5 be 01 01     subfne lr,1
12590 + *[0-9a-f]*:   f5 ba 08 08     subfls r10,8
12591 + *[0-9a-f]*:   f5 bb 0d 63     subfvc r11,99
12592 + *[0-9a-f]*:   f5 b2 0c 49     subfvs r2,73
12593 +
12594 +[0-9a-f]* <subc>:
12595 + *[0-9a-f]*:   f7 bf 00 00     subeq pc,0
12596 + *[0-9a-f]*:   f7 bc 0f ff     subal r12,-1
12597 + *[0-9a-f]*:   f7 b5 08 80     subls r5,-128
12598 + *[0-9a-f]*:   f7 b4 07 7f     subpl r4,127
12599 + *[0-9a-f]*:   f7 be 01 01     subne lr,1
12600 + *[0-9a-f]*:   f7 bc 08 76     subls r12,118
12601 + *[0-9a-f]*:   f7 be 0d f4     subvc lr,-12
12602 + *[0-9a-f]*:   f7 b4 06 f3     submi r4,-13
12603 +
12604 +[0-9a-f]* <movc2>:
12605 + *[0-9a-f]*:   f9 bf 00 00     moveq pc,0
12606 + *[0-9a-f]*:   f9 bc 0f ff     moval r12,-1
12607 + *[0-9a-f]*:   f9 b5 08 80     movls r5,-128
12608 + *[0-9a-f]*:   f9 b4 07 7f     movpl r4,127
12609 + *[0-9a-f]*:   f9 be 01 01     movne lr,1
12610 + *[0-9a-f]*:   f9 b3 05 86     movlt r3,-122
12611 + *[0-9a-f]*:   f9 b8 0d 02     movvc r8,2
12612 + *[0-9a-f]*:   f9 b7 01 91     movne r7,-111
12613 +
12614 +[0-9a-f]* <cp_b>:
12615 + *[0-9a-f]*:   e0 0f 18 00     cp\.b pc,r0
12616 + *[0-9a-f]*:   fe 00 18 00     cp\.b r0,pc
12617 + *[0-9a-f]*:   f0 07 18 00     cp\.b r7,r8
12618 + *[0-9a-f]*:   ee 08 18 00     cp\.b r8,r7
12619 +
12620 +[0-9a-f]* <cp_h>:
12621 + *[0-9a-f]*:   e0 0f 19 00     cp\.h pc,r0
12622 + *[0-9a-f]*:   fe 00 19 00     cp\.h r0,pc
12623 + *[0-9a-f]*:   f0 07 19 00     cp\.h r7,r8
12624 + *[0-9a-f]*:   ee 08 19 00     cp\.h r8,r7
12625 +
12626 +[0-9a-f]* <ldm>:
12627 + *[0-9a-f]*:   e1 cf 00 7e     ldm pc,r1-r6
12628 + *[0-9a-f]*:   e1 cc ff ff     ldm r12,r0-pc
12629 + *[0-9a-f]*:   e1 c5 80 00     ldm r5,pc
12630 + *[0-9a-f]*:   e1 c4 7f ff     ldm r4,r0-lr
12631 + *[0-9a-f]*:   e1 ce 00 01     ldm lr,r0
12632 + *[0-9a-f]*:   e1 c9 40 22     ldm r9,r1,r5,lr
12633 + *[0-9a-f]*:   e1 cb 81 ec     ldm r11,r2-r3,r5-r8,pc
12634 + *[0-9a-f]*:   e1 c6 a2 09     ldm r6,r0,r3,r9,sp,pc
12635 +
12636 +[0-9a-f]* <ldm_pu>:
12637 + *[0-9a-f]*:   e3 cf 03 c0     ldm pc\+\+,r6-r9
12638 + *[0-9a-f]*:   e3 cc ff ff     ldm r12\+\+,r0-pc
12639 + *[0-9a-f]*:   e3 c5 80 00     ldm r5\+\+,pc
12640 + *[0-9a-f]*:   e3 c4 7f ff     ldm r4\+\+,r0-lr
12641 + *[0-9a-f]*:   e3 ce 00 01     ldm lr\+\+,r0
12642 + *[0-9a-f]*:   e3 cc d5 38     ldm r12\+\+,r3-r5,r8,r10,r12,lr-pc
12643 + *[0-9a-f]*:   e3 ca c0 74     ldm r10\+\+,r2,r4-r6,lr-pc
12644 + *[0-9a-f]*:   e3 c6 7e 1a     ldm r6\+\+,r1,r3-r4,r9-lr
12645 +
12646 +[0-9a-f]* <ldmts>:
12647 + *[0-9a-f]*:   e5 cf 01 80     ldmts pc,r7-r8
12648 + *[0-9a-f]*:   e5 cc ff ff     ldmts r12,r0-pc
12649 + *[0-9a-f]*:   e5 c5 80 00     ldmts r5,pc
12650 + *[0-9a-f]*:   e5 c4 7f ff     ldmts r4,r0-lr
12651 + *[0-9a-f]*:   e5 ce 00 01     ldmts lr,r0
12652 + *[0-9a-f]*:   e5 c0 18 06     ldmts r0,r1-r2,r11-r12
12653 + *[0-9a-f]*:   e5 ce 61 97     ldmts lr,r0-r2,r4,r7-r8,sp-lr
12654 + *[0-9a-f]*:   e5 cc c2 3b     ldmts r12,r0-r1,r3-r5,r9,lr-pc
12655 +
12656 +[0-9a-f]* <ldmts_pu>:
12657 + *[0-9a-f]*:   e7 cf 02 00     ldmts pc\+\+,r9
12658 + *[0-9a-f]*:   e7 cc ff ff     ldmts r12\+\+,r0-pc
12659 + *[0-9a-f]*:   e7 c5 80 00     ldmts r5\+\+,pc
12660 + *[0-9a-f]*:   e7 c4 7f ff     ldmts r4\+\+,r0-lr
12661 + *[0-9a-f]*:   e7 ce 00 01     ldmts lr\+\+,r0
12662 + *[0-9a-f]*:   e7 cd 0a bd     ldmts sp\+\+,r0,r2-r5,r7,r9,r11
12663 + *[0-9a-f]*:   e7 c5 0c 8e     ldmts r5\+\+,r1-r3,r7,r10-r11
12664 + *[0-9a-f]*:   e7 c8 a1 9c     ldmts r8\+\+,r2-r4,r7-r8,sp,pc
12665 +
12666 +[0-9a-f]* <stm>:
12667 + *[0-9a-f]*:   e9 cf 00 80     stm pc,r7
12668 + *[0-9a-f]*:   e9 cc ff ff     stm r12,r0-pc
12669 + *[0-9a-f]*:   e9 c5 80 00     stm r5,pc
12670 + *[0-9a-f]*:   e9 c4 7f ff     stm r4,r0-lr
12671 + *[0-9a-f]*:   e9 ce 00 01     stm lr,r0
12672 + *[0-9a-f]*:   e9 cd 49 2c     stm sp,r2-r3,r5,r8,r11,lr
12673 + *[0-9a-f]*:   e9 c4 4c 5f     stm r4,r0-r4,r6,r10-r11,lr
12674 + *[0-9a-f]*:   e9 c9 f2 22     stm r9,r1,r5,r9,r12-pc
12675 +
12676 +[0-9a-f]* <stm_pu>:
12677 + *[0-9a-f]*:   eb cf 00 70     stm --pc,r4-r6
12678 + *[0-9a-f]*:   eb cc ff ff     stm --r12,r0-pc
12679 + *[0-9a-f]*:   eb c5 80 00     stm --r5,pc
12680 + *[0-9a-f]*:   eb c4 7f ff     stm --r4,r0-lr
12681 + *[0-9a-f]*:   eb ce 00 01     stm --lr,r0
12682 + *[0-9a-f]*:   eb cb fb f1     stm --r11,r0,r4-r9,r11-pc
12683 + *[0-9a-f]*:   eb cb 56 09     stm --r11,r0,r3,r9-r10,r12,lr
12684 + *[0-9a-f]*:   eb c6 63 04     stm --r6,r2,r8-r9,sp-lr
12685 +
12686 +[0-9a-f]* <stmts>:
12687 + *[0-9a-f]*:   ed cf 01 00     stmts pc,r8
12688 + *[0-9a-f]*:   ed cc ff ff     stmts r12,r0-pc
12689 + *[0-9a-f]*:   ed c5 80 00     stmts r5,pc
12690 + *[0-9a-f]*:   ed c4 7f ff     stmts r4,r0-lr
12691 + *[0-9a-f]*:   ed ce 00 01     stmts lr,r0
12692 + *[0-9a-f]*:   ed c1 c6 5b     stmts r1,r0-r1,r3-r4,r6,r9-r10,lr-pc
12693 + *[0-9a-f]*:   ed c3 1d c1     stmts r3,r0,r6-r8,r10-r12
12694 + *[0-9a-f]*:   ed cb d6 d1     stmts r11,r0,r4,r6-r7,r9-r10,r12,lr-pc
12695 +
12696 +[0-9a-f]* <stmts_pu>:
12697 + *[0-9a-f]*:   ef cf 01 c0     stmts --pc,r6-r8
12698 + *[0-9a-f]*:   ef cc ff ff     stmts --r12,r0-pc
12699 + *[0-9a-f]*:   ef c5 80 00     stmts --r5,pc
12700 + *[0-9a-f]*:   ef c4 7f ff     stmts --r4,r0-lr
12701 + *[0-9a-f]*:   ef ce 00 01     stmts --lr,r0
12702 + *[0-9a-f]*:   ef c2 36 19     stmts --r2,r0,r3-r4,r9-r10,r12-sp
12703 + *[0-9a-f]*:   ef c3 c0 03     stmts --r3,r0-r1,lr-pc
12704 + *[0-9a-f]*:   ef c0 44 7d     stmts --r0,r0,r2-r6,r10,lr
12705 +
12706 +[0-9a-f]* <ldins_h>:
12707 + *[0-9a-f]*:   ff df 00 00     ldins\.h pc:b,pc\[0\]
12708 + *[0-9a-f]*:   f9 dc 1f ff     ldins\.h r12:t,r12\[-2\]
12709 + *[0-9a-f]*:   eb d5 18 00     ldins\.h r5:t,r5\[-4096\]
12710 + *[0-9a-f]*:   e9 d4 07 ff     ldins\.h r4:b,r4\[4094\]
12711 + *[0-9a-f]*:   fd de 10 01     ldins\.h lr:t,lr\[2\]
12712 + *[0-9a-f]*:   fd d0 13 c5     ldins\.h r0:t,lr\[1930\]
12713 + *[0-9a-f]*:   ef d3 0e f5     ldins\.h r3:b,r7\[-534\]
12714 + *[0-9a-f]*:   f9 d2 0b 9a     ldins\.h r2:b,r12\[-2252\]
12715 +
12716 +[0-9a-f]* <ldins_b>:
12717 + *[0-9a-f]*:   ff df 40 00     ldins\.b pc:b,pc\[0\]
12718 + *[0-9a-f]*:   f9 dc 7f ff     ldins\.b r12:t,r12\[-1\]
12719 + *[0-9a-f]*:   eb d5 68 00     ldins\.b r5:u,r5\[-2048\]
12720 + *[0-9a-f]*:   e9 d4 57 ff     ldins\.b r4:l,r4\[2047\]
12721 + *[0-9a-f]*:   fd de 50 01     ldins\.b lr:l,lr\[1\]
12722 + *[0-9a-f]*:   e9 d6 7d 6a     ldins\.b r6:t,r4\[-662\]
12723 + *[0-9a-f]*:   e3 d5 4f 69     ldins\.b r5:b,r1\[-151\]
12724 + *[0-9a-f]*:   f7 da 78 7d     ldins\.b r10:t,r11\[-1923\]
12725 +
12726 +[0-9a-f]* <ldswp_sh>:
12727 + *[0-9a-f]*:   ff df 20 00     ldswp\.sh pc,pc\[0\]
12728 + *[0-9a-f]*:   f9 dc 2f ff     ldswp\.sh r12,r12\[-2\]
12729 + *[0-9a-f]*:   eb d5 28 00     ldswp\.sh r5,r5\[-4096\]
12730 + *[0-9a-f]*:   e9 d4 27 ff     ldswp\.sh r4,r4\[4094\]
12731 + *[0-9a-f]*:   fd de 20 01     ldswp\.sh lr,lr\[2\]
12732 + *[0-9a-f]*:   f5 d9 27 84     ldswp\.sh r9,r10\[3848\]
12733 + *[0-9a-f]*:   f9 d4 2c 04     ldswp\.sh r4,r12\[-2040\]
12734 + *[0-9a-f]*:   e5 da 26 08     ldswp\.sh r10,r2\[3088\]
12735 +
12736 +[0-9a-f]* <ldswp_uh>:
12737 + *[0-9a-f]*:   ff df 30 00     ldswp\.uh pc,pc\[0\]
12738 + *[0-9a-f]*:   f9 dc 3f ff     ldswp\.uh r12,r12\[-2\]
12739 + *[0-9a-f]*:   eb d5 38 00     ldswp\.uh r5,r5\[-4096\]
12740 + *[0-9a-f]*:   e9 d4 37 ff     ldswp\.uh r4,r4\[4094\]
12741 + *[0-9a-f]*:   fd de 30 01     ldswp\.uh lr,lr\[2\]
12742 + *[0-9a-f]*:   f3 d4 37 46     ldswp\.uh r4,r9\[3724\]
12743 + *[0-9a-f]*:   fb de 3c bc     ldswp\.uh lr,sp\[-1672\]
12744 + *[0-9a-f]*:   f9 d8 38 7d     ldswp\.uh r8,r12\[-3846\]
12745 +
12746 +[0-9a-f]* <ldswp_w>:
12747 + *[0-9a-f]*:   ff df 80 00     ldswp\.w pc,pc\[0\]
12748 + *[0-9a-f]*:   f9 dc 8f ff     ldswp\.w r12,r12\[-4\]
12749 + *[0-9a-f]*:   eb d5 88 00     ldswp\.w r5,r5\[-8192\]
12750 + *[0-9a-f]*:   e9 d4 87 ff     ldswp\.w r4,r4\[8188\]
12751 + *[0-9a-f]*:   fd de 80 01     ldswp\.w lr,lr\[4\]
12752 + *[0-9a-f]*:   ef dd 81 d1     ldswp\.w sp,r7\[1860\]
12753 + *[0-9a-f]*:   eb df 8c c1     ldswp\.w pc,r5\[-3324\]
12754 + *[0-9a-f]*:   f5 dc 8c c8     ldswp\.w r12,r10\[-3296\]
12755 +
12756 +[0-9a-f]* <stswp_h>:
12757 + *[0-9a-f]*:   ff df 90 00     stswp\.h pc\[0\],pc
12758 + *[0-9a-f]*:   f9 dc 9f ff     stswp\.h r12\[-2\],r12
12759 + *[0-9a-f]*:   eb d5 98 00     stswp\.h r5\[-4096\],r5
12760 + *[0-9a-f]*:   e9 d4 97 ff     stswp\.h r4\[4094\],r4
12761 + *[0-9a-f]*:   fd de 90 01     stswp\.h lr\[2\],lr
12762 + *[0-9a-f]*:   ef da 90 20     stswp\.h r7\[64\],r10
12763 + *[0-9a-f]*:   f5 d2 95 e8     stswp\.h r10\[3024\],r2
12764 + *[0-9a-f]*:   e1 da 9b 74     stswp\.h r0\[-2328\],r10
12765 +
12766 +[0-9a-f]* <stswp_w>:
12767 + *[0-9a-f]*:   ff df a0 00     stswp\.w pc\[0\],pc
12768 + *[0-9a-f]*:   f9 dc af ff     stswp\.w r12\[-4\],r12
12769 + *[0-9a-f]*:   eb d5 a8 00     stswp\.w r5\[-8192\],r5
12770 + *[0-9a-f]*:   e9 d4 a7 ff     stswp\.w r4\[8188\],r4
12771 + *[0-9a-f]*:   fd de a0 01     stswp\.w lr\[4\],lr
12772 + *[0-9a-f]*:   ff d8 a1 21     stswp\.w pc\[1156\],r8
12773 + *[0-9a-f]*:   fb da a7 ce     stswp\.w sp\[7992\],r10
12774 + *[0-9a-f]*:   f1 d5 ae db     stswp\.w r8\[-1172\],r5
12775 +
12776 +[0-9a-f]* <and2>:
12777 + *[0-9a-f]*:   ff ef 00 0f     and pc,pc,pc
12778 + *[0-9a-f]*:   f9 ec 01 fc     and r12,r12,r12<<0x1f
12779 + *[0-9a-f]*:   eb e5 01 05     and r5,r5,r5<<0x10
12780 + *[0-9a-f]*:   e9 e4 00 f4     and r4,r4,r4<<0xf
12781 + *[0-9a-f]*:   fd ee 00 1e     and lr,lr,lr<<0x1
12782 + *[0-9a-f]*:   e5 e1 00 1a     and r10,r2,r1<<0x1
12783 + *[0-9a-f]*:   f1 eb 01 bc     and r12,r8,r11<<0x1b
12784 + *[0-9a-f]*:   ef e0 00 3a     and r10,r7,r0<<0x3
12785 +
12786 +[0-9a-f]* <and3>:
12787 + *[0-9a-f]*:   ff ef 02 0f     and pc,pc,pc
12788 + *[0-9a-f]*:   f9 ec 03 fc     and r12,r12,r12>>0x1f
12789 + *[0-9a-f]*:   eb e5 03 05     and r5,r5,r5>>0x10
12790 + *[0-9a-f]*:   e9 e4 02 f4     and r4,r4,r4>>0xf
12791 + *[0-9a-f]*:   fd ee 02 1e     and lr,lr,lr>>0x1
12792 + *[0-9a-f]*:   f1 e7 03 1c     and r12,r8,r7>>0x11
12793 + *[0-9a-f]*:   e9 e9 03 4f     and pc,r4,r9>>0x14
12794 + *[0-9a-f]*:   f3 ea 02 ca     and r10,r9,r10>>0xc
12795 +
12796 +[0-9a-f]* <or2>:
12797 + *[0-9a-f]*:   ff ef 10 0f     or pc,pc,pc
12798 + *[0-9a-f]*:   f9 ec 11 fc     or r12,r12,r12<<0x1f
12799 + *[0-9a-f]*:   eb e5 11 05     or r5,r5,r5<<0x10
12800 + *[0-9a-f]*:   e9 e4 10 f4     or r4,r4,r4<<0xf
12801 + *[0-9a-f]*:   fd ee 10 1e     or lr,lr,lr<<0x1
12802 + *[0-9a-f]*:   fb eb 11 d8     or r8,sp,r11<<0x1d
12803 + *[0-9a-f]*:   f3 e2 11 cf     or pc,r9,r2<<0x1c
12804 + *[0-9a-f]*:   e3 e2 10 35     or r5,r1,r2<<0x3
12805 +
12806 +[0-9a-f]* <or3>:
12807 + *[0-9a-f]*:   ff ef 12 0f     or pc,pc,pc
12808 + *[0-9a-f]*:   f9 ec 13 fc     or r12,r12,r12>>0x1f
12809 + *[0-9a-f]*:   eb e5 13 05     or r5,r5,r5>>0x10
12810 + *[0-9a-f]*:   e9 e4 12 f4     or r4,r4,r4>>0xf
12811 + *[0-9a-f]*:   fd ee 12 1e     or lr,lr,lr>>0x1
12812 + *[0-9a-f]*:   fb ed 12 21     or r1,sp,sp>>0x2
12813 + *[0-9a-f]*:   e3 e1 13 d0     or r0,r1,r1>>0x1d
12814 + *[0-9a-f]*:   f9 e8 12 84     or r4,r12,r8>>0x8
12815 +
12816 +[0-9a-f]* <eor2>:
12817 + *[0-9a-f]*:   ff ef 20 0f     eor pc,pc,pc
12818 + *[0-9a-f]*:   f9 ec 21 fc     eor r12,r12,r12<<0x1f
12819 + *[0-9a-f]*:   eb e5 21 05     eor r5,r5,r5<<0x10
12820 + *[0-9a-f]*:   e9 e4 20 f4     eor r4,r4,r4<<0xf
12821 + *[0-9a-f]*:   fd ee 20 1e     eor lr,lr,lr<<0x1
12822 + *[0-9a-f]*:   f3 e4 20 ba     eor r10,r9,r4<<0xb
12823 + *[0-9a-f]*:   e1 e1 21 f4     eor r4,r0,r1<<0x1f
12824 + *[0-9a-f]*:   e5 ec 20 d6     eor r6,r2,r12<<0xd
12825 +
12826 +[0-9a-f]* <eor3>:
12827 + *[0-9a-f]*:   ff ef 22 0f     eor pc,pc,pc
12828 + *[0-9a-f]*:   f9 ec 23 fc     eor r12,r12,r12>>0x1f
12829 + *[0-9a-f]*:   eb e5 23 05     eor r5,r5,r5>>0x10
12830 + *[0-9a-f]*:   e9 e4 22 f4     eor r4,r4,r4>>0xf
12831 + *[0-9a-f]*:   fd ee 22 1e     eor lr,lr,lr>>0x1
12832 + *[0-9a-f]*:   eb e5 23 65     eor r5,r5,r5>>0x16
12833 + *[0-9a-f]*:   e3 ee 22 3a     eor r10,r1,lr>>0x3
12834 + *[0-9a-f]*:   fd ed 23 a7     eor r7,lr,sp>>0x1a
12835 +
12836 +[0-9a-f]* <sthh_w2>:
12837 + *[0-9a-f]*:   ff ef 8f 0f     sthh\.w pc\[pc\],pc:b,pc:b
12838 + *[0-9a-f]*:   f9 ec bc 3c     sthh\.w r12\[r12<<0x3\],r12:t,r12:t
12839 + *[0-9a-f]*:   eb e5 b5 25     sthh\.w r5\[r5<<0x2\],r5:t,r5:t
12840 + *[0-9a-f]*:   e9 e4 84 14     sthh\.w r4\[r4<<0x1\],r4:b,r4:b
12841 + *[0-9a-f]*:   fd ee be 1e     sthh\.w lr\[lr<<0x1\],lr:t,lr:t
12842 + *[0-9a-f]*:   e3 ec b6 3d     sthh\.w sp\[r6<<0x3\],r1:t,r12:t
12843 + *[0-9a-f]*:   f3 e9 b6 06     sthh\.w r6\[r6\],r9:t,r9:t
12844 + *[0-9a-f]*:   e1 eb 93 0a     sthh\.w r10\[r3\],r0:b,r11:t
12845 +
12846 +[0-9a-f]* <sthh_w1>:
12847 + *[0-9a-f]*:   ff ef c0 0f     sthh\.w pc\[0x0\],pc:b,pc:b
12848 + *[0-9a-f]*:   f9 ec ff fc     sthh\.w r12\[0x3fc\],r12:t,r12:t
12849 + *[0-9a-f]*:   eb e5 f8 05     sthh\.w r5\[0x200\],r5:t,r5:t
12850 + *[0-9a-f]*:   e9 e4 c7 f4     sthh\.w r4\[0x1fc\],r4:b,r4:b
12851 + *[0-9a-f]*:   fd ee f0 1e     sthh\.w lr\[0x4\],lr:t,lr:t
12852 + *[0-9a-f]*:   f3 e0 e6 54     sthh\.w r4\[0x194\],r9:t,r0:b
12853 + *[0-9a-f]*:   e5 ea e5 78     sthh\.w r8\[0x15c\],r2:t,r10:b
12854 + *[0-9a-f]*:   f3 e2 c2 bd     sthh\.w sp\[0xac\],r9:b,r2:b
12855 +
12856 +[0-9a-f]* <cop>:
12857 + *[0-9a-f]*:   e1 a0 00 00     cop cp0,cr0,cr0,cr0,0x0
12858 + *[0-9a-f]*:   e7 af ff ff     cop cp7,cr15,cr15,cr15,0x7f
12859 + *[0-9a-f]*:   e3 a8 75 55     cop cp3,cr5,cr5,cr5,0x31
12860 + *[0-9a-f]*:   e3 a8 44 44     cop cp2,cr4,cr4,cr4,0x30
12861 + *[0-9a-f]*:   e5 ad a8 37     cop cp5,cr8,cr3,cr7,0x5a
12862 +
12863 +[0-9a-f]* <ldc_w1>:
12864 + *[0-9a-f]*:   e9 a0 00 00     ldc\.w cp0,cr0,r0\[0x0\]
12865 + *[0-9a-f]*:   e9 af ef ff     ldc\.w cp7,cr15,pc\[0x3fc\]
12866 + *[0-9a-f]*:   e9 a5 65 80     ldc\.w cp3,cr5,r5\[0x200\]
12867 + *[0-9a-f]*:   e9 a4 44 7f     ldc\.w cp2,cr4,r4\[0x1fc\]
12868 + *[0-9a-f]*:   e9 ad 89 24     ldc\.w cp4,cr9,sp\[0x90\]
12869 +
12870 +[0-9a-f]* <ldc_w2>:
12871 + *[0-9a-f]*:   ef a0 00 40     ldc\.w cp0,cr0,--r0
12872 + *[0-9a-f]*:   ef af ef 40     ldc\.w cp7,cr15,--pc
12873 + *[0-9a-f]*:   ef a5 65 40     ldc\.w cp3,cr5,--r5
12874 + *[0-9a-f]*:   ef a4 44 40     ldc\.w cp2,cr4,--r4
12875 + *[0-9a-f]*:   ef ad 89 40     ldc\.w cp4,cr9,--sp
12876 +
12877 +[0-9a-f]* <ldc_w3>:
12878 + *[0-9a-f]*:   ef a0 10 00     ldc\.w cp0,cr0,r0\[r0\]
12879 + *[0-9a-f]*:   ef af ff 3f     ldc\.w cp7,cr15,pc\[pc<<0x3\]
12880 + *[0-9a-f]*:   ef a5 75 24     ldc\.w cp3,cr5,r5\[r4<<0x2\]
12881 + *[0-9a-f]*:   ef a4 54 13     ldc\.w cp2,cr4,r4\[r3<<0x1\]
12882 + *[0-9a-f]*:   ef ad 99 0c     ldc\.w cp4,cr9,sp\[r12\]
12883 +
12884 +[0-9a-f]* <ldc_d1>:
12885 + *[0-9a-f]*:   e9 a0 10 00     ldc\.d cp0,cr0,r0\[0x0\]
12886 + *[0-9a-f]*:   e9 af fe ff     ldc\.d cp7,cr14,pc\[0x3fc\]
12887 + *[0-9a-f]*:   e9 a5 76 80     ldc\.d cp3,cr6,r5\[0x200\]
12888 + *[0-9a-f]*:   e9 a4 54 7f     ldc\.d cp2,cr4,r4\[0x1fc\]
12889 + *[0-9a-f]*:   e9 ad 98 24     ldc\.d cp4,cr8,sp\[0x90\]
12890 +
12891 +[0-9a-f]* <ldc_d2>:
12892 + *[0-9a-f]*:   ef a0 00 50     ldc\.d cp0,cr0,--r0
12893 + *[0-9a-f]*:   ef af ee 50     ldc\.d cp7,cr14,--pc
12894 + *[0-9a-f]*:   ef a5 66 50     ldc\.d cp3,cr6,--r5
12895 + *[0-9a-f]*:   ef a4 44 50     ldc\.d cp2,cr4,--r4
12896 + *[0-9a-f]*:   ef ad 88 50     ldc\.d cp4,cr8,--sp
12897 +
12898 +[0-9a-f]* <ldc_d3>:
12899 + *[0-9a-f]*:   ef a0 10 40     ldc\.d cp0,cr0,r0\[r0\]
12900 + *[0-9a-f]*:   ef af fe 7f     ldc\.d cp7,cr14,pc\[pc<<0x3\]
12901 + *[0-9a-f]*:   ef a5 76 64     ldc\.d cp3,cr6,r5\[r4<<0x2\]
12902 + *[0-9a-f]*:   ef a4 54 53     ldc\.d cp2,cr4,r4\[r3<<0x1\]
12903 + *[0-9a-f]*:   ef ad 98 4c     ldc\.d cp4,cr8,sp\[r12\]
12904 +
12905 +[0-9a-f]* <stc_w1>:
12906 + *[0-9a-f]*:   eb a0 00 00     stc\.w cp0,r0\[0x0\],cr0
12907 + *[0-9a-f]*:   eb af ef ff     stc\.w cp7,pc\[0x3fc\],cr15
12908 + *[0-9a-f]*:   eb a5 65 80     stc\.w cp3,r5\[0x200\],cr5
12909 + *[0-9a-f]*:   eb a4 44 7f     stc\.w cp2,r4\[0x1fc\],cr4
12910 + *[0-9a-f]*:   eb ad 89 24     stc\.w cp4,sp\[0x90\],cr9
12911 +
12912 +[0-9a-f]* <stc_w2>:
12913 + *[0-9a-f]*:   ef a0 00 60     stc\.w cp0,r0\+\+,cr0
12914 + *[0-9a-f]*:   ef af ef 60     stc\.w cp7,pc\+\+,cr15
12915 + *[0-9a-f]*:   ef a5 65 60     stc\.w cp3,r5\+\+,cr5
12916 + *[0-9a-f]*:   ef a4 44 60     stc\.w cp2,r4\+\+,cr4
12917 + *[0-9a-f]*:   ef ad 89 60     stc\.w cp4,sp\+\+,cr9
12918 +
12919 +[0-9a-f]* <stc_w3>:
12920 + *[0-9a-f]*:   ef a0 10 80     stc\.w cp0,r0\[r0\],cr0
12921 + *[0-9a-f]*:   ef af ff bf     stc\.w cp7,pc\[pc<<0x3\],cr15
12922 + *[0-9a-f]*:   ef a5 75 a4     stc\.w cp3,r5\[r4<<0x2\],cr5
12923 + *[0-9a-f]*:   ef a4 54 93     stc\.w cp2,r4\[r3<<0x1\],cr4
12924 + *[0-9a-f]*:   ef ad 99 8c     stc\.w cp4,sp\[r12\],cr9
12925 +
12926 +[0-9a-f]* <stc_d1>:
12927 + *[0-9a-f]*:   eb a0 10 00     stc\.d cp0,r0\[0x0\],cr0
12928 + *[0-9a-f]*:   eb af fe ff     stc\.d cp7,pc\[0x3fc\],cr14
12929 + *[0-9a-f]*:   eb a5 76 80     stc\.d cp3,r5\[0x200\],cr6
12930 + *[0-9a-f]*:   eb a4 54 7f     stc\.d cp2,r4\[0x1fc\],cr4
12931 + *[0-9a-f]*:   eb ad 98 24     stc\.d cp4,sp\[0x90\],cr8
12932 +
12933 +[0-9a-f]* <stc_d2>:
12934 + *[0-9a-f]*:   ef a0 00 70     stc\.d cp0,r0\+\+,cr0
12935 + *[0-9a-f]*:   ef af ee 70     stc\.d cp7,pc\+\+,cr14
12936 + *[0-9a-f]*:   ef a5 66 70     stc\.d cp3,r5\+\+,cr6
12937 + *[0-9a-f]*:   ef a4 44 70     stc\.d cp2,r4\+\+,cr4
12938 + *[0-9a-f]*:   ef ad 88 70     stc\.d cp4,sp\+\+,cr8
12939 +
12940 +[0-9a-f]* <stc_d3>:
12941 + *[0-9a-f]*:   ef a0 10 c0     stc\.d cp0,r0\[r0\],cr0
12942 + *[0-9a-f]*:   ef af fe ff     stc\.d cp7,pc\[pc<<0x3\],cr14
12943 + *[0-9a-f]*:   ef a5 76 e4     stc\.d cp3,r5\[r4<<0x2\],cr6
12944 + *[0-9a-f]*:   ef a4 54 d3     stc\.d cp2,r4\[r3<<0x1\],cr4
12945 + *[0-9a-f]*:   ef ad 98 cc     stc\.d cp4,sp\[r12\],cr8
12946 +
12947 +[0-9a-f]* <ldc0_w>:
12948 + *[0-9a-f]*:   f1 a0 00 00     ldc0\.w cr0,r0\[0x0\]
12949 + *[0-9a-f]*:   f1 af ff ff     ldc0\.w cr15,pc\[0x3ffc\]
12950 + *[0-9a-f]*:   f1 a5 85 00     ldc0\.w cr5,r5\[0x2000\]
12951 + *[0-9a-f]*:   f1 a4 74 ff     ldc0\.w cr4,r4\[0x1ffc\]
12952 + *[0-9a-f]*:   f1 ad 09 93     ldc0\.w cr9,sp\[0x24c\]
12953 +
12954 +[0-9a-f]* <ldc0_d>:
12955 + *[0-9a-f]*:   f3 a0 00 00     ldc0\.d cr0,r0\[0x0\]
12956 + *[0-9a-f]*:   f3 af fe ff     ldc0\.d cr14,pc\[0x3ffc\]
12957 + *[0-9a-f]*:   f3 a5 86 00     ldc0\.d cr6,r5\[0x2000\]
12958 + *[0-9a-f]*:   f3 a4 74 ff     ldc0\.d cr4,r4\[0x1ffc\]
12959 + *[0-9a-f]*:   f3 ad 08 93     ldc0\.d cr8,sp\[0x24c\]
12960 +
12961 +[0-9a-f]* <stc0_w>:
12962 + *[0-9a-f]*:   f5 a0 00 00     stc0\.w r0\[0x0\],cr0
12963 + *[0-9a-f]*:   f5 af ff ff     stc0\.w pc\[0x3ffc\],cr15
12964 + *[0-9a-f]*:   f5 a5 85 00     stc0\.w r5\[0x2000\],cr5
12965 + *[0-9a-f]*:   f5 a4 74 ff     stc0\.w r4\[0x1ffc\],cr4
12966 + *[0-9a-f]*:   f5 ad 09 93     stc0\.w sp\[0x24c\],cr9
12967 +
12968 +[0-9a-f]* <stc0_d>:
12969 + *[0-9a-f]*:   f7 a0 00 00     stc0\.d r0\[0x0\],cr0
12970 + *[0-9a-f]*:   f7 af fe ff     stc0\.d pc\[0x3ffc\],cr14
12971 + *[0-9a-f]*:   f7 a5 86 00     stc0\.d r5\[0x2000\],cr6
12972 + *[0-9a-f]*:   f7 a4 74 ff     stc0\.d r4\[0x1ffc\],cr4
12973 + *[0-9a-f]*:   f7 ad 08 93     stc0\.d sp\[0x24c\],cr8
12974 +
12975 +[0-9a-f]* <memc>:
12976 + *[0-9a-f]*:   f6 10 00 00     memc 0,0x0
12977 + *[0-9a-f]*:   f6 1f ff ff     memc -4,0x1f
12978 + *[0-9a-f]*:   f6 18 40 00     memc -65536,0x10
12979 + *[0-9a-f]*:   f6 17 bf ff     memc 65532,0xf
12980 +
12981 +[0-9a-f]* <mems>:
12982 + *[0-9a-f]*:   f8 10 00 00     mems 0,0x0
12983 + *[0-9a-f]*:   f8 1f ff ff     mems -4,0x1f
12984 + *[0-9a-f]*:   f8 18 40 00     mems -65536,0x10
12985 + *[0-9a-f]*:   f8 17 bf ff     mems 65532,0xf
12986 +
12987 +[0-9a-f]* <memt>:
12988 + *[0-9a-f]*:   fa 10 00 00     memt 0,0x0
12989 + *[0-9a-f]*:   fa 1f ff ff     memt -4,0x1f
12990 + *[0-9a-f]*:   fa 18 40 00     memt -65536,0x10
12991 + *[0-9a-f]*:   fa 17 bf ff     memt 65532,0xf
12992 +
12993 +[0-9a-f]* <stcond>:
12994 + *[0-9a-f]*:   e1 70 00 00     stcond r0\[0\],r0
12995 + *[0-9a-f]*:   ff 7f ff ff     stcond pc\[-1\],pc
12996 + *[0-9a-f]*:   f1 77 80 00     stcond r8\[-32768\],r7
12997 + *[0-9a-f]*:   ef 78 7f ff     stcond r7\[32767\],r8
12998 + *[0-9a-f]*:   eb 7a 12 34     stcond r5\[4660\],r10
12999 +
13000 +[0-9a-f]* <ldcm_w>:
13001 + *[0-9a-f]*:   ed af 00 ff     ldcm\.w cp0,pc,cr0-cr7
13002 + *[0-9a-f]*:   ed a0 e0 01     ldcm\.w cp7,r0,cr0
13003 + *[0-9a-f]*:   ed a4 90 7f     ldcm\.w cp4,r4\+\+,cr0-cr6
13004 + *[0-9a-f]*:   ed a7 60 80     ldcm\.w cp3,r7,cr7
13005 + *[0-9a-f]*:   ed ac 30 72     ldcm\.w cp1,r12\+\+,cr1,cr4-cr6
13006 + *[0-9a-f]*:   ed af 01 ff     ldcm\.w cp0,pc,cr8-cr15
13007 + *[0-9a-f]*:   ed a0 e1 01     ldcm\.w cp7,r0,cr8
13008 + *[0-9a-f]*:   ed a4 91 7f     ldcm\.w cp4,r4\+\+,cr8-cr14
13009 + *[0-9a-f]*:   ed a7 61 80     ldcm\.w cp3,r7,cr15
13010 + *[0-9a-f]*:   ed ac 31 72     ldcm\.w cp1,r12\+\+,cr9,cr12-cr14
13011 +
13012 +[0-9a-f]* <ldcm_d>:
13013 + *[0-9a-f]*:   ed af 04 ff     ldcm\.d cp0,pc,cr0-cr15
13014 + *[0-9a-f]*:   ed a0 e4 01     ldcm\.d cp7,r0,cr0-cr1
13015 + *[0-9a-f]*:   ed a4 94 7f     ldcm\.d cp4,r4\+\+,cr0-cr13
13016 + *[0-9a-f]*:   ed a7 64 80     ldcm\.d cp3,r7,cr14-cr15
13017 + *[0-9a-f]*:   ed ac 54 93     ldcm\.d cp2,r12\+\+,cr0-cr3,cr8-cr9,cr14-cr15
13018 +
13019 +[0-9a-f]* <stcm_w>:
13020 + *[0-9a-f]*:   ed af 02 ff     stcm\.w cp0,pc,cr0-cr7
13021 + *[0-9a-f]*:   ed a0 e2 01     stcm\.w cp7,r0,cr0
13022 + *[0-9a-f]*:   ed a4 92 7f     stcm\.w cp4,--r4,cr0-cr6
13023 + *[0-9a-f]*:   ed a7 62 80     stcm\.w cp3,r7,cr7
13024 + *[0-9a-f]*:   ed ac 32 72     stcm\.w cp1,--r12,cr1,cr4-cr6
13025 + *[0-9a-f]*:   ed af 03 ff     stcm\.w cp0,pc,cr8-cr15
13026 + *[0-9a-f]*:   ed a0 e3 01     stcm\.w cp7,r0,cr8
13027 + *[0-9a-f]*:   ed a4 93 7f     stcm\.w cp4,--r4,cr8-cr14
13028 + *[0-9a-f]*:   ed a7 63 80     stcm\.w cp3,r7,cr15
13029 + *[0-9a-f]*:   ed ac 33 72     stcm\.w cp1,--r12,cr9,cr12-cr14
13030 +
13031 +[0-9a-f]* <stcm_d>:
13032 + *[0-9a-f]*:   ed af 05 ff     stcm\.d cp0,pc,cr0-cr15
13033 + *[0-9a-f]*:   ed a0 e5 01     stcm\.d cp7,r0,cr0-cr1
13034 + *[0-9a-f]*:   ed a4 95 7f     stcm\.d cp4,--r4,cr0-cr13
13035 + *[0-9a-f]*:   ed a7 65 80     stcm\.d cp3,r7,cr14-cr15
13036 + *[0-9a-f]*:   ed ac 55 93     stcm\.d cp2,--r12,cr0-cr3,cr8-cr9,cr14-cr15
13037 +
13038 +[0-9a-f]* <mvcr_w>:
13039 + *[0-9a-f]*:   ef af ef 00     mvcr\.w cp7,pc,cr15
13040 + *[0-9a-f]*:   ef a0 00 00     mvcr\.w cp0,r0,cr0
13041 + *[0-9a-f]*:   ef af 0f 00     mvcr\.w cp0,pc,cr15
13042 + *[0-9a-f]*:   ef a0 ef 00     mvcr\.w cp7,r0,cr15
13043 + *[0-9a-f]*:   ef af e0 00     mvcr\.w cp7,pc,cr0
13044 + *[0-9a-f]*:   ef a7 88 00     mvcr\.w cp4,r7,cr8
13045 + *[0-9a-f]*:   ef a8 67 00     mvcr\.w cp3,r8,cr7
13046 +
13047 +[0-9a-f]* <mvcr_d>:
13048 + *[0-9a-f]*:   ef ae ee 10     mvcr\.d cp7,lr,cr14
13049 + *[0-9a-f]*:   ef a0 00 10     mvcr\.d cp0,r0,cr0
13050 + *[0-9a-f]*:   ef ae 0e 10     mvcr\.d cp0,lr,cr14
13051 + *[0-9a-f]*:   ef a0 ee 10     mvcr\.d cp7,r0,cr14
13052 + *[0-9a-f]*:   ef ae e0 10     mvcr\.d cp7,lr,cr0
13053 + *[0-9a-f]*:   ef a6 88 10     mvcr\.d cp4,r6,cr8
13054 + *[0-9a-f]*:   ef a8 66 10     mvcr\.d cp3,r8,cr6
13055 +
13056 +[0-9a-f]* <mvrc_w>:
13057 + *[0-9a-f]*:   ef af ef 20     mvrc\.w cp7,cr15,pc
13058 + *[0-9a-f]*:   ef a0 00 20     mvrc\.w cp0,cr0,r0
13059 + *[0-9a-f]*:   ef af 0f 20     mvrc\.w cp0,cr15,pc
13060 + *[0-9a-f]*:   ef a0 ef 20     mvrc\.w cp7,cr15,r0
13061 + *[0-9a-f]*:   ef af e0 20     mvrc\.w cp7,cr0,pc
13062 + *[0-9a-f]*:   ef a7 88 20     mvrc\.w cp4,cr8,r7
13063 + *[0-9a-f]*:   ef a8 67 20     mvrc\.w cp3,cr7,r8
13064 +
13065 +[0-9a-f]* <mvrc_d>:
13066 + *[0-9a-f]*:   ef ae ee 30     mvrc\.d cp7,cr14,lr
13067 + *[0-9a-f]*:   ef a0 00 30     mvrc\.d cp0,cr0,r0
13068 + *[0-9a-f]*:   ef ae 0e 30     mvrc\.d cp0,cr14,lr
13069 + *[0-9a-f]*:   ef a0 ee 30     mvrc\.d cp7,cr14,r0
13070 + *[0-9a-f]*:   ef ae e0 30     mvrc\.d cp7,cr0,lr
13071 + *[0-9a-f]*:   ef a6 88 30     mvrc\.d cp4,cr8,r6
13072 + *[0-9a-f]*:   ef a8 66 30     mvrc\.d cp3,cr6,r8
13073 +
13074 +[0-9a-f]* <bfexts>:
13075 + *[0-9a-f]*:   ff df b3 ff     bfexts pc,pc,0x1f,0x1f
13076 + *[0-9a-f]*:   e1 d0 b0 00     bfexts r0,r0,0x0,0x0
13077 + *[0-9a-f]*:   e1 df b3 ff     bfexts r0,pc,0x1f,0x1f
13078 + *[0-9a-f]*:   ff d0 b3 ff     bfexts pc,r0,0x1f,0x1f
13079 + *[0-9a-f]*:   ff df b0 1f     bfexts pc,pc,0x0,0x1f
13080 + *[0-9a-f]*:   ff df b3 e0     bfexts pc,pc,0x1f,0x0
13081 + *[0-9a-f]*:   ef d8 b1 f0     bfexts r7,r8,0xf,0x10
13082 + *[0-9a-f]*:   f1 d7 b2 0f     bfexts r8,r7,0x10,0xf
13083 +
13084 +[0-9a-f]* <bfextu>:
13085 + *[0-9a-f]*:   ff df c3 ff     bfextu pc,pc,0x1f,0x1f
13086 + *[0-9a-f]*:   e1 d0 c0 00     bfextu r0,r0,0x0,0x0
13087 + *[0-9a-f]*:   e1 df c3 ff     bfextu r0,pc,0x1f,0x1f
13088 + *[0-9a-f]*:   ff d0 c3 ff     bfextu pc,r0,0x1f,0x1f
13089 + *[0-9a-f]*:   ff df c0 1f     bfextu pc,pc,0x0,0x1f
13090 + *[0-9a-f]*:   ff df c3 e0     bfextu pc,pc,0x1f,0x0
13091 + *[0-9a-f]*:   ef d8 c1 f0     bfextu r7,r8,0xf,0x10
13092 + *[0-9a-f]*:   f1 d7 c2 0f     bfextu r8,r7,0x10,0xf
13093 +
13094 +[0-9a-f]* <bfins>:
13095 + *[0-9a-f]*:   ff df d3 ff     bfins pc,pc,0x1f,0x1f
13096 + *[0-9a-f]*:   e1 d0 d0 00     bfins r0,r0,0x0,0x0
13097 + *[0-9a-f]*:   e1 df d3 ff     bfins r0,pc,0x1f,0x1f
13098 + *[0-9a-f]*:   ff d0 d3 ff     bfins pc,r0,0x1f,0x1f
13099 + *[0-9a-f]*:   ff df d0 1f     bfins pc,pc,0x0,0x1f
13100 + *[0-9a-f]*:   ff df d3 e0     bfins pc,pc,0x1f,0x0
13101 + *[0-9a-f]*:   ef d8 d1 f0     bfins r7,r8,0xf,0x10
13102 + *[0-9a-f]*:   f1 d7 d2 0f     bfins r8,r7,0x10,0xf
13103 +
13104 +[0-9a-f]* <rsubc>:
13105 + *[0-9a-f]*:   fb bf 00 00     rsubeq pc,0
13106 + *[0-9a-f]*:   fb bc 0f ff     rsubal r12,-1
13107 + *[0-9a-f]*:   fb b5 08 80     rsubls r5,-128
13108 + *[0-9a-f]*:   fb b4 07 7f     rsubpl r4,127
13109 + *[0-9a-f]*:   fb be 01 01     rsubne lr,1
13110 + *[0-9a-f]*:   fb bc 08 76     rsubls r12,118
13111 + *[0-9a-f]*:   fb be 0d f4     rsubvc lr,-12
13112 + *[0-9a-f]*:   fb b4 06 f3     rsubmi r4,-13
13113 +
13114 +[0-9a-f]* <addc>:
13115 + *[0-9a-f]*:   ff df e0 0f     addeq pc,pc,pc
13116 + *[0-9a-f]*:   f9 dc ef 0c     addal r12,r12,r12
13117 + *[0-9a-f]*:   eb d5 e8 05     addls r5,r5,r5
13118 + *[0-9a-f]*:   e9 d4 e7 04     addpl r4,r4,r4
13119 + *[0-9a-f]*:   fd de e1 0e     addne lr,lr,lr
13120 + *[0-9a-f]*:   e5 d1 e8 0a     addls r10,r2,r1
13121 + *[0-9a-f]*:   f1 db ed 0c     addvc r12,r8,r11
13122 + *[0-9a-f]*:   ef d0 e6 0a     addmi r10,r7,r0
13123 +
13124 +[0-9a-f]* <subc2>:
13125 + *[0-9a-f]*:   ff df e0 1f     subeq pc,pc,pc
13126 + *[0-9a-f]*:   f9 dc ef 1c     subal r12,r12,r12
13127 + *[0-9a-f]*:   eb d5 e8 15     subls r5,r5,r5
13128 + *[0-9a-f]*:   e9 d4 e7 14     subpl r4,r4,r4
13129 + *[0-9a-f]*:   fd de e1 1e     subne lr,lr,lr
13130 + *[0-9a-f]*:   e5 d1 e8 1a     subls r10,r2,r1
13131 + *[0-9a-f]*:   f1 db ed 1c     subvc r12,r8,r11
13132 + *[0-9a-f]*:   ef d0 e6 1a     submi r10,r7,r0
13133 +
13134 +[0-9a-f]* <andc>:
13135 + *[0-9a-f]*:   ff df e0 2f     andeq pc,pc,pc
13136 + *[0-9a-f]*:   f9 dc ef 2c     andal r12,r12,r12
13137 + *[0-9a-f]*:   eb d5 e8 25     andls r5,r5,r5
13138 + *[0-9a-f]*:   e9 d4 e7 24     andpl r4,r4,r4
13139 + *[0-9a-f]*:   fd de e1 2e     andne lr,lr,lr
13140 + *[0-9a-f]*:   e5 d1 e8 2a     andls r10,r2,r1
13141 + *[0-9a-f]*:   f1 db ed 2c     andvc r12,r8,r11
13142 + *[0-9a-f]*:   ef d0 e6 2a     andmi r10,r7,r0
13143 +
13144 +[0-9a-f]* <orc>:
13145 + *[0-9a-f]*:   ff df e0 3f     oreq pc,pc,pc
13146 + *[0-9a-f]*:   f9 dc ef 3c     oral r12,r12,r12
13147 + *[0-9a-f]*:   eb d5 e8 35     orls r5,r5,r5
13148 + *[0-9a-f]*:   e9 d4 e7 34     orpl r4,r4,r4
13149 + *[0-9a-f]*:   fd de e1 3e     orne lr,lr,lr
13150 + *[0-9a-f]*:   e5 d1 e8 3a     orls r10,r2,r1
13151 + *[0-9a-f]*:   f1 db ed 3c     orvc r12,r8,r11
13152 + *[0-9a-f]*:   ef d0 e6 3a     ormi r10,r7,r0
13153 +
13154 +[0-9a-f]* <eorc>:
13155 + *[0-9a-f]*:   ff df e0 4f     eoreq pc,pc,pc
13156 + *[0-9a-f]*:   f9 dc ef 4c     eoral r12,r12,r12
13157 + *[0-9a-f]*:   eb d5 e8 45     eorls r5,r5,r5
13158 + *[0-9a-f]*:   e9 d4 e7 44     eorpl r4,r4,r4
13159 + *[0-9a-f]*:   fd de e1 4e     eorne lr,lr,lr
13160 + *[0-9a-f]*:   e5 d1 e8 4a     eorls r10,r2,r1
13161 + *[0-9a-f]*:   f1 db ed 4c     eorvc r12,r8,r11
13162 + *[0-9a-f]*:   ef d0 e6 4a     eormi r10,r7,r0
13163 +
13164 +[0-9a-f]* <ldcond>:
13165 + *[0-9a-f]*:   ff ff 01 ff     ld.weq  pc,pc[0x7fc]
13166 + *[0-9a-f]*:   f9 fc f3 ff     ld.shal r12,r12[0x3fe]
13167 + *[0-9a-f]*:   eb f5 84 00     ld.shls r5,r5[0x0]
13168 + *[0-9a-f]*:   e9 f4 79 ff     ld.ubpl r4,r4[0x1ff]
13169 + *[0-9a-f]*:   fd fe 16 00     ld.sbne lr,lr[0x0]
13170 + *[0-9a-f]*:   e5 fa 80 00     ld.wls  r10,r2[0x0]
13171 + *[0-9a-f]*:   f1 fc d3 ff     ld.shvc r12,r8[0x3fe]
13172 + *[0-9a-f]*:   ef fa 68 01     ld.ubmi r10,r7[0x1]
13173 +
13174 +[0-9a-f]* <stcond2>:
13175 + *[0-9a-f]*:   ff ff 0b ff     st.weq pc[0x7fc],pc
13176 + *[0-9a-f]*:   f9 fc fd ff     st.hal r12[0x3fe],r12
13177 + *[0-9a-f]*:   eb f5 8c 00     st.hls r5[0x0],r5
13178 + *[0-9a-f]*:   e9 f4 7f ff     st.bpl r4[0x1ff],r4
13179 + *[0-9a-f]*:   fd fe 1e 00     st.bne lr[0x0],lr
13180 + *[0-9a-f]*:   e5 fa 8a 00     st.wls r2[0x0],r10
13181 + *[0-9a-f]*:   f1 fc dd ff     st.hvc r8[0x3fe],r12
13182 + *[0-9a-f]*:   ef fa 6e 01     st.bmi r7[0x1],r10
13183 +
13184 +[0-9a-f]* <movh>:
13185 + *[0-9a-f]*:   fc 1f ff ff     movh pc,0xffff
13186 + *[0-9a-f]*:   fc 10 00 00     movh r0,0x0
13187 + *[0-9a-f]*:   fc 15 00 01     movh r5,0x1
13188 + *[0-9a-f]*:   fc 1c 7f ff     movh r12,0x7fff
13189 +
13190 --- /dev/null
13191 +++ b/gas/testsuite/gas/avr32/allinsn.exp
13192 @@ -0,0 +1,5 @@
13193 +# AVR32 assembler testsuite. -*- Tcl -*-
13194 +
13195 +if [istarget avr32-*-*] {
13196 +    run_dump_test "allinsn"
13197 +}
13198 --- /dev/null
13199 +++ b/gas/testsuite/gas/avr32/allinsn.s
13200 @@ -0,0 +1,3330 @@
13201 + .data
13202 +foodata: .word 42
13203 + .text
13204 +footext:
13205 +       .text
13206 +       .global ld_d5
13207 +ld_d5:
13208 +       ld.d lr,pc[pc<<3]
13209 +       ld.d r0,r0[r0<<0]
13210 +       ld.d r6,r5[r5<<2]
13211 +       ld.d r4,r4[r4<<1]
13212 +       ld.d lr,lr[lr<<1]
13213 +       ld.d r10,r3[sp<<2]
13214 +       ld.d r8,r10[r6<<2]
13215 +       ld.d r2,r7[r9<<0]
13216 +       .text
13217 +       .global ld_w5
13218 +ld_w5:
13219 +       ld.w pc,pc[pc<<0]
13220 +       ld.w r12,r12[r12<<3]
13221 +       ld.w r5,r5[r5<<2]
13222 +       ld.w r4,r4[r4<<1]
13223 +       ld.w lr,lr[lr<<1]
13224 +       ld.w r2,r9[r9<<0]
13225 +       ld.w r11,r2[r6<<0]
13226 +       ld.w r0,r2[sp<<3]
13227 +       .text
13228 +       .global ld_sh5
13229 +ld_sh5:
13230 +       ld.sh pc,pc[pc<<0]
13231 +       ld.sh r12,r12[r12<<3]
13232 +       ld.sh r5,r5[r5<<2]
13233 +       ld.sh r4,r4[r4<<1]
13234 +       ld.sh lr,lr[lr<<1]
13235 +       ld.sh r11,r0[pc<<2]
13236 +       ld.sh r10,sp[r6<<2]
13237 +       ld.sh r12,r2[r2<<0]
13238 +       .text
13239 +       .global ld_uh5
13240 +ld_uh5:
13241 +       ld.uh pc,pc[pc<<0]
13242 +       ld.uh r12,r12[r12<<3]
13243 +       ld.uh r5,r5[r5<<2]
13244 +       ld.uh r4,r4[r4<<1]
13245 +       ld.uh lr,lr[lr<<1]
13246 +       ld.uh r8,pc[lr<<3]
13247 +       ld.uh r6,r1[pc<<1]
13248 +       ld.uh r6,lr[sp<<1]
13249 +       .text
13250 +       .global ld_sb2
13251 +ld_sb2:
13252 +       ld.sb pc,pc[pc<<0]
13253 +       ld.sb r12,r12[r12<<3]
13254 +       ld.sb r5,r5[r5<<2]
13255 +       ld.sb r4,r4[r4<<1]
13256 +       ld.sb lr,lr[lr<<1]
13257 +       ld.sb r9,r1[pc<<3]
13258 +       ld.sb r0,r3[r11<<1]
13259 +       ld.sb r10,r5[r5<<1]
13260 +       .text
13261 +       .global ld_ub5
13262 +ld_ub5:
13263 +       ld.ub pc,pc[pc<<0]
13264 +       ld.ub r12,r12[r12<<3]
13265 +       ld.ub r5,r5[r5<<2]
13266 +       ld.ub r4,r4[r4<<1]
13267 +       ld.ub lr,lr[lr<<1]
13268 +       ld.ub r6,r12[r7<<3]
13269 +       ld.ub r2,r6[r12<<0]
13270 +       ld.ub r0,r7[r11<<1]
13271 +       .text
13272 +       .global st_d5
13273 +st_d5:
13274 +       st.d pc[pc<<0],r14
13275 +       st.d r12[r12<<3],r12
13276 +       st.d r5[r5<<2],r6
13277 +       st.d r4[r4<<1],r4
13278 +       st.d lr[lr<<1],lr
13279 +       st.d r1[r9<<1],r4
13280 +       st.d r10[r2<<1],r4
13281 +       st.d r12[r6<<0],lr
13282 +       .text
13283 +       .global st_w5
13284 +st_w5:
13285 +       st.w pc[pc<<0],pc
13286 +       st.w r12[r12<<3],r12
13287 +       st.w r5[r5<<2],r5
13288 +       st.w r4[r4<<1],r4
13289 +       st.w lr[lr<<1],lr
13290 +       st.w r1[r10<<0],r3
13291 +       st.w r0[r10<<1],r9
13292 +       st.w r4[r5<<3],pc
13293 +       .text
13294 +       .global st_h5
13295 +st_h5:
13296 +       st.h pc[pc<<0],pc
13297 +       st.h r12[r12<<3],r12
13298 +       st.h r5[r5<<2],r5
13299 +       st.h r4[r4<<1],r4
13300 +       st.h lr[lr<<1],lr
13301 +       st.h r2[r9<<0],r11
13302 +       st.h r5[r1<<2],r12
13303 +       st.h pc[r8<<2],r3
13304 +       .text
13305 +       .global st_b5
13306 +st_b5:
13307 +       st.b pc[pc<<0],pc
13308 +       st.b r12[r12<<3],r12
13309 +       st.b r5[r5<<2],r5
13310 +       st.b r4[r4<<1],r4
13311 +       st.b lr[lr<<1],lr
13312 +       st.b r1[r8<<1],r6
13313 +       st.b lr[lr<<3],r1
13314 +       st.b r5[r0<<2],pc
13315 +       .text
13316 +       .global divs
13317 +divs:
13318 +       divs pc,pc,pc
13319 +       divs r12,r12,r12
13320 +       divs r5,r5,r5
13321 +       divs r4,r4,r4
13322 +       divs lr,lr,lr
13323 +       divs r3,pc,pc
13324 +       divs r9,r12,r2
13325 +       divs r7,r4,r1
13326 +       .text
13327 +       .global add1
13328 +add1:
13329 +       add pc,pc
13330 +       add r12,r12
13331 +       add r5,r5
13332 +       add r4,r4
13333 +       add lr,lr
13334 +       add r12,r9
13335 +       add r6,r3
13336 +       add r10,r12
13337 +       .text
13338 +       .global sub1
13339 +sub1:
13340 +       sub pc,pc
13341 +       sub r12,r12
13342 +       sub r5,r5
13343 +       sub r4,r4
13344 +       sub lr,lr
13345 +       sub lr,r6
13346 +       sub r0,sp
13347 +       sub r6,r12
13348 +       .text
13349 +       .global rsub1
13350 +rsub1:
13351 +       rsub pc,pc
13352 +       rsub r12,r12
13353 +       rsub r5,r5
13354 +       rsub r4,r4
13355 +       rsub lr,lr
13356 +       rsub r11,sp
13357 +       rsub r7,r4
13358 +       rsub r9,r1
13359 +       .text
13360 +       .global cp1
13361 +cp1:
13362 +       cp pc,pc
13363 +       cp r12,r12
13364 +       cp r5,r5
13365 +       cp r4,r4
13366 +       cp lr,lr
13367 +       cp r6,r2
13368 +       cp r0,r9
13369 +       cp r3,sp
13370 +       .text
13371 +       .global or1
13372 +or1:
13373 +       or pc,pc
13374 +       or r12,r12
13375 +       or r5,r5
13376 +       or r4,r4
13377 +       or lr,lr
13378 +       or r4,r9
13379 +       or r11,r4
13380 +       or r4,r0
13381 +       .text
13382 +       .global eor1
13383 +eor1:
13384 +       eor pc,pc
13385 +       eor r12,r12
13386 +       eor r5,r5
13387 +       eor r4,r4
13388 +       eor lr,lr
13389 +       eor r12,r11
13390 +       eor r0,r1
13391 +       eor r5,pc
13392 +       .text
13393 +       .global and1
13394 +and1:
13395 +       and pc,pc
13396 +       and r12,r12
13397 +       and r5,r5
13398 +       and r4,r4
13399 +       and lr,lr
13400 +       and r8,r1
13401 +       and r0,sp
13402 +       and r10,r5
13403 +       .text
13404 +       .global tst
13405 +tst:
13406 +       tst pc,pc
13407 +       tst r12,r12
13408 +       tst r5,r5
13409 +       tst r4,r4
13410 +       tst lr,lr
13411 +       tst r0,r12
13412 +       tst r10,r6
13413 +       tst sp,r4
13414 +       .text
13415 +       .global andn
13416 +andn:
13417 +       andn pc,pc
13418 +       andn r12,r12
13419 +       andn r5,r5
13420 +       andn r4,r4
13421 +       andn lr,lr
13422 +       andn r9,r12
13423 +       andn r11,sp
13424 +       andn r12,r5
13425 +       .text
13426 +       .global mov3
13427 +mov3:
13428 +       mov pc,pc
13429 +       mov r12,r12
13430 +       mov r5,r5
13431 +       mov r4,r4
13432 +       mov lr,lr
13433 +       mov r5,r9
13434 +       mov r11,r11
13435 +       mov r2,lr
13436 +       .text
13437 +       .global st_w1
13438 +st_w1:
13439 +       st.w pc++,pc
13440 +       st.w r12++,r12
13441 +       st.w r5++,r5
13442 +       st.w r4++,r4
13443 +       st.w lr++,lr
13444 +       st.w r1++,r11
13445 +       st.w sp++,r0
13446 +       st.w sp++,r1
13447 +       .text
13448 +       .global st_h1
13449 +st_h1:
13450 +       st.h pc++,pc
13451 +       st.h r12++,r12
13452 +       st.h r5++,r5
13453 +       st.h r4++,r4
13454 +       st.h lr++,lr
13455 +       st.h r12++,sp
13456 +       st.h r7++,lr
13457 +       st.h r7++,r4
13458 +       .text
13459 +       .global st_b1
13460 +st_b1:
13461 +       st.b pc++,pc
13462 +       st.b r12++,r12
13463 +       st.b r5++,r5
13464 +       st.b r4++,r4
13465 +       st.b lr++,lr
13466 +       st.b r9++,sp
13467 +       st.b r1++,sp
13468 +       st.b r0++,r4
13469 +       .text
13470 +       .global st_w2
13471 +st_w2:
13472 +       st.w --pc,pc
13473 +       st.w --r12,r12
13474 +       st.w --r5,r5
13475 +       st.w --r4,r4
13476 +       st.w --lr,lr
13477 +       st.w --r1,r7
13478 +       st.w --r3,r9
13479 +       st.w --r5,r5
13480 +       .text
13481 +       .global st_h2
13482 +st_h2:
13483 +       st.h --pc,pc
13484 +       st.h --r12,r12
13485 +       st.h --r5,r5
13486 +       st.h --r4,r4
13487 +       st.h --lr,lr
13488 +       st.h --r5,r7
13489 +       st.h --r8,r8
13490 +       st.h --r7,r2
13491 +       .text
13492 +       .global st_b2
13493 +st_b2:
13494 +       st.b --pc,pc
13495 +       st.b --r12,r12
13496 +       st.b --r5,r5
13497 +       st.b --r4,r4
13498 +       st.b --lr,lr
13499 +       st.b --sp,sp
13500 +       st.b --sp,r11
13501 +       st.b --r4,r5
13502 +       .text
13503 +       .global ld_w1
13504 +ld_w1:
13505 +       ld.w pc,pc++
13506 +       ld.w r12,r12++
13507 +       ld.w r5,r5++
13508 +       ld.w r4,r4++
13509 +       ld.w lr,lr++
13510 +       ld.w r3,r7++
13511 +       ld.w r3,lr++
13512 +       ld.w r12,r5++
13513 +       .text
13514 +       .global ld_sh1
13515 +ld_sh1:
13516 +       ld.sh pc,pc++
13517 +       ld.sh r12,r12++
13518 +       ld.sh r5,r5++
13519 +       ld.sh r4,r4++
13520 +       ld.sh lr,lr++
13521 +       ld.sh r11,r2++
13522 +       ld.sh r2,r8++
13523 +       ld.sh r7,r6++
13524 +       .text
13525 +       .global ld_uh1
13526 +ld_uh1:
13527 +       ld.uh pc,pc++
13528 +       ld.uh r12,r12++
13529 +       ld.uh r5,r5++
13530 +       ld.uh r4,r4++
13531 +       ld.uh lr,lr++
13532 +       ld.uh r6,r7++
13533 +       ld.uh r10,r11++
13534 +       ld.uh lr,r4++
13535 +       .text
13536 +       .global ld_ub1
13537 +ld_ub1:
13538 +       ld.ub pc,pc++
13539 +       ld.ub r12,r12++
13540 +       ld.ub r5,r5++
13541 +       ld.ub r4,r4++
13542 +       ld.ub lr,lr++
13543 +       ld.ub r8,lr++
13544 +       ld.ub r12,r12++
13545 +       ld.ub r11,r10++
13546 +       .text
13547 +       .global ld_w2
13548 +ld_w2:
13549 +       ld.w pc,--pc
13550 +       ld.w r12,--r12
13551 +       ld.w r5,--r5
13552 +       ld.w r4,--r4
13553 +       ld.w lr,--lr
13554 +       ld.w r10,--lr
13555 +       ld.w r12,--r9
13556 +       ld.w r6,--r5
13557 +       .text
13558 +       .global ld_sh2
13559 +ld_sh2:
13560 +       ld.sh pc,--pc
13561 +       ld.sh r12,--r12
13562 +       ld.sh r5,--r5
13563 +       ld.sh r4,--r4
13564 +       ld.sh lr,--lr
13565 +       ld.sh pc,--r10
13566 +       ld.sh r6,--r3
13567 +       ld.sh r4,--r6
13568 +       .text
13569 +       .global ld_uh2
13570 +ld_uh2:
13571 +       ld.uh pc,--pc
13572 +       ld.uh r12,--r12
13573 +       ld.uh r5,--r5
13574 +       ld.uh r4,--r4
13575 +       ld.uh lr,--lr
13576 +       ld.uh r3,--r2
13577 +       ld.uh r1,--r0
13578 +       ld.uh r2,--r9
13579 +       .text
13580 +       .global ld_ub2
13581 +ld_ub2:
13582 +       ld.ub pc,--pc
13583 +       ld.ub r12,--r12
13584 +       ld.ub r5,--r5
13585 +       ld.ub r4,--r4
13586 +       ld.ub lr,--lr
13587 +       ld.ub r1,--r1
13588 +       ld.ub r0,--r6
13589 +       ld.ub r2,--r7
13590 +       .text
13591 +       .global ld_ub3
13592 +ld_ub3:
13593 +       ld.ub pc,pc[0]
13594 +       ld.ub r12,r12[7]
13595 +       ld.ub r5,r5[4]
13596 +       ld.ub r4,r4[3]
13597 +       ld.ub lr,lr[1]
13598 +       ld.ub r6,r9[6]
13599 +       ld.ub r2,lr[4]
13600 +       ld.ub r1,r8[0]
13601 +       .text
13602 +       .global sub3_sp
13603 +sub3_sp:
13604 +       sub sp,0
13605 +       sub sp,-4
13606 +       sub sp,-512
13607 +       sub sp,508
13608 +       sub sp,4
13609 +       sub sp,44
13610 +       sub sp,8
13611 +       sub sp,348
13612 +       .text
13613 +       .global sub3
13614 +sub3:
13615 +       sub pc,0
13616 +       sub r12,-1
13617 +       sub r5,-128
13618 +       sub r4,127
13619 +       sub lr,1
13620 +       sub r6,-41
13621 +       sub r4,37
13622 +       sub r12,56
13623 +       .text
13624 +       .global mov1
13625 +mov1:
13626 +       mov pc,0
13627 +       mov r12,-1
13628 +       mov r5,-128
13629 +       mov r4,127
13630 +       mov lr,1
13631 +       mov pc,14
13632 +       mov r6,-100
13633 +       mov lr,-122
13634 +       .text
13635 +       .global lddsp
13636 +lddsp:
13637 +       lddsp pc,sp[0]
13638 +       lddsp r12,sp[508]
13639 +       lddsp r5,sp[256]
13640 +       lddsp r4,sp[252]
13641 +       lddsp lr,sp[4]
13642 +       lddsp lr,sp[256]
13643 +       lddsp r12,sp[20]
13644 +       lddsp r9,sp[472]
13645 +       .text
13646 +       .global lddpc
13647 +lddpc:
13648 +       lddpc pc,pc[0]
13649 +       lddpc r0,pc[508]
13650 +       lddpc r8,pc[256]
13651 +       lddpc r7,pc[252]
13652 +       lddpc lr,pc[4]
13653 +       lddpc sp,pc[472]
13654 +       lddpc r6,pc[120]
13655 +       lddpc r11,pc[28]
13656 +       .text
13657 +       .global stdsp
13658 +stdsp:
13659 +       stdsp sp[0],pc
13660 +       stdsp sp[508],r12
13661 +       stdsp sp[256],r5
13662 +       stdsp sp[252],r4
13663 +       stdsp sp[4],lr
13664 +       stdsp sp[304],pc
13665 +       stdsp sp[256],r0
13666 +       stdsp sp[336],r5
13667 +       .text
13668 +       .global cp2
13669 +cp2:
13670 +       cp pc,0
13671 +       cp r12,-1
13672 +       cp r5,-32
13673 +       cp r4,31
13674 +       cp lr,1
13675 +       cp r8,3
13676 +       cp lr,16
13677 +       cp r7,-26
13678 +       .text
13679 +       .global acr
13680 +acr:
13681 +       acr pc
13682 +       acr r12
13683 +       acr r5
13684 +       acr r4
13685 +       acr lr
13686 +       acr r2
13687 +       acr r12
13688 +       acr pc
13689 +       .text
13690 +       .global scr
13691 +scr:
13692 +       scr pc
13693 +       scr r12
13694 +       scr r5
13695 +       scr r4
13696 +       scr lr
13697 +       scr pc
13698 +       scr r6
13699 +       scr r1
13700 +       .text
13701 +       .global cpc0
13702 +cpc0:
13703 +       cpc pc
13704 +       cpc r12
13705 +       cpc r5
13706 +       cpc r4
13707 +       cpc lr
13708 +       cpc pc
13709 +       cpc r4
13710 +       cpc r9
13711 +       .text
13712 +       .global neg
13713 +neg:
13714 +       neg pc
13715 +       neg r12
13716 +       neg r5
13717 +       neg r4
13718 +       neg lr
13719 +       neg r7
13720 +       neg r1
13721 +       neg r9
13722 +       .text
13723 +       .global abs
13724 +abs:
13725 +       abs pc
13726 +       abs r12
13727 +       abs r5
13728 +       abs r4
13729 +       abs lr
13730 +       abs r6
13731 +       abs r6
13732 +       abs r4
13733 +       .text
13734 +       .global castu_b
13735 +castu_b:
13736 +       castu.b pc
13737 +       castu.b r12
13738 +       castu.b r5
13739 +       castu.b r4
13740 +       castu.b lr
13741 +       castu.b r7
13742 +       castu.b sp
13743 +       castu.b r9
13744 +       .text
13745 +       .global casts_b
13746 +casts_b:
13747 +       casts.b pc
13748 +       casts.b r12
13749 +       casts.b r5
13750 +       casts.b r4
13751 +       casts.b lr
13752 +       casts.b r11
13753 +       casts.b r1
13754 +       casts.b r10
13755 +       .text
13756 +       .global castu_h
13757 +castu_h:
13758 +       castu.h pc
13759 +       castu.h r12
13760 +       castu.h r5
13761 +       castu.h r4
13762 +       castu.h lr
13763 +       castu.h r10
13764 +       castu.h r11
13765 +       castu.h r1
13766 +       .text
13767 +       .global casts_h
13768 +casts_h:
13769 +       casts.h pc
13770 +       casts.h r12
13771 +       casts.h r5
13772 +       casts.h r4
13773 +       casts.h lr
13774 +       casts.h r0
13775 +       casts.h r5
13776 +       casts.h r9
13777 +       .text
13778 +       .global brev
13779 +brev:
13780 +       brev pc
13781 +       brev r12
13782 +       brev r5
13783 +       brev r4
13784 +       brev lr
13785 +       brev r5
13786 +       brev r10
13787 +       brev r8
13788 +       .text
13789 +       .global swap_h
13790 +swap_h:
13791 +       swap.h pc
13792 +       swap.h r12
13793 +       swap.h r5
13794 +       swap.h r4
13795 +       swap.h lr
13796 +       swap.h r7
13797 +       swap.h r0
13798 +       swap.h r8
13799 +       .text
13800 +       .global swap_b
13801 +swap_b:
13802 +       swap.b pc
13803 +       swap.b r12
13804 +       swap.b r5
13805 +       swap.b r4
13806 +       swap.b lr
13807 +       swap.b r10
13808 +       swap.b r12
13809 +       swap.b r1
13810 +       .text
13811 +       .global swap_bh
13812 +swap_bh:
13813 +       swap.bh pc
13814 +       swap.bh r12
13815 +       swap.bh r5
13816 +       swap.bh r4
13817 +       swap.bh lr
13818 +       swap.bh r9
13819 +       swap.bh r4
13820 +       swap.bh r1
13821 +       .text
13822 +       .global One_s_compliment
13823 +One_s_compliment:
13824 +       com pc
13825 +       com r12
13826 +       com r5
13827 +       com r4
13828 +       com lr
13829 +       com r2
13830 +       com r2
13831 +       com r7
13832 +       .text
13833 +       .global tnbz
13834 +tnbz:
13835 +       tnbz pc
13836 +       tnbz r12
13837 +       tnbz r5
13838 +       tnbz r4
13839 +       tnbz lr
13840 +       tnbz r8
13841 +       tnbz r12
13842 +       tnbz pc
13843 +       .text
13844 +       .global rol
13845 +rol:
13846 +       rol pc
13847 +       rol r12
13848 +       rol r5
13849 +       rol r4
13850 +       rol lr
13851 +       rol r10
13852 +       rol r9
13853 +       rol r5
13854 +       .text
13855 +       .global ror
13856 +ror:
13857 +       ror pc
13858 +       ror r12
13859 +       ror r5
13860 +       ror r4
13861 +       ror lr
13862 +       ror r8
13863 +       ror r4
13864 +       ror r7
13865 +       .text
13866 +       .global icall
13867 +icall:
13868 +       icall pc
13869 +       icall r12
13870 +       icall r5
13871 +       icall r4
13872 +       icall lr
13873 +       icall r3
13874 +       icall r1
13875 +       icall r3
13876 +       .text
13877 +       .global mustr
13878 +mustr:
13879 +       mustr pc
13880 +       mustr r12
13881 +       mustr r5
13882 +       mustr r4
13883 +       mustr lr
13884 +       mustr r1
13885 +       mustr r4
13886 +       mustr r12
13887 +       .text
13888 +       .global musfr
13889 +musfr:
13890 +       musfr pc
13891 +       musfr r12
13892 +       musfr r5
13893 +       musfr r4
13894 +       musfr lr
13895 +       musfr r11
13896 +       musfr r12
13897 +       musfr r2
13898 +       .text
13899 +       .global ret_cond
13900 +ret_cond:
13901 +       reteq pc
13902 +       retal r12
13903 +       retls r5
13904 +       retpl r4
13905 +       retne lr
13906 +       retgt r0
13907 +       retgt r12
13908 +       retge r10
13909 +       .text
13910 +       .global sr_cond
13911 +sr_cond:
13912 +       sreq pc
13913 +       sral r12
13914 +       srls r5
13915 +       srpl r4
13916 +       srne lr
13917 +       srlt r0
13918 +       sral sp
13919 +       srge r9
13920 +       .text
13921 +       .global ld_w3
13922 +ld_w3:
13923 +       ld.w pc,pc[0]
13924 +       ld.w r12,r12[124]
13925 +       ld.w r5,r5[64]
13926 +       ld.w r4,r4[60]
13927 +       ld.w lr,lr[4]
13928 +       ld.w sp,r2[52]
13929 +       ld.w r9,r1[8]
13930 +       ld.w r5,sp[60]
13931 +       .text
13932 +       .global ld_sh3
13933 +ld_sh3:
13934 +       ld.sh pc,pc[0]
13935 +       ld.sh r12,r12[14]
13936 +       ld.sh r5,r5[8]
13937 +       ld.sh r4,r4[6]
13938 +       ld.sh lr,lr[2]
13939 +       ld.sh r4,r2[8]
13940 +       ld.sh sp,lr[10]
13941 +       ld.sh r2,r11[2]
13942 +       .text
13943 +       .global ld_uh3
13944 +ld_uh3:
13945 +       ld.uh pc,pc[0]
13946 +       ld.uh r12,r12[14]
13947 +       ld.uh r5,r5[8]
13948 +       ld.uh r4,r4[6]
13949 +       ld.uh lr,lr[2]
13950 +       ld.uh r10,r0[10]
13951 +       ld.uh r8,r11[8]
13952 +       ld.uh r10,r2[12]
13953 +       .text
13954 +       .global st_w3
13955 +st_w3:
13956 +       st.w pc[0],pc
13957 +       st.w r12[60],r12
13958 +       st.w r5[32],r5
13959 +       st.w r4[28],r4
13960 +       st.w lr[4],lr
13961 +       st.w r7[44],r11
13962 +       st.w r2[24],r6
13963 +       st.w r4[12],r9
13964 +       .text
13965 +       .global st_h3
13966 +st_h3:
13967 +       st.h pc[0],pc
13968 +       st.h r12[14],r12
13969 +       st.h r5[8],r5
13970 +       st.h r4[6],r4
13971 +       st.h lr[2],lr
13972 +       st.h lr[10],r12
13973 +       st.h r6[4],r0
13974 +       st.h r5[12],sp
13975 +       .text
13976 +       .global st_b3
13977 +st_b3:
13978 +       st.b pc[0],pc
13979 +       st.b r12[7],r12
13980 +       st.b r5[4],r5
13981 +       st.b r4[3],r4
13982 +       st.b lr[1],lr
13983 +       st.b r12[6],r9
13984 +       st.b r2[3],lr
13985 +       st.b r1[3],r11
13986 +       .text
13987 +       .global ldd
13988 +ldd:
13989 +       ld.d r0,pc
13990 +       ld.d r14,r12
13991 +       ld.d r8,r5
13992 +       ld.d r6,r4
13993 +       ld.d r2,lr
13994 +       ld.d r14,r7
13995 +       ld.d r4,r4
13996 +       ld.d r14,pc
13997 +       .text
13998 +       .global ldd_postinc
13999 +ldd_postinc:
14000 +       ld.d r0,pc++
14001 +       ld.d r14,r12++
14002 +       ld.d r8,r5++
14003 +       ld.d r6,r4++
14004 +       ld.d r2,lr++
14005 +       ld.d r14,r5++
14006 +       ld.d r12,r11++
14007 +       ld.d r2,r12++
14008 +       .text
14009 +       .global ldd_predec
14010 +ldd_predec:
14011 +       ld.d r0,--pc
14012 +       ld.d r14,--r12
14013 +       ld.d r8,--r5
14014 +       ld.d r6,--r4
14015 +       ld.d r2,--lr
14016 +       ld.d r8,--r0
14017 +       ld.d r10,--pc
14018 +       ld.d r2,--r4
14019 +       .text
14020 +       .global std
14021 +std:
14022 +       st.d pc,r0
14023 +       st.d r12,r14
14024 +       st.d r5,r8
14025 +       st.d r4,r6
14026 +       st.d lr,r2
14027 +       st.d r0,r12
14028 +       st.d sp,r4
14029 +       st.d r12,r12
14030 +       .text
14031 +       .global std_postinc
14032 +std_postinc:
14033 +       st.d pc++,r0
14034 +       st.d r12++,r14
14035 +       st.d r5++,r8
14036 +       st.d r4++,r6
14037 +       st.d lr++,r2
14038 +       st.d sp++,r6
14039 +       st.d r10++,r6
14040 +       st.d r7++,r2
14041 +       .text
14042 +       .global std_predec
14043 +std_predec:
14044 +       st.d --pc,r0
14045 +       st.d --r12,r14
14046 +       st.d --r5,r8
14047 +       st.d --r4,r6
14048 +       st.d --lr,r2
14049 +       st.d --r3,r6
14050 +       st.d --lr,r2
14051 +       st.d --r0,r4
14052 +       .text
14053 +       .global mul
14054 +mul:
14055 +       mul pc,pc
14056 +       mul r12,r12
14057 +       mul r5,r5
14058 +       mul r4,r4
14059 +       mul lr,lr
14060 +       mul r10,lr
14061 +       mul r0,r8
14062 +       mul r8,r5
14063 +       .text
14064 +       .global asr_imm5
14065 +asr_imm5:
14066 +       asr pc,0
14067 +       asr r12,31
14068 +       asr r5,16
14069 +       asr r4,15
14070 +       asr lr,1
14071 +       asr r6,23
14072 +       asr r6,18
14073 +       asr r5,8
14074 +       .text
14075 +       .global lsl_imm5
14076 +lsl_imm5:
14077 +       lsl pc,0
14078 +       lsl r12,31
14079 +       lsl r5,16
14080 +       lsl r4,15
14081 +       lsl lr,1
14082 +       lsl r12,13
14083 +       lsl r6,16
14084 +       lsl r1,25
14085 +       .text
14086 +       .global lsr_imm5
14087 +lsr_imm5:
14088 +       lsr pc,0
14089 +       lsr r12,31
14090 +       lsr r5,16
14091 +       lsr r4,15
14092 +       lsr lr,1
14093 +       lsr r0,1
14094 +       lsr r8,10
14095 +       lsr r7,26
14096 +       .text
14097 +       .global sbr
14098 +sbr:
14099 +       sbr pc,0
14100 +       sbr r12,31
14101 +       sbr r5,16
14102 +       sbr r4,15
14103 +       sbr lr,1
14104 +       sbr r8,31
14105 +       sbr r6,22
14106 +       sbr r1,23
14107 +       .text
14108 +       .global cbr
14109 +cbr:
14110 +       cbr pc,0
14111 +       cbr r12,31
14112 +       cbr r5,16
14113 +       cbr r4,15
14114 +       cbr lr,1
14115 +       cbr r12,10
14116 +       cbr r7,22
14117 +       cbr r8,9
14118 +       .text
14119 +       .global brc1
14120 +brc1:
14121 +       breq 0
14122 +       brpl -2
14123 +       brge -256
14124 +       brcs 254
14125 +       brne 2
14126 +       brcs 230
14127 +       breq -18
14128 +       breq 12
14129 +       .text
14130 +       .global rjmp
14131 +rjmp:
14132 +       rjmp 0
14133 +       rjmp -2
14134 +       rjmp -1024
14135 +       rjmp 1022
14136 +       rjmp 2
14137 +       rjmp -962
14138 +       rjmp 14
14139 +       rjmp -516
14140 +       .text
14141 +       .global rcall1
14142 +rcall1:
14143 +       rcall 0
14144 +       rcall -2
14145 +       rcall -1024
14146 +       rcall 1022
14147 +       rcall 2
14148 +       rcall 216
14149 +       rcall -530
14150 +       rcall -972
14151 +       .text
14152 +       .global acall
14153 +acall:
14154 +       acall 0
14155 +       acall 1020
14156 +       acall 512
14157 +       acall 508
14158 +       acall 4
14159 +       acall 356
14160 +       acall 304
14161 +       acall 172
14162 +       .text
14163 +       .global scall
14164 +scall:
14165 +       scall
14166 +       scall
14167 +       scall
14168 +       scall
14169 +       scall
14170 +       scall
14171 +       scall
14172 +       scall
14173 +       .text
14174 +       .global popm
14175 +popm:
14176 +       /* popm with no argument fails currently */
14177 +       popm pc
14178 +       popm r0-r11,pc,r12=-1
14179 +       popm lr
14180 +       popm r0-r11,pc,r12=1
14181 +       popm r0-r3
14182 +       popm r4-r10,pc
14183 +       popm r0-r3,r11,pc,r12=0
14184 +       popm r0-r7,r10-r12,lr
14185 +       .text
14186 +       .global pushm
14187 +pushm:
14188 +       pushm pc
14189 +       pushm r0-r12,lr,pc
14190 +       pushm pc
14191 +       pushm r0-r12,lr
14192 +       pushm r0-r3
14193 +       pushm r8-r10,lr,pc
14194 +       pushm r0-r3,r10
14195 +       pushm r8-r9,r12
14196 +       .text
14197 +       .global popm_n
14198 +popm_n:
14199 +       popm pc
14200 +       popm r0-r11,pc,r12=-1
14201 +       popm lr
14202 +       popm r0-r11,pc,r12=1
14203 +       popm r0-r3
14204 +       popm r4-r10,pc
14205 +       popm r0-r3,r11,pc,r12=0
14206 +       popm r0-r7,r10-r12,lr
14207 +       .text
14208 +       .global pushm_n
14209 +pushm_n:
14210 +       pushm pc
14211 +       pushm r0-r12,lr,pc
14212 +       pushm pc
14213 +       pushm r0-r12,lr
14214 +       pushm r0-r3
14215 +       pushm r8-r10,lr,pc
14216 +       pushm r0-r3,r10
14217 +       pushm r8-r9,r12
14218 +       .text
14219 +       .global csrfcz
14220 +csrfcz:
14221 +       csrfcz 0
14222 +       csrfcz 31
14223 +       csrfcz 16
14224 +       csrfcz 15
14225 +       csrfcz 1
14226 +       csrfcz 5
14227 +       csrfcz 13
14228 +       csrfcz 23
14229 +       .text
14230 +       .global ssrf
14231 +ssrf:
14232 +       ssrf 0
14233 +       ssrf 31
14234 +       ssrf 16
14235 +       ssrf 15
14236 +       ssrf 1
14237 +       ssrf 29
14238 +       ssrf 13
14239 +       ssrf 13
14240 +       .text
14241 +       .global csrf
14242 +csrf:
14243 +       csrf 0
14244 +       csrf 31
14245 +       csrf 16
14246 +       csrf 15
14247 +       csrf 1
14248 +       csrf 10
14249 +       csrf 15
14250 +       csrf 11
14251 +       .text
14252 +       .global rete
14253 +rete:
14254 +       rete
14255 +       .text
14256 +       .global rets
14257 +rets:
14258 +       rets
14259 +       .text
14260 +       .global retd
14261 +retd:
14262 +       retd
14263 +       .text
14264 +       .global retj
14265 +retj:
14266 +       retj
14267 +       .text
14268 +       .global tlbr
14269 +tlbr:
14270 +       tlbr
14271 +       .text
14272 +       .global tlbs
14273 +tlbs:
14274 +       tlbs
14275 +       .text
14276 +       .global tlbw
14277 +tlbw:
14278 +       tlbw
14279 +       .text
14280 +       .global breakpoint
14281 +breakpoint:
14282 +       breakpoint
14283 +       .text
14284 +       .global incjosp
14285 +incjosp:
14286 +       incjosp 1
14287 +       incjosp 2
14288 +       incjosp 3
14289 +       incjosp 4
14290 +       incjosp -4
14291 +       incjosp -3
14292 +       incjosp -2
14293 +       incjosp -1
14294 +       .text
14295 +       .global nop
14296 +nop:
14297 +       nop
14298 +       .text
14299 +       .global popjc
14300 +popjc:
14301 +       popjc
14302 +       .text
14303 +       .global pushjc
14304 +pushjc:
14305 +       pushjc
14306 +       .text
14307 +       .global add2
14308 +add2:
14309 +       add pc,pc,pc<<0
14310 +       add r12,r12,r12<<3
14311 +       add r5,r5,r5<<2
14312 +       add r4,r4,r4<<1
14313 +       add lr,lr,lr<<1
14314 +       add r0,r12,r0<<1
14315 +       add r9,r12,r4<<0
14316 +       add r12,r12,r7<<2
14317 +       .text
14318 +       .global sub2
14319 +sub2:
14320 +       sub pc,pc,pc<<0
14321 +       sub r12,r12,r12<<3
14322 +       sub r5,r5,r5<<2
14323 +       sub r4,r4,r4<<1
14324 +       sub lr,lr,lr<<1
14325 +       sub sp,r3,r4<<0
14326 +       sub r3,r7,r3<<0
14327 +       sub sp,r10,sp<<1
14328 +       .text
14329 +       .global divu
14330 +divu:
14331 +       divu pc,pc,pc
14332 +       divu r12,r12,r12
14333 +       divu r5,r5,r5
14334 +       divu r4,r4,r4
14335 +       divu lr,lr,lr
14336 +       divu sp,r4,pc
14337 +       divu r5,r5,sp
14338 +       divu r10,sp,r0
14339 +       .text
14340 +       .global addhh_w
14341 +addhh_w:
14342 +       addhh.w pc,pc:b,pc:b
14343 +       addhh.w r12,r12:t,r12:t
14344 +       addhh.w r5,r5:t,r5:t
14345 +       addhh.w r4,r4:b,r4:b
14346 +       addhh.w lr,lr:t,lr:t
14347 +       addhh.w r0,r0:b,r3:b
14348 +       addhh.w lr,r12:t,r7:b
14349 +       addhh.w r3,r10:t,r2:b
14350 +       .text
14351 +       .global subhh_w
14352 +subhh_w:
14353 +       subhh.w pc,pc:b,pc:b
14354 +       subhh.w r12,r12:t,r12:t
14355 +       subhh.w r5,r5:t,r5:t
14356 +       subhh.w r4,r4:b,r4:b
14357 +       subhh.w lr,lr:t,lr:t
14358 +       subhh.w r10,r1:t,r7:b
14359 +       subhh.w pc,r10:t,lr:t
14360 +       subhh.w r3,r0:t,r12:b
14361 +       .text
14362 +       .global adc
14363 +adc:
14364 +       adc pc,pc,pc
14365 +       adc r12,r12,r12
14366 +       adc r5,r5,r5
14367 +       adc r4,r4,r4
14368 +       adc lr,lr,lr
14369 +       adc r4,r0,r7
14370 +       adc sp,r4,r3
14371 +       adc r2,r12,r0
14372 +       .text
14373 +       .global sbc
14374 +sbc:
14375 +       sbc pc,pc,pc
14376 +       sbc r12,r12,r12
14377 +       sbc r5,r5,r5
14378 +       sbc r4,r4,r4
14379 +       sbc lr,lr,lr
14380 +       sbc r6,r7,r9
14381 +       sbc r0,r8,r5
14382 +       sbc r1,r0,r4
14383 +       .text
14384 +       .global mul_2
14385 +mul_2:
14386 +       mul pc,pc,pc
14387 +       mul r12,r12,r12
14388 +       mul r5,r5,r5
14389 +       mul r4,r4,r4
14390 +       mul lr,lr,lr
14391 +       mul pc,r0,r0
14392 +       mul r8,pc,lr
14393 +       mul r4,r12,pc
14394 +       .text
14395 +       .global mac
14396 +mac:
14397 +       mac pc,pc,pc
14398 +       mac r12,r12,r12
14399 +       mac r5,r5,r5
14400 +       mac r4,r4,r4
14401 +       mac lr,lr,lr
14402 +       mac r10,r4,r0
14403 +       mac r7,lr,r0
14404 +       mac r2,r9,r12
14405 +       .text
14406 +       .global mulsd
14407 +mulsd:
14408 +       muls.d pc,pc,pc
14409 +       muls.d r12,r12,r12
14410 +       muls.d r5,r5,r5
14411 +       muls.d r4,r4,r4
14412 +       muls.d lr,lr,lr
14413 +       muls.d r2,r8,lr
14414 +       muls.d r4,r0,r11
14415 +       muls.d r5,lr,r6
14416 +       .text
14417 +       .global macsd
14418 +macsd:
14419 +       macs.d r0,pc,pc
14420 +       macs.d r14,r12,r12
14421 +       macs.d r8,r5,r5
14422 +       macs.d r6,r4,r4
14423 +       macs.d r2,lr,lr
14424 +       macs.d r8,r1,r9
14425 +       macs.d r14,r8,r8
14426 +       macs.d r4,r3,r12
14427 +       .text
14428 +       .global mulud
14429 +mulud:
14430 +       mulu.d r0,pc,pc
14431 +       mulu.d r14,r12,r12
14432 +       mulu.d r8,r5,r5
14433 +       mulu.d r6,r4,r4
14434 +       mulu.d r2,lr,lr
14435 +       mulu.d r6,r5,r0
14436 +       mulu.d r4,r6,r1
14437 +       mulu.d r8,r8,r2
14438 +       .text
14439 +       .global macud
14440 +macud:
14441 +       macu.d r0,pc,pc
14442 +       macu.d r14,r12,r12
14443 +       macu.d r8,r5,r5
14444 +       macu.d r6,r4,r4
14445 +       macu.d r2,lr,lr
14446 +       macu.d r6,sp,r11
14447 +       macu.d r2,r4,r8
14448 +       macu.d r6,r10,r9
14449 +       .text
14450 +       .global asr_1
14451 +asr_1:
14452 +       asr pc,pc,pc
14453 +       asr r12,r12,r12
14454 +       asr r5,r5,r5
14455 +       asr r4,r4,r4
14456 +       asr lr,lr,lr
14457 +       asr pc,r6,pc
14458 +       asr r0,r6,r12
14459 +       asr r4,sp,r0
14460 +       .text
14461 +       .global lsl_1
14462 +lsl_1:
14463 +       lsl pc,pc,pc
14464 +       lsl r12,r12,r12
14465 +       lsl r5,r5,r5
14466 +       lsl r4,r4,r4
14467 +       lsl lr,lr,lr
14468 +       lsl lr,r5,lr
14469 +       lsl r5,pc,r3
14470 +       lsl r1,pc,r9
14471 +       .text
14472 +       .global lsr_1
14473 +lsr_1:
14474 +       lsr pc,pc,pc
14475 +       lsr r12,r12,r12
14476 +       lsr r5,r5,r5
14477 +       lsr r4,r4,r4
14478 +       lsr lr,lr,lr
14479 +       lsr r2,r4,r1
14480 +       lsr r5,r1,r6
14481 +       lsr sp,r6,r7
14482 +       .text
14483 +       .global xchg
14484 +xchg:
14485 +       xchg pc,pc,pc
14486 +       xchg r12,r12,r12
14487 +       xchg r5,r5,r5
14488 +       xchg r4,r4,r4
14489 +       xchg lr,lr,lr
14490 +       xchg lr,r4,sp
14491 +       xchg r1,r5,r12
14492 +       xchg lr,r12,r0
14493 +       .text
14494 +       .global max
14495 +max:
14496 +       max pc,pc,pc
14497 +       max r12,r12,r12
14498 +       max r5,r5,r5
14499 +       max r4,r4,r4
14500 +       max lr,lr,lr
14501 +       max lr,r2,sp
14502 +       max r4,r10,r9
14503 +       max lr,r9,lr
14504 +       .text
14505 +       .global min
14506 +min:
14507 +       min pc,pc,pc
14508 +       min r12,r12,r12
14509 +       min r5,r5,r5
14510 +       min r4,r4,r4
14511 +       min lr,lr,lr
14512 +       min r9,r7,r8
14513 +       min sp,r5,r5
14514 +       min r4,r1,r4
14515 +       .text
14516 +       .global addabs
14517 +addabs:
14518 +       addabs pc,pc,pc
14519 +       addabs r12,r12,r12
14520 +       addabs r5,r5,r5
14521 +       addabs r4,r4,r4
14522 +       addabs lr,lr,lr
14523 +       addabs r7,r10,r0
14524 +       addabs r9,r9,r7
14525 +       addabs r2,r8,r12
14526 +       .text
14527 +       .global mulnhh_w
14528 +mulnhh_w:
14529 +       mulnhh.w pc,pc:b,pc:b
14530 +       mulnhh.w r12,r12:t,r12:t
14531 +       mulnhh.w r5,r5:t,r5:t
14532 +       mulnhh.w r4,r4:b,r4:b
14533 +       mulnhh.w lr,lr:t,lr:t
14534 +       mulnhh.w r11,sp:t,r9:b
14535 +       mulnhh.w sp,r4:b,lr:t
14536 +       mulnhh.w r12,r2:t,r11:b
14537 +       .text
14538 +       .global mulnwh_d
14539 +mulnwh_d:
14540 +       mulnwh.d r0,pc,pc:b
14541 +       mulnwh.d r14,r12,r12:t
14542 +       mulnwh.d r8,r5,r5:t
14543 +       mulnwh.d r6,r4,r4:b
14544 +       mulnwh.d r2,lr,lr:t
14545 +       mulnwh.d r14,r3,r2:t
14546 +       mulnwh.d r4,r5,r9:b
14547 +       mulnwh.d r12,r4,r4:t
14548 +       .text
14549 +       .global machh_w
14550 +machh_w:
14551 +       machh.w pc,pc:b,pc:b
14552 +       machh.w r12,r12:t,r12:t
14553 +       machh.w r5,r5:t,r5:t
14554 +       machh.w r4,r4:b,r4:b
14555 +       machh.w lr,lr:t,lr:t
14556 +       machh.w lr,r5:b,r1:t
14557 +       machh.w r9,r6:b,r7:b
14558 +       machh.w r5,lr:t,r12:b
14559 +       .text
14560 +       .global machh_d
14561 +machh_d:
14562 +       machh.d r0,pc:b,pc:b
14563 +       machh.d r14,r12:t,r12:t
14564 +       machh.d r8,r5:t,r5:t
14565 +       machh.d r6,r4:b,r4:b
14566 +       machh.d r2,lr:t,lr:t
14567 +       machh.d r10,r0:b,r8:b
14568 +       machh.d r14,r4:b,r5:t
14569 +       machh.d r8,r0:b,r4:t
14570 +       .text
14571 +       .global macsathh_w
14572 +macsathh_w:
14573 +       macsathh.w pc,pc:b,pc:b
14574 +       macsathh.w r12,r12:t,r12:t
14575 +       macsathh.w r5,r5:t,r5:t
14576 +       macsathh.w r4,r4:b,r4:b
14577 +       macsathh.w lr,lr:t,lr:t
14578 +       macsathh.w r7,r7:t,pc:t
14579 +       macsathh.w r4,r2:t,r4:b
14580 +       macsathh.w r4,r8:t,r3:t
14581 +       .text
14582 +       .global mulhh_w
14583 +mulhh_w:
14584 +       mulhh.w pc,pc:b,pc:b
14585 +       mulhh.w r12,r12:t,r12:t
14586 +       mulhh.w r5,r5:t,r5:t
14587 +       mulhh.w r4,r4:b,r4:b
14588 +       mulhh.w lr,lr:t,lr:t
14589 +       mulhh.w r7,r4:t,r9:b
14590 +       mulhh.w pc,r3:t,r7:t
14591 +       mulhh.w pc,r4:b,r9:t
14592 +       .text
14593 +       .global mulsathh_h
14594 +mulsathh_h:
14595 +       mulsathh.h pc,pc:b,pc:b
14596 +       mulsathh.h r12,r12:t,r12:t
14597 +       mulsathh.h r5,r5:t,r5:t
14598 +       mulsathh.h r4,r4:b,r4:b
14599 +       mulsathh.h lr,lr:t,lr:t
14600 +       mulsathh.h r3,r1:b,sp:b
14601 +       mulsathh.h r11,lr:t,r11:b
14602 +       mulsathh.h r8,r8:b,r11:t
14603 +       .text
14604 +       .global mulsathh_w
14605 +mulsathh_w:
14606 +       mulsathh.w pc,pc:b,pc:b
14607 +       mulsathh.w r12,r12:t,r12:t
14608 +       mulsathh.w r5,r5:t,r5:t
14609 +       mulsathh.w r4,r4:b,r4:b
14610 +       mulsathh.w lr,lr:t,lr:t
14611 +       mulsathh.w lr,r11:t,r6:b
14612 +       mulsathh.w r6,r6:b,r7:t
14613 +       mulsathh.w r10,r2:b,r3:b
14614 +       .text
14615 +       .global mulsatrndhh_h
14616 +mulsatrndhh_h:
14617 +       mulsatrndhh.h pc,pc:b,pc:b
14618 +       mulsatrndhh.h r12,r12:t,r12:t
14619 +       mulsatrndhh.h r5,r5:t,r5:t
14620 +       mulsatrndhh.h r4,r4:b,r4:b
14621 +       mulsatrndhh.h lr,lr:t,lr:t
14622 +       mulsatrndhh.h r11,r6:b,r9:b
14623 +       mulsatrndhh.h r11,r3:b,r8:t
14624 +       mulsatrndhh.h r5,sp:t,r7:t
14625 +       .text
14626 +       .global mulsatrndwh_w
14627 +mulsatrndwh_w:
14628 +       mulsatrndwh.w pc,pc,pc:b
14629 +       mulsatrndwh.w r12,r12,r12:t
14630 +       mulsatrndwh.w r5,r5,r5:t
14631 +       mulsatrndwh.w r4,r4,r4:b
14632 +       mulsatrndwh.w lr,lr,lr:t
14633 +       mulsatrndwh.w r5,r12,r0:b
14634 +       mulsatrndwh.w r7,r10,pc:b
14635 +       mulsatrndwh.w r10,r8,r5:t
14636 +       .text
14637 +       .global macwh_d
14638 +macwh_d:
14639 +       macwh.d r0,pc,pc:b
14640 +       macwh.d r14,r12,r12:t
14641 +       macwh.d r8,r5,r5:t
14642 +       macwh.d r6,r4,r4:b
14643 +       macwh.d r2,lr,lr:t
14644 +       macwh.d r4,r10,r12:t
14645 +       macwh.d r4,r7,sp:b
14646 +       macwh.d r14,r9,r11:b
14647 +       .text
14648 +       .global mulwh_d
14649 +mulwh_d:
14650 +       mulwh.d r0,pc,pc:b
14651 +       mulwh.d r14,r12,r12:t
14652 +       mulwh.d r8,r5,r5:t
14653 +       mulwh.d r6,r4,r4:b
14654 +       mulwh.d r2,lr,lr:t
14655 +       mulwh.d r12,r5,r1:b
14656 +       mulwh.d r0,r1,r3:t
14657 +       mulwh.d r0,r9,r2:b
14658 +       .text
14659 +       .global mulsatwh_w
14660 +mulsatwh_w:
14661 +       mulsatwh.w pc,pc,pc:b
14662 +       mulsatwh.w r12,r12,r12:t
14663 +       mulsatwh.w r5,r5,r5:t
14664 +       mulsatwh.w r4,r4,r4:b
14665 +       mulsatwh.w lr,lr,lr:t
14666 +       mulsatwh.w r11,pc,r10:t
14667 +       mulsatwh.w sp,r12,r9:t
14668 +       mulsatwh.w r0,r3,r2:t
14669 +       .text
14670 +       .global ldw7
14671 +ldw7:
14672 +       ld.w pc,pc[pc:b<<2]
14673 +       ld.w r12,r12[r12:t<<2]
14674 +       ld.w r5,r5[r5:u<<2]
14675 +       ld.w r4,r4[r4:l<<2]
14676 +       ld.w lr,lr[lr:l<<2]
14677 +       ld.w r9,r10[r6:l<<2]
14678 +       ld.w r2,r10[r10:b<<2]
14679 +       ld.w r11,r5[pc:b<<2]
14680 +       .text
14681 +       .global satadd_w
14682 +satadd_w:
14683 +       satadd.w pc,pc,pc
14684 +       satadd.w r12,r12,r12
14685 +       satadd.w r5,r5,r5
14686 +       satadd.w r4,r4,r4
14687 +       satadd.w lr,lr,lr
14688 +       satadd.w r4,r8,r11
14689 +       satadd.w r3,r12,r6
14690 +       satadd.w r3,lr,r9
14691 +       .text
14692 +       .global satsub_w1
14693 +satsub_w1:
14694 +       satsub.w pc,pc,pc
14695 +       satsub.w r12,r12,r12
14696 +       satsub.w r5,r5,r5
14697 +       satsub.w r4,r4,r4
14698 +       satsub.w lr,lr,lr
14699 +       satsub.w r8,sp,r0
14700 +       satsub.w r9,r8,r4
14701 +       satsub.w pc,lr,r2
14702 +       .text
14703 +       .global satadd_h
14704 +satadd_h:
14705 +       satadd.h pc,pc,pc
14706 +       satadd.h r12,r12,r12
14707 +       satadd.h r5,r5,r5
14708 +       satadd.h r4,r4,r4
14709 +       satadd.h lr,lr,lr
14710 +       satadd.h r7,r3,r9
14711 +       satadd.h r1,r0,r2
14712 +       satadd.h r1,r4,lr
14713 +       .text
14714 +       .global satsub_h
14715 +satsub_h:
14716 +       satsub.h pc,pc,pc
14717 +       satsub.h r12,r12,r12
14718 +       satsub.h r5,r5,r5
14719 +       satsub.h r4,r4,r4
14720 +       satsub.h lr,lr,lr
14721 +       satsub.h lr,lr,r3
14722 +       satsub.h r11,r6,r5
14723 +       satsub.h r3,sp,r0
14724 +       .text
14725 +       .global mul3
14726 +mul3:
14727 +       mul pc,pc,0
14728 +       mul r12,r12,-1
14729 +       mul r5,r5,-128
14730 +       mul r4,r4,127
14731 +       mul lr,lr,1
14732 +       mul r12,r2,-7
14733 +       mul r1,pc,95
14734 +       mul r4,r6,19
14735 +       .text
14736 +       .global rsub2
14737 +rsub2:
14738 +       rsub pc,pc,0
14739 +       rsub r12,r12,-1
14740 +       rsub r5,r5,-128
14741 +       rsub r4,r4,127
14742 +       rsub lr,lr,1
14743 +       rsub r9,lr,96
14744 +       rsub r11,r1,56
14745 +       rsub r0,r7,-87
14746 +       .text
14747 +       .global clz
14748 +clz:
14749 +       clz pc,pc
14750 +       clz r12,r12
14751 +       clz r5,r5
14752 +       clz r4,r4
14753 +       clz lr,lr
14754 +       clz r2,r3
14755 +       clz r5,r11
14756 +       clz pc,r3
14757 +       .text
14758 +       .global cpc1
14759 +cpc1:
14760 +       cpc pc,pc
14761 +       cpc r12,r12
14762 +       cpc r5,r5
14763 +       cpc r4,r4
14764 +       cpc lr,lr
14765 +       cpc pc,r4
14766 +       cpc r5,r9
14767 +       cpc r6,r7
14768 +       .text
14769 +       .global asr3
14770 +asr3:
14771 +       asr pc,pc,0
14772 +       asr r12,r12,31
14773 +       asr r5,r5,16
14774 +       asr r4,r4,15
14775 +       asr lr,lr,1
14776 +       asr r4,r11,19
14777 +       asr sp,pc,26
14778 +       asr r11,sp,8
14779 +       .text
14780 +       .global lsl3
14781 +lsl3:
14782 +       lsl pc,pc,0
14783 +       lsl r12,r12,31
14784 +       lsl r5,r5,16
14785 +       lsl r4,r4,15
14786 +       lsl lr,lr,1
14787 +       lsl r8,r10,17
14788 +       lsl r2,lr,3
14789 +       lsl lr,r11,14
14790 +       .text
14791 +       .global lsr3
14792 +lsr3:
14793 +       lsr pc,pc,0
14794 +       lsr r12,r12,31
14795 +       lsr r5,r5,16
14796 +       lsr r4,r4,15
14797 +       lsr lr,lr,1
14798 +       lsr r4,r3,31
14799 +       lsr pc,r9,14
14800 +       lsr r3,r0,6
14801 +/*     .text
14802 +       .global extract_b
14803 +extract_b:
14804 +       extract.b pc,pc:b
14805 +       extract.b r12,r12:t
14806 +       extract.b r5,r5:u
14807 +       extract.b r4,r4:l
14808 +       extract.b lr,lr:l
14809 +       extract.b r2,r5:l
14810 +       extract.b r12,r3:l
14811 +       extract.b sp,r3:l
14812 +       .text
14813 +       .global insert_b
14814 +insert_b:
14815 +       insert.b pc:b,pc
14816 +       insert.b r12:t,r12
14817 +       insert.b r5:u,r5
14818 +       insert.b r4:l,r4
14819 +       insert.b lr:l,lr
14820 +       insert.b r12:u,r3
14821 +       insert.b r10:l,lr
14822 +       insert.b r11:l,r12
14823 +       .text
14824 +       .global extract_h
14825 +extract_h:
14826 +       extract.h pc,pc:b
14827 +       extract.h r12,r12:t
14828 +       extract.h r5,r5:t
14829 +       extract.h r4,r4:b
14830 +       extract.h lr,lr:t
14831 +       extract.h r11,lr:b
14832 +       extract.h r10,r0:b
14833 +       extract.h r11,r12:b
14834 +       .text
14835 +       .global insert_h
14836 +insert_h:
14837 +       insert.h pc:b,pc
14838 +       insert.h r12:t,r12
14839 +       insert.h r5:t,r5
14840 +       insert.h r4:b,r4
14841 +       insert.h lr:t,lr
14842 +       insert.h r12:t,r11
14843 +       insert.h r7:b,r6
14844 +       insert.h r1:t,r11 */
14845 +       .text
14846 +       .global movc1
14847 +movc1:
14848 +       moveq pc,pc
14849 +       moval r12,r12
14850 +       movls r5,r5
14851 +       movpl r4,r4
14852 +       movne lr,lr
14853 +       movne pc,r11
14854 +       movmi r10,r2
14855 +       movls r8,r12
14856 +       .text
14857 +       .global padd_h
14858 +padd_h:
14859 +       padd.h pc,pc,pc
14860 +       padd.h r12,r12,r12
14861 +       padd.h r5,r5,r5
14862 +       padd.h r4,r4,r4
14863 +       padd.h lr,lr,lr
14864 +       padd.h r8,r2,r7
14865 +       padd.h r0,r0,r3
14866 +       padd.h sp,r11,r6
14867 +       .text
14868 +       .global psub_h
14869 +psub_h:
14870 +       psub.h pc,pc,pc
14871 +       psub.h r12,r12,r12
14872 +       psub.h r5,r5,r5
14873 +       psub.h r4,r4,r4
14874 +       psub.h lr,lr,lr
14875 +       psub.h lr,r6,r8
14876 +       psub.h r0,r1,sp
14877 +       psub.h pc,pc,sp
14878 +       .text
14879 +       .global paddx_h
14880 +paddx_h:
14881 +       paddx.h pc,pc,pc
14882 +       paddx.h r12,r12,r12
14883 +       paddx.h r5,r5,r5
14884 +       paddx.h r4,r4,r4
14885 +       paddx.h lr,lr,lr
14886 +       paddx.h pc,pc,r1
14887 +       paddx.h r10,r4,r5
14888 +       paddx.h r5,pc,r2
14889 +       .text
14890 +       .global psubx_h
14891 +psubx_h:
14892 +       psubx.h pc,pc,pc
14893 +       psubx.h r12,r12,r12
14894 +       psubx.h r5,r5,r5
14895 +       psubx.h r4,r4,r4
14896 +       psubx.h lr,lr,lr
14897 +       psubx.h r5,r12,r5
14898 +       psubx.h r3,r8,r3
14899 +       psubx.h r5,r2,r3
14900 +       .text
14901 +       .global padds_sh
14902 +padds_sh:
14903 +       padds.sh pc,pc,pc
14904 +       padds.sh r12,r12,r12
14905 +       padds.sh r5,r5,r5
14906 +       padds.sh r4,r4,r4
14907 +       padds.sh lr,lr,lr
14908 +       padds.sh r9,lr,r2
14909 +       padds.sh r6,r8,r1
14910 +       padds.sh r6,r4,r10
14911 +       .text
14912 +       .global psubs_sh
14913 +psubs_sh:
14914 +       psubs.sh pc,pc,pc
14915 +       psubs.sh r12,r12,r12
14916 +       psubs.sh r5,r5,r5
14917 +       psubs.sh r4,r4,r4
14918 +       psubs.sh lr,lr,lr
14919 +       psubs.sh r6,lr,r11
14920 +       psubs.sh r2,r12,r4
14921 +       psubs.sh r0,r9,r0
14922 +       .text
14923 +       .global paddxs_sh
14924 +paddxs_sh:
14925 +       paddxs.sh pc,pc,pc
14926 +       paddxs.sh r12,r12,r12
14927 +       paddxs.sh r5,r5,r5
14928 +       paddxs.sh r4,r4,r4
14929 +       paddxs.sh lr,lr,lr
14930 +       paddxs.sh r0,r3,r9
14931 +       paddxs.sh pc,r10,r11
14932 +       paddxs.sh pc,r10,pc
14933 +       .text
14934 +       .global psubxs_sh
14935 +psubxs_sh:
14936 +       psubxs.sh pc,pc,pc
14937 +       psubxs.sh r12,r12,r12
14938 +       psubxs.sh r5,r5,r5
14939 +       psubxs.sh r4,r4,r4
14940 +       psubxs.sh lr,lr,lr
14941 +       psubxs.sh r7,r4,r4
14942 +       psubxs.sh r7,r8,r3
14943 +       psubxs.sh pc,r6,r5
14944 +       .text
14945 +       .global padds_uh
14946 +padds_uh:
14947 +       padds.uh pc,pc,pc
14948 +       padds.uh r12,r12,r12
14949 +       padds.uh r5,r5,r5
14950 +       padds.uh r4,r4,r4
14951 +       padds.uh lr,lr,lr
14952 +       padds.uh r12,r11,r7
14953 +       padds.uh r7,r8,lr
14954 +       padds.uh r6,r9,r7
14955 +       .text
14956 +       .global psubs_uh
14957 +psubs_uh:
14958 +       psubs.uh pc,pc,pc
14959 +       psubs.uh r12,r12,r12
14960 +       psubs.uh r5,r5,r5
14961 +       psubs.uh r4,r4,r4
14962 +       psubs.uh lr,lr,lr
14963 +       psubs.uh lr,r10,r6
14964 +       psubs.uh sp,r2,pc
14965 +       psubs.uh r2,r9,r2
14966 +       .text
14967 +       .global paddxs_uh
14968 +paddxs_uh:
14969 +       paddxs.uh pc,pc,pc
14970 +       paddxs.uh r12,r12,r12
14971 +       paddxs.uh r5,r5,r5
14972 +       paddxs.uh r4,r4,r4
14973 +       paddxs.uh lr,lr,lr
14974 +       paddxs.uh r7,r9,r5
14975 +       paddxs.uh r9,r1,r4
14976 +       paddxs.uh r5,r2,r3
14977 +       .text
14978 +       .global psubxs_uh
14979 +psubxs_uh:
14980 +       psubxs.uh pc,pc,pc
14981 +       psubxs.uh r12,r12,r12
14982 +       psubxs.uh r5,r5,r5
14983 +       psubxs.uh r4,r4,r4
14984 +       psubxs.uh lr,lr,lr
14985 +       psubxs.uh sp,r5,sp
14986 +       psubxs.uh sp,r6,r6
14987 +       psubxs.uh r3,r11,r8
14988 +       .text
14989 +       .global paddh_sh
14990 +paddh_sh:
14991 +       paddh.sh pc,pc,pc
14992 +       paddh.sh r12,r12,r12
14993 +       paddh.sh r5,r5,r5
14994 +       paddh.sh r4,r4,r4
14995 +       paddh.sh lr,lr,lr
14996 +       paddh.sh r12,sp,r3
14997 +       paddh.sh pc,r5,r3
14998 +       paddh.sh r8,r8,sp
14999 +       .text
15000 +       .global psubh_sh
15001 +psubh_sh:
15002 +       psubh.sh pc,pc,pc
15003 +       psubh.sh r12,r12,r12
15004 +       psubh.sh r5,r5,r5
15005 +       psubh.sh r4,r4,r4
15006 +       psubh.sh lr,lr,lr
15007 +       psubh.sh r1,r5,r8
15008 +       psubh.sh r7,r3,r6
15009 +       psubh.sh r4,r3,r3
15010 +       .text
15011 +       .global paddxh_sh
15012 +paddxh_sh:
15013 +       paddxh.sh pc,pc,pc
15014 +       paddxh.sh r12,r12,r12
15015 +       paddxh.sh r5,r5,r5
15016 +       paddxh.sh r4,r4,r4
15017 +       paddxh.sh lr,lr,lr
15018 +       paddxh.sh r6,r0,r4
15019 +       paddxh.sh r9,r8,r9
15020 +       paddxh.sh r3,r0,sp
15021 +       .text
15022 +       .global psubxh_sh
15023 +psubxh_sh:
15024 +       psubxh.sh pc,pc,pc
15025 +       psubxh.sh r12,r12,r12
15026 +       psubxh.sh r5,r5,r5
15027 +       psubxh.sh r4,r4,r4
15028 +       psubxh.sh lr,lr,lr
15029 +       psubxh.sh r4,pc,r12
15030 +       psubxh.sh r8,r4,r6
15031 +       psubxh.sh r12,r9,r4
15032 +       .text
15033 +       .global paddsub_h
15034 +paddsub_h:
15035 +       paddsub.h pc,pc:b,pc:b
15036 +       paddsub.h r12,r12:t,r12:t
15037 +       paddsub.h r5,r5:t,r5:t
15038 +       paddsub.h r4,r4:b,r4:b
15039 +       paddsub.h lr,lr:t,lr:t
15040 +       paddsub.h r5,r2:t,lr:b
15041 +       paddsub.h r7,r1:b,r8:b
15042 +       paddsub.h r6,r10:t,r5:t
15043 +       .text
15044 +       .global psubadd_h
15045 +psubadd_h:
15046 +       psubadd.h pc,pc:b,pc:b
15047 +       psubadd.h r12,r12:t,r12:t
15048 +       psubadd.h r5,r5:t,r5:t
15049 +       psubadd.h r4,r4:b,r4:b
15050 +       psubadd.h lr,lr:t,lr:t
15051 +       psubadd.h r9,r11:t,r8:t
15052 +       psubadd.h r10,r7:t,lr:t
15053 +       psubadd.h r6,pc:t,pc:b
15054 +       .text
15055 +       .global paddsubs_sh
15056 +paddsubs_sh:
15057 +       paddsubs.sh pc,pc:b,pc:b
15058 +       paddsubs.sh r12,r12:t,r12:t
15059 +       paddsubs.sh r5,r5:t,r5:t
15060 +       paddsubs.sh r4,r4:b,r4:b
15061 +       paddsubs.sh lr,lr:t,lr:t
15062 +       paddsubs.sh r0,lr:t,r0:b
15063 +       paddsubs.sh r9,r2:t,r4:t
15064 +       paddsubs.sh r12,r9:t,sp:t
15065 +       .text
15066 +       .global psubadds_sh
15067 +psubadds_sh:
15068 +       psubadds.sh pc,pc:b,pc:b
15069 +       psubadds.sh r12,r12:t,r12:t
15070 +       psubadds.sh r5,r5:t,r5:t
15071 +       psubadds.sh r4,r4:b,r4:b
15072 +       psubadds.sh lr,lr:t,lr:t
15073 +       psubadds.sh pc,lr:b,r1:t
15074 +       psubadds.sh r11,r3:b,r12:b
15075 +       psubadds.sh r10,r2:t,r8:t
15076 +       .text
15077 +       .global paddsubs_uh
15078 +paddsubs_uh:
15079 +       paddsubs.uh pc,pc:b,pc:b
15080 +       paddsubs.uh r12,r12:t,r12:t
15081 +       paddsubs.uh r5,r5:t,r5:t
15082 +       paddsubs.uh r4,r4:b,r4:b
15083 +       paddsubs.uh lr,lr:t,lr:t
15084 +       paddsubs.uh r9,r2:b,r3:b
15085 +       paddsubs.uh sp,sp:b,r7:t
15086 +       paddsubs.uh lr,r0:b,r10:t
15087 +       .text
15088 +       .global psubadds_uh
15089 +psubadds_uh:
15090 +       psubadds.uh pc,pc:b,pc:b
15091 +       psubadds.uh r12,r12:t,r12:t
15092 +       psubadds.uh r5,r5:t,r5:t
15093 +       psubadds.uh r4,r4:b,r4:b
15094 +       psubadds.uh lr,lr:t,lr:t
15095 +       psubadds.uh r12,r9:t,pc:t
15096 +       psubadds.uh r8,r6:b,r8:b
15097 +       psubadds.uh r8,r8:b,r4:b
15098 +       .text
15099 +       .global paddsubh_sh
15100 +paddsubh_sh:
15101 +       paddsubh.sh pc,pc:b,pc:b
15102 +       paddsubh.sh r12,r12:t,r12:t
15103 +       paddsubh.sh r5,r5:t,r5:t
15104 +       paddsubh.sh r4,r4:b,r4:b
15105 +       paddsubh.sh lr,lr:t,lr:t
15106 +       paddsubh.sh r8,r9:t,r9:b
15107 +       paddsubh.sh r0,sp:t,r1:t
15108 +       paddsubh.sh r3,r1:b,r0:t
15109 +       .text
15110 +       .global psubaddh_sh
15111 +psubaddh_sh:
15112 +       psubaddh.sh pc,pc:b,pc:b
15113 +       psubaddh.sh r12,r12:t,r12:t
15114 +       psubaddh.sh r5,r5:t,r5:t
15115 +       psubaddh.sh r4,r4:b,r4:b
15116 +       psubaddh.sh lr,lr:t,lr:t
15117 +       psubaddh.sh r7,r3:t,r10:b
15118 +       psubaddh.sh r7,r2:t,r1:t
15119 +       psubaddh.sh r11,r3:b,r6:b
15120 +       .text
15121 +       .global padd_b
15122 +padd_b:
15123 +       padd.b pc,pc,pc
15124 +       padd.b r12,r12,r12
15125 +       padd.b r5,r5,r5
15126 +       padd.b r4,r4,r4
15127 +       padd.b lr,lr,lr
15128 +       padd.b r2,r6,pc
15129 +       padd.b r8,r9,r12
15130 +       padd.b r5,r12,r3
15131 +       .text
15132 +       .global psub_b
15133 +psub_b:
15134 +       psub.b pc,pc,pc
15135 +       psub.b r12,r12,r12
15136 +       psub.b r5,r5,r5
15137 +       psub.b r4,r4,r4
15138 +       psub.b lr,lr,lr
15139 +       psub.b r0,r12,pc
15140 +       psub.b r7,sp,r10
15141 +       psub.b r5,sp,r12
15142 +       .text
15143 +       .global padds_sb
15144 +padds_sb:
15145 +       padds.sb pc,pc,pc
15146 +       padds.sb r12,r12,r12
15147 +       padds.sb r5,r5,r5
15148 +       padds.sb r4,r4,r4
15149 +       padds.sb lr,lr,lr
15150 +       padds.sb sp,r11,r4
15151 +       padds.sb r11,r10,r11
15152 +       padds.sb r5,r12,r6
15153 +       .text
15154 +       .global psubs_sb
15155 +psubs_sb:
15156 +       psubs.sb pc,pc,pc
15157 +       psubs.sb r12,r12,r12
15158 +       psubs.sb r5,r5,r5
15159 +       psubs.sb r4,r4,r4
15160 +       psubs.sb lr,lr,lr
15161 +       psubs.sb r7,r6,r8
15162 +       psubs.sb r12,r10,r9
15163 +       psubs.sb pc,r11,r0
15164 +       .text
15165 +       .global padds_ub
15166 +padds_ub:
15167 +       padds.ub pc,pc,pc
15168 +       padds.ub r12,r12,r12
15169 +       padds.ub r5,r5,r5
15170 +       padds.ub r4,r4,r4
15171 +       padds.ub lr,lr,lr
15172 +       padds.ub r3,r2,r11
15173 +       padds.ub r10,r8,r1
15174 +       padds.ub r11,r8,r10
15175 +       .text
15176 +       .global psubs_ub
15177 +psubs_ub:
15178 +       psubs.ub pc,pc,pc
15179 +       psubs.ub r12,r12,r12
15180 +       psubs.ub r5,r5,r5
15181 +       psubs.ub r4,r4,r4
15182 +       psubs.ub lr,lr,lr
15183 +       psubs.ub r0,r2,r7
15184 +       psubs.ub lr,r5,r3
15185 +       psubs.ub r6,r7,r9
15186 +       .text
15187 +       .global paddh_ub
15188 +paddh_ub:
15189 +       paddh.ub pc,pc,pc
15190 +       paddh.ub r12,r12,r12
15191 +       paddh.ub r5,r5,r5
15192 +       paddh.ub r4,r4,r4
15193 +       paddh.ub lr,lr,lr
15194 +       paddh.ub lr,r1,r0
15195 +       paddh.ub r2,r7,r7
15196 +       paddh.ub r2,r1,r2
15197 +       .text
15198 +       .global psubh_ub
15199 +psubh_ub:
15200 +       psubh.ub pc,pc,pc
15201 +       psubh.ub r12,r12,r12
15202 +       psubh.ub r5,r5,r5
15203 +       psubh.ub r4,r4,r4
15204 +       psubh.ub lr,lr,lr
15205 +       psubh.ub r0,r1,r6
15206 +       psubh.ub r4,lr,r10
15207 +       psubh.ub r9,r8,r1
15208 +       .text
15209 +       .global pmax_ub
15210 +pmax_ub:
15211 +       pmax.ub pc,pc,pc
15212 +       pmax.ub r12,r12,r12
15213 +       pmax.ub r5,r5,r5
15214 +       pmax.ub r4,r4,r4
15215 +       pmax.ub lr,lr,lr
15216 +       pmax.ub pc,r2,r11
15217 +       pmax.ub r12,r1,r1
15218 +       pmax.ub r5,r2,r0
15219 +       .text
15220 +       .global pmax_sh
15221 +pmax_sh:
15222 +       pmax.sh pc,pc,pc
15223 +       pmax.sh r12,r12,r12
15224 +       pmax.sh r5,r5,r5
15225 +       pmax.sh r4,r4,r4
15226 +       pmax.sh lr,lr,lr
15227 +       pmax.sh lr,r6,r12
15228 +       pmax.sh r2,pc,r5
15229 +       pmax.sh pc,r2,r7
15230 +       .text
15231 +       .global pmin_ub
15232 +pmin_ub:
15233 +       pmin.ub pc,pc,pc
15234 +       pmin.ub r12,r12,r12
15235 +       pmin.ub r5,r5,r5
15236 +       pmin.ub r4,r4,r4
15237 +       pmin.ub lr,lr,lr
15238 +       pmin.ub r8,r1,r5
15239 +       pmin.ub r1,r8,r3
15240 +       pmin.ub r0,r2,r7
15241 +       .text
15242 +       .global pmin_sh
15243 +pmin_sh:
15244 +       pmin.sh pc,pc,pc
15245 +       pmin.sh r12,r12,r12
15246 +       pmin.sh r5,r5,r5
15247 +       pmin.sh r4,r4,r4
15248 +       pmin.sh lr,lr,lr
15249 +       pmin.sh r8,r4,r10
15250 +       pmin.sh lr,r10,r12
15251 +       pmin.sh r2,r6,r2
15252 +       .text
15253 +       .global pavg_ub
15254 +pavg_ub:
15255 +       pavg.ub pc,pc,pc
15256 +       pavg.ub r12,r12,r12
15257 +       pavg.ub r5,r5,r5
15258 +       pavg.ub r4,r4,r4
15259 +       pavg.ub lr,lr,lr
15260 +       pavg.ub r0,r1,r6
15261 +       pavg.ub r8,r3,r6
15262 +       pavg.ub pc,r12,r10
15263 +       .text
15264 +       .global pavg_sh
15265 +pavg_sh:
15266 +       pavg.sh pc,pc,pc
15267 +       pavg.sh r12,r12,r12
15268 +       pavg.sh r5,r5,r5
15269 +       pavg.sh r4,r4,r4
15270 +       pavg.sh lr,lr,lr
15271 +       pavg.sh r9,pc,sp
15272 +       pavg.sh pc,sp,r3
15273 +       pavg.sh r6,r1,r9
15274 +       .text
15275 +       .global pabs_sb
15276 +pabs_sb:
15277 +       pabs.sb pc,pc
15278 +       pabs.sb r12,r12
15279 +       pabs.sb r5,r5
15280 +       pabs.sb r4,r4
15281 +       pabs.sb lr,lr
15282 +       pabs.sb r11,r6
15283 +       pabs.sb lr,r9
15284 +       pabs.sb sp,r7
15285 +       .text
15286 +       .global pabs_sh
15287 +pabs_sh:
15288 +       pabs.sh pc,pc
15289 +       pabs.sh r12,r12
15290 +       pabs.sh r5,r5
15291 +       pabs.sh r4,r4
15292 +       pabs.sh lr,lr
15293 +       pabs.sh pc,r3
15294 +       pabs.sh r5,r7
15295 +       pabs.sh r4,r0
15296 +       .text
15297 +       .global psad
15298 +psad:
15299 +       psad pc,pc,pc
15300 +       psad r12,r12,r12
15301 +       psad r5,r5,r5
15302 +       psad r4,r4,r4
15303 +       psad lr,lr,lr
15304 +       psad r9,r11,r11
15305 +       psad lr,r4,sp
15306 +       psad lr,r4,r5
15307 +       .text
15308 +       .global pasr_b
15309 +pasr_b:
15310 +       pasr.b pc,pc,0
15311 +       pasr.b r12,r12,7
15312 +       pasr.b r5,r5,4
15313 +       pasr.b r4,r4,3
15314 +       pasr.b lr,lr,1
15315 +       pasr.b pc,r7,1
15316 +       pasr.b sp,lr,6
15317 +       pasr.b sp,r3,2
15318 +       .text
15319 +       .global plsl_b
15320 +plsl_b:
15321 +       plsl.b pc,pc,0
15322 +       plsl.b r12,r12,7
15323 +       plsl.b r5,r5,4
15324 +       plsl.b r4,r4,3
15325 +       plsl.b lr,lr,1
15326 +       plsl.b r2,r11,4
15327 +       plsl.b r8,r5,7
15328 +       plsl.b pc,r0,2
15329 +       .text
15330 +       .global plsr_b
15331 +plsr_b:
15332 +       plsr.b pc,pc,0
15333 +       plsr.b r12,r12,7
15334 +       plsr.b r5,r5,4
15335 +       plsr.b r4,r4,3
15336 +       plsr.b lr,lr,1
15337 +       plsr.b r12,r1,2
15338 +       plsr.b r6,pc,7
15339 +       plsr.b r12,r11,2
15340 +       .text
15341 +       .global pasr_h
15342 +pasr_h:
15343 +       pasr.h pc,pc,0
15344 +       pasr.h r12,r12,15
15345 +       pasr.h r5,r5,8
15346 +       pasr.h r4,r4,7
15347 +       pasr.h lr,lr,1
15348 +       pasr.h r0,r11,10
15349 +       pasr.h r4,r6,8
15350 +       pasr.h r6,r2,4
15351 +       .text
15352 +       .global plsl_h
15353 +plsl_h:
15354 +       plsl.h pc,pc,0
15355 +       plsl.h r12,r12,15
15356 +       plsl.h r5,r5,8
15357 +       plsl.h r4,r4,7
15358 +       plsl.h lr,lr,1
15359 +       plsl.h r5,r10,9
15360 +       plsl.h sp,lr,8
15361 +       plsl.h r0,lr,7
15362 +       .text
15363 +       .global plsr_h
15364 +plsr_h:
15365 +       plsr.h pc,pc,0
15366 +       plsr.h r12,r12,15
15367 +       plsr.h r5,r5,8
15368 +       plsr.h r4,r4,7
15369 +       plsr.h lr,lr,1
15370 +       plsr.h r11,r0,15
15371 +       plsr.h lr,r3,3
15372 +       plsr.h r8,lr,10
15373 +       .text
15374 +       .global packw_sh
15375 +packw_sh:
15376 +       packw.sh pc,pc,pc
15377 +       packw.sh r12,r12,r12
15378 +       packw.sh r5,r5,r5
15379 +       packw.sh r4,r4,r4
15380 +       packw.sh lr,lr,lr
15381 +       packw.sh sp,r11,r10
15382 +       packw.sh r8,r2,r12
15383 +       packw.sh r8,r1,r5
15384 +       .text
15385 +       .global punpckub_h
15386 +punpckub_h:
15387 +       punpckub.h pc,pc:b
15388 +       punpckub.h r12,r12:t
15389 +       punpckub.h r5,r5:t
15390 +       punpckub.h r4,r4:b
15391 +       punpckub.h lr,lr:t
15392 +       punpckub.h r6,r1:t
15393 +       punpckub.h lr,r5:b
15394 +       punpckub.h lr,r2:t
15395 +       .text
15396 +       .global punpcksb_h
15397 +punpcksb_h:
15398 +       punpcksb.h pc,pc:b
15399 +       punpcksb.h r12,r12:t
15400 +       punpcksb.h r5,r5:t
15401 +       punpcksb.h r4,r4:b
15402 +       punpcksb.h lr,lr:t
15403 +       punpcksb.h r4,r7:t
15404 +       punpcksb.h r6,lr:b
15405 +       punpcksb.h r12,r12:t
15406 +       .text
15407 +       .global packsh_ub
15408 +packsh_ub:
15409 +       packsh.ub pc,pc,pc
15410 +       packsh.ub r12,r12,r12
15411 +       packsh.ub r5,r5,r5
15412 +       packsh.ub r4,r4,r4
15413 +       packsh.ub lr,lr,lr
15414 +       packsh.ub r3,r6,r3
15415 +       packsh.ub r8,r0,r3
15416 +       packsh.ub r9,r3,lr
15417 +       .text
15418 +       .global packsh_sb
15419 +packsh_sb:
15420 +       packsh.sb pc,pc,pc
15421 +       packsh.sb r12,r12,r12
15422 +       packsh.sb r5,r5,r5
15423 +       packsh.sb r4,r4,r4
15424 +       packsh.sb lr,lr,lr
15425 +       packsh.sb r6,r8,r1
15426 +       packsh.sb lr,r9,r8
15427 +       packsh.sb sp,r6,r6
15428 +       .text
15429 +       .global andl
15430 +andl:
15431 +       andl pc,0
15432 +       andl r12,65535
15433 +       andl r5,32768
15434 +       andl r4,32767
15435 +       andl lr,1
15436 +       andl pc,23128
15437 +       andl r8,47262
15438 +       andl r7,13719
15439 +       .text
15440 +       .global andl_coh
15441 +andl_coh:
15442 +       andl pc,0,COH
15443 +       andl r12,65535,COH
15444 +       andl r5,32768,COH
15445 +       andl r4,32767,COH
15446 +       andl lr,1,COH
15447 +       andl r6,22753,COH
15448 +       andl r0,40653,COH
15449 +       andl r4,48580,COH
15450 +       .text
15451 +       .global andh
15452 +andh:
15453 +       andh pc,0
15454 +       andh r12,65535
15455 +       andh r5,32768
15456 +       andh r4,32767
15457 +       andh lr,1
15458 +       andh r12,52312
15459 +       andh r3,8675
15460 +       andh r2,42987
15461 +       .text
15462 +       .global andh_coh
15463 +andh_coh:
15464 +       andh pc,0,COH
15465 +       andh r12,65535,COH
15466 +       andh r5,32768,COH
15467 +       andh r4,32767,COH
15468 +       andh lr,1,COH
15469 +       andh r11,34317,COH
15470 +       andh r8,52982,COH
15471 +       andh r10,23683,COH
15472 +       .text
15473 +       .global orl
15474 +orl:
15475 +       orl pc,0
15476 +       orl r12,65535
15477 +       orl r5,32768
15478 +       orl r4,32767
15479 +       orl lr,1
15480 +       orl sp,16766
15481 +       orl r0,21181
15482 +       orl pc,44103
15483 +       .text
15484 +       .global orh
15485 +orh:
15486 +       orh pc,0
15487 +       orh r12,65535
15488 +       orh r5,32768
15489 +       orh r4,32767
15490 +       orh lr,1
15491 +       orh r8,28285
15492 +       orh r12,30492
15493 +       orh r1,59930
15494 +       .text
15495 +       .global eorl
15496 +eorl:
15497 +       eorl pc,0
15498 +       eorl r12,65535
15499 +       eorl r5,32768
15500 +       eorl r4,32767
15501 +       eorl lr,1
15502 +       eorl r4,51129
15503 +       eorl r6,64477
15504 +       eorl r1,20913
15505 +       .text
15506 +       .global eorh
15507 +eorh:
15508 +       eorh pc,0
15509 +       eorh r12,65535
15510 +       eorh r5,32768
15511 +       eorh r4,32767
15512 +       eorh lr,1
15513 +       eorh r0,11732
15514 +       eorh r10,38069
15515 +       eorh r9,57130
15516 +       .text
15517 +       .global mcall
15518 +mcall:
15519 +       mcall pc[0]
15520 +       mcall r12[-4]
15521 +       mcall r5[-131072]
15522 +       mcall r4[131068]
15523 +       mcall lr[4]
15524 +       mcall sp[61180]
15525 +       mcall r4[-35000]
15526 +       mcall r0[9924]
15527 +       .text
15528 +       .global pref
15529 +pref:
15530 +       pref pc[0]
15531 +       pref r12[-1]
15532 +       pref r5[-32768]
15533 +       pref r4[32767]
15534 +       pref lr[1]
15535 +       pref r7[7748]
15536 +       pref r7[-7699]
15537 +       pref r2[-25892]
15538 +       .text
15539 +       .global cache
15540 +cache:
15541 +       cache pc[0],0
15542 +       cache r12[-1],31
15543 +       cache r5[-1024],16
15544 +       cache r4[1023],15
15545 +       cache lr[1],1
15546 +       cache r3[-964],17
15547 +       cache r4[-375],22
15548 +       cache r3[-888],17
15549 +       .text
15550 +       .global sub4
15551 +sub4:
15552 +       sub pc,0
15553 +       sub r12,-1
15554 +       sub r5,-1048576
15555 +       sub r4,1048575
15556 +       sub lr,1
15557 +       sub r2,-619156
15558 +       sub lr,461517
15559 +       sub r8,-185051
15560 +       .text
15561 +       .global cp3
15562 +cp3:
15563 +       cp pc,0
15564 +       cp r12,-1
15565 +       cp r5,-1048576
15566 +       cp r4,1048575
15567 +       cp lr,1
15568 +       cp r1,124078
15569 +       cp r0,-378909
15570 +       cp r4,-243180
15571 +       .text
15572 +       .global mov2
15573 +mov2:
15574 +       mov pc,0
15575 +       mov r12,-1
15576 +       mov r5,-1048576
15577 +       mov r4,1048575
15578 +       mov lr,1
15579 +       mov r5,-317021
15580 +       mov sp,-749164
15581 +       mov r5,940179
15582 +       .text
15583 +       .global brc2
15584 +brc2:
15585 +       breq 0
15586 +       bral -2
15587 +       brls -2097152
15588 +       brpl 2097150
15589 +       brne 2
15590 +       brhi -1796966
15591 +       brqs 1321368
15592 +       brls -577434
15593 +       .text
15594 +       .global rcall2
15595 +rcall2:
15596 +       rcall 0
15597 +       rcall -2
15598 +       rcall -2097152
15599 +       rcall 2097150
15600 +       rcall 2
15601 +       rcall 496820
15602 +       rcall 1085092
15603 +       rcall -1058
15604 +       .text
15605 +       .global sub5
15606 +sub5:
15607 +       sub pc,pc,0
15608 +       sub r12,r12,-1
15609 +       sub r5,r5,-32768
15610 +       sub r4,r4,32767
15611 +       sub lr,lr,1
15612 +       sub pc,pc,-12744
15613 +       sub r7,r7,-27365
15614 +       sub r2,r9,-17358
15615 +       .text
15616 +       .global satsub_w2
15617 +satsub_w2:
15618 +       satsub.w pc,pc,0
15619 +       satsub.w r12,r12,-1
15620 +       satsub.w r5,r5,-32768
15621 +       satsub.w r4,r4,32767
15622 +       satsub.w lr,lr,1
15623 +       satsub.w r2,lr,-2007
15624 +       satsub.w r7,r12,-784
15625 +       satsub.w r4,r7,23180
15626 +       .text
15627 +       .global ld_d4
15628 +ld_d4:
15629 +       ld.d r0,pc[0]
15630 +       ld.d r14,r12[-1]
15631 +       ld.d r8,r5[-32768]
15632 +       ld.d r6,r4[32767]
15633 +       ld.d r2,lr[1]
15634 +       ld.d r14,r11[14784]
15635 +       ld.d r6,r9[-18905]
15636 +       ld.d r2,r3[-6355]
15637 +       .text
15638 +       .global ld_w4
15639 +ld_w4:
15640 +       ld.w pc,pc[0]
15641 +       ld.w r12,r12[-1]
15642 +       ld.w r5,r5[-32768]
15643 +       ld.w r4,r4[32767]
15644 +       ld.w lr,lr[1]
15645 +       ld.w r0,r12[-22133]
15646 +       ld.w sp,pc[-20521]
15647 +       /* ld.w r3,r5[29035] */
15648 +       nop
15649 +       .text
15650 +       .global ld_sh4
15651 +ld_sh4:
15652 +       ld.sh pc,pc[0]
15653 +       ld.sh r12,r12[-1]
15654 +       ld.sh r5,r5[-32768]
15655 +       ld.sh r4,r4[32767]
15656 +       ld.sh lr,lr[1]
15657 +       ld.sh r6,r10[30930]
15658 +       ld.sh r6,r10[21973]
15659 +       /* ld.sh r11,r10[-2058] */
15660 +       nop
15661 +       .text
15662 +       .global ld_uh4
15663 +ld_uh4:
15664 +       ld.uh pc,pc[0]
15665 +       ld.uh r12,r12[-1]
15666 +       ld.uh r5,r5[-32768]
15667 +       ld.uh r4,r4[32767]
15668 +       ld.uh lr,lr[1]
15669 +       ld.uh r1,r9[-13354]
15670 +       ld.uh lr,r11[21337]
15671 +       /* ld.uh r2,lr[-25370] */
15672 +       nop
15673 +       .text
15674 +       .global ld_sb1
15675 +ld_sb1:
15676 +       ld.sb pc,pc[0]
15677 +       ld.sb r12,r12[-1]
15678 +       ld.sb r5,r5[-32768]
15679 +       ld.sb r4,r4[32767]
15680 +       ld.sb lr,lr[1]
15681 +       ld.sb r7,sp[-28663]
15682 +       ld.sb r2,r1[-5879]
15683 +       ld.sb r12,r3[18734]
15684 +       .text
15685 +       .global ld_ub4
15686 +ld_ub4:
15687 +       ld.ub pc,pc[0]
15688 +       ld.ub r12,r12[-1]
15689 +       ld.ub r5,r5[-32768]
15690 +       ld.ub r4,r4[32767]
15691 +       ld.ub lr,lr[1]
15692 +       ld.ub pc,r4[8277]
15693 +       ld.ub r5,r12[19172]
15694 +       ld.ub r10,lr[26347]
15695 +       .text
15696 +       .global st_d4
15697 +st_d4:
15698 +       st.d pc[0],r0
15699 +       st.d r12[-1],r14
15700 +       st.d r5[-32768],r8
15701 +       st.d r4[32767],r6
15702 +       st.d lr[1],r2
15703 +       st.d r5[13200],r10
15704 +       st.d r5[9352],r10
15705 +       st.d r5[32373],r4
15706 +       .text
15707 +       .global st_w4
15708 +st_w4:
15709 +       st.w pc[0],pc
15710 +       st.w r12[-1],r12
15711 +       st.w r5[-32768],r5
15712 +       st.w r4[32767],r4
15713 +       st.w lr[1],lr
15714 +       st.w sp[6136],r7
15715 +       st.w r6[27087],r12
15716 +       /* st.w r3[20143],r7 */
15717 +       nop
15718 +       .text
15719 +       .global st_h4
15720 +st_h4:
15721 +       st.h pc[0],pc
15722 +       st.h r12[-1],r12
15723 +       st.h r5[-32768],r5
15724 +       st.h r4[32767],r4
15725 +       st.h lr[1],lr
15726 +       st.h r4[-9962],r7
15727 +       st.h r9[-16250],r3
15728 +       /* st.h r8[-28810],r7 */
15729 +       nop
15730 +       .text
15731 +       .global st_b4
15732 +st_b4:
15733 +       st.b pc[0],pc
15734 +       st.b r12[-1],r12
15735 +       st.b r5[-32768],r5
15736 +       st.b r4[32767],r4
15737 +       st.b lr[1],lr
15738 +       st.b r12[30102],r6
15739 +       st.b r5[28977],r1
15740 +       st.b r0[5470],r1
15741 +       .text
15742 +       .global mfsr
15743 +mfsr:
15744 +       mfsr pc,0
15745 +       mfsr r12,1020
15746 +       mfsr r5,512
15747 +       mfsr r4,508
15748 +       mfsr lr,4
15749 +       mfsr r2,696
15750 +       mfsr r4,260
15751 +       mfsr r10,1016
15752 +       .text
15753 +       .global mtsr
15754 +mtsr:
15755 +       mtsr 0,pc
15756 +       mtsr 1020,r12
15757 +       mtsr 512,r5
15758 +       mtsr 508,r4
15759 +       mtsr 4,lr
15760 +       mtsr 224,r10
15761 +       mtsr 836,r12
15762 +       mtsr 304,r9
15763 +       .text
15764 +       .global mfdr
15765 +mfdr:
15766 +       mfdr pc,0
15767 +       mfdr r12,1020
15768 +       mfdr r5,512
15769 +       mfdr r4,508
15770 +       mfdr lr,4
15771 +       mfdr r6,932
15772 +       mfdr r5,36
15773 +       mfdr r9,300
15774 +       .text
15775 +       .global mtdr
15776 +mtdr:
15777 +       mtdr 0,pc
15778 +       mtdr 1020,r12
15779 +       mtdr 512,r5
15780 +       mtdr 508,r4
15781 +       mtdr 4,lr
15782 +       mtdr 180,r8
15783 +       mtdr 720,r10
15784 +       mtdr 408,lr
15785 +       .text
15786 +       .global sleep
15787 +sleep:
15788 +       sleep 0
15789 +       sleep 255
15790 +       sleep 128
15791 +       sleep 127
15792 +       sleep 1
15793 +       sleep 254
15794 +       sleep 15
15795 +       sleep 43
15796 +       .text
15797 +       .global sync
15798 +sync:
15799 +       sync 0
15800 +       sync 255
15801 +       sync 128
15802 +       sync 127
15803 +       sync 1
15804 +       sync 166
15805 +       sync 230
15806 +       sync 180
15807 +       .text
15808 +       .global bld
15809 +bld:
15810 +       bld pc,0
15811 +       bld r12,31
15812 +       bld r5,16
15813 +       bld r4,15
15814 +       bld lr,1
15815 +       bld r9,15
15816 +       bld r0,4
15817 +       bld lr,26
15818 +       .text
15819 +       .global bst
15820 +bst:
15821 +       bst pc,0
15822 +       bst r12,31
15823 +       bst r5,16
15824 +       bst r4,15
15825 +       bst lr,1
15826 +       bst r10,28
15827 +       bst r0,3
15828 +       bst sp,2
15829 +       .text
15830 +       .global sats
15831 +sats:
15832 +       sats pc>>0,0
15833 +       sats r12>>31,31
15834 +       sats r5>>16,16
15835 +       sats r4>>15,15
15836 +       sats lr>>1,1
15837 +       sats r10>>3,19
15838 +       sats r10>>2,26
15839 +       sats r1>>20,1
15840 +       .text
15841 +       .global satu
15842 +satu:
15843 +       satu pc>>0,0
15844 +       satu r12>>31,31
15845 +       satu r5>>16,16
15846 +       satu r4>>15,15
15847 +       satu lr>>1,1
15848 +       satu pc>>5,7
15849 +       satu r7>>5,5
15850 +       satu r2>>26,19
15851 +       .text
15852 +       .global satrnds
15853 +satrnds:
15854 +       satrnds pc>>0,0
15855 +       satrnds r12>>31,31
15856 +       satrnds r5>>16,16
15857 +       satrnds r4>>15,15
15858 +       satrnds lr>>1,1
15859 +       satrnds r0>>21,19
15860 +       satrnds sp>>0,2
15861 +       satrnds r7>>6,29
15862 +       .text
15863 +       .global satrndu
15864 +satrndu:
15865 +       satrndu pc>>0,0
15866 +       satrndu r12>>31,31
15867 +       satrndu r5>>16,16
15868 +       satrndu r4>>15,15
15869 +       satrndu lr>>1,1
15870 +       satrndu r12>>0,26
15871 +       satrndu r4>>21,3
15872 +       satrndu r10>>3,16
15873 +       .text
15874 +       .global subfc
15875 +subfc:
15876 +       subfeq pc,0
15877 +       subfal r12,-1
15878 +       subfls r5,-128
15879 +       subfpl r4,127
15880 +       subfne lr,1
15881 +       subfls r10,8
15882 +       subfvc r11,99
15883 +       subfvs r2,73
15884 +       .text
15885 +       .global subc
15886 +subc:
15887 +       subeq pc,0
15888 +       subal r12,-1
15889 +       subls r5,-128
15890 +       subpl r4,127
15891 +       subne lr,1
15892 +       subls r12,118
15893 +       subvc lr,-12
15894 +       submi r4,-13
15895 +       .text
15896 +       .global movc2
15897 +movc2:
15898 +       moveq pc,0
15899 +       moval r12,-1
15900 +       movls r5,-128
15901 +       movpl r4,127
15902 +       movne lr,1
15903 +       movlt r3,-122
15904 +       movvc r8,2
15905 +       movne r7,-111
15906 +       .text
15907 +       .global cp_b
15908 +cp_b:
15909 +       cp.b pc,r0
15910 +       cp.b r0,pc
15911 +       cp.b r7,r8
15912 +       cp.b r8,r7
15913 +       .text
15914 +       .global cp_h
15915 +cp_h:
15916 +       cp.h pc,r0
15917 +       cp.h r0,pc
15918 +       cp.h r7,r8
15919 +       cp.h r8,r7
15920 +       .text
15921 +       .global ldm
15922 +ldm:
15923 +       ldm pc,r1-r6
15924 +       ldm r12,r0-r15
15925 +       ldm r5,r15
15926 +       ldm r4,r0-r14
15927 +       ldm lr,r0
15928 +       ldm r9,r1,r5,r14
15929 +       ldm r11,r2-r3,r5-r8,r15
15930 +       ldm r6,r0,r3,r9,r13,r15
15931 +       .text
15932 +       .global ldm_pu
15933 +ldm_pu:
15934 +       ldm pc++,r6-r9
15935 +       ldm r12++,r0-r15
15936 +       ldm r5++,r15
15937 +       ldm r4++,r0-r14
15938 +       ldm lr++,r0
15939 +       ldm r12++,r3-r5,r8,r10,r12,r14-r15
15940 +       ldm r10++,r2,r4-r6,r14-r15
15941 +       ldm r6++,r1,r3-r4,r9-r14
15942 +       .text
15943 +       .global ldmts
15944 +ldmts:
15945 +       ldmts pc,r7-r8
15946 +       ldmts r12,r0-r15
15947 +       ldmts r5,r15
15948 +       ldmts r4,r0-r14
15949 +       ldmts lr,r0
15950 +       ldmts r0,r1-r2,r11-r12
15951 +       ldmts lr,r0-r2,r4,r7-r8,r13-r14
15952 +       ldmts r12,r0-r1,r3-r5,r9,r14-r15
15953 +       .text
15954 +       .global ldmts_pu
15955 +ldmts_pu:
15956 +       ldmts pc++,r9
15957 +       ldmts r12++,r0-r15
15958 +       ldmts r5++,r15
15959 +       ldmts r4++,r0-r14
15960 +       ldmts lr++,r0
15961 +       ldmts sp++,r0,r2-r5,r7,r9,r11
15962 +       ldmts r5++,r1-r3,r7,r10-r11
15963 +       ldmts r8++,r2-r4,r7-r8,r13,r15
15964 +       .text
15965 +       .global stm
15966 +stm:
15967 +       stm pc,r7
15968 +       stm r12,r0-r15
15969 +       stm r5,r15
15970 +       stm r4,r0-r14
15971 +       stm lr,r0
15972 +       stm sp,r2-r3,r5,r8,r11,r14
15973 +       stm r4,r0-r4,r6,r10-r11,r14
15974 +       stm r9,r1,r5,r9,r12-r15
15975 +       .text
15976 +       .global stm_pu
15977 +stm_pu:
15978 +       stm --pc,r4-r6
15979 +       stm --r12,r0-r15
15980 +       stm --r5,r15
15981 +       stm --r4,r0-r14
15982 +       stm --lr,r0
15983 +       stm --r11,r0,r4-r9,r11-r15
15984 +       stm --r11,r0,r3,r9-r10,r12,r14
15985 +       stm --r6,r2,r8-r9,r13-r14
15986 +       .text
15987 +       .global stmts
15988 +stmts:
15989 +       stmts pc,r8
15990 +       stmts r12,r0-r15
15991 +       stmts r5,r15
15992 +       stmts r4,r0-r14
15993 +       stmts lr,r0
15994 +       stmts r1,r0-r1,r3-r4,r6,r9-r10,r14-r15
15995 +       stmts r3,r0,r6-r8,r10-r12
15996 +       stmts r11,r0,r4,r6-r7,r9-r10,r12,r14-r15
15997 +       .text
15998 +       .global stmts_pu
15999 +stmts_pu:
16000 +       stmts --pc,r6-r8
16001 +       stmts --r12,r0-r15
16002 +       stmts --r5,r15
16003 +       stmts --r4,r0-r14
16004 +       stmts --lr,r0
16005 +       stmts --r2,r0,r3-r4,r9-r10,r12-r13
16006 +       stmts --r3,r0-r1,r14-r15
16007 +       stmts --r0,r0,r2-r6,r10,r14
16008 +       .text
16009 +       .global ldins_h
16010 +ldins_h:
16011 +       ldins.h pc:b,pc[0]
16012 +       ldins.h r12:t,r12[-2]
16013 +       ldins.h r5:t,r5[-4096]
16014 +       ldins.h r4:b,r4[4094]
16015 +       ldins.h lr:t,lr[2]
16016 +       ldins.h r0:t,lr[1930]
16017 +       ldins.h r3:b,r7[-534]
16018 +       ldins.h r2:b,r12[-2252]
16019 +       .text
16020 +       .global ldins_b
16021 +ldins_b:
16022 +       ldins.b pc:b,pc[0]
16023 +       ldins.b r12:t,r12[-1]
16024 +       ldins.b r5:u,r5[-2048]
16025 +       ldins.b r4:l,r4[2047]
16026 +       ldins.b lr:l,lr[1]
16027 +       ldins.b r6:t,r4[-662]
16028 +       ldins.b r5:b,r1[-151]
16029 +       ldins.b r10:t,r11[-1923]
16030 +       .text
16031 +       .global ldswp_sh
16032 +ldswp_sh:
16033 +       ldswp.sh pc,pc[0]
16034 +       ldswp.sh r12,r12[-2]
16035 +       ldswp.sh r5,r5[-4096]
16036 +       ldswp.sh r4,r4[4094]
16037 +       ldswp.sh lr,lr[2]
16038 +       ldswp.sh r9,r10[3848]
16039 +       ldswp.sh r4,r12[-2040]
16040 +       ldswp.sh r10,r2[3088]
16041 +       .text
16042 +       .global ldswp_uh
16043 +ldswp_uh:
16044 +       ldswp.uh pc,pc[0]
16045 +       ldswp.uh r12,r12[-2]
16046 +       ldswp.uh r5,r5[-4096]
16047 +       ldswp.uh r4,r4[4094]
16048 +       ldswp.uh lr,lr[2]
16049 +       ldswp.uh r4,r9[3724]
16050 +       ldswp.uh lr,sp[-1672]
16051 +       ldswp.uh r8,r12[-3846]
16052 +       .text
16053 +       .global ldswp_w
16054 +ldswp_w:
16055 +       ldswp.w pc,pc[0]
16056 +       ldswp.w r12,r12[-4]
16057 +       ldswp.w r5,r5[-8192]
16058 +       ldswp.w r4,r4[8188]
16059 +       ldswp.w lr,lr[4]
16060 +       ldswp.w sp,r7[1860]
16061 +       ldswp.w pc,r5[-3324]
16062 +       ldswp.w r12,r10[-3296]
16063 +       .text
16064 +       .global stswp_h
16065 +stswp_h:
16066 +       stswp.h pc[0],pc
16067 +       stswp.h r12[-2],r12
16068 +       stswp.h r5[-4096],r5
16069 +       stswp.h r4[4094],r4
16070 +       stswp.h lr[2],lr
16071 +       stswp.h r7[64],r10
16072 +       stswp.h r10[3024],r2
16073 +       stswp.h r0[-2328],r10
16074 +       .text
16075 +       .global stswp_w
16076 +stswp_w:
16077 +       stswp.w pc[0],pc
16078 +       stswp.w r12[-4],r12
16079 +       stswp.w r5[-8192],r5
16080 +       stswp.w r4[8188],r4
16081 +       stswp.w lr[4],lr
16082 +       stswp.w pc[1156],r8
16083 +       stswp.w sp[7992],r10
16084 +       stswp.w r8[-1172],r5
16085 +       .text
16086 +       .global and2
16087 +and2:
16088 +       and pc,pc,pc<<0
16089 +       and r12,r12,r12<<31
16090 +       and r5,r5,r5<<16
16091 +       and r4,r4,r4<<15
16092 +       and lr,lr,lr<<1
16093 +       and r10,r2,r1<<1
16094 +       and r12,r8,r11<<27
16095 +       and r10,r7,r0<<3
16096 +       .text
16097 +       .global and3
16098 +and3:
16099 +       and pc,pc,pc>>0
16100 +       and r12,r12,r12>>31
16101 +       and r5,r5,r5>>16
16102 +       and r4,r4,r4>>15
16103 +       and lr,lr,lr>>1
16104 +       and r12,r8,r7>>17
16105 +       and pc,r4,r9>>20
16106 +       and r10,r9,r10>>12
16107 +       .text
16108 +       .global or2
16109 +or2:
16110 +       or pc,pc,pc<<0
16111 +       or r12,r12,r12<<31
16112 +       or r5,r5,r5<<16
16113 +       or r4,r4,r4<<15
16114 +       or lr,lr,lr<<1
16115 +       or r8,sp,r11<<29
16116 +       or pc,r9,r2<<28
16117 +       or r5,r1,r2<<3
16118 +       .text
16119 +       .global or3
16120 +or3:
16121 +       or pc,pc,pc>>0
16122 +       or r12,r12,r12>>31
16123 +       or r5,r5,r5>>16
16124 +       or r4,r4,r4>>15
16125 +       or lr,lr,lr>>1
16126 +       or r1,sp,sp>>2
16127 +       or r0,r1,r1>>29
16128 +       or r4,r12,r8>>8
16129 +       .text
16130 +       .global eor2
16131 +eor2:
16132 +       eor pc,pc,pc<<0
16133 +       eor r12,r12,r12<<31
16134 +       eor r5,r5,r5<<16
16135 +       eor r4,r4,r4<<15
16136 +       eor lr,lr,lr<<1
16137 +       eor r10,r9,r4<<11
16138 +       eor r4,r0,r1<<31
16139 +       eor r6,r2,r12<<13
16140 +       .text
16141 +       .global eor3
16142 +eor3:
16143 +       eor pc,pc,pc>>0
16144 +       eor r12,r12,r12>>31
16145 +       eor r5,r5,r5>>16
16146 +       eor r4,r4,r4>>15
16147 +       eor lr,lr,lr>>1
16148 +       eor r5,r5,r5>>22
16149 +       eor r10,r1,lr>>3
16150 +       eor r7,lr,sp>>26
16151 +       .text
16152 +       .global sthh_w2
16153 +sthh_w2:
16154 +       sthh.w pc[pc<<0],pc:b,pc:b
16155 +       sthh.w r12[r12<<3],r12:t,r12:t
16156 +       sthh.w r5[r5<<2],r5:t,r5:t
16157 +       sthh.w r4[r4<<1],r4:b,r4:b
16158 +       sthh.w lr[lr<<1],lr:t,lr:t
16159 +       sthh.w sp[r6<<3],r1:t,r12:t
16160 +       sthh.w r6[r6<<0],r9:t,r9:t
16161 +       sthh.w r10[r3<<0],r0:b,r11:t
16162 +       .text
16163 +       .global sthh_w1
16164 +sthh_w1:
16165 +       sthh.w pc[0],pc:b,pc:b
16166 +       sthh.w r12[1020],r12:t,r12:t
16167 +       sthh.w r5[512],r5:t,r5:t
16168 +       sthh.w r4[508],r4:b,r4:b
16169 +       sthh.w lr[4],lr:t,lr:t
16170 +       sthh.w r4[404],r9:t,r0:b
16171 +       sthh.w r8[348],r2:t,r10:b
16172 +       sthh.w sp[172],r9:b,r2:b
16173 +       .text
16174 +       .global cop
16175 +cop:
16176 +       cop cp0,cr0,cr0,cr0,0
16177 +       cop cp7,cr15,cr15,cr15,0x7f
16178 +       cop cp3,cr5,cr5,cr5,0x31
16179 +       cop cp2,cr4,cr4,cr4,0x30
16180 +       cop cp5,cr8,cr3,cr7,0x5a
16181 +       .text
16182 +       .global ldc_w1
16183 +ldc_w1:
16184 +       ldc.w cp0,cr0,r0[0]
16185 +       ldc.w cp7,cr15,pc[255<<2]
16186 +       ldc.w cp3,cr5,r5[128<<2]
16187 +       ldc.w cp2,cr4,r4[127<<2]
16188 +       ldc.w cp4,cr9,r13[36<<2]
16189 +       .text
16190 +       .global ldc_w2
16191 +ldc_w2:
16192 +       ldc.w cp0,cr0,--r0
16193 +       ldc.w cp7,cr15,--pc
16194 +       ldc.w cp3,cr5,--r5
16195 +       ldc.w cp2,cr4,--r4
16196 +       ldc.w cp4,cr9,--r13
16197 +       .text
16198 +       .global ldc_w3
16199 +ldc_w3:
16200 +       ldc.w cp0,cr0,r0[r0]
16201 +       ldc.w cp7,cr15,pc[pc<<3]
16202 +       ldc.w cp3,cr5,r5[r4<<2]
16203 +       ldc.w cp2,cr4,r4[r3<<1]
16204 +       ldc.w cp4,cr9,r13[r12<<0]
16205 +       .text
16206 +       .global ldc_d1
16207 +ldc_d1:
16208 +       ldc.d cp0,cr0,r0[0]
16209 +       ldc.d cp7,cr14,pc[255<<2]
16210 +       ldc.d cp3,cr6,r5[128<<2]
16211 +       ldc.d cp2,cr4,r4[127<<2]
16212 +       ldc.d cp4,cr8,r13[36<<2]
16213 +       .text
16214 +       .global ldc_d2
16215 +ldc_d2:
16216 +       ldc.d cp0,cr0,--r0
16217 +       ldc.d cp7,cr14,--pc
16218 +       ldc.d cp3,cr6,--r5
16219 +       ldc.d cp2,cr4,--r4
16220 +       ldc.d cp4,cr8,--r13
16221 +       .text
16222 +       .global ldc_d3
16223 +ldc_d3:
16224 +       ldc.d cp0,cr0,r0[r0]
16225 +       ldc.d cp7,cr14,pc[pc<<3]
16226 +       ldc.d cp3,cr6,r5[r4<<2]
16227 +       ldc.d cp2,cr4,r4[r3<<1]
16228 +       ldc.d cp4,cr8,r13[r12<<0]
16229 +       .text
16230 +       .global stc_w1
16231 +stc_w1:
16232 +       stc.w cp0,r0[0],cr0
16233 +       stc.w cp7,pc[255<<2],cr15
16234 +       stc.w cp3,r5[128<<2],cr5
16235 +       stc.w cp2,r4[127<<2],cr4
16236 +       stc.w cp4,r13[36<<2],cr9
16237 +       .text
16238 +       .global stc_w2
16239 +stc_w2:
16240 +       stc.w cp0,r0++,cr0
16241 +       stc.w cp7,pc++,cr15
16242 +       stc.w cp3,r5++,cr5
16243 +       stc.w cp2,r4++,cr4
16244 +       stc.w cp4,r13++,cr9
16245 +       .text
16246 +       .global stc_w3
16247 +stc_w3:
16248 +       stc.w cp0,r0[r0],cr0
16249 +       stc.w cp7,pc[pc<<3],cr15
16250 +       stc.w cp3,r5[r4<<2],cr5
16251 +       stc.w cp2,r4[r3<<1],cr4
16252 +       stc.w cp4,r13[r12<<0],cr9
16253 +       .text
16254 +       .global stc_d1
16255 +stc_d1:
16256 +       stc.d cp0,r0[0],cr0
16257 +       stc.d cp7,pc[255<<2],cr14
16258 +       stc.d cp3,r5[128<<2],cr6
16259 +       stc.d cp2,r4[127<<2],cr4
16260 +       stc.d cp4,r13[36<<2],cr8
16261 +       .text
16262 +       .global stc_d2
16263 +stc_d2:
16264 +       stc.d cp0,r0++,cr0
16265 +       stc.d cp7,pc++,cr14
16266 +       stc.d cp3,r5++,cr6
16267 +       stc.d cp2,r4++,cr4
16268 +       stc.d cp4,r13++,cr8
16269 +       .text
16270 +       .global stc_d3
16271 +stc_d3:
16272 +       stc.d cp0,r0[r0],cr0
16273 +       stc.d cp7,pc[pc<<3],cr14
16274 +       stc.d cp3,r5[r4<<2],cr6
16275 +       stc.d cp2,r4[r3<<1],cr4
16276 +       stc.d cp4,r13[r12<<0],cr8
16277 +       .text
16278 +       .global ldc0_w
16279 +ldc0_w:
16280 +       ldc0.w cr0,r0[0]
16281 +       ldc0.w cr15,pc[4095<<2]
16282 +       ldc0.w cr5,r5[2048<<2]
16283 +       ldc0.w cr4,r4[2047<<2]
16284 +       ldc0.w cr9,r13[147<<2]
16285 +       .text
16286 +       .global ldc0_d
16287 +ldc0_d:
16288 +       ldc0.d cr0,r0[0]
16289 +       ldc0.d cr14,pc[4095<<2]
16290 +       ldc0.d cr6,r5[2048<<2]
16291 +       ldc0.d cr4,r4[2047<<2]
16292 +       ldc0.d cr8,r13[147<<2]
16293 +       .text
16294 +       .global stc0_w
16295 +stc0_w:
16296 +       stc0.w r0[0],cr0
16297 +       stc0.w pc[4095<<2],cr15
16298 +       stc0.w r5[2048<<2],cr5
16299 +       stc0.w r4[2047<<2],cr4
16300 +       stc0.w r13[147<<2],cr9
16301 +       .text
16302 +       .global stc0_d
16303 +stc0_d:
16304 +       stc0.d r0[0],cr0
16305 +       stc0.d pc[4095<<2],cr14
16306 +       stc0.d r5[2048<<2],cr6
16307 +       stc0.d r4[2047<<2],cr4
16308 +       stc0.d r13[147<<2],cr8
16309 +       .text
16310 +       .global memc
16311 +memc:
16312 +       memc 0, 0
16313 +       memc -4, 31
16314 +       memc -65536, 16
16315 +       memc 65532, 15
16316 +       .text
16317 +       .global mems
16318 +mems:
16319 +       mems 0, 0
16320 +       mems -4, 31
16321 +       mems -65536, 16
16322 +       mems 65532, 15
16323 +       .text
16324 +       .global memt
16325 +memt:
16326 +       memt 0, 0
16327 +       memt -4, 31
16328 +       memt -65536, 16
16329 +       memt 65532, 15
16330 +
16331 +       .text
16332 +       .global stcond
16333 +stcond:
16334 +       stcond r0[0], r0
16335 +       stcond pc[-1], pc
16336 +       stcond r8[-32768], r7
16337 +       stcond r7[32767], r8
16338 +       stcond r5[0x1234], r10
16339 +
16340 +ldcm_w:
16341 +       ldcm.w cp0,pc,cr0-cr7
16342 +       ldcm.w cp7,r0,cr0
16343 +       ldcm.w cp4,r4++,cr0-cr6
16344 +       ldcm.w cp3,r7,cr7
16345 +       ldcm.w cp1,r12++,cr1,cr4-cr6
16346 +       ldcm.w cp0,pc,cr8-cr15
16347 +       ldcm.w cp7,r0,cr8
16348 +       ldcm.w cp4,r4++,cr8-cr14
16349 +       ldcm.w cp3,r7,cr15
16350 +       ldcm.w cp1,r12++,cr9,cr12-cr14
16351 +
16352 +ldcm_d:
16353 +       ldcm.d cp0,pc,cr0-cr15
16354 +       ldcm.d cp7,r0,cr0,cr1
16355 +       ldcm.d cp4,r4++,cr0-cr13
16356 +       ldcm.d cp3,r7,cr14-cr15
16357 +       ldcm.d cp2,r12++,cr0-cr3,cr8-cr9,cr14-cr15
16358 +
16359 +stcm_w:
16360 +       stcm.w cp0,pc,cr0-cr7
16361 +       stcm.w cp7,r0,cr0
16362 +       stcm.w cp4,--r4,cr0-cr6
16363 +       stcm.w cp3,r7,cr7
16364 +       stcm.w cp1,--r12,cr1,cr4-cr6
16365 +       stcm.w cp0,pc,cr8-cr15
16366 +       stcm.w cp7,r0,cr8
16367 +       stcm.w cp4,--r4,cr8-cr14
16368 +       stcm.w cp3,r7,cr15
16369 +       stcm.w cp1,--r12,cr9,cr12-cr14
16370 +
16371 +stcm_d:
16372 +       stcm.d cp0,pc,cr0-cr15
16373 +       stcm.d cp7,r0,cr0,cr1
16374 +       stcm.d cp4,--r4,cr0-cr13
16375 +       stcm.d cp3,r7,cr14-cr15
16376 +       stcm.d cp2,--r12,cr0-cr3,cr8-cr9,cr14-cr15
16377 +
16378 +mvcr_w:
16379 +       mvcr.w cp7,pc,cr15
16380 +       mvcr.w cp0,r0,cr0
16381 +       mvcr.w cp0,pc,cr15
16382 +       mvcr.w cp7,r0,cr15
16383 +       mvcr.w cp7,pc,cr0
16384 +       mvcr.w cp4,r7,cr8
16385 +       mvcr.w cp3,r8,cr7
16386 +
16387 +mvcr_d:
16388 +       mvcr.d cp7,lr,cr14
16389 +       mvcr.d cp0,r0,cr0
16390 +       mvcr.d cp0,lr,cr14
16391 +       mvcr.d cp7,r0,cr14
16392 +       mvcr.d cp7,lr,cr0
16393 +       mvcr.d cp4,r6,cr8
16394 +       mvcr.d cp3,r8,cr6
16395 +
16396 +mvrc_w:
16397 +       mvrc.w cp7,cr15,pc
16398 +       mvrc.w cp0,cr0,r0
16399 +       mvrc.w cp0,cr15,pc
16400 +       mvrc.w cp7,cr15,r0
16401 +       mvrc.w cp7,cr0,pc
16402 +       mvrc.w cp4,cr8,r7
16403 +       mvrc.w cp3,cr7,r8
16404 +
16405 +mvrc_d:
16406 +       mvrc.d cp7,cr14,lr
16407 +       mvrc.d cp0,cr0,r0
16408 +       mvrc.d cp0,cr14,lr
16409 +       mvrc.d cp7,cr14,r0
16410 +       mvrc.d cp7,cr0,lr
16411 +       mvrc.d cp4,cr8,r6
16412 +       mvrc.d cp3,cr6,r8
16413 +
16414 +bfexts:
16415 +       bfexts pc,pc,31,31
16416 +       bfexts r0,r0,0,0
16417 +       bfexts r0,pc,31,31
16418 +       bfexts pc,r0,31,31
16419 +       bfexts pc,pc,0,31
16420 +       bfexts pc,pc,31,0
16421 +       bfexts r7,r8,15,16
16422 +       bfexts r8,r7,16,15
16423 +
16424 +bfextu:
16425 +       bfextu pc,pc,31,31
16426 +       bfextu r0,r0,0,0
16427 +       bfextu r0,pc,31,31
16428 +       bfextu pc,r0,31,31
16429 +       bfextu pc,pc,0,31
16430 +       bfextu pc,pc,31,0
16431 +       bfextu r7,r8,15,16
16432 +       bfextu r8,r7,16,15
16433 +
16434 +bfins:
16435 +       bfins pc,pc,31,31
16436 +       bfins r0,r0,0,0
16437 +       bfins r0,pc,31,31
16438 +       bfins pc,r0,31,31
16439 +       bfins pc,pc,0,31
16440 +       bfins pc,pc,31,0
16441 +       bfins r7,r8,15,16
16442 +       bfins r8,r7,16,15
16443 +
16444 +rsubc:
16445 +       rsubeq pc,0
16446 +       rsubal r12,-1
16447 +       rsubls r5,-128
16448 +       rsubpl r4,127
16449 +       rsubne lr,1
16450 +       rsubls r12,118
16451 +       rsubvc lr,-12
16452 +       rsubmi r4,-13
16453 +
16454 +addc:
16455 +       addeq pc,pc,pc
16456 +       addal r12,r12,r12
16457 +       addls r5,r5,r5
16458 +       addpl r4,r4,r4
16459 +       addne lr,lr,lr
16460 +       addls r10,r2,r1
16461 +       addvc r12,r8,r11
16462 +       addmi r10,r7,r0
16463 +
16464 +subc2:
16465 +       subeq pc,pc,pc
16466 +       subal r12,r12,r12
16467 +       subls r5,r5,r5
16468 +       subpl r4,r4,r4
16469 +       subne lr,lr,lr
16470 +       subls r10,r2,r1
16471 +       subvc r12,r8,r11
16472 +       submi r10,r7,r0
16473 +
16474 +andc:
16475 +       andeq pc,pc,pc
16476 +       andal r12,r12,r12
16477 +       andls r5,r5,r5
16478 +       andpl r4,r4,r4
16479 +       andne lr,lr,lr
16480 +       andls r10,r2,r1
16481 +       andvc r12,r8,r11
16482 +       andmi r10,r7,r0
16483 +
16484 +orc:
16485 +       oreq pc,pc,pc
16486 +       oral r12,r12,r12
16487 +       orls r5,r5,r5
16488 +       orpl r4,r4,r4
16489 +       orne lr,lr,lr
16490 +       orls r10,r2,r1
16491 +       orvc r12,r8,r11
16492 +       ormi r10,r7,r0
16493 +
16494 +eorc:
16495 +       eoreq pc,pc,pc
16496 +       eoral r12,r12,r12
16497 +       eorls r5,r5,r5
16498 +       eorpl r4,r4,r4
16499 +       eorne lr,lr,lr
16500 +       eorls r10,r2,r1
16501 +       eorvc r12,r8,r11
16502 +       eormi r10,r7,r0
16503 +
16504 +ldcond:
16505 +       ld.weq  pc,pc[2044]
16506 +       ld.shal r12,r12[1022]
16507 +       ld.uhls r5,r5[0]
16508 +       ld.ubpl r4,r4[511]
16509 +       ld.sbne lr,lr[0]
16510 +       ld.wls  r10,r2[0]
16511 +       ld.shvc r12,r8[0x3fe]
16512 +       ld.ubmi r10,r7[1]
16513 +
16514 +stcond2:
16515 +       st.weq pc[2044],pc
16516 +       st.hal r12[1022],r12
16517 +       st.hls r5[0],r5
16518 +       st.bpl r4[511],r4
16519 +       st.bne lr[0],lr
16520 +       st.wls r2[0],r10
16521 +       st.hvc r8[0x3fe],r12
16522 +       st.bmi r7[1],r10
16523 +
16524 +movh:
16525 +       movh    pc, 65535
16526 +       movh    r0, 0
16527 +       movh    r5, 1
16528 +       movh    r12, 32767
16529 +
16530 +
16531 --- /dev/null
16532 +++ b/gas/testsuite/gas/avr32/avr32.exp
16533 @@ -0,0 +1,23 @@
16534 +# AVR32 assembler testsuite. -*- Tcl -*-
16535 +
16536 +if [istarget avr32-*-*] {
16537 +    run_dump_test "hwrd-lwrd"
16538 +    run_dump_test "pcrel"
16539 +    run_dump_test "aliases"
16540 +    run_dump_test "dwarf2"
16541 +    run_dump_test "pic_reloc"
16542 +    run_dump_test "fpinsn"
16543 +    run_dump_test "pico"
16544 +    run_dump_test "lda_pic"
16545 +    run_dump_test "lda_pic_linkrelax"
16546 +    run_dump_test "lda_nopic"
16547 +    run_dump_test "lda_nopic_linkrelax"
16548 +    run_dump_test "call_pic"
16549 +    run_dump_test "call_pic_linkrelax"
16550 +    run_dump_test "call_nopic"
16551 +    run_dump_test "call_nopic_linkrelax"
16552 +    run_dump_test "jmptable"
16553 +    run_dump_test "jmptable_linkrelax"
16554 +    run_dump_test "symdiff"
16555 +    run_dump_test "symdiff_linkrelax"
16556 +}
16557 --- /dev/null
16558 +++ b/gas/testsuite/gas/avr32/call_nopic.d
16559 @@ -0,0 +1,36 @@
16560 +#source: call.s
16561 +#as:
16562 +#objdump: -dr
16563 +#name: call_nopic
16564 +
16565 +.*: +file format .*
16566 +
16567 +Disassembly of section \.text:
16568 +
16569 +00000000 <call_test>:
16570 +       0:      d7 03           nop
16571 +
16572 +00000002 <toofar_negative>:
16573 +       \.\.\.
16574 +  1ffffe:      00 00           add r0,r0
16575 +  200000:      f0 a0 00 00     rcall 0 <call_test>
16576 +  200004:      f0 1f 00 0c     mcall 200034 <toofar_negative\+0x200032>
16577 +  200008:      f0 1f 00 0c     mcall 200038 <toofar_negative\+0x200036>
16578 +  20000c:      f0 1f 00 0c     mcall 20003c <toofar_negative\+0x20003a>
16579 +  200010:      f0 1f 00 0c     mcall 200040 <toofar_negative\+0x20003e>
16580 +       \.\.\.
16581 +  200030:      ee b0 ff ff     rcall 40002e <far_positive>
16582 +       \.\.\.
16583 +                       200034: R_AVR32_32_CPENT        \.text\+0x2
16584 +                       200038: R_AVR32_32_CPENT        \.text\.init
16585 +                       20003c: R_AVR32_32_CPENT        undefined
16586 +                       200040: R_AVR32_32_CPENT        \.text\+0x40002c
16587 +
16588 +0040002c <toofar_positive>:
16589 +  40002c:      d7 03           nop
16590 +0040002e <far_positive>:
16591 +  40002e:      d7 03           nop
16592 +Disassembly of section \.text\.init:
16593 +
16594 +00000000 <different_section>:
16595 +   0:  e2 c0 00 00     sub r0,r1,0
16596 --- /dev/null
16597 +++ b/gas/testsuite/gas/avr32/call_nopic_linkrelax.d
16598 @@ -0,0 +1,43 @@
16599 +#source: call.s
16600 +#as: --linkrelax
16601 +#objdump: -dr
16602 +#name: call_nopic_linkrelax
16603 +
16604 +.*: +file format .*
16605 +
16606 +Disassembly of section \.text:
16607 +
16608 +00000000 <call_test>:
16609 +       0:      d7 03           nop
16610 +
16611 +00000002 <toofar_negative>:
16612 +       \.\.\.
16613 +  1ffffe:      00 00           add r0,r0
16614 +  200000:      e0 a0 00 00     rcall 200000 <toofar_negative\+0x1ffffe>
16615 +                       200000: R_AVR32_22H_PCREL       \.text
16616 +  200004:      f0 1f 00 00     mcall 200004 <toofar_negative\+0x200002>
16617 +                       200004: R_AVR32_CPCALL  \.text\+0x200034
16618 +  200008:      f0 1f 00 00     mcall 200008 <toofar_negative\+0x200006>
16619 +                       200008: R_AVR32_CPCALL  \.text\+0x200038
16620 +  20000c:      f0 1f 00 00     mcall 20000c <toofar_negative\+0x20000a>
16621 +                       20000c: R_AVR32_CPCALL  \.text\+0x20003c
16622 +  200010:      f0 1f 00 00     mcall 200010 <toofar_negative\+0x20000e>
16623 +                       200010: R_AVR32_CPCALL  \.text\+0x200040
16624 +       \.\.\.
16625 +  200030:      e0 a0 00 00     rcall 200030 <toofar_negative\+0x20002e>
16626 +                       200030: R_AVR32_22H_PCREL       \.text\+0x40002e
16627 +       \.\.\.
16628 +                       200034: R_AVR32_ALIGN   \*ABS\*\+0x2
16629 +                       200034: R_AVR32_32_CPENT        \.text\+0x2
16630 +                       200038: R_AVR32_32_CPENT        \.text\.init
16631 +                       20003c: R_AVR32_32_CPENT        undefined
16632 +                       200040: R_AVR32_32_CPENT        \.text\+0x40002c
16633 +
16634 +0040002c <toofar_positive>:
16635 +  40002c:      d7 03           nop
16636 +0040002e <far_positive>:
16637 +  40002e:      d7 03           nop
16638 +Disassembly of section \.text\.init:
16639 +
16640 +00000000 <different_section>:
16641 +   0:  e2 c0 00 00     sub r0,r1,0
16642 --- /dev/null
16643 +++ b/gas/testsuite/gas/avr32/call_pic.d
16644 @@ -0,0 +1,36 @@
16645 +#source: call.s
16646 +#as: --pic
16647 +#objdump: -dr
16648 +#name: call_pic
16649 +
16650 +.*: +file format .*
16651 +
16652 +Disassembly of section \.text:
16653 +
16654 +00000000 <call_test>:
16655 +       0:      d7 03           nop
16656 +
16657 +00000002 <toofar_negative>:
16658 +       \.\.\.
16659 +  1ffffe:      00 00           add r0,r0
16660 +  200000:      f0 a0 00 00     rcall 0 <call_test>
16661 +  200004:      f0 16 00 00     mcall r6\[0\]
16662 +                       200004: R_AVR32_GOT18SW toofar_negative
16663 +  200008:      f0 16 00 00     mcall r6\[0\]
16664 +                       200008: R_AVR32_GOT18SW different_section
16665 +  20000c:      f0 16 00 00     mcall r6\[0\]
16666 +                       20000c: R_AVR32_GOT18SW undefined
16667 +  200010:      f0 16 00 00     mcall r6\[0\]
16668 +                       200010: R_AVR32_GOT18SW toofar_positive
16669 +       \.\.\.
16670 +  200030:      ee b0 ff ff     rcall 40002e <far_positive>
16671 +       \.\.\.
16672 +
16673 +0040002c <toofar_positive>:
16674 +  40002c:      d7 03           nop
16675 +0040002e <far_positive>:
16676 +  40002e:      d7 03           nop
16677 +Disassembly of section \.text\.init:
16678 +
16679 +00000000 <different_section>:
16680 +   0:  e2 c0 00 00     sub r0,r1,0
16681 --- /dev/null
16682 +++ b/gas/testsuite/gas/avr32/call_pic_linkrelax.d
16683 @@ -0,0 +1,47 @@
16684 +#source: call.s
16685 +#as: --pic --linkrelax
16686 +#objdump: -dr
16687 +#name: call_pic_linkrelax
16688 +
16689 +.*: +file format .*
16690 +
16691 +Disassembly of section \.text:
16692 +
16693 +00000000 <call_test>:
16694 +       0:      d7 03           nop
16695 +
16696 +00000002 <toofar_negative>:
16697 +       \.\.\.
16698 +  1ffffe:      00 00           add r0,r0
16699 +  200000:      e0 a0 00 00     rcall 200000 <toofar_negative\+0x1ffffe>
16700 +                       200000: R_AVR32_22H_PCREL       \.text
16701 +  200004:      e0 6e 00 00     mov lr,0
16702 +                       200004: R_AVR32_GOTCALL toofar_negative
16703 +  200008:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16704 +  20000c:      5d 1e           icall lr
16705 +  20000e:      e0 6e 00 00     mov lr,0
16706 +                       20000e: R_AVR32_GOTCALL different_section
16707 +  200012:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16708 +  200016:      5d 1e           icall lr
16709 +  200018:      e0 6e 00 00     mov lr,0
16710 +                       200018: R_AVR32_GOTCALL undefined
16711 +  20001c:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16712 +  200020:      5d 1e           icall lr
16713 +  200022:      e0 6e 00 00     mov lr,0
16714 +                       200022: R_AVR32_GOTCALL toofar_positive
16715 +  200026:      ec 0e 03 2e     ld\.w lr,r6\[lr<<0x2\]
16716 +  20002a:      5d 1e           icall lr
16717 +  20002c:      00 00           add r0,r0
16718 +  20002e:      00 00           add r0,r0
16719 +  200030:      e0 a0 00 00     rcall 200030 <toofar_negative\+0x20002e>
16720 +                       200030: R_AVR32_22H_PCREL       \.text\+0x40002e
16721 +       \.\.\.
16722 +
16723 +0040002c <toofar_positive>:
16724 +  40002c:      d7 03           nop
16725 +0040002e <far_positive>:
16726 +  40002e:      d7 03           nop
16727 +Disassembly of section \.text\.init:
16728 +
16729 +00000000 <different_section>:
16730 +   0:  e2 c0 00 00     sub r0,r1,0
16731 --- /dev/null
16732 +++ b/gas/testsuite/gas/avr32/call.s
16733 @@ -0,0 +1,30 @@
16734 +
16735 +       .text
16736 +       .global call_test
16737 +call_test:
16738 +far_negative:
16739 +       nop
16740 +toofar_negative:
16741 +
16742 +       .org    0x200000
16743 +
16744 +       call    far_negative
16745 +       call    toofar_negative
16746 +       call    different_section
16747 +       call    undefined
16748 +       call    toofar_positive
16749 +       .org    0x200030
16750 +       call    far_positive
16751 +
16752 +       .cpool
16753 +
16754 +       .org    0x40002c
16755 +
16756 +toofar_positive:
16757 +       nop
16758 +far_positive:
16759 +       nop
16760 +
16761 +       .section .text.init,"ax",@progbits
16762 +different_section:
16763 +       sub     r0, r1, 0
16764 --- /dev/null
16765 +++ b/gas/testsuite/gas/avr32/dwarf2.d
16766 @@ -0,0 +1,42 @@
16767 +#readelf: -wl
16768 +#name: dwarf2
16769 +#source: dwarf2.s
16770 +
16771 +Dump of debug contents of section \.debug_line:
16772 +
16773 +  Length:                      53
16774 +  DWARF Version:               2
16775 +  Prologue Length:             26
16776 +  Minimum Instruction Length:  1
16777 +  Initial value of 'is_stmt':  1
16778 +  Line Base:                   -5
16779 +  Line Range:                  14
16780 +  Opcode Base:                 10
16781 +  \(Pointer size:               4\)
16782 +
16783 + Opcodes:
16784 +  Opcode 1 has 0 args
16785 +  Opcode 2 has 1 args
16786 +  Opcode 3 has 1 args
16787 +  Opcode 4 has 1 args
16788 +  Opcode 5 has 1 args
16789 +  Opcode 6 has 0 args
16790 +  Opcode 7 has 0 args
16791 +  Opcode 8 has 0 args
16792 +  Opcode 9 has 1 args
16793 +
16794 + The Directory Table is empty\.
16795 +
16796 + The File Name Table:
16797 +  Entry        Dir     Time    Size    Name
16798 +  1    0       0       0       main\.c
16799 +
16800 + Line Number Statements:
16801 +  Extended opcode 2: set Address to 0x0
16802 +  Advance Line by 87 to 88
16803 +  Copy
16804 +  Advance Line by 23 to 111
16805 +  Special opcode .*: advance Address by 4 to 0x4 and Line by 0 to 111
16806 +  Special opcode .*: advance Address by 10 to 0xe and Line by 1 to 112
16807 +  Advance PC by 530 to 220
16808 +  Extended opcode 1: End of Sequence
16809 --- /dev/null
16810 +++ b/gas/testsuite/gas/avr32/dwarf2.s
16811 @@ -0,0 +1,67 @@
16812 +# Source file used to test DWARF2 information for AVR32.
16813 +
16814 +       .file   "main.c"
16815 +
16816 +       .section .debug_abbrev,"",@progbits
16817 +.Ldebug_abbrev0:
16818 +       .section .debug_info,"",@progbits
16819 +.Ldebug_info0:
16820 +       .section .debug_line,"",@progbits
16821 +.Ldebug_line0:
16822 +
16823 +       .text
16824 +       .align  1
16825 +       .globl  main
16826 +       .type   main, @function
16827 +.Ltext0:
16828 +main:
16829 +       .file 1 "main.c"
16830 +       .loc 1 88 0
16831 +       pushm   r0-r7,lr
16832 +       sub     sp, 4
16833 +       .loc 1 111 0
16834 +       lddpc   r12, .LC1
16835 +       lddpc   r7, .LC1
16836 +       icall   r7
16837 +       .loc 1 112 0
16838 +       lddpc   r6, .LC4
16839 +
16840 +       .align  2
16841 +.LC4:  .int    0
16842 +
16843 +       .fill   256, 2, 0
16844 +
16845 +       .align  2
16846 +.LC1:
16847 +       .int    0
16848 +.LC2:
16849 +       .int    0
16850 +.LC3:
16851 +       .int    0
16852 +       .size   main, . - main
16853 +
16854 +.Letext0:
16855 +
16856 +       .section .debug_info
16857 +       .int    .Ledebug_info0 - .Ldebug_info0  // size
16858 +       .short  2                               // version
16859 +       .int    .Ldebug_abbrev0                 // abbrev offset
16860 +       .byte   4                               // bytes per addr
16861 +
16862 +       .uleb128 1                              // abbrev 1
16863 +       .int    .Ldebug_line0                   // DW_AT_stmt_list
16864 +       .int    .Letext0                        // DW_AT_high_pc
16865 +       .int    .Ltext0                         // DW_AT_low_pc
16866 +
16867 +.Ledebug_info0:
16868 +
16869 +       .section .debug_abbrev
16870 +       .uleb128 0x01
16871 +       .uleb128 0x11           // DW_TAG_compile_unit
16872 +       .byte   0               // DW_CHILDREN_no
16873 +       .uleb128 0x10, 0x6      // DW_AT_stmt_list
16874 +       .uleb128 0x12, 0x1      // DW_AT_high_pc
16875 +       .uleb128 0x11, 0x1      // DW_AT_low_pc
16876 +       .uleb128 0, 0
16877 +
16878 +       .byte   0
16879 --- /dev/null
16880 +++ b/gas/testsuite/gas/avr32/fpinsn.d
16881 @@ -0,0 +1,271 @@
16882 +#as:
16883 +#objdump: -dr
16884 +#name: fpinsn
16885 +
16886 +.*: +file format .*
16887 +
16888 +Disassembly of section \.text:
16889 +
16890 +[0-9a-f]* <fadd_s>:
16891 + *[0-9a-f]*:   e1 a2 0f ff     cop cp0,cr15,cr15,cr15,0x4
16892 + *[0-9a-f]*:   e1 a2 00 00     cop cp0,cr0,cr0,cr0,0x4
16893 + *[0-9a-f]*:   e1 a2 00 ff     cop cp0,cr0,cr15,cr15,0x4
16894 + *[0-9a-f]*:   e1 a2 0f 0f     cop cp0,cr15,cr0,cr15,0x4
16895 + *[0-9a-f]*:   e1 a2 0f f0     cop cp0,cr15,cr15,cr0,0x4
16896 + *[0-9a-f]*:   e1 a2 07 88     cop cp0,cr7,cr8,cr8,0x4
16897 + *[0-9a-f]*:   e1 a2 08 78     cop cp0,cr8,cr7,cr8,0x4
16898 + *[0-9a-f]*:   e1 a2 08 87     cop cp0,cr8,cr8,cr7,0x4
16899 +
16900 +[0-9a-f]* <fsub_s>:
16901 + *[0-9a-f]*:   e1 a2 1f ff     cop cp0,cr15,cr15,cr15,0x5
16902 + *[0-9a-f]*:   e1 a2 10 00     cop cp0,cr0,cr0,cr0,0x5
16903 + *[0-9a-f]*:   e1 a2 10 ff     cop cp0,cr0,cr15,cr15,0x5
16904 + *[0-9a-f]*:   e1 a2 1f 0f     cop cp0,cr15,cr0,cr15,0x5
16905 + *[0-9a-f]*:   e1 a2 1f f0     cop cp0,cr15,cr15,cr0,0x5
16906 + *[0-9a-f]*:   e1 a2 17 88     cop cp0,cr7,cr8,cr8,0x5
16907 + *[0-9a-f]*:   e1 a2 18 78     cop cp0,cr8,cr7,cr8,0x5
16908 + *[0-9a-f]*:   e1 a2 18 87     cop cp0,cr8,cr8,cr7,0x5
16909 +
16910 +[0-9a-f]* <fmac_s>:
16911 + *[0-9a-f]*:   e1 a0 0f ff     cop cp0,cr15,cr15,cr15,0x0
16912 + *[0-9a-f]*:   e1 a0 00 00     cop cp0,cr0,cr0,cr0,0x0
16913 + *[0-9a-f]*:   e1 a0 00 ff     cop cp0,cr0,cr15,cr15,0x0
16914 + *[0-9a-f]*:   e1 a0 0f 0f     cop cp0,cr15,cr0,cr15,0x0
16915 + *[0-9a-f]*:   e1 a0 0f f0     cop cp0,cr15,cr15,cr0,0x0
16916 + *[0-9a-f]*:   e1 a0 07 88     cop cp0,cr7,cr8,cr8,0x0
16917 + *[0-9a-f]*:   e1 a0 08 78     cop cp0,cr8,cr7,cr8,0x0
16918 + *[0-9a-f]*:   e1 a0 08 87     cop cp0,cr8,cr8,cr7,0x0
16919 +
16920 +[0-9a-f]* <fnmac_s>:
16921 + *[0-9a-f]*:   e1 a0 1f ff     cop cp0,cr15,cr15,cr15,0x1
16922 + *[0-9a-f]*:   e1 a0 10 00     cop cp0,cr0,cr0,cr0,0x1
16923 + *[0-9a-f]*:   e1 a0 10 ff     cop cp0,cr0,cr15,cr15,0x1
16924 + *[0-9a-f]*:   e1 a0 1f 0f     cop cp0,cr15,cr0,cr15,0x1
16925 + *[0-9a-f]*:   e1 a0 1f f0     cop cp0,cr15,cr15,cr0,0x1
16926 + *[0-9a-f]*:   e1 a0 17 88     cop cp0,cr7,cr8,cr8,0x1
16927 + *[0-9a-f]*:   e1 a0 18 78     cop cp0,cr8,cr7,cr8,0x1
16928 + *[0-9a-f]*:   e1 a0 18 87     cop cp0,cr8,cr8,cr7,0x1
16929 +
16930 +[0-9a-f]* <fmsc_s>:
16931 + *[0-9a-f]*:   e1 a1 0f ff     cop cp0,cr15,cr15,cr15,0x2
16932 + *[0-9a-f]*:   e1 a1 00 00     cop cp0,cr0,cr0,cr0,0x2
16933 + *[0-9a-f]*:   e1 a1 00 ff     cop cp0,cr0,cr15,cr15,0x2
16934 + *[0-9a-f]*:   e1 a1 0f 0f     cop cp0,cr15,cr0,cr15,0x2
16935 + *[0-9a-f]*:   e1 a1 0f f0     cop cp0,cr15,cr15,cr0,0x2
16936 + *[0-9a-f]*:   e1 a1 07 88     cop cp0,cr7,cr8,cr8,0x2
16937 + *[0-9a-f]*:   e1 a1 08 78     cop cp0,cr8,cr7,cr8,0x2
16938 + *[0-9a-f]*:   e1 a1 08 87     cop cp0,cr8,cr8,cr7,0x2
16939 +
16940 +[0-9a-f]* <fnmsc_s>:
16941 + *[0-9a-f]*:   e1 a1 1f ff     cop cp0,cr15,cr15,cr15,0x3
16942 + *[0-9a-f]*:   e1 a1 10 00     cop cp0,cr0,cr0,cr0,0x3
16943 + *[0-9a-f]*:   e1 a1 10 ff     cop cp0,cr0,cr15,cr15,0x3
16944 + *[0-9a-f]*:   e1 a1 1f 0f     cop cp0,cr15,cr0,cr15,0x3
16945 + *[0-9a-f]*:   e1 a1 1f f0     cop cp0,cr15,cr15,cr0,0x3
16946 + *[0-9a-f]*:   e1 a1 17 88     cop cp0,cr7,cr8,cr8,0x3
16947 + *[0-9a-f]*:   e1 a1 18 78     cop cp0,cr8,cr7,cr8,0x3
16948 + *[0-9a-f]*:   e1 a1 18 87     cop cp0,cr8,cr8,cr7,0x3
16949 +
16950 +[0-9a-f]* <fmul_s>:
16951 + *[0-9a-f]*:   e1 a3 0f ff     cop cp0,cr15,cr15,cr15,0x6
16952 + *[0-9a-f]*:   e1 a3 00 00     cop cp0,cr0,cr0,cr0,0x6
16953 + *[0-9a-f]*:   e1 a3 00 ff     cop cp0,cr0,cr15,cr15,0x6
16954 + *[0-9a-f]*:   e1 a3 0f 0f     cop cp0,cr15,cr0,cr15,0x6
16955 + *[0-9a-f]*:   e1 a3 0f f0     cop cp0,cr15,cr15,cr0,0x6
16956 + *[0-9a-f]*:   e1 a3 07 88     cop cp0,cr7,cr8,cr8,0x6
16957 + *[0-9a-f]*:   e1 a3 08 78     cop cp0,cr8,cr7,cr8,0x6
16958 + *[0-9a-f]*:   e1 a3 08 87     cop cp0,cr8,cr8,cr7,0x6
16959 +
16960 +[0-9a-f]* <fnmul_s>:
16961 + *[0-9a-f]*:   e1 a3 1f ff     cop cp0,cr15,cr15,cr15,0x7
16962 + *[0-9a-f]*:   e1 a3 10 00     cop cp0,cr0,cr0,cr0,0x7
16963 + *[0-9a-f]*:   e1 a3 10 ff     cop cp0,cr0,cr15,cr15,0x7
16964 + *[0-9a-f]*:   e1 a3 1f 0f     cop cp0,cr15,cr0,cr15,0x7
16965 + *[0-9a-f]*:   e1 a3 1f f0     cop cp0,cr15,cr15,cr0,0x7
16966 + *[0-9a-f]*:   e1 a3 17 88     cop cp0,cr7,cr8,cr8,0x7
16967 + *[0-9a-f]*:   e1 a3 18 78     cop cp0,cr8,cr7,cr8,0x7
16968 + *[0-9a-f]*:   e1 a3 18 87     cop cp0,cr8,cr8,cr7,0x7
16969 +
16970 +[0-9a-f]* <fneg_s>:
16971 + *[0-9a-f]*:   e1 a4 0f f0     cop cp0,cr15,cr15,cr0,0x8
16972 + *[0-9a-f]*:   e1 a4 00 00     cop cp0,cr0,cr0,cr0,0x8
16973 + *[0-9a-f]*:   e1 a4 00 f0     cop cp0,cr0,cr15,cr0,0x8
16974 + *[0-9a-f]*:   e1 a4 0f 00     cop cp0,cr15,cr0,cr0,0x8
16975 + *[0-9a-f]*:   e1 a4 07 80     cop cp0,cr7,cr8,cr0,0x8
16976 + *[0-9a-f]*:   e1 a4 08 70     cop cp0,cr8,cr7,cr0,0x8
16977 +
16978 +[0-9a-f]* <fabs_s>:
16979 + *[0-9a-f]*:   e1 a4 1f f0     cop cp0,cr15,cr15,cr0,0x9
16980 + *[0-9a-f]*:   e1 a4 10 00     cop cp0,cr0,cr0,cr0,0x9
16981 + *[0-9a-f]*:   e1 a4 10 f0     cop cp0,cr0,cr15,cr0,0x9
16982 + *[0-9a-f]*:   e1 a4 1f 00     cop cp0,cr15,cr0,cr0,0x9
16983 + *[0-9a-f]*:   e1 a4 17 80     cop cp0,cr7,cr8,cr0,0x9
16984 + *[0-9a-f]*:   e1 a4 18 70     cop cp0,cr8,cr7,cr0,0x9
16985 +
16986 +[0-9a-f]* <fcmp_s>:
16987 + *[0-9a-f]*:   e1 a6 10 ff     cop cp0,cr0,cr15,cr15,0xd
16988 + *[0-9a-f]*:   e1 a6 10 00     cop cp0,cr0,cr0,cr0,0xd
16989 + *[0-9a-f]*:   e1 a6 10 0f     cop cp0,cr0,cr0,cr15,0xd
16990 + *[0-9a-f]*:   e1 a6 10 f0     cop cp0,cr0,cr15,cr0,0xd
16991 + *[0-9a-f]*:   e1 a6 10 78     cop cp0,cr0,cr7,cr8,0xd
16992 + *[0-9a-f]*:   e1 a6 10 87     cop cp0,cr0,cr8,cr7,0xd
16993 +
16994 +[0-9a-f]* <fadd_d>:
16995 + *[0-9a-f]*:   e5 a2 0e ee     cop cp0,cr14,cr14,cr14,0x44
16996 + *[0-9a-f]*:   e5 a2 00 00     cop cp0,cr0,cr0,cr0,0x44
16997 + *[0-9a-f]*:   e5 a2 00 ee     cop cp0,cr0,cr14,cr14,0x44
16998 + *[0-9a-f]*:   e5 a2 0e 0e     cop cp0,cr14,cr0,cr14,0x44
16999 + *[0-9a-f]*:   e5 a2 0e e0     cop cp0,cr14,cr14,cr0,0x44
17000 + *[0-9a-f]*:   e5 a2 06 88     cop cp0,cr6,cr8,cr8,0x44
17001 + *[0-9a-f]*:   e5 a2 08 68     cop cp0,cr8,cr6,cr8,0x44
17002 + *[0-9a-f]*:   e5 a2 08 86     cop cp0,cr8,cr8,cr6,0x44
17003 +
17004 +[0-9a-f]* <fsub_d>:
17005 + *[0-9a-f]*:   e5 a2 1e ee     cop cp0,cr14,cr14,cr14,0x45
17006 + *[0-9a-f]*:   e5 a2 10 00     cop cp0,cr0,cr0,cr0,0x45
17007 + *[0-9a-f]*:   e5 a2 10 ee     cop cp0,cr0,cr14,cr14,0x45
17008 + *[0-9a-f]*:   e5 a2 1e 0e     cop cp0,cr14,cr0,cr14,0x45
17009 + *[0-9a-f]*:   e5 a2 1e e0     cop cp0,cr14,cr14,cr0,0x45
17010 + *[0-9a-f]*:   e5 a2 16 88     cop cp0,cr6,cr8,cr8,0x45
17011 + *[0-9a-f]*:   e5 a2 18 68     cop cp0,cr8,cr6,cr8,0x45
17012 + *[0-9a-f]*:   e5 a2 18 86     cop cp0,cr8,cr8,cr6,0x45
17013 +
17014 +[0-9a-f]* <fmac_d>:
17015 + *[0-9a-f]*:   e5 a0 0e ee     cop cp0,cr14,cr14,cr14,0x40
17016 + *[0-9a-f]*:   e5 a0 00 00     cop cp0,cr0,cr0,cr0,0x40
17017 + *[0-9a-f]*:   e5 a0 00 ee     cop cp0,cr0,cr14,cr14,0x40
17018 + *[0-9a-f]*:   e5 a0 0e 0e     cop cp0,cr14,cr0,cr14,0x40
17019 + *[0-9a-f]*:   e5 a0 0e e0     cop cp0,cr14,cr14,cr0,0x40
17020 + *[0-9a-f]*:   e5 a0 06 88     cop cp0,cr6,cr8,cr8,0x40
17021 + *[0-9a-f]*:   e5 a0 08 68     cop cp0,cr8,cr6,cr8,0x40
17022 + *[0-9a-f]*:   e5 a0 08 86     cop cp0,cr8,cr8,cr6,0x40
17023 +
17024 +[0-9a-f]* <fnmac_d>:
17025 + *[0-9a-f]*:   e5 a0 1e ee     cop cp0,cr14,cr14,cr14,0x41
17026 + *[0-9a-f]*:   e5 a0 10 00     cop cp0,cr0,cr0,cr0,0x41
17027 + *[0-9a-f]*:   e5 a0 10 ee     cop cp0,cr0,cr14,cr14,0x41
17028 + *[0-9a-f]*:   e5 a0 1e 0e     cop cp0,cr14,cr0,cr14,0x41
17029 + *[0-9a-f]*:   e5 a0 1e e0     cop cp0,cr14,cr14,cr0,0x41
17030 + *[0-9a-f]*:   e5 a0 16 88     cop cp0,cr6,cr8,cr8,0x41
17031 + *[0-9a-f]*:   e5 a0 18 68     cop cp0,cr8,cr6,cr8,0x41
17032 + *[0-9a-f]*:   e5 a0 18 86     cop cp0,cr8,cr8,cr6,0x41
17033 +
17034 +[0-9a-f]* <fmsc_d>:
17035 + *[0-9a-f]*:   e5 a1 0e ee     cop cp0,cr14,cr14,cr14,0x42
17036 + *[0-9a-f]*:   e5 a1 00 00     cop cp0,cr0,cr0,cr0,0x42
17037 + *[0-9a-f]*:   e5 a1 00 ee     cop cp0,cr0,cr14,cr14,0x42
17038 + *[0-9a-f]*:   e5 a1 0e 0e     cop cp0,cr14,cr0,cr14,0x42
17039 + *[0-9a-f]*:   e5 a1 0e e0     cop cp0,cr14,cr14,cr0,0x42
17040 + *[0-9a-f]*:   e5 a1 06 88     cop cp0,cr6,cr8,cr8,0x42
17041 + *[0-9a-f]*:   e5 a1 08 68     cop cp0,cr8,cr6,cr8,0x42
17042 + *[0-9a-f]*:   e5 a1 08 86     cop cp0,cr8,cr8,cr6,0x42
17043 +
17044 +[0-9a-f]* <fnmsc_d>:
17045 + *[0-9a-f]*:   e5 a1 1e ee     cop cp0,cr14,cr14,cr14,0x43
17046 + *[0-9a-f]*:   e5 a1 10 00     cop cp0,cr0,cr0,cr0,0x43
17047 + *[0-9a-f]*:   e5 a1 10 ee     cop cp0,cr0,cr14,cr14,0x43
17048 + *[0-9a-f]*:   e5 a1 1e 0e     cop cp0,cr14,cr0,cr14,0x43
17049 + *[0-9a-f]*:   e5 a1 1e e0     cop cp0,cr14,cr14,cr0,0x43
17050 + *[0-9a-f]*:   e5 a1 16 88     cop cp0,cr6,cr8,cr8,0x43
17051 + *[0-9a-f]*:   e5 a1 18 68     cop cp0,cr8,cr6,cr8,0x43
17052 + *[0-9a-f]*:   e5 a1 18 86     cop cp0,cr8,cr8,cr6,0x43
17053 +
17054 +[0-9a-f]* <fmul_d>:
17055 + *[0-9a-f]*:   e5 a3 0e ee     cop cp0,cr14,cr14,cr14,0x46
17056 + *[0-9a-f]*:   e5 a3 00 00     cop cp0,cr0,cr0,cr0,0x46
17057 + *[0-9a-f]*:   e5 a3 00 ee     cop cp0,cr0,cr14,cr14,0x46
17058 + *[0-9a-f]*:   e5 a3 0e 0e     cop cp0,cr14,cr0,cr14,0x46
17059 + *[0-9a-f]*:   e5 a3 0e e0     cop cp0,cr14,cr14,cr0,0x46
17060 + *[0-9a-f]*:   e5 a3 06 88     cop cp0,cr6,cr8,cr8,0x46
17061 + *[0-9a-f]*:   e5 a3 08 68     cop cp0,cr8,cr6,cr8,0x46
17062 + *[0-9a-f]*:   e5 a3 08 86     cop cp0,cr8,cr8,cr6,0x46
17063 +
17064 +[0-9a-f]* <fnmul_d>:
17065 + *[0-9a-f]*:   e5 a3 1e ee     cop cp0,cr14,cr14,cr14,0x47
17066 + *[0-9a-f]*:   e5 a3 10 00     cop cp0,cr0,cr0,cr0,0x47
17067 + *[0-9a-f]*:   e5 a3 10 ee     cop cp0,cr0,cr14,cr14,0x47
17068 + *[0-9a-f]*:   e5 a3 1e 0e     cop cp0,cr14,cr0,cr14,0x47
17069 + *[0-9a-f]*:   e5 a3 1e e0     cop cp0,cr14,cr14,cr0,0x47
17070 + *[0-9a-f]*:   e5 a3 16 88     cop cp0,cr6,cr8,cr8,0x47
17071 + *[0-9a-f]*:   e5 a3 18 68     cop cp0,cr8,cr6,cr8,0x47
17072 + *[0-9a-f]*:   e5 a3 18 86     cop cp0,cr8,cr8,cr6,0x47
17073 +
17074 +[0-9a-f]* <fneg_d>:
17075 + *[0-9a-f]*:   e5 a4 0e e0     cop cp0,cr14,cr14,cr0,0x48
17076 + *[0-9a-f]*:   e5 a4 00 00     cop cp0,cr0,cr0,cr0,0x48
17077 + *[0-9a-f]*:   e5 a4 00 e0     cop cp0,cr0,cr14,cr0,0x48
17078 + *[0-9a-f]*:   e5 a4 0e 00     cop cp0,cr14,cr0,cr0,0x48
17079 + *[0-9a-f]*:   e5 a4 06 80     cop cp0,cr6,cr8,cr0,0x48
17080 + *[0-9a-f]*:   e5 a4 08 60     cop cp0,cr8,cr6,cr0,0x48
17081 +
17082 +[0-9a-f]* <fabs_d>:
17083 + *[0-9a-f]*:   e5 a4 1e e0     cop cp0,cr14,cr14,cr0,0x49
17084 + *[0-9a-f]*:   e5 a4 10 00     cop cp0,cr0,cr0,cr0,0x49
17085 + *[0-9a-f]*:   e5 a4 10 e0     cop cp0,cr0,cr14,cr0,0x49
17086 + *[0-9a-f]*:   e5 a4 1e 00     cop cp0,cr14,cr0,cr0,0x49
17087 + *[0-9a-f]*:   e5 a4 16 80     cop cp0,cr6,cr8,cr0,0x49
17088 + *[0-9a-f]*:   e5 a4 18 60     cop cp0,cr8,cr6,cr0,0x49
17089 +
17090 +[0-9a-f]* <fcmp_d>:
17091 + *[0-9a-f]*:   e5 a6 10 ee     cop cp0,cr0,cr14,cr14,0x4d
17092 + *[0-9a-f]*:   e5 a6 10 00     cop cp0,cr0,cr0,cr0,0x4d
17093 + *[0-9a-f]*:   e5 a6 10 0e     cop cp0,cr0,cr0,cr14,0x4d
17094 + *[0-9a-f]*:   e5 a6 10 e0     cop cp0,cr0,cr14,cr0,0x4d
17095 + *[0-9a-f]*:   e5 a6 10 68     cop cp0,cr0,cr6,cr8,0x4d
17096 + *[0-9a-f]*:   e5 a6 10 86     cop cp0,cr0,cr8,cr6,0x4d
17097 +
17098 +[0-9a-f]* <fmov_s>:
17099 + *[0-9a-f]*:   e1 a5 0f f0     cop cp0,cr15,cr15,cr0,0xa
17100 + *[0-9a-f]*:   e1 a5 00 00     cop cp0,cr0,cr0,cr0,0xa
17101 + *[0-9a-f]*:   e1 a5 0f 00     cop cp0,cr15,cr0,cr0,0xa
17102 + *[0-9a-f]*:   e1 a5 00 f0     cop cp0,cr0,cr15,cr0,0xa
17103 + *[0-9a-f]*:   e1 a5 08 70     cop cp0,cr8,cr7,cr0,0xa
17104 + *[0-9a-f]*:   e1 a5 07 80     cop cp0,cr7,cr8,cr0,0xa
17105 + *[0-9a-f]*:   ef af 0f 00     mvcr.w cp0,pc,cr15
17106 + *[0-9a-f]*:   ef a0 00 00     mvcr.w cp0,r0,cr0
17107 + *[0-9a-f]*:   ef af 00 00     mvcr.w cp0,pc,cr0
17108 + *[0-9a-f]*:   ef a0 0f 00     mvcr.w cp0,r0,cr15
17109 + *[0-9a-f]*:   ef a8 07 00     mvcr.w cp0,r8,cr7
17110 + *[0-9a-f]*:   ef a7 08 00     mvcr.w cp0,r7,cr8
17111 + *[0-9a-f]*:   ef af 0f 20     mvrc.w cp0,cr15,pc
17112 + *[0-9a-f]*:   ef a0 00 20     mvrc.w cp0,cr0,r0
17113 + *[0-9a-f]*:   ef a0 0f 20     mvrc.w cp0,cr15,r0
17114 + *[0-9a-f]*:   ef af 00 20     mvrc.w cp0,cr0,pc
17115 + *[0-9a-f]*:   ef a7 08 20     mvrc.w cp0,cr8,r7
17116 + *[0-9a-f]*:   ef a8 07 20     mvrc.w cp0,cr7,r8
17117 +
17118 +[0-9a-f]* <fmov_d>:
17119 + *[0-9a-f]*:   e5 a5 0e e0     cop cp0,cr14,cr14,cr0,0x4a
17120 + *[0-9a-f]*:   e5 a5 00 00     cop cp0,cr0,cr0,cr0,0x4a
17121 + *[0-9a-f]*:   e5 a5 0e 00     cop cp0,cr14,cr0,cr0,0x4a
17122 + *[0-9a-f]*:   e5 a5 00 e0     cop cp0,cr0,cr14,cr0,0x4a
17123 + *[0-9a-f]*:   e5 a5 08 60     cop cp0,cr8,cr6,cr0,0x4a
17124 + *[0-9a-f]*:   e5 a5 06 80     cop cp0,cr6,cr8,cr0,0x4a
17125 + *[0-9a-f]*:   ef ae 0e 10     mvcr.d cp0,lr,cr14
17126 + *[0-9a-f]*:   ef a0 00 10     mvcr.d cp0,r0,cr0
17127 + *[0-9a-f]*:   ef ae 00 10     mvcr.d cp0,lr,cr0
17128 + *[0-9a-f]*:   ef a0 0e 10     mvcr.d cp0,r0,cr14
17129 + *[0-9a-f]*:   ef a8 06 10     mvcr.d cp0,r8,cr6
17130 + *[0-9a-f]*:   ef a6 08 10     mvcr.d cp0,r6,cr8
17131 + *[0-9a-f]*:   ef ae 0e 30     mvrc.d cp0,cr14,lr
17132 + *[0-9a-f]*:   ef a0 00 30     mvrc.d cp0,cr0,r0
17133 + *[0-9a-f]*:   ef a0 0e 30     mvrc.d cp0,cr14,r0
17134 + *[0-9a-f]*:   ef ae 00 30     mvrc.d cp0,cr0,lr
17135 + *[0-9a-f]*:   ef a6 08 30     mvrc.d cp0,cr8,r6
17136 + *[0-9a-f]*:   ef a8 06 30     mvrc.d cp0,cr6,r8
17137 +
17138 +[0-9a-f]* <fcasts_d>:
17139 + *[0-9a-f]*:   e1 a7 1f e0     cop cp0,cr15,cr14,cr0,0xf
17140 + *[0-9a-f]*:   e1 a7 10 00     cop cp0,cr0,cr0,cr0,0xf
17141 + *[0-9a-f]*:   e1 a7 1f 00     cop cp0,cr15,cr0,cr0,0xf
17142 + *[0-9a-f]*:   e1 a7 10 e0     cop cp0,cr0,cr14,cr0,0xf
17143 + *[0-9a-f]*:   e1 a7 18 60     cop cp0,cr8,cr6,cr0,0xf
17144 + *[0-9a-f]*:   e1 a7 17 80     cop cp0,cr7,cr8,cr0,0xf
17145 +
17146 +[0-9a-f]* <fcastd_s>:
17147 + *[0-9a-f]*:   e1 a8 0e f0     cop cp0,cr14,cr15,cr0,0x10
17148 + *[0-9a-f]*:   e1 a8 00 00     cop cp0,cr0,cr0,cr0,0x10
17149 + *[0-9a-f]*:   e1 a8 0e 00     cop cp0,cr14,cr0,cr0,0x10
17150 + *[0-9a-f]*:   e1 a8 00 f0     cop cp0,cr0,cr15,cr0,0x10
17151 + *[0-9a-f]*:   e1 a8 08 70     cop cp0,cr8,cr7,cr0,0x10
17152 + *[0-9a-f]*:   e1 a8 06 80     cop cp0,cr6,cr8,cr0,0x10
17153 --- /dev/null
17154 +++ b/gas/testsuite/gas/avr32/fpinsn.s
17155 @@ -0,0 +1,266 @@
17156 +
17157 +       .text
17158 +       .global fadd_s
17159 +fadd_s:
17160 +       fadd.s fr15, fr15, fr15
17161 +       fadd.s fr0, fr0, fr0
17162 +       fadd.s fr0, fr15, fr15
17163 +       fadd.s fr15, fr0, fr15
17164 +       fadd.s fr15, fr15, fr0
17165 +       fadd.s fr7, fr8, fr8
17166 +       fadd.s fr8, fr7, fr8
17167 +       fadd.s fr8, fr8, fr7
17168 +       .global fsub_s
17169 +fsub_s:
17170 +       fsub.s fr15, fr15, fr15
17171 +       fsub.s fr0, fr0, fr0
17172 +       fsub.s fr0, fr15, fr15
17173 +       fsub.s fr15, fr0, fr15
17174 +       fsub.s fr15, fr15, fr0
17175 +       fsub.s fr7, fr8, fr8
17176 +       fsub.s fr8, fr7, fr8
17177 +       fsub.s fr8, fr8, fr7
17178 +       .global fmac_s
17179 +fmac_s:
17180 +       fmac.s fr15, fr15, fr15
17181 +       fmac.s fr0, fr0, fr0
17182 +       fmac.s fr0, fr15, fr15
17183 +       fmac.s fr15, fr0, fr15
17184 +       fmac.s fr15, fr15, fr0
17185 +       fmac.s fr7, fr8, fr8
17186 +       fmac.s fr8, fr7, fr8
17187 +       fmac.s fr8, fr8, fr7
17188 +       .global fnmac_s
17189 +fnmac_s:
17190 +       fnmac.s fr15, fr15, fr15
17191 +       fnmac.s fr0, fr0, fr0
17192 +       fnmac.s fr0, fr15, fr15
17193 +       fnmac.s fr15, fr0, fr15
17194 +       fnmac.s fr15, fr15, fr0
17195 +       fnmac.s fr7, fr8, fr8
17196 +       fnmac.s fr8, fr7, fr8
17197 +       fnmac.s fr8, fr8, fr7
17198 +       .global fmsc_s
17199 +fmsc_s:
17200 +       fmsc.s fr15, fr15, fr15
17201 +       fmsc.s fr0, fr0, fr0
17202 +       fmsc.s fr0, fr15, fr15
17203 +       fmsc.s fr15, fr0, fr15
17204 +       fmsc.s fr15, fr15, fr0
17205 +       fmsc.s fr7, fr8, fr8
17206 +       fmsc.s fr8, fr7, fr8
17207 +       fmsc.s fr8, fr8, fr7
17208 +       .global fnmsc_s
17209 +fnmsc_s:
17210 +       fnmsc.s fr15, fr15, fr15
17211 +       fnmsc.s fr0, fr0, fr0
17212 +       fnmsc.s fr0, fr15, fr15
17213 +       fnmsc.s fr15, fr0, fr15
17214 +       fnmsc.s fr15, fr15, fr0
17215 +       fnmsc.s fr7, fr8, fr8
17216 +       fnmsc.s fr8, fr7, fr8
17217 +       fnmsc.s fr8, fr8, fr7
17218 +       .global fmul_s
17219 +fmul_s:
17220 +       fmul.s fr15, fr15, fr15
17221 +       fmul.s fr0, fr0, fr0
17222 +       fmul.s fr0, fr15, fr15
17223 +       fmul.s fr15, fr0, fr15
17224 +       fmul.s fr15, fr15, fr0
17225 +       fmul.s fr7, fr8, fr8
17226 +       fmul.s fr8, fr7, fr8
17227 +       fmul.s fr8, fr8, fr7
17228 +       .global fnmul_s
17229 +fnmul_s:
17230 +       fnmul.s fr15, fr15, fr15
17231 +       fnmul.s fr0, fr0, fr0
17232 +       fnmul.s fr0, fr15, fr15
17233 +       fnmul.s fr15, fr0, fr15
17234 +       fnmul.s fr15, fr15, fr0
17235 +       fnmul.s fr7, fr8, fr8
17236 +       fnmul.s fr8, fr7, fr8
17237 +       fnmul.s fr8, fr8, fr7
17238 +       .global fneg_s
17239 +fneg_s:
17240 +       fneg.s fr15, fr15
17241 +       fneg.s fr0, fr0
17242 +       fneg.s fr0, fr15
17243 +       fneg.s fr15, fr0
17244 +       fneg.s fr7, fr8
17245 +       fneg.s fr8, fr7
17246 +       .global fabs_s
17247 +fabs_s:
17248 +       fabs.s fr15, fr15
17249 +       fabs.s fr0, fr0
17250 +       fabs.s fr0, fr15
17251 +       fabs.s fr15, fr0
17252 +       fabs.s fr7, fr8
17253 +       fabs.s fr8, fr7
17254 +       .global fcmp_s
17255 +fcmp_s:
17256 +       fcmp.s fr15, fr15
17257 +       fcmp.s fr0, fr0
17258 +       fcmp.s fr0, fr15
17259 +       fcmp.s fr15, fr0
17260 +       fcmp.s fr7, fr8
17261 +       fcmp.s fr8, fr7
17262 +       .global fadd_d
17263 +fadd_d:
17264 +       fadd.d fr14, fr14, fr14
17265 +       fadd.d fr0, fr0, fr0
17266 +       fadd.d fr0, fr14, fr14
17267 +       fadd.d fr14, fr0, fr14
17268 +       fadd.d fr14, fr14, fr0
17269 +       fadd.d fr6, fr8, fr8
17270 +       fadd.d fr8, fr6, fr8
17271 +       fadd.d fr8, fr8, fr6
17272 +       .global fsub_d
17273 +fsub_d:
17274 +       fsub.d fr14, fr14, fr14
17275 +       fsub.d fr0, fr0, fr0
17276 +       fsub.d fr0, fr14, fr14
17277 +       fsub.d fr14, fr0, fr14
17278 +       fsub.d fr14, fr14, fr0
17279 +       fsub.d fr6, fr8, fr8
17280 +       fsub.d fr8, fr6, fr8
17281 +       fsub.d fr8, fr8, fr6
17282 +       .global fmac_d
17283 +fmac_d:
17284 +       fmac.d fr14, fr14, fr14
17285 +       fmac.d fr0, fr0, fr0
17286 +       fmac.d fr0, fr14, fr14
17287 +       fmac.d fr14, fr0, fr14
17288 +       fmac.d fr14, fr14, fr0
17289 +       fmac.d fr6, fr8, fr8
17290 +       fmac.d fr8, fr6, fr8
17291 +       fmac.d fr8, fr8, fr6
17292 +       .global fnmac_d
17293 +fnmac_d:
17294 +       fnmac.d fr14, fr14, fr14
17295 +       fnmac.d fr0, fr0, fr0
17296 +       fnmac.d fr0, fr14, fr14
17297 +       fnmac.d fr14, fr0, fr14
17298 +       fnmac.d fr14, fr14, fr0
17299 +       fnmac.d fr6, fr8, fr8
17300 +       fnmac.d fr8, fr6, fr8
17301 +       fnmac.d fr8, fr8, fr6
17302 +       .global fmsc_d
17303 +fmsc_d:
17304 +       fmsc.d fr14, fr14, fr14
17305 +       fmsc.d fr0, fr0, fr0
17306 +       fmsc.d fr0, fr14, fr14
17307 +       fmsc.d fr14, fr0, fr14
17308 +       fmsc.d fr14, fr14, fr0
17309 +       fmsc.d fr6, fr8, fr8
17310 +       fmsc.d fr8, fr6, fr8
17311 +       fmsc.d fr8, fr8, fr6
17312 +       .global fnmsc_d
17313 +fnmsc_d:
17314 +       fnmsc.d fr14, fr14, fr14
17315 +       fnmsc.d fr0, fr0, fr0
17316 +       fnmsc.d fr0, fr14, fr14
17317 +       fnmsc.d fr14, fr0, fr14
17318 +       fnmsc.d fr14, fr14, fr0
17319 +       fnmsc.d fr6, fr8, fr8
17320 +       fnmsc.d fr8, fr6, fr8
17321 +       fnmsc.d fr8, fr8, fr6
17322 +       .global fmul_d
17323 +fmul_d:
17324 +       fmul.d fr14, fr14, fr14
17325 +       fmul.d fr0, fr0, fr0
17326 +       fmul.d fr0, fr14, fr14
17327 +       fmul.d fr14, fr0, fr14
17328 +       fmul.d fr14, fr14, fr0
17329 +       fmul.d fr6, fr8, fr8
17330 +       fmul.d fr8, fr6, fr8
17331 +       fmul.d fr8, fr8, fr6
17332 +       .global fnmul_d
17333 +fnmul_d:
17334 +       fnmul.d fr14, fr14, fr14
17335 +       fnmul.d fr0, fr0, fr0
17336 +       fnmul.d fr0, fr14, fr14
17337 +       fnmul.d fr14, fr0, fr14
17338 +       fnmul.d fr14, fr14, fr0
17339 +       fnmul.d fr6, fr8, fr8
17340 +       fnmul.d fr8, fr6, fr8
17341 +       fnmul.d fr8, fr8, fr6
17342 +       .global fneg_d
17343 +fneg_d:
17344 +       fneg.d fr14, fr14
17345 +       fneg.d fr0, fr0
17346 +       fneg.d fr0, fr14
17347 +       fneg.d fr14, fr0
17348 +       fneg.d fr6, fr8
17349 +       fneg.d fr8, fr6
17350 +       .global fabs_d
17351 +fabs_d:
17352 +       fabs.d fr14, fr14
17353 +       fabs.d fr0, fr0
17354 +       fabs.d fr0, fr14
17355 +       fabs.d fr14, fr0
17356 +       fabs.d fr6, fr8
17357 +       fabs.d fr8, fr6
17358 +       .global fcmp_d
17359 +fcmp_d:
17360 +       fcmp.d fr14, fr14
17361 +       fcmp.d fr0, fr0
17362 +       fcmp.d fr0, fr14
17363 +       fcmp.d fr14, fr0
17364 +       fcmp.d fr6, fr8
17365 +       fcmp.d fr8, fr6
17366 +       .global fmov_s
17367 +fmov_s:
17368 +       fmov.s fr15, fr15
17369 +       fmov.s fr0, fr0
17370 +       fmov.s fr15, fr0
17371 +       fmov.s fr0, fr15
17372 +       fmov.s fr8, fr7
17373 +       fmov.s fr7, fr8
17374 +       fmov.s pc, fr15
17375 +       fmov.s r0, fr0
17376 +       fmov.s pc, fr0
17377 +       fmov.s r0, fr15
17378 +       fmov.s r8, fr7
17379 +       fmov.s r7, fr8
17380 +       fmov.s fr15, pc
17381 +       fmov.s fr0, r0
17382 +       fmov.s fr15, r0
17383 +       fmov.s fr0, pc
17384 +       fmov.s fr8, r7
17385 +       fmov.s fr7, r8
17386 +       .global fmov_d
17387 +fmov_d:
17388 +       fmov.d fr14, fr14
17389 +       fmov.d fr0, fr0
17390 +       fmov.d fr14, fr0
17391 +       fmov.d fr0, fr14
17392 +       fmov.d fr8, fr6
17393 +       fmov.d fr6, fr8
17394 +       fmov.d lr, fr14
17395 +       fmov.d r0, fr0
17396 +       fmov.d lr, fr0
17397 +       fmov.d r0, fr14
17398 +       fmov.d r8, fr6
17399 +       fmov.d r6, fr8
17400 +       fmov.d fr14, lr
17401 +       fmov.d fr0, r0
17402 +       fmov.d fr14, r0
17403 +       fmov.d fr0, lr
17404 +       fmov.d fr8, r6
17405 +       fmov.d fr6, r8
17406 +       .global fcasts_d
17407 +fcasts_d:
17408 +       fcasts.d fr15, fr14
17409 +       fcasts.d fr0, fr0
17410 +       fcasts.d fr15, fr0
17411 +       fcasts.d fr0, fr14
17412 +       fcasts.d fr8, fr6
17413 +       fcasts.d fr7, fr8
17414 +       .global fcastd_s
17415 +fcastd_s:
17416 +       fcastd.s fr14, fr15
17417 +       fcastd.s fr0, fr0
17418 +       fcastd.s fr14, fr0
17419 +       fcastd.s fr0, fr15
17420 +       fcastd.s fr8, fr7
17421 +       fcastd.s fr6, fr8
17422 --- /dev/null
17423 +++ b/gas/testsuite/gas/avr32/hwrd-lwrd.d
17424 @@ -0,0 +1,47 @@
17425 +#as:
17426 +#objdump: -dr
17427 +#name: hwrd-lwrd
17428 +
17429 +.*: +file format .*
17430 +
17431 +Disassembly of section \.text:
17432 +
17433 +00000000 <test_hwrd>:
17434 +   0:  e0 60 87 65     mov r0,34661
17435 +   4:  e0 60 12 34     mov r0,4660
17436 +   8:  e0 60 00 00     mov r0,0
17437 +                       8: R_AVR32_HI16 \.text\+0x60
17438 +   c:  e0 60 00 00     mov r0,0
17439 +                       c: R_AVR32_HI16 extsym1
17440 +  10:  ea 10 87 65     orh r0,0x8765
17441 +  14:  ea 10 12 34     orh r0,0x1234
17442 +  18:  ea 10 00 00     orh r0,0x0
17443 +                       18: R_AVR32_HI16        \.text\+0x60
17444 +  1c:  ea 10 00 00     orh r0,0x0
17445 +                       1c: R_AVR32_HI16        extsym1
17446 +  20:  e4 10 87 65     andh r0,0x8765
17447 +  24:  e4 10 12 34     andh r0,0x1234
17448 +  28:  e4 10 00 00     andh r0,0x0
17449 +                       28: R_AVR32_HI16        \.text\+0x60
17450 +  2c:  e4 10 00 00     andh r0,0x0
17451 +                       2c: R_AVR32_HI16        extsym1
17452 +
17453 +00000030 <test_lwrd>:
17454 +  30:  e0 60 43 21     mov r0,17185
17455 +  34:  e0 60 56 78     mov r0,22136
17456 +  38:  e0 60 00 00     mov r0,0
17457 +                       38: R_AVR32_LO16        \.text\+0x60
17458 +  3c:  e0 60 00 00     mov r0,0
17459 +                       3c: R_AVR32_LO16        extsym1
17460 +  40:  e8 10 43 21     orl r0,0x4321
17461 +  44:  e8 10 56 78     orl r0,0x5678
17462 +  48:  e8 10 00 00     orl r0,0x0
17463 +                       48: R_AVR32_LO16        \.text\+0x60
17464 +  4c:  e8 10 00 00     orl r0,0x0
17465 +                       4c: R_AVR32_LO16        extsym1
17466 +  50:  e0 10 43 21     andl r0,0x4321
17467 +  54:  e0 10 56 78     andl r0,0x5678
17468 +  58:  e0 10 00 00     andl r0,0x0
17469 +                       58: R_AVR32_LO16        \.text\+0x60
17470 +  5c:  e0 10 00 00     andl r0,0x0
17471 +                       5c: R_AVR32_LO16        extsym1
17472 --- /dev/null
17473 +++ b/gas/testsuite/gas/avr32/hwrd-lwrd.s
17474 @@ -0,0 +1,39 @@
17475 +
17476 +        .equ    sym1, 0x12345678
17477 +
17478 +        .text
17479 +        .global test_hwrd
17480 +test_hwrd:
17481 +        mov     r0, hi(0x87654321)
17482 +        mov     r0, hi(sym1)
17483 +        mov     r0, hi(sym2)
17484 +        mov     r0, hi(extsym1)
17485 +
17486 +        orh    r0, hi(0x87654321)
17487 +        orh    r0, hi(sym1)
17488 +        orh    r0, hi(sym2)
17489 +        orh    r0, hi(extsym1)
17490 +
17491 +        andh   r0, hi(0x87654321)
17492 +        andh   r0, hi(sym1)
17493 +        andh   r0, hi(sym2)
17494 +        andh   r0, hi(extsym1)
17495 +
17496 +        .global test_lwrd
17497 +test_lwrd:
17498 +        mov     r0, lo(0x87654321)
17499 +        mov     r0, lo(sym1)
17500 +        mov     r0, lo(sym2)
17501 +        mov     r0, lo(extsym1)
17502 +
17503 +        orl    r0, lo(0x87654321)
17504 +        orl    r0, lo(sym1)
17505 +        orl    r0, lo(sym2)
17506 +        orl    r0, lo(extsym1)
17507 +
17508 +        andl   r0, lo(0x87654321)
17509 +        andl   r0, lo(sym1)
17510 +        andl   r0, lo(sym2)
17511 +        andl   r0, lo(extsym1)
17512 +
17513 +sym2:
17514 --- /dev/null
17515 +++ b/gas/testsuite/gas/avr32/jmptable.d
17516 @@ -0,0 +1,20 @@
17517 +#source: jmptable.s
17518 +#as:
17519 +#objdump: -dr
17520 +#name: jmptable
17521 +
17522 +.*: +file format .*
17523 +
17524 +Disassembly of section \.text:
17525 +
17526 +00000000 <jmptable_test>:
17527 +   0:  fe c8 ff f4     sub r8,pc,-12
17528 +   4:  f0 00 00 2f     add pc,r8,r0<<0x2
17529 +   8:  d7 03           nop
17530 +   a:  00 00           add r0,r0
17531 +   c:  c0 38           rjmp 12 <jmptable_test\+0x12>
17532 +   e:  c0 38           rjmp 14 <jmptable_test\+0x14>
17533 +  10:  c0 38           rjmp 16 <jmptable_test\+0x16>
17534 +  12:  d7 03           nop
17535 +  14:  d7 03           nop
17536 +  16:  d7 03           nop
17537 --- /dev/null
17538 +++ b/gas/testsuite/gas/avr32/jmptable_linkrelax.d
17539 @@ -0,0 +1,25 @@
17540 +#source: jmptable.s
17541 +#as: --linkrelax
17542 +#objdump: -dr
17543 +#name: jmptable_linkrelax
17544 +
17545 +.*: +file format .*
17546 +
17547 +Disassembly of section \.text:
17548 +
17549 +00000000 <jmptable_test>:
17550 +   0:  fe c8 00 00     sub r8,pc,0
17551 +                       0: R_AVR32_16N_PCREL    \.text\+0xc
17552 +   4:  f0 00 00 2f     add pc,r8,r0<<0x2
17553 +   8:  d7 03           nop
17554 +   a:  00 00           add r0,r0
17555 +                       a: R_AVR32_ALIGN        \*ABS\*\+0x2
17556 +   c:  c0 08           rjmp c <jmptable_test\+0xc>
17557 +                       c: R_AVR32_11H_PCREL    \.text\+0x12
17558 +   e:  c0 08           rjmp e <jmptable_test\+0xe>
17559 +                       e: R_AVR32_11H_PCREL    \.text\+0x14
17560 +  10:  c0 08           rjmp 10 <jmptable_test\+0x10>
17561 +                       10: R_AVR32_11H_PCREL   \.text\+0x16
17562 +  12:  d7 03           nop
17563 +  14:  d7 03           nop
17564 +  16:  d7 03           nop
17565 --- /dev/null
17566 +++ b/gas/testsuite/gas/avr32/jmptable.s
17567 @@ -0,0 +1,14 @@
17568 +
17569 +       .text
17570 +       .global jmptable_test
17571 +jmptable_test:
17572 +       sub     r8, pc, -(.L1 - .)
17573 +       add     pc, r8, r0 << 2
17574 +       nop
17575 +       .align  2
17576 +.L1:   rjmp    1f
17577 +       rjmp    2f
17578 +       rjmp    3f
17579 +1:     nop
17580 +2:     nop
17581 +3:     nop
17582 --- /dev/null
17583 +++ b/gas/testsuite/gas/avr32/lda_nopic.d
17584 @@ -0,0 +1,32 @@
17585 +#source: lda.s
17586 +#as:
17587 +#objdump: -dr
17588 +#name: lda_nopic
17589 +
17590 +.*: +file format .*
17591 +
17592 +Disassembly of section \.text:
17593 +
17594 +00000000 <lda_test>:
17595 +       0:      f2 c8 00 00     sub r8,r9,0
17596 +
17597 +00000004 <far_negative>:
17598 +       4:      f6 ca 00 00     sub r10,r11,0
17599 +       ...
17600 +    8000:      fe c0 7f fc     sub r0,pc,32764
17601 +    8004:      48 31           lddpc r1,8010 <far_negative\+0x800c>
17602 +    8006:      48 42           lddpc r2,8014 <far_negative\+0x8010>
17603 +    8008:      48 43           lddpc r3,8018 <far_negative\+0x8014>
17604 +    800a:      48 54           lddpc r4,801c <far_negative\+0x8018>
17605 +    800c:      fe c5 80 04     sub r5,pc,-32764
17606 +       ...
17607 +                       8010: R_AVR32_32_CPENT  \.text
17608 +                       8014: R_AVR32_32_CPENT  \.data
17609 +                       8018: R_AVR32_32_CPENT  undefined
17610 +                       801c: R_AVR32_32_CPENT  \.text\+0x1001c
17611 +
17612 +00010008 <far_positive>:
17613 +   10008:      fa cc 00 00     sub r12,sp,0
17614 +       ...
17615 +0001001c <toofar_positive>:
17616 +   1001c:      fe ce 00 00     sub lr,pc,0
17617 --- /dev/null
17618 +++ b/gas/testsuite/gas/avr32/lda_nopic_linkrelax.d
17619 @@ -0,0 +1,41 @@
17620 +#source: lda.s
17621 +#as: --linkrelax
17622 +#objdump: -dr
17623 +#name: lda_nopic_linkrelax
17624 +
17625 +.*: +file format .*
17626 +
17627 +Disassembly of section \.text:
17628 +
17629 +00000000 <lda_test>:
17630 +       0:      f2 c8 00 00     sub r8,r9,0
17631 +
17632 +00000004 <far_negative>:
17633 +       4:      f6 ca 00 00     sub r10,r11,0
17634 +       \.\.\.
17635 +    8000:      48 00           lddpc r0,8000 <far_negative\+0x7ffc>
17636 +                       8000: R_AVR32_9W_CP     \.text\+0x800c
17637 +    8002:      48 01           lddpc r1,8000 <far_negative\+0x7ffc>
17638 +                       8002: R_AVR32_9W_CP     \.text\+0x8010
17639 +    8004:      48 02           lddpc r2,8004 <far_negative\+0x8000>
17640 +                       8004: R_AVR32_9W_CP     \.text\+0x8014
17641 +    8006:      48 03           lddpc r3,8004 <far_negative\+0x8000>
17642 +                       8006: R_AVR32_9W_CP     \.text\+0x8018
17643 +    8008:      48 04           lddpc r4,8008 <far_negative\+0x8004>
17644 +                       8008: R_AVR32_9W_CP     \.text\+0x801c
17645 +    800a:      48 05           lddpc r5,8008 <far_negative\+0x8004>
17646 +                       800a: R_AVR32_9W_CP     \.text\+0x8020
17647 +       \.\.\.
17648 +                       800c: R_AVR32_ALIGN     \*ABS\*\+0x2
17649 +                       800c: R_AVR32_32_CPENT  \.text\+0x4
17650 +                       8010: R_AVR32_32_CPENT  \.text
17651 +                       8014: R_AVR32_32_CPENT  \.data
17652 +                       8018: R_AVR32_32_CPENT  undefined
17653 +                       801c: R_AVR32_32_CPENT  \.text\+0x10020
17654 +                       8020: R_AVR32_32_CPENT  \.text\+0x1000c
17655 +
17656 +0001000c <far_positive>:
17657 +   1000c:      fa cc 00 00     sub r12,sp,0
17658 +       \.\.\.
17659 +00010020 <toofar_positive>:
17660 +   10020:      fe ce 00 00     sub lr,pc,0
17661 --- /dev/null
17662 +++ b/gas/testsuite/gas/avr32/lda_pic.d
17663 @@ -0,0 +1,32 @@
17664 +#source: lda.s
17665 +#as: --pic
17666 +#objdump: -dr
17667 +#name: lda_pic
17668 +
17669 +.*: +file format .*
17670 +
17671 +Disassembly of section \.text:
17672 +
17673 +00000000 <lda_test>:
17674 +       0:      f2 c8 00 00     sub r8,r9,0
17675 +
17676 +00000004 <far_negative>:
17677 +       4:      f6 ca 00 00     sub r10,r11,0
17678 +       ...
17679 +    8000:      fe c0 7f fc     sub r0,pc,32764
17680 +    8004:      ec f1 00 00     ld.w r1,r6\[0\]
17681 +                       8004: R_AVR32_GOT16S    toofar_negative
17682 +    8008:      ec f2 00 00     ld.w r2,r6\[0\]
17683 +                       8008: R_AVR32_GOT16S    different_section
17684 +    800c:      ec f3 00 00     ld.w r3,r6\[0\]
17685 +                       800c: R_AVR32_GOT16S    undefined
17686 +    8010:      ec f4 00 00     ld.w r4,r6\[0\]
17687 +                       8010: R_AVR32_GOT16S    toofar_positive
17688 +    8014:      fe c5 80 14     sub r5,pc,-32748
17689 +       ...
17690 +
17691 +00010000 <far_positive>:
17692 +   10000:      fa cc 00 00     sub r12,sp,0
17693 +       ...
17694 +00010014 <toofar_positive>:
17695 +   10014:      fe ce 00 00     sub lr,pc,0
17696 --- /dev/null
17697 +++ b/gas/testsuite/gas/avr32/lda_pic_linkrelax.d
17698 @@ -0,0 +1,40 @@
17699 +#source: lda.s
17700 +#as: --pic --linkrelax
17701 +#objdump: -dr
17702 +#name: lda_pic_linkrelax
17703 +
17704 +.*: +file format .*
17705 +
17706 +Disassembly of section \.text:
17707 +
17708 +00000000 <lda_test>:
17709 +       0:      f2 c8 00 00     sub r8,r9,0
17710 +
17711 +00000004 <far_negative>:
17712 +       4:      f6 ca 00 00     sub r10,r11,0
17713 +       ...
17714 +    8000:      e0 60 00 00     mov r0,0
17715 +                       8000: R_AVR32_LDA_GOT   far_negative
17716 +    8004:      ec 00 03 20     ld\.w r0,r6\[r0<<0x2\]
17717 +    8008:      e0 61 00 00     mov r1,0
17718 +                       8008: R_AVR32_LDA_GOT   toofar_negative
17719 +    800c:      ec 01 03 21     ld\.w r1,r6\[r1<<0x2\]
17720 +    8010:      e0 62 00 00     mov r2,0
17721 +                       8010: R_AVR32_LDA_GOT   different_section
17722 +    8014:      ec 02 03 22     ld\.w r2,r6\[r2<<0x2\]
17723 +    8018:      e0 63 00 00     mov r3,0
17724 +                       8018: R_AVR32_LDA_GOT   undefined
17725 +    801c:      ec 03 03 23     ld\.w r3,r6\[r3<<0x2\]
17726 +    8020:      e0 64 00 00     mov r4,0
17727 +                       8020: R_AVR32_LDA_GOT   toofar_positive
17728 +    8024:      ec 04 03 24     ld\.w r4,r6\[r4<<0x2\]
17729 +    8028:      e0 65 00 00     mov r5,0
17730 +                       8028: R_AVR32_LDA_GOT   far_positive
17731 +    802c:      ec 05 03 25     ld\.w r5,r6\[r5<<0x2\]
17732 +       ...
17733 +
17734 +00010018 <far_positive>:
17735 +   10018:      fa cc 00 00     sub r12,sp,0
17736 +       ...
17737 +0001002c <toofar_positive>:
17738 +   1002c:      fe ce 00 00     sub lr,pc,0
17739 --- /dev/null
17740 +++ b/gas/testsuite/gas/avr32/lda.s
17741 @@ -0,0 +1,30 @@
17742 +
17743 +       .text
17744 +       .global lda_test
17745 +lda_test:
17746 +toofar_negative:
17747 +       sub     r8, r9, 0
17748 +far_negative:
17749 +       sub     r10, r11, 0
17750 +
17751 +       .fill   32760, 1, 0x00
17752 +
17753 +       lda.w   r0, far_negative
17754 +       lda.w   r1, toofar_negative
17755 +       lda.w   r2, different_section
17756 +       lda.w   r3, undefined
17757 +       lda.w   r4, toofar_positive
17758 +       lda.w   r5, far_positive
17759 +
17760 +       .cpool
17761 +
17762 +       .fill   32744, 1, 0x00
17763 +far_positive:
17764 +       sub     r12, sp, 0
17765 +       .fill   16, 1, 0x00
17766 +toofar_positive:
17767 +       sub     lr, pc, 0
17768 +
17769 +       .data
17770 +different_section:
17771 +       .long   0x12345678
17772 --- /dev/null
17773 +++ b/gas/testsuite/gas/avr32/pcrel.d
17774 @@ -0,0 +1,64 @@
17775 +#as:
17776 +#objdump: -dr
17777 +#name: pcrel
17778 +
17779 +.*: +file format .*
17780 +
17781 +Disassembly of section \.text:
17782 +
17783 +00000000 <test_rjmp>:
17784 +   0:  d7 03           nop
17785 +   2:  c0 28           rjmp 6 <test_rjmp\+0x6>
17786 +   4:  d7 03           nop
17787 +   6:  e0 8f 00 00     bral 6 <test_rjmp\+0x6>
17788 +                       6: R_AVR32_22H_PCREL    extsym10
17789 +
17790 +0000000a <test_rcall>:
17791 +   a:  d7 03           nop
17792 +0000000c <test_rcall2>:
17793 +   c:  c0 2c           rcall 10 <test_rcall2\+0x4>
17794 +   e:  d7 03           nop
17795 +  10:  e0 a0 00 00     rcall 10 <test_rcall2\+0x4>
17796 +                       10: R_AVR32_22H_PCREL   extsym21
17797 +
17798 +00000014 <test_branch>:
17799 +  14:  c0 31           brne 1a <test_branch\+0x6>
17800 +  16:  e0 8f 00 00     bral 16 <test_branch\+0x2>
17801 +                       16: R_AVR32_22H_PCREL   test_branch
17802 +  1a:  e0 80 00 00     breq 1a <test_branch\+0x6>
17803 +                       1a: R_AVR32_22H_PCREL   extsym21
17804 +
17805 +0000001e <test_lddpc>:
17806 +  1e:  48 30           lddpc r0,28 <sym1>
17807 +  20:  48 20           lddpc r0,28 <sym1>
17808 +  22:  fe f0 00 00     ld.w r0,pc\[0\]
17809 +                       22: R_AVR32_16B_PCREL   extsym16
17810 +       \.\.\.
17811 +
17812 +00000028 <sym1>:
17813 +  28:  d7 03           nop
17814 +  2a:  d7 03           nop
17815 +
17816 +0000002c <test_local>:
17817 +  2c:  48 20           lddpc r0,34 <test_local\+0x8>
17818 +  2e:  48 30           lddpc r0,38 <test_local\+0xc>
17819 +  30:  48 20           lddpc r0,38 <test_local\+0xc>
17820 +  32:  00 00           add r0,r0
17821 +  34:  d7 03           nop
17822 +  36:  d7 03           nop
17823 +  38:  d7 03           nop
17824 +  3a:  d7 03           nop
17825 +
17826 +Disassembly of section \.text\.init:
17827 +
17828 +00000000 <test_inter_section>:
17829 +   0:  e0 a0 .. ..     rcall [0-9a-f]+ <.*>
17830 +                       0: R_AVR32_22H_PCREL    test_rcall
17831 +   4:  d7 03           nop
17832 +   6:  e0 a0 .. ..     rcall [0-9a-f]+ <.*>
17833 +                       6: R_AVR32_22H_PCREL    test_rcall
17834 +   a:  e0 a0 .. ..     rcall [0-9a-z]+ <.*>
17835 +                       a: R_AVR32_22H_PCREL    \.text\+0xc
17836 +   e:  d7 03           nop
17837 +  10:  e0 a0 .. ..     rcall [0-9a-f]+ <.*>
17838 +                       10: R_AVR32_22H_PCREL   \.text\+0xc
17839 --- /dev/null
17840 +++ b/gas/testsuite/gas/avr32/pcrel.s
17841 @@ -0,0 +1,57 @@
17842 +
17843 +        .text
17844 +        .global test_rjmp
17845 +test_rjmp:
17846 +        nop
17847 +        rjmp    0f
17848 +        nop
17849 +0:      rjmp    extsym10
17850 +
17851 +        .global test_rcall
17852 +test_rcall:
17853 +        nop
17854 +test_rcall2:
17855 +        rcall   0f
17856 +        nop
17857 +0:      rcall   extsym21
17858 +
17859 +        .global test_branch
17860 +test_branch:
17861 +        brne    0f
17862 +       /* This will generate a reloc since test_branch is global */
17863 +        bral    test_branch
17864 +0:     breq    extsym21
17865 +
17866 +        .global test_lddpc
17867 +test_lddpc:
17868 +        lddpc   r0,sym1
17869 +        lddpc   r0,sym1
17870 +        lddpc   r0,extsym16
17871 +
17872 +        .align 2
17873 +sym1:   nop
17874 +        nop
17875 +
17876 +       .global test_local
17877 +test_local:
17878 +       lddpc   r0, .LC1
17879 +       lddpc   r0, .LC2
17880 +       lddpc   r0, .LC1 + 0x4
17881 +
17882 +       .align  2
17883 +.LC1:
17884 +       nop
17885 +       nop
17886 +.LC2:
17887 +       nop
17888 +       nop
17889 +
17890 +       .section .text.init,"ax"
17891 +       .global test_inter_section
17892 +test_inter_section:
17893 +       rcall   test_rcall
17894 +       nop
17895 +       rcall   test_rcall
17896 +       rcall   test_rcall2
17897 +       nop
17898 +       rcall   test_rcall2
17899 --- /dev/null
17900 +++ b/gas/testsuite/gas/avr32/pico.d
17901 @@ -0,0 +1,149 @@
17902 +#as:
17903 +#objdump: -dr
17904 +#name: pico
17905 +
17906 +.*: +file format .*
17907 +
17908 +Disassembly of section \.text:
17909 +
17910 +[0-9a-f]* <picosvmac>:
17911 + *[0-9a-f]*:   e1 a6 20 00     cop cp1,cr0,cr0,cr0,0xc
17912 + *[0-9a-f]*:   e1 a7 2b bb     cop cp1,cr11,cr11,cr11,0xe
17913 + *[0-9a-f]*:   e1 a6 3a 05     cop cp1,cr10,cr0,cr5,0xd
17914 + *[0-9a-f]*:   e1 a7 36 90     cop cp1,cr6,cr9,cr0,0xf
17915 +
17916 +[0-9a-f]* <picosvmul>:
17917 + *[0-9a-f]*:   e1 a4 20 00     cop cp1,cr0,cr0,cr0,0x8
17918 + *[0-9a-f]*:   e1 a5 2b bb     cop cp1,cr11,cr11,cr11,0xa
17919 + *[0-9a-f]*:   e1 a4 3a 05     cop cp1,cr10,cr0,cr5,0x9
17920 + *[0-9a-f]*:   e1 a5 36 90     cop cp1,cr6,cr9,cr0,0xb
17921 +
17922 +[0-9a-f]* <picovmac>:
17923 + *[0-9a-f]*:   e1 a2 20 00     cop cp1,cr0,cr0,cr0,0x4
17924 + *[0-9a-f]*:   e1 a3 2b bb     cop cp1,cr11,cr11,cr11,0x6
17925 + *[0-9a-f]*:   e1 a2 3a 05     cop cp1,cr10,cr0,cr5,0x5
17926 + *[0-9a-f]*:   e1 a3 36 90     cop cp1,cr6,cr9,cr0,0x7
17927 +
17928 +[0-9a-f]* <picovmul>:
17929 + *[0-9a-f]*:   e1 a0 20 00     cop cp1,cr0,cr0,cr0,0x0
17930 + *[0-9a-f]*:   e1 a1 2b bb     cop cp1,cr11,cr11,cr11,0x2
17931 + *[0-9a-f]*:   e1 a0 3a 05     cop cp1,cr10,cr0,cr5,0x1
17932 + *[0-9a-f]*:   e1 a1 36 90     cop cp1,cr6,cr9,cr0,0x3
17933 +
17934 +[0-9a-f]* <picold_d>:
17935 + *[0-9a-f]*:   e9 af 3e ff     ldc\.d cp1,cr14,pc\[0x3fc\]
17936 + *[0-9a-f]*:   e9 a0 30 ff     ldc\.d cp1,cr0,r0\[0x3fc\]
17937 + *[0-9a-f]*:   e9 a0 30 00     ldc\.d cp1,cr0,r0\[0x0\]
17938 + *[0-9a-f]*:   ef a8 26 50     ldc\.d cp1,cr6,--r8
17939 + *[0-9a-f]*:   ef a7 28 50     ldc\.d cp1,cr8,--r7
17940 + *[0-9a-f]*:   ef aa 32 65     ldc\.d cp1,cr2,r10\[r5<<0x2\]
17941 + *[0-9a-f]*:   ef a3 3c 46     ldc\.d cp1,cr12,r3\[r6\]
17942 +
17943 +[0-9a-f]* <picold_w>:
17944 + *[0-9a-f]*:   e9 af 2f ff     ldc\.w cp1,cr15,pc\[0x3fc\]
17945 + *[0-9a-f]*:   e9 a0 20 ff     ldc\.w cp1,cr0,r0\[0x3fc\]
17946 + *[0-9a-f]*:   e9 a0 20 00     ldc\.w cp1,cr0,r0\[0x0\]
17947 + *[0-9a-f]*:   ef a8 27 40     ldc\.w cp1,cr7,--r8
17948 + *[0-9a-f]*:   ef a7 28 40     ldc\.w cp1,cr8,--r7
17949 + *[0-9a-f]*:   ef aa 31 25     ldc\.w cp1,cr1,r10\[r5<<0x2\]
17950 + *[0-9a-f]*:   ef a3 3d 06     ldc\.w cp1,cr13,r3\[r6\]
17951 +
17952 +[0-9a-f]* <picoldm_d>:
17953 + *[0-9a-f]*:   ed af 24 ff     ldcm\.d cp1,pc,cr0-cr15
17954 + *[0-9a-f]*:   ed a0 24 01     ldcm\.d cp1,r0,cr0-cr1
17955 + *[0-9a-f]*:   ed a7 24 80     ldcm\.d cp1,r7,cr14-cr15
17956 + *[0-9a-f]*:   ed a8 24 7f     ldcm\.d cp1,r8,cr0-cr13
17957 +
17958 +[0-9a-f]* <picoldm_d_pu>:
17959 + *[0-9a-f]*:   ed af 34 ff     ldcm\.d cp1,pc\+\+,cr0-cr15
17960 + *[0-9a-f]*:   ed a0 34 01     ldcm\.d cp1,r0\+\+,cr0-cr1
17961 + *[0-9a-f]*:   ed a7 34 80     ldcm\.d cp1,r7\+\+,cr14-cr15
17962 + *[0-9a-f]*:   ed a8 34 7f     ldcm\.d cp1,r8\+\+,cr0-cr13
17963 +
17964 +[0-9a-f]* <picoldm_w>:
17965 + *[0-9a-f]*:   ed af 20 ff     ldcm\.w cp1,pc,cr0-cr7
17966 + *[0-9a-f]*:   ed a0 20 01     ldcm\.w cp1,r0,cr0
17967 + *[0-9a-f]*:   ed a7 20 80     ldcm\.w cp1,r7,cr7
17968 + *[0-9a-f]*:   ed a8 20 7f     ldcm\.w cp1,r8,cr0-cr6
17969 + *[0-9a-f]*:   ed af 21 ff     ldcm\.w cp1,pc,cr8-cr15
17970 + *[0-9a-f]*:   ed a0 21 01     ldcm\.w cp1,r0,cr8
17971 + *[0-9a-f]*:   ed a7 21 80     ldcm\.w cp1,r7,cr15
17972 + *[0-9a-f]*:   ed a8 21 7f     ldcm\.w cp1,r8,cr8-cr14
17973 +
17974 +[0-9a-f]* <picoldm_w_pu>:
17975 + *[0-9a-f]*:   ed af 30 ff     ldcm\.w cp1,pc\+\+,cr0-cr7
17976 + *[0-9a-f]*:   ed a0 30 01     ldcm\.w cp1,r0\+\+,cr0
17977 + *[0-9a-f]*:   ed a7 30 80     ldcm\.w cp1,r7\+\+,cr7
17978 + *[0-9a-f]*:   ed a8 30 7f     ldcm\.w cp1,r8\+\+,cr0-cr6
17979 + *[0-9a-f]*:   ed af 31 ff     ldcm\.w cp1,pc\+\+,cr8-cr15
17980 + *[0-9a-f]*:   ed a0 31 01     ldcm\.w cp1,r0\+\+,cr8
17981 + *[0-9a-f]*:   ed a7 31 80     ldcm\.w cp1,r7\+\+,cr15
17982 + *[0-9a-f]*:   ed a8 31 7f     ldcm\.w cp1,r8\+\+,cr8-cr14
17983 +
17984 +[0-9a-f]* <picomv_d>:
17985 + *[0-9a-f]*:   ef ae 2e 30     mvrc\.d cp1,cr14,lr
17986 + *[0-9a-f]*:   ef a0 20 30     mvrc\.d cp1,cr0,r0
17987 + *[0-9a-f]*:   ef a8 26 30     mvrc\.d cp1,cr6,r8
17988 + *[0-9a-f]*:   ef a6 28 30     mvrc\.d cp1,cr8,r6
17989 + *[0-9a-f]*:   ef ae 2e 10     mvcr\.d cp1,lr,cr14
17990 + *[0-9a-f]*:   ef a0 20 10     mvcr\.d cp1,r0,cr0
17991 + *[0-9a-f]*:   ef a8 26 10     mvcr\.d cp1,r8,cr6
17992 + *[0-9a-f]*:   ef a6 28 10     mvcr\.d cp1,r6,cr8
17993 +
17994 +[0-9a-f]* <picomv_w>:
17995 + *[0-9a-f]*:   ef af 2f 20     mvrc\.w cp1,cr15,pc
17996 + *[0-9a-f]*:   ef a0 20 20     mvrc\.w cp1,cr0,r0
17997 + *[0-9a-f]*:   ef a8 27 20     mvrc\.w cp1,cr7,r8
17998 + *[0-9a-f]*:   ef a7 28 20     mvrc\.w cp1,cr8,r7
17999 + *[0-9a-f]*:   ef af 2f 00     mvcr\.w cp1,pc,cr15
18000 + *[0-9a-f]*:   ef a0 20 00     mvcr\.w cp1,r0,cr0
18001 + *[0-9a-f]*:   ef a8 27 00     mvcr\.w cp1,r8,cr7
18002 + *[0-9a-f]*:   ef a7 28 00     mvcr\.w cp1,r7,cr8
18003 +
18004 +[0-9a-f]* <picost_d>:
18005 + *[0-9a-f]*:   eb af 3e ff     stc\.d cp1,pc\[0x3fc\],cr14
18006 + *[0-9a-f]*:   eb a0 30 00     stc\.d cp1,r0\[0x0\],cr0
18007 + *[0-9a-f]*:   ef a8 26 70     stc\.d cp1,r8\+\+,cr6
18008 + *[0-9a-f]*:   ef a7 28 70     stc\.d cp1,r7\+\+,cr8
18009 + *[0-9a-f]*:   ef aa 32 e5     stc\.d cp1,r10\[r5<<0x2\],cr2
18010 + *[0-9a-f]*:   ef a3 3c c6     stc\.d cp1,r3\[r6\],cr12
18011 +
18012 +[0-9a-f]* <picost_w>:
18013 + *[0-9a-f]*:   eb af 2f ff     stc\.w cp1,pc\[0x3fc\],cr15
18014 + *[0-9a-f]*:   eb a0 20 00     stc\.w cp1,r0\[0x0\],cr0
18015 + *[0-9a-f]*:   ef a8 27 60     stc\.w cp1,r8\+\+,cr7
18016 + *[0-9a-f]*:   ef a7 28 60     stc\.w cp1,r7\+\+,cr8
18017 + *[0-9a-f]*:   ef aa 31 a5     stc\.w cp1,r10\[r5<<0x2\],cr1
18018 + *[0-9a-f]*:   ef a3 3d 86     stc\.w cp1,r3\[r6\],cr13
18019 +
18020 +[0-9a-f]* <picostm_d>:
18021 + *[0-9a-f]*:   ed af 25 ff     stcm\.d cp1,pc,cr0-cr15
18022 + *[0-9a-f]*:   ed a0 25 01     stcm\.d cp1,r0,cr0-cr1
18023 + *[0-9a-f]*:   ed a7 25 80     stcm\.d cp1,r7,cr14-cr15
18024 + *[0-9a-f]*:   ed a8 25 7f     stcm\.d cp1,r8,cr0-cr13
18025 +
18026 +[0-9a-f]* <picostm_d_pu>:
18027 + *[0-9a-f]*:   ed af 35 ff     stcm\.d cp1,--pc,cr0-cr15
18028 + *[0-9a-f]*:   ed a0 35 01     stcm\.d cp1,--r0,cr0-cr1
18029 + *[0-9a-f]*:   ed a7 35 80     stcm\.d cp1,--r7,cr14-cr15
18030 + *[0-9a-f]*:   ed a8 35 7f     stcm\.d cp1,--r8,cr0-cr13
18031 +
18032 +[0-9a-f]* <picostm_w>:
18033 + *[0-9a-f]*:   ed af 22 ff     stcm\.w cp1,pc,cr0-cr7
18034 + *[0-9a-f]*:   ed a0 22 01     stcm\.w cp1,r0,cr0
18035 + *[0-9a-f]*:   ed a7 22 80     stcm\.w cp1,r7,cr7
18036 + *[0-9a-f]*:   ed a8 22 7f     stcm\.w cp1,r8,cr0-cr6
18037 + *[0-9a-f]*:   ed af 23 ff     stcm\.w cp1,pc,cr8-cr15
18038 + *[0-9a-f]*:   ed a0 23 01     stcm\.w cp1,r0,cr8
18039 + *[0-9a-f]*:   ed a7 23 80     stcm\.w cp1,r7,cr15
18040 + *[0-9a-f]*:   ed a8 23 7f     stcm\.w cp1,r8,cr8-cr14
18041 +
18042 +[0-9a-f]* <picostm_w_pu>:
18043 + *[0-9a-f]*:   ed af 32 ff     stcm\.w cp1,--pc,cr0-cr7
18044 + *[0-9a-f]*:   ed a0 32 01     stcm\.w cp1,--r0,cr0
18045 + *[0-9a-f]*:   ed a7 32 80     stcm\.w cp1,--r7,cr7
18046 + *[0-9a-f]*:   ed a8 32 7f     stcm\.w cp1,--r8,cr0-cr6
18047 + *[0-9a-f]*:   ed af 33 ff     stcm\.w cp1,--pc,cr8-cr15
18048 + *[0-9a-f]*:   ed a0 33 01     stcm\.w cp1,--r0,cr8
18049 + *[0-9a-f]*:   ed a7 33 80     stcm\.w cp1,--r7,cr15
18050 + *[0-9a-f]*:   ed a8 33 7f     stcm\.w cp1,--r8,cr8-cr14
18051 --- /dev/null
18052 +++ b/gas/testsuite/gas/avr32/pico.s
18053 @@ -0,0 +1,144 @@
18054 +
18055 +       .text
18056 +       .global picosvmac
18057 +picosvmac:
18058 +       picosvmac       out0, in0, in0, in0
18059 +       picosvmac       out2, in11, in11, in11
18060 +       picosvmac       out1, in10, in0, in5
18061 +       picosvmac       out3, in6, in9, in0
18062 +       .global picosvmul
18063 +picosvmul:
18064 +       picosvmul       out0, in0, in0, in0
18065 +       picosvmul       out2, in11, in11, in11
18066 +       picosvmul       out1, in10, in0, in5
18067 +       picosvmul       out3, in6, in9, in0
18068 +       .global picovmac
18069 +picovmac:
18070 +       picovmac        out0, in0, in0, in0
18071 +       picovmac        out2, in11, in11, in11
18072 +       picovmac        out1, in10, in0, in5
18073 +       picovmac        out3, in6, in9, in0
18074 +       .global picovmul
18075 +picovmul:
18076 +       picovmul        out0, in0, in0, in0
18077 +       picovmul        out2, in11, in11, in11
18078 +       picovmul        out1, in10, in0, in5
18079 +       picovmul        out3, in6, in9, in0
18080 +       .global picold_d
18081 +picold_d:
18082 +       picold.d        vmu2_out, pc[1020]
18083 +       picold.d        inpix2, r0[1020]
18084 +       picold.d        inpix2, r0[0]
18085 +       picold.d        coeff0_a, --r8
18086 +       picold.d        coeff1_a, --r7
18087 +       picold.d        inpix0, r10[r5 << 2]
18088 +       picold.d        vmu0_out, r3[r6 << 0]
18089 +       .global picold_w
18090 +picold_w:
18091 +       picold.w        config, pc[1020]
18092 +       picold.w        inpix2, r0[1020]
18093 +       picold.w        inpix2, r0[0]
18094 +       picold.w        coeff0_b, --r8
18095 +       picold.w        coeff1_a, --r7
18096 +       picold.w        inpix1, r10[r5 << 2]
18097 +       picold.w        vmu1_out, r3[r6 << 0]
18098 +       .global picoldm_d
18099 +picoldm_d:
18100 +       picoldm.d       pc, inpix2-config
18101 +       picoldm.d       r0, inpix2, inpix1
18102 +       picoldm.d       r7, vmu2_out, config
18103 +       picoldm.d       r8, inpix2-vmu1_out
18104 +       .global picoldm_d_pu
18105 +picoldm_d_pu:
18106 +       picoldm.d       pc++, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out, vmu2_out, config
18107 +       picoldm.d       r0++, inpix2, inpix1
18108 +       picoldm.d       r7++, vmu2_out, config
18109 +       picoldm.d       r8++, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out
18110 +       .global picoldm_w
18111 +picoldm_w:
18112 +       picoldm.w       pc, inpix2-coeff0_b
18113 +       picoldm.w       r0, inpix2
18114 +       picoldm.w       r7, coeff0_b
18115 +       picoldm.w       r8, inpix2-coeff0_a
18116 +       picoldm.w       pc, coeff1_a-config
18117 +       picoldm.w       r0, coeff1_a
18118 +       picoldm.w       r7, config
18119 +       picoldm.w       r8, coeff1_a-vmu2_out
18120 +       .global picoldm_w_pu
18121 +picoldm_w_pu:
18122 +       picoldm.w       pc++, inpix2-coeff0_b
18123 +       picoldm.w       r0++, inpix2
18124 +       picoldm.w       r7++, coeff0_b
18125 +       picoldm.w       r8++, inpix2-coeff0_a
18126 +       picoldm.w       pc++, coeff1_a-config
18127 +       picoldm.w       r0++, coeff1_a
18128 +       picoldm.w       r7++, config
18129 +       picoldm.w       r8++, coeff1_a-vmu2_out
18130 +       .global picomv_d
18131 +picomv_d:
18132 +       picomv.d        vmu2_out, lr
18133 +       picomv.d        inpix2, r0
18134 +       picomv.d        coeff0_a, r8
18135 +       picomv.d        coeff1_a, r6
18136 +       picomv.d        pc, vmu2_out
18137 +       picomv.d        r0, inpix2
18138 +       picomv.d        r8, coeff0_a
18139 +       picomv.d        r6, coeff1_a
18140 +       .global picomv_w
18141 +picomv_w:
18142 +       picomv.w        config, pc
18143 +       picomv.w        inpix2, r0
18144 +       picomv.w        coeff0_b, r8
18145 +       picomv.w        coeff1_a, r7
18146 +       picomv.w        pc, config
18147 +       picomv.w        r0, inpix2
18148 +       picomv.w        r8, coeff0_b
18149 +       picomv.w        r7, coeff1_a
18150 +       .global picost_d
18151 +picost_d:
18152 +       picost.d        pc[1020], vmu2_out
18153 +       picost.d        r0[0], inpix2
18154 +       picost.d        r8++, coeff0_a
18155 +       picost.d        r7++, coeff1_a
18156 +       picost.d        r10[r5 << 2], inpix0
18157 +       picost.d        r3[r6 << 0], vmu0_out
18158 +       .global picost_w
18159 +picost_w:
18160 +       picost.w        pc[1020], config
18161 +       picost.w        r0[0], inpix2
18162 +       picost.w        r8++, coeff0_b
18163 +       picost.w        r7++, coeff1_a
18164 +       picost.w        r10[r5 << 2], inpix1
18165 +       picost.w        r3[r6 << 0], vmu1_out
18166 +       .global picostm_d
18167 +picostm_d:
18168 +       picostm.d       pc, inpix2-config
18169 +       picostm.d       r0, inpix2, inpix1
18170 +       picostm.d       r7, vmu2_out, config
18171 +       picostm.d       r8, inpix2-vmu1_out
18172 +       .global picostm_d_pu
18173 +picostm_d_pu:
18174 +       picostm.d       --pc, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out, vmu2_out, config
18175 +       picostm.d       --r0, inpix2, inpix1
18176 +       picostm.d       --r7, vmu2_out, config
18177 +       picostm.d       --r8, inpix2, inpix1, inpix0, outpix2, outpix1, outpix0, coeff0_a, coeff0_b, coeff1_a, coeff1_b, coeff2_a, coeff2_b, vmu0_out, vmu1_out
18178 +       .global picostm_w
18179 +picostm_w:
18180 +       picostm.w       pc, inpix2-coeff0_b
18181 +       picostm.w       r0, inpix2
18182 +       picostm.w       r7, coeff0_b
18183 +       picostm.w       r8, inpix2-coeff0_a
18184 +       picostm.w       pc, coeff1_a-config
18185 +       picostm.w       r0, coeff1_a
18186 +       picostm.w       r7, config
18187 +       picostm.w       r8, coeff1_a-vmu2_out
18188 +       .global picostm_w_pu
18189 +picostm_w_pu:
18190 +       picostm.w       --pc, inpix2-coeff0_b
18191 +       picostm.w       --r0, inpix2
18192 +       picostm.w       --r7, coeff0_b
18193 +       picostm.w       --r8, inpix2-coeff0_a
18194 +       picostm.w       --pc, coeff1_a-config
18195 +       picostm.w       --r0, coeff1_a
18196 +       picostm.w       --r7, config
18197 +       picostm.w       --r8, coeff1_a-vmu2_out
18198 --- /dev/null
18199 +++ b/gas/testsuite/gas/avr32/pic_reloc.d
18200 @@ -0,0 +1,27 @@
18201 +#as:
18202 +#objdump: -dr
18203 +#name: pic_reloc
18204 +
18205 +.*: +file format .*
18206 +
18207 +Disassembly of section \.text:
18208 +
18209 +00000000 <mcall_got>:
18210 +   0:  f0 16 00 00     mcall r6\[0\]
18211 +                       0: R_AVR32_GOT18SW      extfunc
18212 +   4:  f0 16 00 00     mcall r6\[0\]
18213 +                       4: R_AVR32_GOT18SW      \.L1
18214 +   8:  f0 16 00 00     mcall r6\[0\]
18215 +                       8: R_AVR32_GOT18SW      \.L2
18216 +   c:  f0 16 00 00     mcall r6\[0\]
18217 +                       c: R_AVR32_GOT18SW      mcall_got
18218 +
18219 +00000010 <ldw_got>:
18220 +  10:  ec f0 00 00     ld.w r0,r6\[0\]
18221 +                       10: R_AVR32_GOT16S      extvar
18222 +  14:  ec f0 00 00     ld.w r0,r6\[0\]
18223 +                       14: R_AVR32_GOT16S      \.L3
18224 +  18:  ec f0 00 00     ld.w r0,r6\[0\]
18225 +                       18: R_AVR32_GOT16S      \.L4
18226 +  1c:  ec f0 00 00     ld.w r0,r6\[0\]
18227 +                       1c: R_AVR32_GOT16S      ldw_got
18228 --- /dev/null
18229 +++ b/gas/testsuite/gas/avr32/pic_reloc.s
18230 @@ -0,0 +1,18 @@
18231 +
18232 +       .text
18233 +       .global mcall_got
18234 +mcall_got:
18235 +.L1:
18236 +       mcall   r6[extfunc@got]
18237 +       mcall   r6[.L1@got]
18238 +       mcall   r6[.L2@got]
18239 +       mcall   r6[mcall_got@got]
18240 +.L2:
18241 +
18242 +       .global ldw_got
18243 +ldw_got:
18244 +.L3:   ld.w    r0,r6[extvar@got]
18245 +       ld.w    r0,r6[.L3@got]
18246 +       ld.w    r0,r6[.L4@got]
18247 +       ld.w    r0,r6[ldw_got@got]
18248 +.L4:
18249 --- /dev/null
18250 +++ b/gas/testsuite/gas/avr32/symdiff.d
18251 @@ -0,0 +1,24 @@
18252 +#source: symdiff.s
18253 +#as:
18254 +#objdump: -dr
18255 +#name: symdiff
18256 +
18257 +.*: +file format .*
18258 +
18259 +Disassembly of section \.text:
18260 +
18261 +00000000 <diff32>:
18262 +   0:  00 00           add r0,r0
18263 +   2:  00 04           add r4,r0
18264 +
18265 +00000004 <diff16>:
18266 +   4:  00 04           add r4,r0
18267 +
18268 +00000006 <diff8>:
18269 +   6:  04 00           add r0,r2
18270 +
18271 +00000008 <symdiff_test>:
18272 +   8:  d7 03           nop
18273 +   a:  d7 03           nop
18274 +   c:  d7 03           nop
18275 +   e:  d7 03           nop
18276 --- /dev/null
18277 +++ b/gas/testsuite/gas/avr32/symdiff_linkrelax.d
18278 @@ -0,0 +1,28 @@
18279 +#source: symdiff.s
18280 +#as: --linkrelax
18281 +#objdump: -dr
18282 +#name: symdiff_linkrelax
18283 +
18284 +.*: +file format .*
18285 +
18286 +Disassembly of section \.text:
18287 +
18288 +00000000 <diff32>:
18289 +   0:  00 00           add r0,r0
18290 +                       0: R_AVR32_DIFF32       \.text\+0xa
18291 +   2:  00 04           add r4,r0
18292 +
18293 +00000004 <diff16>:
18294 +   4:  00 04           add r4,r0
18295 +                       4: R_AVR32_DIFF16       \.text\+0xa
18296 +
18297 +00000006 <diff8>:
18298 +   6:  04 00           add r0,r2
18299 +                       6: R_AVR32_DIFF8        \.text\+0xa
18300 +                       7: R_AVR32_ALIGN        \*ABS\*\+0x1
18301 +
18302 +00000008 <symdiff_test>:
18303 +   8:  d7 03           nop
18304 +   a:  d7 03           nop
18305 +   c:  d7 03           nop
18306 +   e:  d7 03           nop
18307 --- /dev/null
18308 +++ b/gas/testsuite/gas/avr32/symdiff.s
18309 @@ -0,0 +1,19 @@
18310 +
18311 +       .text
18312 +       .global diff32
18313 +diff32:
18314 +       .long   .L2 - .L1
18315 +       .global diff16
18316 +diff16:
18317 +       .short  .L2 - .L1
18318 +       .global diff8
18319 +diff8:
18320 +       .byte   .L2 - .L1
18321 +
18322 +       .global symdiff_test
18323 +       .align  1
18324 +symdiff_test:
18325 +       nop
18326 +.L1:   nop
18327 +       nop
18328 +.L2:   nop
18329 --- a/gas/write.c
18330 +++ b/gas/write.c
18331 @@ -2227,6 +2227,10 @@ relax_frag (segT segment, fragS *fragP,
18332
18333  #endif /* defined (TC_GENERIC_RELAX_TABLE)  */
18334
18335 +#ifdef TC_RELAX_ALIGN
18336 +#define RELAX_ALIGN(SEG, FRAG, ADDR) TC_RELAX_ALIGN(SEG, FRAG, ADDR)
18337 +#else
18338 +#define RELAX_ALIGN(SEG, FRAG, ADDR) relax_align(ADDR, (FRAG)->fr_offset)
18339  /* Relax_align. Advance location counter to next address that has 'alignment'
18340     lowest order bits all 0s, return size of adjustment made.  */
18341  static relax_addressT
18342 @@ -2246,6 +2250,7 @@ relax_align (register relax_addressT add
18343  #endif
18344    return (new_address - address);
18345  }
18346 +#endif
18347
18348  /* Now we have a segment, not a crowd of sub-segments, we can make
18349     fr_address values.
18350 @@ -2292,7 +2297,7 @@ relax_segment (struct frag *segment_frag
18351         case rs_align_code:
18352         case rs_align_test:
18353           {
18354 -           addressT offset = relax_align (address, (int) fragP->fr_offset);
18355 +           addressT offset = RELAX_ALIGN(segment, fragP, address);
18356
18357             if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype)
18358               offset = 0;
18359 @@ -2503,10 +2508,10 @@ relax_segment (struct frag *segment_frag
18360                 {
18361                   addressT oldoff, newoff;
18362
18363 -                 oldoff = relax_align (was_address + fragP->fr_fix,
18364 -                                       (int) offset);
18365 -                 newoff = relax_align (address + fragP->fr_fix,
18366 -                                       (int) offset);
18367 +                 oldoff = RELAX_ALIGN (segment, fragP,
18368 +                                       was_address + fragP->fr_fix);
18369 +                 newoff = RELAX_ALIGN (segment, fragP,
18370 +                                       address + fragP->fr_fix);
18371
18372                   if (fragP->fr_subtype != 0)
18373                     {
18374 --- a/include/dis-asm.h
18375 +++ b/include/dis-asm.h
18376 @@ -222,6 +222,7 @@ typedef int (*disassembler_ftype) (bfd_v
18377
18378  extern int print_insn_alpha            (bfd_vma, disassemble_info *);
18379  extern int print_insn_avr              (bfd_vma, disassemble_info *);
18380 +extern int print_insn_avr32            (bfd_vma, disassemble_info *);
18381  extern int print_insn_bfin             (bfd_vma, disassemble_info *);
18382  extern int print_insn_big_arm          (bfd_vma, disassemble_info *);
18383  extern int print_insn_big_mips         (bfd_vma, disassemble_info *);
18384 @@ -304,7 +305,9 @@ extern void print_i386_disassembler_opti
18385  extern void print_mips_disassembler_options (FILE *);
18386  extern void print_ppc_disassembler_options (FILE *);
18387  extern void print_arm_disassembler_options (FILE *);
18388 +extern void print_avr32_disassembler_options (FILE *);
18389  extern void parse_arm_disassembler_option (char *);
18390 +extern void parse_avr32_disassembler_option (char *);
18391  extern void print_s390_disassembler_options (FILE *);
18392  extern int  get_arm_regname_num_options (void);
18393  extern int  set_arm_regname_option (int);
18394 --- /dev/null
18395 +++ b/include/elf/avr32.h
18396 @@ -0,0 +1,98 @@
18397 +/* AVR32 ELF support for BFD.
18398 +   Copyright 2003,2004,2005,2006,2007,2008,2009 Atmel Corporation.
18399 +
18400 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
18401 +
18402 +   This file is part of BFD, the Binary File Descriptor library.
18403 +
18404 +   This program is free software; you can redistribute it and/or
18405 +   modify it under the terms of the GNU General Public License as
18406 +   published by the Free Software Foundation; either version 2 of the
18407 +   License, or (at your option) any later version.
18408 +
18409 +   This program is distributed in the hope that it will be useful, but
18410 +   WITHOUT ANY WARRANTY; without even the implied warranty of
18411 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18412 +   General Public License for more details.
18413 +
18414 +   You should have received a copy of the GNU General Public License
18415 +   along with this program; if not, write to the Free Software
18416 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
18417 +   02111-1307, USA.  */
18418 +
18419 +#include "elf/reloc-macros.h"
18420 +
18421 +/* CPU-specific flags for the ELF header e_flags field */
18422 +#define EF_AVR32_LINKRELAX             0x01
18423 +#define EF_AVR32_PIC                   0x02
18424 +
18425 +START_RELOC_NUMBERS (elf_avr32_reloc_type)
18426 +    RELOC_NUMBER (R_AVR32_NONE,                        0)
18427 +
18428 +    /* Data Relocations */
18429 +    RELOC_NUMBER (R_AVR32_32,                  1)
18430 +    RELOC_NUMBER (R_AVR32_16,                  2)
18431 +    RELOC_NUMBER (R_AVR32_8,                   3)
18432 +    RELOC_NUMBER (R_AVR32_32_PCREL,            4)
18433 +    RELOC_NUMBER (R_AVR32_16_PCREL,            5)
18434 +    RELOC_NUMBER (R_AVR32_8_PCREL,             6)
18435 +    RELOC_NUMBER (R_AVR32_DIFF32,              7)
18436 +    RELOC_NUMBER (R_AVR32_DIFF16,              8)
18437 +    RELOC_NUMBER (R_AVR32_DIFF8,               9)
18438 +    RELOC_NUMBER (R_AVR32_GOT32,               10)
18439 +    RELOC_NUMBER (R_AVR32_GOT16,               11)
18440 +    RELOC_NUMBER (R_AVR32_GOT8,                        12)
18441 +
18442 +    /* Normal Code Relocations */
18443 +    RELOC_NUMBER (R_AVR32_21S,                 13)
18444 +    RELOC_NUMBER (R_AVR32_16U,                 14)
18445 +    RELOC_NUMBER (R_AVR32_16S,                 15)
18446 +    RELOC_NUMBER (R_AVR32_8S,                  16)
18447 +    RELOC_NUMBER (R_AVR32_8S_EXT,              17)
18448 +
18449 +    /* PC-Relative Code Relocations */
18450 +    RELOC_NUMBER (R_AVR32_22H_PCREL,           18)
18451 +    RELOC_NUMBER (R_AVR32_18W_PCREL,           19)
18452 +    RELOC_NUMBER (R_AVR32_16B_PCREL,           20)
18453 +    RELOC_NUMBER (R_AVR32_16N_PCREL,           21)
18454 +    RELOC_NUMBER (R_AVR32_14UW_PCREL,          22)
18455 +    RELOC_NUMBER (R_AVR32_11H_PCREL,           23)
18456 +    RELOC_NUMBER (R_AVR32_10UW_PCREL,          24)
18457 +    RELOC_NUMBER (R_AVR32_9H_PCREL,            25)
18458 +    RELOC_NUMBER (R_AVR32_9UW_PCREL,           26)
18459 +
18460 +    /* Special Code Relocations */
18461 +    RELOC_NUMBER (R_AVR32_HI16,                        27)
18462 +    RELOC_NUMBER (R_AVR32_LO16,                        28)
18463 +
18464 +    /* PIC Relocations */
18465 +    RELOC_NUMBER (R_AVR32_GOTPC,               29)
18466 +    RELOC_NUMBER (R_AVR32_GOTCALL,             30)
18467 +    RELOC_NUMBER (R_AVR32_LDA_GOT,             31)
18468 +    RELOC_NUMBER (R_AVR32_GOT21S,              32)
18469 +    RELOC_NUMBER (R_AVR32_GOT18SW,             33)
18470 +    RELOC_NUMBER (R_AVR32_GOT16S,              34)
18471 +    RELOC_NUMBER (R_AVR32_GOT7UW,              35)
18472 +
18473 +    /* Constant Pool Relocations */
18474 +    RELOC_NUMBER (R_AVR32_32_CPENT,            36)
18475 +    RELOC_NUMBER (R_AVR32_CPCALL,              37)
18476 +    RELOC_NUMBER (R_AVR32_16_CP,               38)
18477 +    RELOC_NUMBER (R_AVR32_9W_CP,               39)
18478 +
18479 +    /* Dynamic Relocations */
18480 +    RELOC_NUMBER (R_AVR32_RELATIVE,            40)
18481 +    RELOC_NUMBER (R_AVR32_GLOB_DAT,            41)
18482 +    RELOC_NUMBER (R_AVR32_JMP_SLOT,            42)
18483 +
18484 +    /* Linkrelax Information */
18485 +    RELOC_NUMBER (R_AVR32_ALIGN,               43)
18486 +
18487 +    RELOC_NUMBER (R_AVR32_15S,                 44)
18488 +
18489 +END_RELOC_NUMBERS (R_AVR32_max)
18490 +
18491 +/* Processor specific dynamic array tags.  */
18492 +
18493 +/* The total size in bytes of the Global Offset Table */
18494 +#define DT_AVR32_GOTSZ                 0x70000001
18495 --- a/include/elf/common.h
18496 +++ b/include/elf/common.h
18497 @@ -289,7 +289,7 @@
18498  #define EM_INTEL182    182     /* Reserved by Intel */
18499  #define EM_res183      183     /* Reserved by ARM */
18500  #define EM_res184      184     /* Reserved by ARM */
18501 -#define EM_AVR32       185     /* Atmel Corporation 32-bit microprocessor family */
18502 +#define EM_AVR32_OLD   185     /* Atmel Corporation 32-bit microprocessor family */
18503  #define EM_STM8        186     /* STMicroeletronics STM8 8-bit microcontroller */
18504  #define EM_TILE64      187     /* Tilera TILE64 multicore architecture family */
18505  #define EM_TILEPRO     188     /* Tilera TILEPro multicore architecture family */
18506 @@ -369,6 +369,9 @@
18507  /* V850 backend magic number.  Written in the absense of an ABI.  */
18508  #define EM_CYGNUS_V850         0x9080
18509
18510 +/* AVR32 magic number, picked by IAR Systems. */
18511 +#define EM_AVR32               0x18ad
18512 +
18513  /* old S/390 backend magic number. Written in the absence of an ABI.  */
18514  #define EM_S390_OLD            0xa390
18515
18516 --- a/ld/configdoc.texi
18517 +++ b/ld/configdoc.texi
18518 @@ -7,6 +7,7 @@
18519  @set H8300
18520  @set HPPA
18521  @set I960
18522 +@set AVR32
18523  @set M68HC11
18524  @set M68K
18525  @set MMIX
18526 --- a/ld/configure.tgt
18527 +++ b/ld/configure.tgt
18528 @@ -113,6 +113,9 @@ xscale-*-elf)               targ_emul=armelf
18529  avr-*-*)               targ_emul=avr2
18530                         targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6"
18531                         ;;
18532 +avr32-*-none)           targ_emul=avr32elf_ap7000
18533 +                        targ_extra_emuls="avr32elf_ap7001 avr32elf_ap7002 avr32elf_ap7200 avr32elf_uc3a0128 avr32elf_uc3a0256 avr32elf_uc3a0512 avr32elf_uc3a0512es avr32elf_uc3a1128 avr32elf_uc3a1256 avr32elf_uc3a1512es avr32elf_uc3a1512 avr32elf_uc3a364 avr32elf_uc3a364s avr32elf_uc3a3128 avr32elf_uc3a3128s avr32elf_uc3a3256 avr32elf_uc3a3256s avr32elf_uc3b064 avr32elf_uc3b0128 avr32elf_uc3b0256es avr32elf_uc3b0256 avr32elf_uc3b0512 avr32elf_uc3b0512revc avr32elf_uc3b164 avr32elf_uc3b1128 avr32elf_uc3b1256es avr32elf_uc3b1256 avr32elf_uc3b1512 avr32elf_uc3b1512revc avr32elf_uc3c0512crevc avr32elf_uc3c1512crevc avr32elf_uc3c2512crevc avr32elf_atuc3l0256 avr32elf_mxt768e avr32elf_uc3l064 avr32elf_uc3l032 avr32elf_uc3l016 avr32elf_uc3l064revb avr32elf_uc3c064c avr32elf_uc3c0128c avr32elf_uc3c0256c avr32elf_uc3c0512c avr32elf_uc3c164c avr32elf_uc3c1128c avr32elf_uc3c1256c avr32elf_uc3c1512c avr32elf_uc3c264c avr32elf_uc3c2128c avr32elf_uc3c2256c avr32elf_uc3c2512c" ;;
18534 +avr32-*-linux*)         targ_emul=avr32linux ;;
18535  bfin-*-elf)            targ_emul=elf32bfin;
18536                         targ_extra_emuls="elf32bfinfd"
18537                         targ_extra_libpath=$targ_extra_emuls
18538 --- /dev/null
18539 +++ b/ld/emulparams/avr32elf.sh
18540 @@ -0,0 +1,402 @@
18541 +# This script is called from ld/genscript.sh
18542 +# There is a difference on how 'bash' and POSIX handles
18543 +# the  '.' (source) command in a script.
18544 +# genscript.sh calls this script with argument ${EMULATION_NAME}
18545 +# but that will fail on POSIX compilant shells like 'sh' or 'dash'
18546 +# therefor I use the variable directly instead of $1
18547 +EMULATION=${EMULATION_NAME}
18548 +SCRIPT_NAME=avr32
18549 +TEMPLATE_NAME=elf32
18550 +EXTRA_EM_FILE=avr32elf
18551 +OUTPUT_FORMAT="elf32-avr32"
18552 +ARCH=avr32
18553 +MAXPAGESIZE=4096
18554 +ENTRY=_start
18555 +EMBEDDED=yes
18556 +NO_SMALL_DATA=yes
18557 +NOP=0xd703d703
18558 +
18559 +DATA_SEGMENT_ALIGN=8
18560 +BSS_ALIGNMENT=8
18561 +
18562 +RO_LMA_REGION="FLASH"
18563 +RO_VMA_REGION="FLASH"
18564 +RW_LMA_REGION="FLASH"
18565 +RW_VMA_REGION="CPUSRAM"
18566 +
18567 +STACK_SIZE=_stack_size
18568 +STACK_ADDR="ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - ${STACK_SIZE}"
18569 +
18570 +DATA_SEGMENT_END="
18571 +  __heap_start__ = ALIGN(8);
18572 +  . = ${STACK_ADDR};
18573 +  __heap_end__ = .;
18574 +"
18575 +
18576 +case "$EMULATION" in
18577 +avr32elf_ap*)
18578 +    MACHINE=ap
18579 +    INITIAL_READONLY_SECTIONS="
18580 +    .reset : {  *(.reset) } >FLASH AT>FLASH
18581 +    . = . & 0x9fffffff;
18582 +"
18583 +    TEXT_START_ADDR=0xa0000000
18584 +    case "$EMULATION" in
18585 +           avr32elf_ap700[0-2])
18586 +              MEMORY="
18587 +MEMORY
18588 +{
18589 +    FLASH (rxai) : ORIGIN = 0x00000000, LENGTH = 64M
18590 +    CPUSRAM (rwxa) : ORIGIN = 0x24000000, LENGTH = 32K
18591 +}
18592 +"
18593 +        ;;
18594 +    avr32elf_ap7200)
18595 +        MEMORY="
18596 +MEMORY
18597 +{
18598 +    FLASH (rxai) : ORIGIN = 0x00000000, LENGTH = 64M
18599 +    CPUSRAM (rwxa) : ORIGIN = 0x08000000, LENGTH = 64K
18600 +}
18601 +"
18602 +        ;;
18603 +    esac
18604 +    ;;
18605 +
18606 +avr32elf_mxt768e)
18607 +    MACHINE=uc
18608 +    INITIAL_READONLY_SECTIONS=".reset : {  *(.reset) } >FLASH AT>FLASH"
18609 +    TEXT_START_ADDR=0x80000000
18610 +    OTHER_SECTIONS="
18611 +  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE
18612 +  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE
18613 +"
18614 +        MEMORY="
18615 +MEMORY
18616 +{
18617 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18618 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18619 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18620 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18621 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18622 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18623 +}
18624 +"
18625 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18626 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18627 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18628 +"
18629 +      ;;
18630 +
18631 +avr32elf_atuc3*)
18632 +    MACHINE=uc
18633 +    INITIAL_READONLY_SECTIONS=".reset : {  *(.reset) } >FLASH AT>FLASH"
18634 +    TEXT_START_ADDR=0x80000000
18635 +    OTHER_SECTIONS="
18636 +  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE
18637 +  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE
18638 +"
18639 +    case "$EMULATION" in
18640 +    avr32elf_atuc3l0256)
18641 +        MEMORY="
18642 +MEMORY
18643 +{
18644 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18645 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18646 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18647 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18648 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18649 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18650 +}
18651 +"
18652 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18653 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18654 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18655 +"
18656 +        ;;
18657 +    esac
18658 +    ;;
18659 +
18660 +avr32elf_uc3*)
18661 +    MACHINE=uc
18662 +    INITIAL_READONLY_SECTIONS=".reset : {  *(.reset) } >FLASH AT>FLASH"
18663 +    TEXT_START_ADDR=0x80000000
18664 +    OTHER_SECTIONS="
18665 +  .userpage :  { *(.userpage .userpage.*)  } >USERPAGE AT>USERPAGE
18666 +  .factorypage :  { *(.factorypage .factorypage.*)  } >FACTORYPAGE AT>FACTORYPAGE
18667 +"
18668 +
18669 +    case "$EMULATION" in
18670 +    avr32elf_uc3c[012]512c)
18671 +        MEMORY="
18672 +MEMORY
18673 +{
18674 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18675 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18676 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18677 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18678 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18679 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18680 +}
18681 +"
18682 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18683 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18684 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18685 +"
18686 +        ;;
18687 +
18688 +    avr32elf_uc3c[012]256c)
18689 +        MEMORY="
18690 +MEMORY
18691 +{
18692 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18693 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18694 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18695 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18696 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18697 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18698 +}
18699 +"
18700 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18701 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18702 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18703 +"
18704 +        ;;
18705 +
18706 +    avr32elf_uc3c[012]128c)
18707 +        MEMORY="
18708 +MEMORY
18709 +{
18710 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
18711 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
18712 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18713 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18714 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18715 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18716 +}
18717 +"
18718 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18719 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18720 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18721 +"
18722 +        ;;
18723 +
18724 +    avr32elf_uc3c[012]64c)
18725 +        MEMORY="
18726 +MEMORY
18727 +{
18728 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18729 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18730 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18731 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18732 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18733 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18734 +}
18735 +"
18736 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18737 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18738 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18739 +"
18740 +        ;;
18741 +
18742 +   avr32elf_uc3[ac][012]512*)
18743 +       MEMORY="
18744 +MEMORY
18745 +{
18746 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18747 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18748 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18749 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18750 +}
18751 +"
18752 +        ;;
18753 +
18754 +    avr32elf_uc3a[012]256*)
18755 +        MEMORY="
18756 +MEMORY
18757 +{
18758 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18759 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18760 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18761 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18762 +}
18763 +"
18764 +        ;;
18765 +
18766 +    avr32elf_uc3b[01]512revc)
18767 +        MEMORY="
18768 +MEMORY
18769 +{
18770 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18771 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x17FFC
18772 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18773 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18774 +}
18775 +"
18776 +         PADDING="
18777 +  .padding : {
18778 +  QUAD(0)
18779 +  QUAD(0)
18780 +  QUAD(0)
18781 +  QUAD(0)
18782 +  } >FLASH AT>FLASH
18783 +"
18784 +        ;;
18785 +
18786 +    avr32elf_uc3b[01]512)
18787 +        MEMORY="
18788 +MEMORY
18789 +{
18790 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 512K
18791 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x17FFC
18792 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18793 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18794 +}
18795 +"
18796 +        ;;
18797 +
18798 +    avr32elf_uc3b[01]256*)
18799 +        MEMORY="
18800 +MEMORY
18801 +{
18802 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18803 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
18804 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18805 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18806 +}
18807 +"
18808 +        ;;
18809 +
18810 +    avr32elf_uc3[ab][012]128*)
18811 +        MEMORY="
18812 +MEMORY
18813 +{
18814 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
18815 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x7FFC
18816 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18817 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18818 +}
18819 +"
18820 +        ;;
18821 +
18822 +    avr32elf_uc3b[0123]64*)
18823 +        MEMORY="
18824 +MEMORY
18825 +{
18826 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18827 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18828 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18829 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18830 +}
18831 +"
18832 +        ;;
18833 +
18834 +    avr32elf_uc3a3256*)
18835 +        MEMORY="
18836 +MEMORY
18837 +{
18838 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 256K
18839 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18840 +    HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18841 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18842 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18843 +}
18844 +"
18845 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18846 +  .hsbsram       : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18847 +"
18848 +
18849 +        ;;
18850 +
18851 +    avr32elf_uc3a3128*)
18852 +        MEMORY="
18853 +MEMORY
18854 +{
18855 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 128K
18856 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18857 +    HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18858 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18859 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18860 +}
18861 +"
18862 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18863 +  .hsbsram       : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18864 +"
18865 +        ;;
18866 +
18867 +    avr32elf_uc3a364*)
18868 +        MEMORY="
18869 +MEMORY
18870 +{
18871 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18872 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
18873 +    HSBSRAM (wxa!ri) : ORIGIN = 0xFF000000, LENGTH = 64K
18874 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18875 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18876 +}
18877 +"
18878 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18879 +  .hsbsram       : { *(.hsbsram .hsbsram.*) } >HSBSRAM AT>FLASH :FLASH
18880 +"
18881 +        ;;
18882 +
18883 +
18884 +    avr32elf_uc3l[0123]64*)
18885 +        MEMORY="
18886 +MEMORY
18887 +{
18888 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 64K
18889 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18890 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18891 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18892 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18893 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18894 +}
18895 +"
18896 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18897 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18898 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18899 +"
18900 +        ;;
18901 +
18902 +    avr32elf_uc3l[0123]32*)
18903 +        MEMORY="
18904 +MEMORY
18905 +{
18906 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 32K
18907 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x3FFC
18908 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18909 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18910 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18911 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18912 +}
18913 +"
18914 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18915 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18916 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18917 +"
18918 +        ;;
18919 +
18920 +    avr32elf_uc3l[0123]16*)
18921 +        MEMORY="
18922 +MEMORY
18923 +{
18924 +    FLASH (rxai!w) : ORIGIN = 0x80000000, LENGTH = 16K
18925 +    CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0x1FFC
18926 +    USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
18927 +    FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
18928 +    FLASHVAULT_FLASH_SIZE (r) : ORIGIN = 0x80800400, LENGTH = 8
18929 +    FLASHVAULT_RAM_SIZE (r) : ORIGIN = 0x80800408, LENGTH = 8
18930 +}
18931 +"
18932 +        OTHER_SECTIONS="${OTHER_SECTIONS}
18933 +  .flashvault_flash_size : { KEEP(*(.flashvault_flash_size .flashvault_flash_size.*)) } > FLASHVAULT_FLASH_SIZE
18934 +  .flashvault_ram_size   : { KEEP(*(.flashvault_ram_size .flashvault_ram_size.*)) } > FLASHVAULT_RAM_SIZE
18935 +"
18936 +        ;;
18937 +
18938 +
18939 +    esac
18940 +    ;;
18941 +
18942 +esac
18943 --- /dev/null
18944 +++ b/ld/emulparams/avr32linux.sh
18945 @@ -0,0 +1,14 @@
18946 +ARCH=avr32
18947 +SCRIPT_NAME=elf
18948 +TEMPLATE_NAME=elf32
18949 +EXTRA_EM_FILE=avr32elf
18950 +OUTPUT_FORMAT="elf32-avr32"
18951 +GENERATE_SHLIB_SCRIPT=yes
18952 +MAXPAGESIZE=0x1000
18953 +TEXT_START_ADDR=0x00001000
18954 +NOP=0xd703d703
18955 +
18956 +# This appears to place the GOT before the data section, which is
18957 +# essential for uClinux.  We don't use those .s* sections on AVR32
18958 +# anyway, so it shouldn't hurt for regular Linux either...
18959 +NO_SMALL_DATA=yes
18960 --- /dev/null
18961 +++ b/ld/emultempl/avr32elf.em
18962 @@ -0,0 +1,162 @@
18963 +# This shell script emits a C file. -*- C -*-
18964 +#   Copyright (C) 2007,2008,2009 Atmel Corporation
18965 +#
18966 +# This file is part of GLD, the Gnu Linker.
18967 +#
18968 +# This program is free software; you can redistribute it and/or modify
18969 +# it under the terms of the GNU General Public License as published by
18970 +# the Free Software Foundation; either version 2 of the License, or
18971 +# (at your option) any later version.
18972 +#
18973 +# This program is distributed in the hope that it will be useful,
18974 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
18975 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18976 +# GNU General Public License for more details.
18977 +#
18978 +# You should have received a copy of the GNU General Public License
18979 +# along with this program; if not, write to the Free Software
18980 +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
18981 +#
18982 +
18983 +# This file is sourced from elf32.em, and defines extra avr32-elf
18984 +# specific routines.
18985 +#
18986 +
18987 +# Generate linker script for writable rodata
18988 +LD_FLAG=rodata-writable
18989 +DATA_ALIGNMENT=${DATA_ALIGNMENT_}
18990 +RELOCATING=" "
18991 +WRITABLE_RODATA=" "
18992 +( echo "/* Linker script for writable rodata */"
18993 +  . ${CUSTOMIZER_SCRIPT} ${EMULATION_NAME}
18994 +  . ${srcdir}/scripttempl/${SCRIPT_NAME}.sc
18995 +) | sed -e '/^ *$/d;s/[        ]*$//' > ldscripts/${EMULATION_NAME}.xwr
18996 +
18997 +
18998 +cat >> e${EMULATION_NAME}.c <<EOF
18999 +
19000 +#include "libbfd.h"
19001 +#include "elf32-avr32.h"
19002 +
19003 +/* Whether to allow direct references (sub or mov) to SEC_DATA and
19004 +   !SEC_CONTENTS sections when optimizing.  Not enabled by default
19005 +   since it might cause link errors.  */
19006 +static int direct_data_refs = 0;
19007 +
19008 +static void avr32_elf_after_open (void)
19009 +{
19010 +  bfd_elf32_avr32_set_options (&link_info, direct_data_refs);
19011 +  gld${EMULATION_NAME}_after_open ();
19012 +}
19013 +
19014 +static int rodata_writable = 0;
19015 +
19016 +static int stack_size = 0x1000;
19017 +
19018 +static void avr32_elf_set_symbols (void)
19019 +{
19020 +  /* Glue the assignments into the abs section.  */
19021 +  lang_statement_list_type *save = stat_ptr;
19022 +
19023 +
19024 +  stat_ptr = &(abs_output_section->children);
19025 +
19026 +  lang_add_assignment (exp_assop ('=', "_stack_size",
19027 +                                  exp_intop (stack_size)));
19028 +
19029 +  stat_ptr = save;
19030 +}
19031 +
19032 +static char * gld${EMULATION_NAME}_get_script (int *isfile);
19033 +
19034 +static char * avr32_elf_get_script (int *isfile)
19035 +{
19036 +  if ( rodata_writable )
19037 +    {
19038 +EOF
19039 +if test -n "$COMPILE_IN"
19040 +then
19041 +# Scripts compiled in.
19042 +
19043 +# sed commands to quote an ld script as a C string.
19044 +sc="-f stringify.sed"
19045 +
19046 +cat >>e${EMULATION_NAME}.c <<EOF
19047 +      *isfile = 0;
19048 +      return
19049 +EOF
19050 +sed $sc ldscripts/${EMULATION_NAME}.xwr                        >> e${EMULATION_NAME}.c
19051 +echo  ';'                                              >> e${EMULATION_NAME}.c
19052 +else
19053 +# Scripts read from the filesystem.
19054 +
19055 +cat >>e${EMULATION_NAME}.c <<EOF
19056 +      *isfile = 1;
19057 +      return "ldscripts/${EMULATION_NAME}.xwr";
19058 +EOF
19059 +fi
19060 +
19061 +cat >>e${EMULATION_NAME}.c <<EOF
19062 +    }
19063 +  return gld${EMULATION_NAME}_get_script (isfile);
19064 +}
19065 +
19066 +
19067 +EOF
19068 +
19069 +# Define some shell vars to insert bits of code into the standard elf
19070 +# parse_args and list_options functions.
19071 +#
19072 +PARSE_AND_LIST_PROLOGUE='
19073 +#define OPTION_DIRECT_DATA             300
19074 +#define OPTION_NO_DIRECT_DATA          301
19075 +#define OPTION_RODATA_WRITABLE         302
19076 +#define OPTION_NO_RODATA_WRITABLE      303
19077 +#define OPTION_STACK                   304
19078 +'
19079 +
19080 +PARSE_AND_LIST_LONGOPTS='
19081 +  { "direct-data", no_argument, NULL, OPTION_DIRECT_DATA },
19082 +  { "no-direct-data", no_argument, NULL, OPTION_NO_DIRECT_DATA },
19083 +  { "rodata-writable", no_argument, NULL, OPTION_RODATA_WRITABLE },
19084 +  { "no-rodata-writable", no_argument, NULL, OPTION_NO_RODATA_WRITABLE },
19085 +  { "stack", required_argument, NULL, OPTION_STACK },
19086 +'
19087 +
19088 +PARSE_AND_LIST_OPTIONS='
19089 +  fprintf (file, _("  --direct-data\t\tAllow direct data references when optimizing\n"));
19090 +  fprintf (file, _("  --no-direct-data\tDo not allow direct data references when optimizing\n"));
19091 +  fprintf (file, _("  --rodata-writable\tPut read-only data in writable data section\n"));
19092 +  fprintf (file, _("  --no-rodata-writable\tDo not put read-only data in writable data section\n"));
19093 +  fprintf (file, _("  --stack <size>\tSet the initial size of the stack\n"));
19094 +'
19095 +
19096 +PARSE_AND_LIST_ARGS_CASES='
19097 +    case OPTION_DIRECT_DATA:
19098 +      direct_data_refs = 1;
19099 +      break;
19100 +    case OPTION_NO_DIRECT_DATA:
19101 +      direct_data_refs = 0;
19102 +      break;
19103 +    case OPTION_RODATA_WRITABLE:
19104 +      rodata_writable = 1;
19105 +      break;
19106 +    case OPTION_NO_RODATA_WRITABLE:
19107 +      rodata_writable = 0;
19108 +      break;
19109 +    case OPTION_STACK:
19110 +     {
19111 +      char *end;
19112 +      stack_size = strtoul (optarg, &end, 0);
19113 +      if (end == optarg)
19114 +        einfo (_("%P%F: invalid hex number for parameter '%s'\n"), optarg);
19115 +      optarg = end;
19116 +      break;
19117 +     }
19118 +'
19119 +
19120 +# Replace some of the standard ELF functions with our own versions.
19121 +#
19122 +LDEMUL_AFTER_OPEN=avr32_elf_after_open
19123 +LDEMUL_GET_SCRIPT=avr32_elf_get_script
19124 +LDEMUL_SET_SYMBOLS=avr32_elf_set_symbols
19125 --- a/ld/Makefile.am
19126 +++ b/ld/Makefile.am
19127 @@ -163,6 +163,53 @@ ALL_EMULATION_SOURCES = \
19128         eavr5.c \
19129         eavr51.c \
19130         eavr6.c \
19131 +       eavr32elf_ap7000.c \
19132 +       eavr32elf_ap7001.c \
19133 +       eavr32elf_ap7002.c \
19134 +       eavr32elf_ap7200.c \
19135 +       eavr32elf_uc3a0128.c \
19136 +       eavr32elf_uc3a0256.c \
19137 +       eavr32elf_uc3a0512.c \
19138 +       eavr32elf_uc3a0512es.c \
19139 +       eavr32elf_uc3a1128.c \
19140 +       eavr32elf_uc3a1256.c \
19141 +       eavr32elf_uc3a1512es.c \
19142 +       eavr32elf_uc3a1512.c \
19143 +       eavr32elf_uc3a364.c \
19144 +       eavr32elf_uc3a364s.c \
19145 +       eavr32elf_uc3a3128.c \
19146 +       eavr32elf_uc3a3128s.c \
19147 +       eavr32elf_uc3a3256.c \
19148 +       eavr32elf_uc3a3256s.c \
19149 +       eavr32elf_uc3b064.c \
19150 +       eavr32elf_uc3b0128.c \
19151 +       eavr32elf_uc3b0256es.c \
19152 +       eavr32elf_uc3b0256.c \
19153 +       eavr32elf_uc3b0512.c \
19154 +       eavr32elf_uc3b0512revc.c \
19155 +       eavr32elf_uc3b164.c \
19156 +       eavr32elf_uc3b1128.c \
19157 +       eavr32elf_uc3b1256es.c \
19158 +       eavr32elf_uc3b1256.c \
19159 +       eavr32elf_uc3b1512.c \
19160 +       eavr32elf_uc3b1512revc.c \
19161 +       eavr32elf_uc3c064c.c \
19162 +       eavr32elf_uc3c0128c.c \
19163 +       eavr32elf_uc3c0256c.c \
19164 +       eavr32elf_uc3c0512crevc.c \
19165 +       eavr32elf_uc3c164c.c \
19166 +       eavr32elf_uc3c1128c.c \
19167 +       eavr32elf_uc3c1256c.c \
19168 +       eavr32elf_uc3c1512crevc.c \
19169 +       eavr32elf_uc3c264c.c \
19170 +       eavr32elf_uc3c2128c.c \
19171 +       eavr32elf_uc3c2256c.c \
19172 +       eavr32elf_uc3c2512crevc.c \
19173 +       eavr32elf_uc3l064.c \
19174 +       eavr32elf_uc3l032.c \
19175 +       eavr32elf_uc3l016.c \
19176 +       eavr32elf_uc3l064revb.c \
19177 +       eavr32linux.c \
19178         ecoff_i860.c \
19179         ecoff_sparc.c \
19180         ecrisaout.c \
19181 @@ -766,6 +813,214 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(
19182    $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
19183    ${GEN_DEPENDS}
19184         ${GENSCRIPTS} avr6 "$(tdir_avr2)"
19185 +eavr32elf_ap7000.c: $(srcdir)/emulparams/avr32elf.sh \
19186 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19187 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19188 +       ${GENSCRIPTS} avr32elf_ap7000 "$(tdir_avr32)" avr32elf
19189 +eavr32elf_ap7001.c: $(srcdir)/emulparams/avr32elf.sh \
19190 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19191 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19192 +       ${GENSCRIPTS} avr32elf_ap7001 "$(tdir_avr32)" avr32elf
19193 +eavr32elf_ap7002.c: $(srcdir)/emulparams/avr32elf.sh \
19194 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19195 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19196 +       ${GENSCRIPTS} avr32elf_ap7002 "$(tdir_avr32)" avr32elf
19197 +eavr32elf_ap7200.c: $(srcdir)/emulparams/avr32elf.sh \
19198 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19199 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19200 +       ${GENSCRIPTS} avr32elf_ap7200 "$(tdir_avr32)" avr32elf
19201 +eavr32elf_uc3a0128.c: $(srcdir)/emulparams/avr32elf.sh \
19202 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19203 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19204 +       ${GENSCRIPTS} avr32elf_uc3a0128 "$(tdir_avr32)" avr32elf
19205 +eavr32elf_uc3a0256.c: $(srcdir)/emulparams/avr32elf.sh \
19206 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19207 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19208 +       ${GENSCRIPTS} avr32elf_uc3a0256 "$(tdir_avr32)" avr32elf
19209 +eavr32elf_uc3a0512.c: $(srcdir)/emulparams/avr32elf.sh \
19210 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19211 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19212 +       ${GENSCRIPTS} avr32elf_uc3a0512 "$(tdir_avr32)" avr32elf
19213 +eavr32elf_uc3a0512es.c: $(srcdir)/emulparams/avr32elf.sh \
19214 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19215 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19216 +       ${GENSCRIPTS} avr32elf_uc3a0512es "$(tdir_avr32)" avr32elf
19217 +eavr32elf_uc3a1128.c: $(srcdir)/emulparams/avr32elf.sh \
19218 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19219 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19220 +       ${GENSCRIPTS} avr32elf_uc3a1128 "$(tdir_avr32)" avr32elf
19221 +eavr32elf_uc3a1256.c: $(srcdir)/emulparams/avr32elf.sh \
19222 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19223 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19224 +       ${GENSCRIPTS} avr32elf_uc3a1256 "$(tdir_avr32)" avr32elf
19225 +eavr32elf_uc3a1512.c: $(srcdir)/emulparams/avr32elf.sh \
19226 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19227 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19228 +       ${GENSCRIPTS} avr32elf_uc3a1512 "$(tdir_avr32)" avr32elf
19229 +eavr32elf_uc3a1512es.c: $(srcdir)/emulparams/avr32elf.sh \
19230 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19231 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19232 +       ${GENSCRIPTS} avr32elf_uc3a1512es "$(tdir_avr32)" avr32elf
19233 +eavr32elf_uc3a364.c: $(srcdir)/emulparams/avr32elf.sh \
19234 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19235 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19236 +       ${GENSCRIPTS} avr32elf_uc3a364 "$(tdir_avr32)" avr32elf
19237 +eavr32elf_uc3a364s.c: $(srcdir)/emulparams/avr32elf.sh \
19238 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19239 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19240 +       ${GENSCRIPTS} avr32elf_uc3a364s "$(tdir_avr32)" avr32elf
19241 +eavr32elf_uc3a3128.c: $(srcdir)/emulparams/avr32elf.sh \
19242 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19243 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19244 +       ${GENSCRIPTS} avr32elf_uc3a3128 "$(tdir_avr32)" avr32elf
19245 +eavr32elf_uc3a3128s.c: $(srcdir)/emulparams/avr32elf.sh \
19246 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19247 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19248 +       ${GENSCRIPTS} avr32elf_uc3a3128s "$(tdir_avr32)" avr32elf
19249 +eavr32elf_uc3a3256.c: $(srcdir)/emulparams/avr32elf.sh \
19250 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19251 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19252 +       ${GENSCRIPTS} avr32elf_uc3a3256 "$(tdir_avr32)" avr32elf
19253 +eavr32elf_uc3a3256s.c: $(srcdir)/emulparams/avr32elf.sh \
19254 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19255 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19256 +       ${GENSCRIPTS} avr32elf_uc3a3256s "$(tdir_avr32)" avr32elf
19257 +eavr32elf_uc3b064.c: $(srcdir)/emulparams/avr32elf.sh \
19258 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19259 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19260 +       ${GENSCRIPTS} avr32elf_uc3b064 "$(tdir_avr32)" avr32elf
19261 +eavr32elf_uc3b0128.c: $(srcdir)/emulparams/avr32elf.sh \
19262 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19263 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19264 +       ${GENSCRIPTS} avr32elf_uc3b0128 "$(tdir_avr32)" avr32elf
19265 +eavr32elf_uc3b0256.c: $(srcdir)/emulparams/avr32elf.sh \
19266 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19267 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19268 +       ${GENSCRIPTS} avr32elf_uc3b0256 "$(tdir_avr32)" avr32elf
19269 +eavr32elf_uc3b0256es.c: $(srcdir)/emulparams/avr32elf.sh \
19270 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19271 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19272 +       ${GENSCRIPTS} avr32elf_uc3b0256es "$(tdir_avr32)" avr32elf
19273 +eavr32elf_uc3b0512.c: $(srcdir)/emulparams/avr32elf.sh \
19274 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19275 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19276 +       ${GENSCRIPTS} avr32elf_uc3b0512 "$(tdir_avr32)" avr32elf
19277 +eavr32elf_uc3b0512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19278 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19279 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19280 +       ${GENSCRIPTS} avr32elf_uc3b0512revc "$(tdir_avr32)" avr32elf
19281 +eavr32elf_uc3b164.c: $(srcdir)/emulparams/avr32elf.sh \
19282 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19283 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19284 +       ${GENSCRIPTS} avr32elf_uc3b164 "$(tdir_avr32)" avr32elf
19285 +eavr32elf_uc3b1128.c: $(srcdir)/emulparams/avr32elf.sh \
19286 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19287 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19288 +       ${GENSCRIPTS} avr32elf_uc3b1128 "$(tdir_avr32)" avr32elf
19289 +eavr32elf_uc3b1256.c: $(srcdir)/emulparams/avr32elf.sh \
19290 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19291 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19292 +       ${GENSCRIPTS} avr32elf_uc3b1256 "$(tdir_avr32)" avr32elf
19293 +eavr32elf_uc3b1256es.c: $(srcdir)/emulparams/avr32elf.sh \
19294 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19295 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19296 +       ${GENSCRIPTS} avr32elf_uc3b1256es "$(tdir_avr32)" avr32elf
19297 +eavr32elf_uc3b1512.c: $(srcdir)/emulparams/avr32elf.sh \
19298 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19299 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19300 +       ${GENSCRIPTS} avr32elf_uc3b1512 "$(tdir_avr32)" avr32elf
19301 +eavr32elf_uc3b1512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19302 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19303 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19304 +       ${GENSCRIPTS} avr32elf_uc3b1512revc "$(tdir_avr32)" avr32elf
19305 +eavr32elf_uc3c0512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19306 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19307 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19308 +       ${GENSCRIPTS} avr32elf_uc3c0512crevc "$(tdir_avr32)" avr32elf
19309 +eavr32elf_uc3c1512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19310 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19311 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19312 +       ${GENSCRIPTS} avr32elf_uc3c1512crevc "$(tdir_avr32)" avr32elf
19313 +eavr32elf_uc3c2512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19314 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19315 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19316 +       ${GENSCRIPTS} avr32elf_uc3c2512crevc "$(tdir_avr32)" avr32elf
19317 +eavr32elf_atuc3l0256.c: $(srcdir)/emulparams/avr32elf.sh \
19318 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19319 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19320 +       ${GENSCRIPTS} avr32elf_atuc3l0256 "$(tdir_avr32)" avr32elf
19321 +eavr32elf_mxt768e.c: $(srcdir)/emulparams/avr32elf.sh \
19322 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19323 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19324 +       ${GENSCRIPTS} avr32elf_mxt768e "$(tdir_avr32)" avr32elf
19325 +eavr32elf_uc3l064.c: $(srcdir)/emulparams/avr32elf.sh \
19326 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19327 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19328 +       ${GENSCRIPTS} avr32elf_uc3l064 "$(tdir_avr32)" avr32elf
19329 +eavr32elf_uc3l032.c: $(srcdir)/emulparams/avr32elf.sh \
19330 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19331 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19332 +       ${GENSCRIPTS} avr32elf_uc3l032 "$(tdir_avr32)" avr32elf
19333 +eavr32elf_uc3l016.c: $(srcdir)/emulparams/avr32elf.sh \
19334 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19335 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19336 +       ${GENSCRIPTS} avr32elf_uc3l016 "$(tdir_avr32)" avr32elf
19337 +eavr32elf_uc3l064revb.c: $(srcdir)/emulparams/avr32elf.sh \
19338 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19339 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19340 +       ${GENSCRIPTS} avr32elf_uc3l064revb "$(tdir_avr32)" avr32elf
19341 +eavr32elf_uc3c064c.c: $(srcdir)/emulparams/avr32elf.sh \
19342 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19343 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19344 +       ${GENSCRIPTS} avr32elf_uc3c064c "$(tdir_avr32)" avr32elf
19345 +eavr32elf_uc3c0128c.c: $(srcdir)/emulparams/avr32elf.sh \
19346 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19347 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19348 +       ${GENSCRIPTS} avr32elf_uc3c0128c "$(tdir_avr32)" avr32elf
19349 +eavr32elf_uc3c0256c.c: $(srcdir)/emulparams/avr32elf.sh \
19350 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19351 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19352 +       ${GENSCRIPTS} avr32elf_uc3c0256c "$(tdir_avr32)" avr32elf
19353 +eavr32elf_uc3c0512c.c: $(srcdir)/emulparams/avr32elf.sh \
19354 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19355 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19356 +       ${GENSCRIPTS} avr32elf_uc3c0512c "$(tdir_avr32)" avr32elf
19357 +eavr32elf_uc3c164c.c: $(srcdir)/emulparams/avr32elf.sh \
19358 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19359 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19360 +       ${GENSCRIPTS} avr32elf_uc3c164c "$(tdir_avr32)" avr32elf
19361 +eavr32elf_uc3c1128c.c: $(srcdir)/emulparams/avr32elf.sh \
19362 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19363 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19364 +       ${GENSCRIPTS} avr32elf_uc3c1128c "$(tdir_avr32)" avr32elf
19365 +eavr32elf_uc3c1256c.c: $(srcdir)/emulparams/avr32elf.sh \
19366 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19367 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19368 +       ${GENSCRIPTS} avr32elf_uc3c1256c "$(tdir_avr32)" avr32elf
19369 +eavr32elf_uc3c1512c.c: $(srcdir)/emulparams/avr32elf.sh \
19370 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19371 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19372 +       ${GENSCRIPTS} avr32elf_uc3c1512c "$(tdir_avr32)" avr32elf
19373 +eavr32elf_uc3c264c.c: $(srcdir)/emulparams/avr32elf.sh \
19374 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19375 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19376 +       ${GENSCRIPTS} avr32elf_uc3c264c "$(tdir_avr32)" avr32elf
19377 +eavr32elf_uc3c2128c.c: $(srcdir)/emulparams/avr32elf.sh \
19378 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19379 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19380 +       ${GENSCRIPTS} avr32elf_uc3c2128c "$(tdir_avr32)" avr32elf
19381 +eavr32elf_uc3c2256c.c: $(srcdir)/emulparams/avr32elf.sh \
19382 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19383 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19384 +       ${GENSCRIPTS} avr32elf_uc3c2256c "$(tdir_avr32)" avr32elf
19385 +eavr32elf_uc3c2512c.c: $(srcdir)/emulparams/avr32elf.sh \
19386 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19387 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19388 +       ${GENSCRIPTS} avr32elf_uc3c2512c "$(tdir_avr32)" avr32elf
19389 +eavr32linux.c: $(srcdir)/emulparams/avr32linux.sh \
19390 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19391 +  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
19392 +       ${GENSCRIPTS} avr32linux "$(tdir_avr32)"
19393  ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
19394    $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
19395         ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
19396 @@ -2059,7 +2314,9 @@ install-exec-local: ld-new$(EXEEXT) inst
19397           fi; \
19398         fi
19399
19400 -install-data-local:
19401 +# We want install to imply install-info as per GNU standards, despite the
19402 +# cygnus option.
19403 +install-data-local: install-info
19404         $(mkinstalldirs) $(DESTDIR)$(scriptdir)/ldscripts
19405         for f in ldscripts/*; do \
19406           $(INSTALL_DATA) $$f $(DESTDIR)$(scriptdir)/$$f ; \
19407 --- a/ld/Makefile.in
19408 +++ b/ld/Makefile.in
19409 @@ -468,6 +468,53 @@ ALL_EMULATION_SOURCES = \
19410         eavr5.c \
19411         eavr51.c \
19412         eavr6.c \
19413 +       eavr32elf_ap7000.c \
19414 +       eavr32elf_ap7001.c \
19415 +       eavr32elf_ap7002.c \
19416 +       eavr32elf_ap7200.c \
19417 +       eavr32elf_uc3a0128.c \
19418 +       eavr32elf_uc3a0256.c \
19419 +       eavr32elf_uc3a0512.c \
19420 +       eavr32elf_uc3a0512es.c \
19421 +       eavr32elf_uc3a1128.c \
19422 +       eavr32elf_uc3a1256.c \
19423 +       eavr32elf_uc3a1512es.c \
19424 +       eavr32elf_uc3a1512.c \
19425 +       eavr32elf_uc3a364.c \
19426 +       eavr32elf_uc3a364s.c \
19427 +       eavr32elf_uc3a3128.c \
19428 +       eavr32elf_uc3a3128s.c \
19429 +       eavr32elf_uc3a3256.c \
19430 +       eavr32elf_uc3a3256s.c \
19431 +       eavr32elf_uc3b064.c \
19432 +       eavr32elf_uc3b0128.c \
19433 +       eavr32elf_uc3b0256es.c \
19434 +       eavr32elf_uc3b0256.c \
19435 +       eavr32elf_uc3b0512.c \
19436 +       eavr32elf_uc3b0512revc.c \
19437 +       eavr32elf_uc3b164.c \
19438 +       eavr32elf_uc3b1128.c \
19439 +       eavr32elf_uc3b1256es.c \
19440 +       eavr32elf_uc3b1256.c \
19441 +       eavr32elf_uc3b1512.c \
19442 +       eavr32elf_uc3b1512revc.c \
19443 +       eavr32elf_uc3c064c.c \
19444 +       eavr32elf_uc3c0128c.c \
19445 +       eavr32elf_uc3c0256c.c \
19446 +       eavr32elf_uc3c0512crevc.c \
19447 +       eavr32elf_uc3c164c.c \
19448 +       eavr32elf_uc3c1128c.c \
19449 +       eavr32elf_uc3c1256c.c \
19450 +       eavr32elf_uc3c1512crevc.c \
19451 +       eavr32elf_uc3c264c.c \
19452 +       eavr32elf_uc3c2128c.c \
19453 +       eavr32elf_uc3c2256c.c \
19454 +       eavr32elf_uc3c2512crevc.c \
19455 +       eavr32elf_uc3l064.c \
19456 +       eavr32elf_uc3l032.c \
19457 +       eavr32elf_uc3l016.c \
19458 +       eavr32elf_uc3l064revb.c \
19459 +       eavr32linux.c \
19460         ecoff_i860.c \
19461         ecoff_sparc.c \
19462         ecrisaout.c \
19463 @@ -2201,6 +2248,194 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(
19464    $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
19465    ${GEN_DEPENDS}
19466         ${GENSCRIPTS} avr6 "$(tdir_avr2)"
19467 +eavr32elf_ap7000.c: $(srcdir)/emulparams/avr32elf.sh \
19468 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19469 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19470 +       ${GENSCRIPTS} avr32elf_ap7000 "$(tdir_avr32)" avr32elf
19471 +eavr32elf_ap7001.c: $(srcdir)/emulparams/avr32elf.sh \
19472 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19473 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19474 +       ${GENSCRIPTS} avr32elf_ap7001 "$(tdir_avr32)" avr32elf
19475 +eavr32elf_ap7002.c: $(srcdir)/emulparams/avr32elf.sh \
19476 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19477 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19478 +       ${GENSCRIPTS} avr32elf_ap7002 "$(tdir_avr32)" avr32elf
19479 +eavr32elf_ap7200.c: $(srcdir)/emulparams/avr32elf.sh \
19480 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19481 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19482 +       ${GENSCRIPTS} avr32elf_ap7200 "$(tdir_avr32)" avr32elf
19483 +eavr32elf_uc3a0128.c: $(srcdir)/emulparams/avr32elf.sh \
19484 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19485 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19486 +       ${GENSCRIPTS} avr32elf_uc3a0128 "$(tdir_avr32)" avr32elf
19487 +eavr32elf_uc3a0256.c: $(srcdir)/emulparams/avr32elf.sh \
19488 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19489 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19490 +       ${GENSCRIPTS} avr32elf_uc3a0256 "$(tdir_avr32)" avr32elf
19491 +eavr32elf_uc3a0512.c: $(srcdir)/emulparams/avr32elf.sh \
19492 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19493 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19494 +       ${GENSCRIPTS} avr32elf_uc3a0512 "$(tdir_avr32)" avr32elf
19495 +eavr32elf_uc3a0512es.c: $(srcdir)/emulparams/avr32elf.sh \
19496 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19497 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19498 +       ${GENSCRIPTS} avr32elf_uc3a0512es "$(tdir_avr32)" avr32elf
19499 +eavr32elf_uc3a1128.c: $(srcdir)/emulparams/avr32elf.sh \
19500 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19501 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19502 +       ${GENSCRIPTS} avr32elf_uc3a1128 "$(tdir_avr32)" avr32elf
19503 +eavr32elf_uc3a1256.c: $(srcdir)/emulparams/avr32elf.sh \
19504 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19505 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19506 +       ${GENSCRIPTS} avr32elf_uc3a1256 "$(tdir_avr32)" avr32elf
19507 +eavr32elf_uc3a1512.c: $(srcdir)/emulparams/avr32elf.sh \
19508 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19509 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19510 +       ${GENSCRIPTS} avr32elf_uc3a1512 "$(tdir_avr32)" avr32elf
19511 +eavr32elf_uc3a1512es.c: $(srcdir)/emulparams/avr32elf.sh \
19512 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19513 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19514 +       ${GENSCRIPTS} avr32elf_uc3a1512es "$(tdir_avr32)" avr32elf
19515 +eavr32elf_uc3a364.c: $(srcdir)/emulparams/avr32elf.sh \
19516 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19517 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19518 +       ${GENSCRIPTS} avr32elf_uc3a364 "$(tdir_avr32)" avr32elf
19519 +eavr32elf_uc3a364s.c: $(srcdir)/emulparams/avr32elf.sh \
19520 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19521 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19522 +       ${GENSCRIPTS} avr32elf_uc3a364s "$(tdir_avr32)" avr32elf
19523 +eavr32elf_uc3a3128.c: $(srcdir)/emulparams/avr32elf.sh \
19524 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19525 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19526 +       ${GENSCRIPTS} avr32elf_uc3a3128 "$(tdir_avr32)" avr32elf
19527 +eavr32elf_uc3a3128s.c: $(srcdir)/emulparams/avr32elf.sh \
19528 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19529 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19530 +       ${GENSCRIPTS} avr32elf_uc3a3128s "$(tdir_avr32)" avr32elf
19531 +eavr32elf_uc3a3256.c: $(srcdir)/emulparams/avr32elf.sh \
19532 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19533 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19534 +       ${GENSCRIPTS} avr32elf_uc3a3256 "$(tdir_avr32)" avr32elf
19535 +eavr32elf_uc3a3256s.c: $(srcdir)/emulparams/avr32elf.sh \
19536 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19537 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19538 +       ${GENSCRIPTS} avr32elf_uc3a3256s "$(tdir_avr32)" avr32elf
19539 +eavr32elf_uc3b064.c: $(srcdir)/emulparams/avr32elf.sh \
19540 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19541 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19542 +       ${GENSCRIPTS} avr32elf_uc3b064 "$(tdir_avr32)" avr32elf
19543 +eavr32elf_uc3b0128.c: $(srcdir)/emulparams/avr32elf.sh \
19544 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19545 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19546 +       ${GENSCRIPTS} avr32elf_uc3b0128 "$(tdir_avr32)" avr32elf
19547 +eavr32elf_uc3b0256.c: $(srcdir)/emulparams/avr32elf.sh \
19548 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19549 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19550 +       ${GENSCRIPTS} avr32elf_uc3b0256 "$(tdir_avr32)" avr32elf
19551 +eavr32elf_uc3b0256es.c: $(srcdir)/emulparams/avr32elf.sh \
19552 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19553 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19554 +       ${GENSCRIPTS} avr32elf_uc3b0256es "$(tdir_avr32)" avr32elf
19555 +eavr32elf_uc3b0512.c: $(srcdir)/emulparams/avr32elf.sh \
19556 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19557 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19558 +       ${GENSCRIPTS} avr32elf_uc3b0512 "$(tdir_avr32)" avr32elf
19559 +eavr32elf_uc3b0512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19560 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19561 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19562 +       ${GENSCRIPTS} avr32elf_uc3b0512revc "$(tdir_avr32)" avr32elf
19563 +eavr32elf_uc3b164.c: $(srcdir)/emulparams/avr32elf.sh \
19564 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19565 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19566 +       ${GENSCRIPTS} avr32elf_uc3b164 "$(tdir_avr32)" avr32elf
19567 +eavr32elf_uc3b1128.c: $(srcdir)/emulparams/avr32elf.sh \
19568 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19569 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19570 +       ${GENSCRIPTS} avr32elf_uc3b1128 "$(tdir_avr32)" avr32elf
19571 +eavr32elf_uc3b1256.c: $(srcdir)/emulparams/avr32elf.sh \
19572 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19573 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19574 +       ${GENSCRIPTS} avr32elf_uc3b1256 "$(tdir_avr32)" avr32elf
19575 +eavr32elf_uc3b1256es.c: $(srcdir)/emulparams/avr32elf.sh \
19576 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19577 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19578 +       ${GENSCRIPTS} avr32elf_uc3b1256es "$(tdir_avr32)" avr32elf
19579 +eavr32elf_uc3b1512.c: $(srcdir)/emulparams/avr32elf.sh \
19580 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19581 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19582 +       ${GENSCRIPTS} avr32elf_uc3b1512 "$(tdir_avr32)" avr32elf
19583 +eavr32elf_uc3b1512revc.c: $(srcdir)/emulparams/avr32elf.sh \
19584 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19585 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19586 +       ${GENSCRIPTS} avr32elf_uc3b1512revc "$(tdir_avr32)" avr32elf
19587 +eavr32elf_uc3c064c.c: $(srcdir)/emulparams/avr32elf.sh \
19588 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19589 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19590 +       ${GENSCRIPTS} avr32elf_uc3c064c "$(tdir_avr32)" avr32elf
19591 +eavr32elf_uc3c0128c.c: $(srcdir)/emulparams/avr32elf.sh \
19592 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19593 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19594 +       ${GENSCRIPTS} avr32elf_uc3c0128c "$(tdir_avr32)" avr32elf
19595 +eavr32elf_uc3c0256c.c: $(srcdir)/emulparams/avr32elf.sh \
19596 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19597 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19598 +       ${GENSCRIPTS} avr32elf_uc3c0256c "$(tdir_avr32)" avr32elf
19599 +eavr32elf_uc3c0512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19600 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19601 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19602 +       ${GENSCRIPTS} avr32elf_uc3c0512crevc "$(tdir_avr32)" avr32elf
19603 +eavr32elf_uc3c164c.c: $(srcdir)/emulparams/avr32elf.sh \
19604 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19605 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19606 +       ${GENSCRIPTS} avr32elf_uc3c164c "$(tdir_avr32)" avr32elf
19607 +eavr32elf_uc3c1128c.c: $(srcdir)/emulparams/avr32elf.sh \
19608 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19609 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19610 +       ${GENSCRIPTS} avr32elf_uc3c1128c "$(tdir_avr32)" avr32elf
19611 +eavr32elf_uc3c1256c.c: $(srcdir)/emulparams/avr32elf.sh \
19612 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19613 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19614 +       ${GENSCRIPTS} avr32elf_uc3c1256c "$(tdir_avr32)" avr32elf
19615 +eavr32elf_uc3c1512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19616 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19617 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19618 +       ${GENSCRIPTS} avr32elf_uc3c1512crevc "$(tdir_avr32)" avr32elf
19619 +eavr32elf_uc3c264c.c: $(srcdir)/emulparams/avr32elf.sh \
19620 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19621 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19622 +       ${GENSCRIPTS} avr32elf_uc3c264c "$(tdir_avr32)" avr32elf
19623 +eavr32elf_uc3c2128c.c: $(srcdir)/emulparams/avr32elf.sh \
19624 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19625 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19626 +       ${GENSCRIPTS} avr32elf_uc3c2128c "$(tdir_avr32)" avr32elf
19627 +eavr32elf_uc3c2256c.c: $(srcdir)/emulparams/avr32elf.sh \
19628 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19629 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19630 +       ${GENSCRIPTS} avr32elf_uc3c2256c "$(tdir_avr32)" avr32elf
19631 +eavr32elf_uc3c2512crevc.c: $(srcdir)/emulparams/avr32elf.sh \
19632 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19633 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19634 +       ${GENSCRIPTS} avr32elf_uc3c2512crevc "$(tdir_avr32)" avr32elf
19635 +eavr32elf_uc3l064.c: $(srcdir)/emulparams/avr32elf.sh \
19636 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19637 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19638 +       ${GENSCRIPTS} avr32elf_uc3l064 "$(tdir_avr32)" avr32elf
19639 +eavr32elf_uc3l032.c: $(srcdir)/emulparams/avr32elf.sh \
19640 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19641 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19642 +       ${GENSCRIPTS} avr32elf_uc3l032 "$(tdir_avr32)" avr32elf
19643 +eavr32elf_uc3l016.c: $(srcdir)/emulparams/avr32elf.sh \
19644 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19645 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19646 +       ${GENSCRIPTS} avr32elf_uc3l016 "$(tdir_avr32)" avr32elf
19647 +eavr32elf_uc3l064revb.c: $(srcdir)/emulparams/avr32elf.sh \
19648 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19649 +  $(srcdir)/scripttempl/avr32.sc ${GEN_DEPENDS}
19650 +       ${GENSCRIPTS} avr32elf_uc3l064revb "$(tdir_avr32)" avr32elf
19651 +eavr32linux.c: $(srcdir)/emulparams/avr32linux.sh \
19652 +  $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/avr32elf.em \
19653 +  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
19654 +       ${GENSCRIPTS} avr32linux "$(tdir_avr32)"
19655  ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
19656    $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
19657         ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
19658 --- /dev/null
19659 +++ b/ld/scripttempl/avr32.sc
19660 @@ -0,0 +1,459 @@
19661 +#
19662 +# Unusual variables checked by this code:
19663 +#      NOP - four byte opcode for no-op (defaults to 0)
19664 +#      NO_SMALL_DATA - no .sbss/.sbss2/.sdata/.sdata2 sections if not
19665 +#              empty.
19666 +#      SMALL_DATA_CTOR - .ctors contains small data.
19667 +#      SMALL_DATA_DTOR - .dtors contains small data.
19668 +#      DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
19669 +#      INITIAL_READONLY_SECTIONS - at start of text segment
19670 +#      OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
19671 +#              (e.g., .PARISC.milli)
19672 +#      OTHER_TEXT_SECTIONS - these get put in .text when relocating
19673 +#      OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
19674 +#              (e.g., .PARISC.global)
19675 +#      OTHER_RELRO_SECTIONS - other than .data.rel.ro ...
19676 +#              (e.g. PPC32 .fixup, .got[12])
19677 +#      OTHER_BSS_SECTIONS - other than .bss .sbss ...
19678 +#      OTHER_SECTIONS - at the end
19679 +#      EXECUTABLE_SYMBOLS - symbols that must be defined for an
19680 +#              executable (e.g., _DYNAMIC_LINK)
19681 +#       TEXT_START_ADDR - the first byte of the text segment, after any
19682 +#               headers.
19683 +#       TEXT_BASE_ADDRESS - the first byte of the text segment.
19684 +#      TEXT_START_SYMBOLS - symbols that appear at the start of the
19685 +#              .text section.
19686 +#      DATA_START_SYMBOLS - symbols that appear at the start of the
19687 +#              .data section.
19688 +#      OTHER_GOT_SYMBOLS - symbols defined just before .got.
19689 +#      OTHER_GOT_SECTIONS - sections just after .got.
19690 +#      OTHER_SDATA_SECTIONS - sections just after .sdata.
19691 +#      OTHER_BSS_SYMBOLS - symbols that appear at the start of the
19692 +#              .bss section besides __bss_start.
19693 +#      DATA_PLT - .plt should be in data segment, not text segment.
19694 +#      PLT_BEFORE_GOT - .plt just before .got when .plt is in data segement.
19695 +#      BSS_PLT - .plt should be in bss segment
19696 +#      TEXT_DYNAMIC - .dynamic in text segment, not data segment.
19697 +#      EMBEDDED - whether this is for an embedded system.
19698 +#      SHLIB_TEXT_START_ADDR - if set, add to SIZEOF_HEADERS to set
19699 +#              start address of shared library.
19700 +#      INPUT_FILES - INPUT command of files to always include
19701 +#      WRITABLE_RODATA - if set, the .rodata section should be writable
19702 +#      INIT_START, INIT_END -  statements just before and just after
19703 +#      combination of .init sections.
19704 +#      FINI_START, FINI_END - statements just before and just after
19705 +#      combination of .fini sections.
19706 +#      STACK_ADDR - start of a .stack section.
19707 +#      OTHER_END_SYMBOLS - symbols to place right at the end of the script.
19708 +#      SEPARATE_GOTPLT - if set, .got.plt should be separate output section,
19709 +#              so that .got can be in the RELRO area.  It should be set to
19710 +#              the number of bytes in the beginning of .got.plt which can be
19711 +#              in the RELRO area as well.
19712 +#
19713 +# When adding sections, do note that the names of some sections are used
19714 +# when specifying the start address of the next.
19715 +#
19716 +
19717 +#  Many sections come in three flavours.  There is the 'real' section,
19718 +#  like ".data".  Then there are the per-procedure or per-variable
19719 +#  sections, generated by -ffunction-sections and -fdata-sections in GCC,
19720 +#  and useful for --gc-sections, which for a variable "foo" might be
19721 +#  ".data.foo".  Then there are the linkonce sections, for which the linker
19722 +#  eliminates duplicates, which are named like ".gnu.linkonce.d.foo".
19723 +#  The exact correspondences are:
19724 +#
19725 +#  Section     Linkonce section
19726 +#  .text       .gnu.linkonce.t.foo
19727 +#  .rodata     .gnu.linkonce.r.foo
19728 +#  .data       .gnu.linkonce.d.foo
19729 +#  .bss                .gnu.linkonce.b.foo
19730 +#  .sdata      .gnu.linkonce.s.foo
19731 +#  .sbss       .gnu.linkonce.sb.foo
19732 +#  .sdata2     .gnu.linkonce.s2.foo
19733 +#  .sbss2      .gnu.linkonce.sb2.foo
19734 +#  .debug_info .gnu.linkonce.wi.foo
19735 +#  .tdata      .gnu.linkonce.td.foo
19736 +#  .tbss       .gnu.linkonce.tb.foo
19737 +#
19738 +#  Each of these can also have corresponding .rel.* and .rela.* sections.
19739 +
19740 +test -z "$ENTRY" && ENTRY=_start
19741 +test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
19742 +test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
19743 +if [ -z "$MACHINE" ]; then OUTPUT_ARCH=${ARCH}; else OUTPUT_ARCH=${ARCH}:${MACHINE}; fi
19744 +test -z "${ELFSIZE}" && ELFSIZE=32
19745 +test -z "${ALIGNMENT}" && ALIGNMENT="${ELFSIZE} / 8"
19746 +test "$LD_FLAG" = "N" && DATA_ADDR=.
19747 +test -n "$CREATE_SHLIB$CREATE_PIE" && test -n "$SHLIB_DATA_ADDR" && COMMONPAGESIZE=""
19748 +test -z "$CREATE_SHLIB$CREATE_PIE" && test -n "$DATA_ADDR" && COMMONPAGESIZE=""
19749 +test -n "$RELRO_NOW" && unset SEPARATE_GOTPLT
19750 +if test -n "$RELOCATING"; then
19751 +  RO_REGION="${RO_VMA_REGION+ >}${RO_VMA_REGION}${RO_LMA_REGION+ AT>}${RO_LMA_REGION}"
19752 +  RW_REGION="${RW_VMA_REGION+ >}${RW_VMA_REGION}${RW_LMA_REGION+ AT>}${RW_LMA_REGION}"
19753 +  RW_BSS_REGION="${RW_VMA_REGION+ >}${RW_VMA_REGION}"
19754 +else
19755 +  RO_REGION=""
19756 +  RW_REGION=""
19757 +  RW_BSS_REGION=""
19758 +fi
19759 +INTERP=".interp       ${RELOCATING-0} : { *(.interp) }${RO_REGION}"
19760 +PLT=".plt          ${RELOCATING-0} : { *(.plt) }"
19761 +if test -z "$GOT"; then
19762 +  if test -z "$SEPARATE_GOTPLT"; then
19763 +    GOT=".got          ${RELOCATING-0} : { *(.got.plt) *(.got) }"
19764 +  else
19765 +    GOT=".got          ${RELOCATING-0} : { *(.got) }"
19766 +    GOTPLT="${RELOCATING+${DATA_SEGMENT_RELRO_GOTPLT_END}}
19767 +  .got.plt      ${RELOCATING-0} : { *(.got.plt) }"
19768 +  fi
19769 +fi
19770 +DALIGN=".dalign        : { . = ALIGN(${DATA_SEGMENT_ALIGN}); PROVIDE(_data_lma = .); }${RO_REGION}"
19771 +BALIGN=".balign        : { . = ALIGN(${BSS_ALIGNMENT}); _edata = .; }${RW_REGION}"
19772 +DYNAMIC=".dynamic      ${RELOCATING-0} : { *(.dynamic) }"
19773 +RODATA=".rodata       ${RELOCATING-0} : { *(.rodata${RELOCATING+ .rodata.* .gnu.linkonce.r.*}) }"
19774 +DATARELRO=".data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }${RW_REGION}"
19775 +STACKNOTE="/DISCARD/ : { *(.note.GNU-stack) }"
19776 +if test -z "${NO_SMALL_DATA}"; then
19777 +  SBSS=".sbss         ${RELOCATING-0} :
19778 +  {
19779 +    ${RELOCATING+PROVIDE (__sbss_start = .);}
19780 +    ${RELOCATING+PROVIDE (___sbss_start = .);}
19781 +    ${CREATE_SHLIB+*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)}
19782 +    *(.dynsbss)
19783 +    *(.sbss${RELOCATING+ .sbss.* .gnu.linkonce.sb.*})
19784 +    *(.scommon)
19785 +    ${RELOCATING+PROVIDE (__sbss_end = .);}
19786 +    ${RELOCATING+PROVIDE (___sbss_end = .);}
19787 +  }${RW_BSS_REGION}"
19788 +  SBSS2=".sbss2        ${RELOCATING-0} : { *(.sbss2${RELOCATING+ .sbss2.* .gnu.linkonce.sb2.*}) }${RW_REGION}"
19789 +  SDATA="/* We want the small data sections together, so single-instruction offsets
19790 +     can access them all, and initialized data all before uninitialized, so
19791 +     we can shorten the on-disk segment size.  */
19792 +  .sdata        ${RELOCATING-0} :
19793 +  {
19794 +    ${RELOCATING+${SDATA_START_SYMBOLS}}
19795 +    ${CREATE_SHLIB+*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)}
19796 +    *(.sdata${RELOCATING+ .sdata.* .gnu.linkonce.s.*})
19797 +  }${RW_REGION}"
19798 +  SDATA2=".sdata2       ${RELOCATING-0} : { *(.sdata2${RELOCATING+ .sdata2.* .gnu.linkonce.s2.*}) }${RW_REGION}"
19799 +  REL_SDATA=".rel.sdata    ${RELOCATING-0} : { *(.rel.sdata${RELOCATING+ .rel.sdata.* .rel.gnu.linkonce.s.*}) }${RO_REGION}
19800 +  .rela.sdata   ${RELOCATING-0} : { *(.rela.sdata${RELOCATING+ .rela.sdata.* .rela.gnu.linkonce.s.*}) }"
19801 +  REL_SBSS=".rel.sbss     ${RELOCATING-0} : { *(.rel.sbss${RELOCATING+ .rel.sbss.* .rel.gnu.linkonce.sb.*}) }${RO_REGION}
19802 +  .rela.sbss    ${RELOCATING-0} : { *(.rela.sbss${RELOCATING+ .rela.sbss.* .rela.gnu.linkonce.sb.*}) }${RO_REGION}"
19803 +  REL_SDATA2=".rel.sdata2   ${RELOCATING-0} : { *(.rel.sdata2${RELOCATING+ .rel.sdata2.* .rel.gnu.linkonce.s2.*}) }${RO_REGION}
19804 +  .rela.sdata2  ${RELOCATING-0} : { *(.rela.sdata2${RELOCATING+ .rela.sdata2.* .rela.gnu.linkonce.s2.*}) }${RO_REGION}"
19805 +  REL_SBSS2=".rel.sbss2    ${RELOCATING-0} : { *(.rel.sbss2${RELOCATING+ .rel.sbss2.* .rel.gnu.linkonce.sb2.*}) }${RO_REGION}
19806 +  .rela.sbss2   ${RELOCATING-0} : { *(.rela.sbss2${RELOCATING+ .rela.sbss2.* .rela.gnu.linkonce.sb2.*}) }${RO_REGION}"
19807 +else
19808 +  NO_SMALL_DATA=" "
19809 +fi
19810 +test -n "$SEPARATE_GOTPLT" && SEPARATE_GOTPLT=" "
19811 +CTOR=".ctors        ${CONSTRUCTING-0} :
19812 +  {
19813 +    ${CONSTRUCTING+${CTOR_START}}
19814 +    /* gcc uses crtbegin.o to find the start of
19815 +       the constructors, so we make sure it is
19816 +       first.  Because this is a wildcard, it
19817 +       doesn't matter if the user does not
19818 +       actually link against crtbegin.o; the
19819 +       linker won't look for a file to match a
19820 +       wildcard.  The wildcard also means that it
19821 +       doesn't matter which directory crtbegin.o
19822 +       is in.  */
19823 +
19824 +    KEEP (*crtbegin*.o(.ctors))
19825 +
19826 +    /* We don't want to include the .ctor section from
19827 +       from the crtend.o file until after the sorted ctors.
19828 +       The .ctor section from the crtend file contains the
19829 +       end of ctors marker and it must be last */
19830 +
19831 +    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .ctors))
19832 +    KEEP (*(SORT(.ctors.*)))
19833 +    KEEP (*(.ctors))
19834 +    ${CONSTRUCTING+${CTOR_END}}
19835 +  }"
19836 +DTOR=".dtors        ${CONSTRUCTING-0} :
19837 +  {
19838 +    ${CONSTRUCTING+${DTOR_START}}
19839 +    KEEP (*crtbegin*.o(.dtors))
19840 +    KEEP (*(EXCLUDE_FILE (*crtend*.o $OTHER_EXCLUDE_FILES) .dtors))
19841 +    KEEP (*(SORT(.dtors.*)))
19842 +    KEEP (*(.dtors))
19843 +    ${CONSTRUCTING+${DTOR_END}}
19844 +  }"
19845 +STACK=".stack        ${RELOCATING-0}${RELOCATING+${STACK_ADDR}} :
19846 +  {
19847 +    ${RELOCATING+_stack = .;}
19848 +    *(.stack)
19849 +    ${RELOCATING+${STACK_SIZE+. = ${STACK_SIZE};}}
19850 +    ${RELOCATING+_estack = .;}
19851 +  }${RW_BSS_REGION}"
19852 +
19853 +# if this is for an embedded system, don't add SIZEOF_HEADERS.
19854 +if [ -z "$EMBEDDED" ]; then
19855 +   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR} + SIZEOF_HEADERS"
19856 +else
19857 +   test -z "${TEXT_BASE_ADDRESS}" && TEXT_BASE_ADDRESS="${TEXT_START_ADDR}"
19858 +fi
19859 +
19860 +cat <<EOF
19861 +OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
19862 +             "${LITTLE_OUTPUT_FORMAT}")
19863 +OUTPUT_ARCH(${OUTPUT_ARCH})
19864 +ENTRY(${ENTRY})
19865 +
19866 +${RELOCATING+${LIB_SEARCH_DIRS}}
19867 +${RELOCATING+/* Do we need any of these for elf?
19868 +   __DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}}  */}
19869 +${RELOCATING+${EXECUTABLE_SYMBOLS}}
19870 +${RELOCATING+${INPUT_FILES}}
19871 +${RELOCATING- /* For some reason, the Solaris linker makes bad executables
19872 +  if gld -r is used and the intermediate file has sections starting
19873 +  at non-zero addresses.  Could be a Solaris ld bug, could be a GNU ld
19874 +  bug.  But for now assigning the zero vmas works.  */}
19875 +
19876 +${RELOCATING+${MEMORY}}
19877 +
19878 +SECTIONS
19879 +{
19880 +  /* Read-only sections, merged into text segment: */
19881 +  ${CREATE_SHLIB-${CREATE_PIE-${RELOCATING+PROVIDE (__executable_start = ${TEXT_START_ADDR}); . = ${TEXT_BASE_ADDRESS};}}}
19882 +  ${PADDING}
19883 +  ${CREATE_SHLIB+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
19884 +  ${CREATE_PIE+${RELOCATING+. = ${SHLIB_TEXT_START_ADDR:-0} + SIZEOF_HEADERS;}}
19885 +  ${CREATE_SHLIB-${INTERP}}
19886 +  ${INITIAL_READONLY_SECTIONS}
19887 +  ${TEXT_DYNAMIC+${DYNAMIC}${RO_REGION}}
19888 +  .hash         ${RELOCATING-0} : { *(.hash) }${RO_REGION}
19889 +  .dynsym       ${RELOCATING-0} : { *(.dynsym) }${RO_REGION}
19890 +  .dynstr       ${RELOCATING-0} : { *(.dynstr) }${RO_REGION}
19891 +  .gnu.version  ${RELOCATING-0} : { *(.gnu.version) }${RO_REGION}
19892 +  .gnu.version_d ${RELOCATING-0}: { *(.gnu.version_d) }${RO_REGION}
19893 +  .gnu.version_r ${RELOCATING-0}: { *(.gnu.version_r) }${RO_REGION}
19894 +
19895 +EOF
19896 +if [ "x$COMBRELOC" = x ]; then
19897 +  COMBRELOCCAT=cat
19898 +else
19899 +  COMBRELOCCAT="cat > $COMBRELOC"
19900 +fi
19901 +eval $COMBRELOCCAT <<EOF
19902 +  .rel.init     ${RELOCATING-0} : { *(.rel.init) }${RO_REGION}
19903 +  .rela.init    ${RELOCATING-0} : { *(.rela.init) }${RO_REGION}
19904 +  .rel.text     ${RELOCATING-0} : { *(.rel.text${RELOCATING+ .rel.text.* .rel.gnu.linkonce.t.*}) }${RO_REGION}
19905 +  .rela.text    ${RELOCATING-0} : { *(.rela.text${RELOCATING+ .rela.text.* .rela.gnu.linkonce.t.*}) }${RO_REGION}
19906 +  .rel.fini     ${RELOCATING-0} : { *(.rel.fini) }${RO_REGION}
19907 +  .rela.fini    ${RELOCATING-0} : { *(.rela.fini) }${RO_REGION}
19908 +  .rel.rodata   ${RELOCATING-0} : { *(.rel.rodata${RELOCATING+ .rel.rodata.* .rel.gnu.linkonce.r.*}) }${RO_REGION}
19909 +  .rela.rodata  ${RELOCATING-0} : { *(.rela.rodata${RELOCATING+ .rela.rodata.* .rela.gnu.linkonce.r.*}) }${RO_REGION}
19910 +  ${OTHER_READONLY_RELOC_SECTIONS}
19911 +  .rel.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }${RO_REGION}
19912 +  .rela.data.rel.ro ${RELOCATING-0} : { *(.rel.data.rel.ro${RELOCATING+*}) }${RO_REGION}
19913 +  .rel.data     ${RELOCATING-0} : { *(.rel.data${RELOCATING+ .rel.data.* .rel.gnu.linkonce.d.*}) }${RO_REGION}
19914 +  .rela.data    ${RELOCATING-0} : { *(.rela.data${RELOCATING+ .rela.data.* .rela.gnu.linkonce.d.*}) }${RO_REGION}
19915 +  .rel.tdata   ${RELOCATING-0} : { *(.rel.tdata${RELOCATING+ .rel.tdata.* .rel.gnu.linkonce.td.*}) }${RO_REGION}
19916 +  .rela.tdata  ${RELOCATING-0} : { *(.rela.tdata${RELOCATING+ .rela.tdata.* .rela.gnu.linkonce.td.*}) }${RO_REGION}
19917 +  .rel.tbss    ${RELOCATING-0} : { *(.rel.tbss${RELOCATING+ .rel.tbss.* .rel.gnu.linkonce.tb.*}) }${RO_REGION}
19918 +  .rela.tbss   ${RELOCATING-0} : { *(.rela.tbss${RELOCATING+ .rela.tbss.* .rela.gnu.linkonce.tb.*}) }${RO_REGION}
19919 +  .rel.ctors    ${RELOCATING-0} : { *(.rel.ctors) }${RO_REGION}
19920 +  .rela.ctors   ${RELOCATING-0} : { *(.rela.ctors) }${RO_REGION}
19921 +  .rel.dtors    ${RELOCATING-0} : { *(.rel.dtors) }${RO_REGION}
19922 +  .rela.dtors   ${RELOCATING-0} : { *(.rela.dtors) }${RO_REGION}
19923 +  .rel.got      ${RELOCATING-0} : { *(.rel.got) }${RO_REGION}
19924 +  .rela.got     ${RELOCATING-0} : { *(.rela.got) }${RO_REGION}
19925 +  ${OTHER_GOT_RELOC_SECTIONS}
19926 +  ${REL_SDATA}
19927 +  ${REL_SBSS}
19928 +  ${REL_SDATA2}
19929 +  ${REL_SBSS2}
19930 +  .rel.bss      ${RELOCATING-0} : { *(.rel.bss${RELOCATING+ .rel.bss.* .rel.gnu.linkonce.b.*}) }${RO_REGION}
19931 +  .rela.bss     ${RELOCATING-0} : { *(.rela.bss${RELOCATING+ .rela.bss.* .rela.gnu.linkonce.b.*}) }${RO_REGION}
19932 +EOF
19933 +if [ -n "$COMBRELOC" ]; then
19934 +cat <<EOF
19935 +  .rel.dyn      ${RELOCATING-0} :
19936 +    {
19937 +EOF
19938 +sed -e '/^[    ]*[{}][         ]*$/d;/:[       ]*$/d;/\.rela\./d;s/^.*: { *\(.*\)}$/      \1/' $COMBRELOC
19939 +cat <<EOF
19940 +    }${RO_REGION}
19941 +  .rela.dyn     ${RELOCATING-0} :
19942 +    {
19943 +EOF
19944 +sed -e '/^[    ]*[{}][         ]*$/d;/:[       ]*$/d;/\.rel\./d;s/^.*: { *\(.*\)}/      \1/' $COMBRELOC
19945 +cat <<EOF
19946 +    }${RO_REGION}
19947 +EOF
19948 +fi
19949 +cat <<EOF
19950 +  .rel.plt      ${RELOCATING-0} : { *(.rel.plt) }${RO_REGION}
19951 +  .rela.plt     ${RELOCATING-0} : { *(.rela.plt) }${RO_REGION}
19952 +  ${OTHER_PLT_RELOC_SECTIONS}
19953 +
19954 +  .init         ${RELOCATING-0} :
19955 +  {
19956 +    ${RELOCATING+${INIT_START}}
19957 +    KEEP (*(.init))
19958 +    ${RELOCATING+${INIT_END}}
19959 +  }${RO_REGION} =${NOP-0}
19960 +
19961 +  ${DATA_PLT-${BSS_PLT-${PLT}${RO_REGION}}}
19962 +  .text         ${RELOCATING-0} :
19963 +  {
19964 +    ${RELOCATING+${TEXT_START_SYMBOLS}}
19965 +    *(.text .stub${RELOCATING+ .text.* .gnu.linkonce.t.*})
19966 +    KEEP (*(.text.*personality*))
19967 +    /* .gnu.warning sections are handled specially by elf32.em.  */
19968 +    *(.gnu.warning)
19969 +    ${RELOCATING+${OTHER_TEXT_SECTIONS}}
19970 +  }${RO_REGION} =${NOP-0}
19971 +  .fini         ${RELOCATING-0} :
19972 +  {
19973 +    ${RELOCATING+${FINI_START}}
19974 +    KEEP (*(.fini))
19975 +    ${RELOCATING+${FINI_END}}
19976 +  }${RO_REGION} =${NOP-0}
19977 +  ${RELOCATING+PROVIDE (__etext = .);}
19978 +  ${RELOCATING+PROVIDE (_etext = .);}
19979 +  ${RELOCATING+PROVIDE (etext = .);}
19980 +  ${WRITABLE_RODATA-${RODATA}${RO_REGION}}
19981 +  .rodata1      ${RELOCATING-0} : { *(.rodata1) }${RO_REGION}
19982 +  ${CREATE_SHLIB-${SDATA2}}
19983 +  ${CREATE_SHLIB-${SBSS2}}
19984 +  ${OTHER_READONLY_SECTIONS}
19985 +  .eh_frame_hdr : { *(.eh_frame_hdr) }${RO_REGION}
19986 +  .eh_frame     ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.eh_frame)) }${RO_REGION}
19987 +  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }${RO_REGION}
19988 +
19989 +  ${RELOCATING+${DALIGN}}
19990 +  ${RELOCATING+PROVIDE (_data = ORIGIN(${RW_VMA_REGION}));}
19991 +  . = ORIGIN(${RW_VMA_REGION});
19992 +  /* Exception handling  */
19993 +  .eh_frame     ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.eh_frame)) }${RW_REGION}
19994 +  .gcc_except_table ${RELOCATING-0} : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }${RW_REGION}
19995 +
19996 +  /* Thread Local Storage sections  */
19997 +  .tdata       ${RELOCATING-0} : { *(.tdata${RELOCATING+ .tdata.* .gnu.linkonce.td.*}) }${RW_REGION}
19998 +  .tbss                ${RELOCATING-0} : { *(.tbss${RELOCATING+ .tbss.* .gnu.linkonce.tb.*})${RELOCATING+ *(.tcommon)} }${RW_BSS_REGION}
19999 +
20000 +  /* Ensure the __preinit_array_start label is properly aligned.  We
20001 +     could instead move the label definition inside the section, but
20002 +     the linker would then create the section even if it turns out to
20003 +     be empty, which isn't pretty.  */
20004 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_start = ALIGN(${ALIGNMENT}));}}
20005 +  .preinit_array   ${RELOCATING-0} : { KEEP (*(.preinit_array)) }${RW_REGION}
20006 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__preinit_array_end = .);}}
20007 +
20008 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_start = .);}}
20009 +  .init_array   ${RELOCATING-0} : { KEEP (*(.init_array)) }${RW_REGION}
20010 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__init_array_end = .);}}
20011 +
20012 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_start = .);}}
20013 +  .fini_array   ${RELOCATING-0} : { KEEP (*(.fini_array)) }${RW_REGION}
20014 +  ${RELOCATING+${CREATE_SHLIB-PROVIDE (__fini_array_end = .);}}
20015 +
20016 +  ${SMALL_DATA_CTOR-${RELOCATING+${CTOR}${RW_REGION}}}
20017 +  ${SMALL_DATA_DTOR-${RELOCATING+${DTOR}${RW_REGION}}}
20018 +  .jcr          ${RELOCATING-0} : { KEEP (*(.jcr)) }${RW_REGION}
20019 +
20020 +  ${RELOCATING+${DATARELRO}}
20021 +  ${OTHER_RELRO_SECTIONS}
20022 +  ${TEXT_DYNAMIC-${DYNAMIC}${RW_REGION}}
20023 +  ${NO_SMALL_DATA+${RELRO_NOW+${GOT}${RW_REGION}}}
20024 +  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOT}${RW_REGION}}}}
20025 +  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT+${GOTPLT}${RW_REGION}}}}
20026 +  ${RELOCATING+${DATA_SEGMENT_RELRO_END}}
20027 +  ${NO_SMALL_DATA+${RELRO_NOW-${SEPARATE_GOTPLT-${GOT}${RW_REGION}}}}
20028 +
20029 +  ${DATA_PLT+${PLT_BEFORE_GOT-${PLT}${RW_REGION}}}
20030 +
20031 +  .data         ${RELOCATING-0} :
20032 +  {
20033 +    ${RELOCATING+${DATA_START_SYMBOLS}}
20034 +    *(.data${RELOCATING+ .data.* .gnu.linkonce.d.*})
20035 +    KEEP (*(.gnu.linkonce.d.*personality*))
20036 +    ${CONSTRUCTING+SORT(CONSTRUCTORS)}
20037 +  }${RW_REGION}
20038 +  .data1        ${RELOCATING-0} : { *(.data1) }${RW_REGION}
20039 +  ${WRITABLE_RODATA+${RODATA}${RW_REGION}}
20040 +  ${OTHER_READWRITE_SECTIONS}
20041 +  ${SMALL_DATA_CTOR+${RELOCATING+${CTOR}${RW_REGION}}}
20042 +  ${SMALL_DATA_DTOR+${RELOCATING+${DTOR}${RW_REGION}}}
20043 +  ${DATA_PLT+${PLT_BEFORE_GOT+${PLT}${RW_REGION}}}
20044 +  ${RELOCATING+${OTHER_GOT_SYMBOLS}}
20045 +  ${NO_SMALL_DATA-${GOT}${RW_REGION}}
20046 +  ${OTHER_GOT_SECTIONS}
20047 +  ${SDATA}
20048 +  ${OTHER_SDATA_SECTIONS}
20049 +  ${RELOCATING+${BALIGN}}
20050 +  ${RELOCATING+_edata = .;}
20051 +  ${RELOCATING+PROVIDE (edata = .);}
20052 +  ${RELOCATING+__bss_start = .;}
20053 +  ${RELOCATING+${OTHER_BSS_SYMBOLS}}
20054 +  ${SBSS}
20055 +  ${BSS_PLT+${PLT}${RW_REGION}}
20056 +  .bss          ${RELOCATING-0} :
20057 +  {
20058 +   *(.dynbss)
20059 +   *(.bss${RELOCATING+ .bss.* .gnu.linkonce.b.*})
20060 +   *(COMMON)
20061 +   /* Align here to ensure that the .bss section occupies space up to
20062 +      _end.  Align after .bss to ensure correct alignment even if the
20063 +      .bss section disappears because there are no input sections.  */
20064 +   ${RELOCATING+. = ALIGN(${BSS_ALIGNMENT});}
20065 +  }${RW_BSS_REGION}
20066 +  ${OTHER_BSS_SECTIONS}
20067 +  ${RELOCATING+. = ALIGN(${BSS_ALIGNMENT});}
20068 +  ${RELOCATING+_end = .;}
20069 +  ${RELOCATING+${OTHER_BSS_END_SYMBOLS}}
20070 +  ${RELOCATING+PROVIDE (end = .);}
20071 +  ${RELOCATING+${DATA_SEGMENT_END}}
20072 +
20073 +  /* Stabs debugging sections.  */
20074 +  .stab          0 : { *(.stab) }
20075 +  .stabstr       0 : { *(.stabstr) }
20076 +  .stab.excl     0 : { *(.stab.excl) }
20077 +  .stab.exclstr  0 : { *(.stab.exclstr) }
20078 +  .stab.index    0 : { *(.stab.index) }
20079 +  .stab.indexstr 0 : { *(.stab.indexstr) }
20080 +
20081 +  .comment       0 : { *(.comment) }
20082 +
20083 +  /* DWARF debug sections.
20084 +     Symbols in the DWARF debugging sections are relative to the beginning
20085 +     of the section so we begin them at 0.  */
20086 +
20087 +  /* DWARF 1 */
20088 +  .debug          0 : { *(.debug) }
20089 +  .line           0 : { *(.line) }
20090 +
20091 +  /* GNU DWARF 1 extensions */
20092 +  .debug_srcinfo  0 : { *(.debug_srcinfo) }
20093 +  .debug_sfnames  0 : { *(.debug_sfnames) }
20094 +
20095 +  /* DWARF 1.1 and DWARF 2 */
20096 +  .debug_aranges  0 : { *(.debug_aranges) }
20097 +  .debug_pubnames 0 : { *(.debug_pubnames) }
20098 +
20099 +  /* DWARF 2 */
20100 +  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
20101 +  .debug_abbrev   0 : { *(.debug_abbrev) }
20102 +  .debug_line     0 : { *(.debug_line) }
20103 +  .debug_frame    0 : { *(.debug_frame) }
20104 +  .debug_str      0 : { *(.debug_str) }
20105 +  .debug_loc      0 : { *(.debug_loc) }
20106 +  .debug_macinfo  0 : { *(.debug_macinfo) }
20107 +
20108 +  /* SGI/MIPS DWARF 2 extensions */
20109 +  .debug_weaknames 0 : { *(.debug_weaknames) }
20110 +  .debug_funcnames 0 : { *(.debug_funcnames) }
20111 +  .debug_typenames 0 : { *(.debug_typenames) }
20112 +  .debug_varnames  0 : { *(.debug_varnames) }
20113 +
20114 +  ${STACK_ADDR+${STACK}}
20115 +  ${OTHER_SECTIONS}
20116 +  ${RELOCATING+${OTHER_END_SYMBOLS}}
20117 +  ${RELOCATING+${STACKNOTE}}
20118 +}
20119 +EOF
20120 --- /dev/null
20121 +++ b/ld/testsuite/ld-avr32/avr32.exp
20122 @@ -0,0 +1,25 @@
20123 +# Expect script for AVR32 ELF linker tests.
20124 +#   Copyright 2004-2006 Atmel Corporation.
20125 +#
20126 +# This file is free software; you can redistribute it and/or modify
20127 +# it under the terms of the GNU General Public License as published by
20128 +# the Free Software Foundation; either version 2 of the License, or
20129 +# (at your option) any later version.
20130 +#
20131 +# This program is distributed in the hope that it will be useful,
20132 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
20133 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20134 +# GNU General Public License for more details.
20135 +#
20136 +# You should have received a copy of the GNU General Public License
20137 +# along with this program; if not, write to the Free Software
20138 +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20139 +#
20140 +# Written by Haavard Skinnemoen (hskinnemoen@atmel.com)
20141 +#
20142 +
20143 +if ![istarget avr32-*-*] {
20144 +    return
20145 +}
20146 +
20147 +run_dump_test "pcrel"
20148 --- /dev/null
20149 +++ b/ld/testsuite/ld-avr32/pcrel.d
20150 @@ -0,0 +1,74 @@
20151 +#name: AVR32 ELF PC-relative external relocs
20152 +#source: symbols.s
20153 +#source: ../../../gas/testsuite/gas/avr32/pcrel.s
20154 +#ld: -T $srcdir/$subdir/pcrel.ld
20155 +#objdump: -d
20156 +
20157 +.*:     file format elf.*avr32.*
20158 +
20159 +Disassembly of section .text:
20160 +
20161 +a0000000 <_start>:
20162 +a0000000:      d7 03           nop
20163 +a0000002:      d7 03           nop
20164 +
20165 +a0000004 <test_rjmp>:
20166 +a0000004:      d7 03           nop
20167 +a0000006:      c0 28           rjmp a000000a <test_rjmp\+0x6>
20168 +a0000008:      d7 03           nop
20169 +a000000a:      e0 8f 01 fb     bral a0000400 <extsym10>
20170 +
20171 +a000000e <test_rcall>:
20172 +a000000e:      d7 03           nop
20173 +a0000010 <test_rcall2>:
20174 +a0000010:      c0 2c           rcall a0000014 <test_rcall2\+0x4>
20175 +a0000012:      d7 03           nop
20176 +a0000014:      ee b0 ff f6     rcall a0200000 <extsym21>
20177 +
20178 +a0000018 <test_branch>:
20179 +a0000018:      c0 31           brne a000001e <test_branch\+0x6>
20180 +a000001a:      fe 9f ff ff     bral a0000018 <test_branch>
20181 +a000001e:      ee 90 ff f1     breq a0200000 <extsym21>
20182 +
20183 +a0000022 <test_lddpc>:
20184 +a0000022:      48 30           lddpc r0,a000002c <sym1>
20185 +a0000024:      48 20           lddpc r0,a000002c <sym1>
20186 +a0000026:      fe f0 7f da     ld.w r0,pc\[32730\]
20187 +       ...
20188 +
20189 +a000002c <sym1>:
20190 +a000002c:      d7 03           nop
20191 +a000002e:      d7 03           nop
20192 +
20193 +a0000030 <test_local>:
20194 +a0000030:      48 20           lddpc r0,a0000038 <test_local\+0x8>
20195 +a0000032:      48 30           lddpc r0,a000003c <test_local\+0xc>
20196 +a0000034:      48 20           lddpc r0,a000003c <test_local\+0xc>
20197 +a0000036:      00 00           add r0,r0
20198 +a0000038:      d7 03           nop
20199 +a000003a:      d7 03           nop
20200 +a000003c:      d7 03           nop
20201 +a000003e:      d7 03           nop
20202 +
20203 +Disassembly of section \.text\.init:
20204 +a0000040 <test_inter_section>:
20205 +a0000040:      fe b0 ff e7     rcall a000000e <test_rcall>
20206 +a0000044:      d7 03           nop
20207 +a0000046:      fe b0 ff e4     rcall a000000e <test_rcall>
20208 +a000004a:      fe b0 ff e3     rcall a0000010 <test_rcall2>
20209 +a000004e:      d7 03           nop
20210 +a0000050:      fe b0 ff e0     rcall a0000010 <test_rcall2>
20211 +
20212 +Disassembly of section \.text\.pcrel10:
20213 +
20214 +a0000400 <extsym10>:
20215 +a0000400:      d7 03           nop
20216 +
20217 +Disassembly of section \.text\.pcrel16:
20218 +
20219 +a0008000 <extsym16>:
20220 +a0008000:      d7 03           nop
20221 +
20222 +Disassembly of section \.text\.pcrel21:
20223 +a0200000 <extsym21>:
20224 +a0200000:      d7 03           nop
20225 --- /dev/null
20226 +++ b/ld/testsuite/ld-avr32/pcrel.ld
20227 @@ -0,0 +1,23 @@
20228 +ENTRY(_start)
20229 +SECTIONS
20230 +{
20231 +       .text 0xa0000000:
20232 +       {
20233 +               *(.text)
20234 +       }
20235 +
20236 +       .text.pcrel10 0xa0000400:
20237 +       {
20238 +               *(.text.pcrel10)
20239 +       }
20240 +
20241 +       .text.pcrel16 0xa0008000:
20242 +       {
20243 +               *(.text.pcrel16)
20244 +       }
20245 +
20246 +       .text.pcrel21 0xa0200000:
20247 +       {
20248 +               *(.text.pcrel21)
20249 +       }
20250 +}
20251 --- /dev/null
20252 +++ b/ld/testsuite/ld-avr32/symbols.s
20253 @@ -0,0 +1,20 @@
20254 +       .text
20255 +       .global _start
20256 +_start:
20257 +       nop
20258 +       nop
20259 +
20260 +       .section .text.pcrel10,"ax"
20261 +       .global extsym10
20262 +extsym10:
20263 +       nop
20264 +
20265 +       .section .text.pcrel16,"ax"
20266 +       .global extsym16
20267 +extsym16:
20268 +       nop
20269 +
20270 +       .section .text.pcrel21,"ax"
20271 +       .global extsym21
20272 +extsym21:
20273 +       nop
20274 --- /dev/null
20275 +++ b/opcodes/avr32-asm.c
20276 @@ -0,0 +1,244 @@
20277 +/* Assembler interface for AVR32.
20278 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
20279 +
20280 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20281 +
20282 +   This file is part of libopcodes.
20283 +
20284 +   This program is free software; you can redistribute it and/or
20285 +   modify it under the terms of the GNU General Public License as
20286 +   published by the Free Software Foundation; either version 2 of the
20287 +   License, or (at your option) any later version.
20288 +
20289 +   This program is distributed in the hope that it will be useful, but
20290 +   WITHOUT ANY WARRANTY; without even the implied warranty of
20291 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
20292 +   General Public License for more details.
20293 +
20294 +   You should have received a copy of the GNU General Public License
20295 +   along with this program; if not, write to the Free Software
20296 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20297 +   02111-1307, USA.  */
20298 +
20299 +#include <string.h>
20300 +
20301 +#include "avr32-opc.h"
20302 +#include "avr32-asm.h"
20303 +
20304 +/* Structure for a register hash table entry.  */
20305 +struct reg_entry
20306 +{
20307 +  const char   *name;
20308 +  int          number;
20309 +};
20310 +
20311 +/* Integer Registers.  */
20312 +static const struct reg_entry reg_table[] =
20313 +  {
20314 +    /* Primary names (used by the disassembler) */
20315 +    { "r0",   0 }, { "r1",   1 }, { "r2",   2 }, { "r3",   3 },
20316 +    { "r4",   4 }, { "r5",   5 }, { "r6",   6 }, { "r7",   7 },
20317 +    { "r8",   8 }, { "r9",   9 }, { "r10", 10 }, { "r11", 11 },
20318 +    { "r12", 12 }, { "sp",  13 }, { "lr",  14 }, { "pc",  15 },
20319 +    /* Alternatives to sp, lr and pc.  */
20320 +    { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
20321 +  };
20322 +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0]))
20323 +
20324 +/* Coprocessor Registers.  */
20325 +static const struct reg_entry cr_table[] =
20326 +  {
20327 +    { "cr0",   0 }, { "cr1",   1 }, { "cr2",   2 }, { "cr3",   3 },
20328 +    { "cr4",   4 }, { "cr5",   5 }, { "cr6",   6 }, { "cr7",   7 },
20329 +    { "cr8",   8 }, { "cr9",   9 }, { "cr10", 10 }, { "cr11", 11 },
20330 +    { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 },
20331 +  };
20332 +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0]))
20333 +
20334 +#define AVR32_NR_FPREGS (sizeof(fr_table)/sizeof(fr_table[0]))
20335 +
20336 +/* PiCo Registers.  */
20337 +static const struct reg_entry pico_table[] =
20338 +  {
20339 +    { "inpix2",    0 }, { "inpix1",    1 }, { "inpix0",    2 },
20340 +    { "outpix2",   3 }, { "outpix1",   4 }, { "outpix0",   5 },
20341 +    { "coeff0_a",  6 }, { "coeff0_b",  7 }, { "coeff1_a",  8 },
20342 +    { "coeff1_b",  9 }, { "coeff2_a", 10 }, { "coeff2_b", 11 },
20343 +    { "vmu0_out", 12 }, { "vmu1_out", 13 }, { "vmu2_out", 14 },
20344 +    { "config",   15 },
20345 +  };
20346 +#define AVR32_NR_PICOREGS (sizeof(pico_table)/sizeof(pico_table[0]))
20347 +
20348 +int
20349 +avr32_parse_intreg(const char *str)
20350 +{
20351 +  unsigned int i;
20352 +
20353 +  for (i = 0; i < AVR32_NR_INTREGS; i++)
20354 +    {
20355 +      if (strcasecmp(reg_table[i].name, str) == 0)
20356 +       return reg_table[i].number;
20357 +    }
20358 +
20359 +  return -1;
20360 +}
20361 +
20362 +int
20363 +avr32_parse_cpreg(const char *str)
20364 +{
20365 +  unsigned int i;
20366 +
20367 +  for (i = 0; i < AVR32_NR_CPREGS; i++)
20368 +    {
20369 +      if (strcasecmp(cr_table[i].name, str) == 0)
20370 +       return cr_table[i].number;
20371 +    }
20372 +
20373 +  return -1;
20374 +}
20375 +
20376 +
20377 +int avr32_parse_picoreg(const char *str)
20378 +{
20379 +  unsigned int i;
20380 +
20381 +  for (i = 0; i < AVR32_NR_PICOREGS; i++)
20382 +    {
20383 +      if (strcasecmp(pico_table[i].name, str) == 0)
20384 +       return pico_table[i].number;
20385 +    }
20386 +
20387 +  return -1;
20388 +}
20389 +
20390 +static unsigned long
20391 +parse_reglist(char *str, char **endptr, int (*parse_reg)(const char *))
20392 +{
20393 +  int reg_from, reg_to;
20394 +  unsigned long result = 0;
20395 +  char *p1, *p2, c;
20396 +
20397 +  while (*str)
20398 +    {
20399 +      for (p1 = str; *p1; p1++)
20400 +       if (*p1 == ',' || *p1 == '-')
20401 +         break;
20402 +
20403 +      c = *p1, *p1 = 0;
20404 +      reg_from = parse_reg(str);
20405 +      *p1 = c;
20406 +
20407 +      if (reg_from < 0)
20408 +       break;
20409 +
20410 +      if (*p1 == '-')
20411 +       {
20412 +         for (p2 = ++p1; *p2; p2++)
20413 +           if (*p2 == ',')
20414 +             break;
20415 +
20416 +         c = *p2, *p2 = 0;
20417 +         /* printf("going to parse reg_to from `%s'\n", p1); */
20418 +         reg_to = parse_reg(p1);
20419 +         *p2 = c;
20420 +
20421 +         if (reg_to < 0)
20422 +           break;
20423 +
20424 +         while (reg_from <= reg_to)
20425 +           result |= (1 << reg_from++);
20426 +         p1 = p2;
20427 +       }
20428 +      else
20429 +       result |= (1 << reg_from);
20430 +
20431 +      str = p1;
20432 +      if (*str) ++str;
20433 +    }
20434 +
20435 +  if (endptr)
20436 +    *endptr = str;
20437 +
20438 +  return result;
20439 +}
20440 +
20441 +unsigned long
20442 +avr32_parse_reglist(char *str, char **endptr)
20443 +{
20444 +  return parse_reglist(str, endptr, avr32_parse_intreg);
20445 +}
20446 +
20447 +unsigned long
20448 +avr32_parse_cpreglist(char *str, char **endptr)
20449 +{
20450 +  return parse_reglist(str, endptr, avr32_parse_cpreg);
20451 +}
20452 +
20453 +unsigned long
20454 +avr32_parse_pico_reglist(char *str, char **endptr)
20455 +{
20456 +  return parse_reglist(str, endptr, avr32_parse_picoreg);
20457 +}
20458 +
20459 +int
20460 +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8)
20461 +{
20462 +  unsigned long result = 0;
20463 +
20464 +  /* printf("convert regmask16 0x%04lx\n", regmask16); */
20465 +
20466 +  if (regmask16 & 0xf)
20467 +    {
20468 +      if ((regmask16 & 0xf) == 0xf)
20469 +       result |= 1 << 0;
20470 +      else
20471 +       return -1;
20472 +    }
20473 +  if (regmask16 & 0xf0)
20474 +    {
20475 +      if ((regmask16 & 0xf0) == 0xf0)
20476 +       result |= 1 << 1;
20477 +      else
20478 +       return -1;
20479 +    }
20480 +  if (regmask16 & 0x300)
20481 +    {
20482 +      if ((regmask16 & 0x300) == 0x300)
20483 +       result |= 1 << 2;
20484 +      else
20485 +       return -1;
20486 +    }
20487 +  if (regmask16 & (1 << 13))
20488 +    return -1;
20489 +
20490 +  if (regmask16 & (1 << 10))
20491 +    result |= 1 << 3;
20492 +  if (regmask16 & (1 << 11))
20493 +    result |= 1 << 4;
20494 +  if (regmask16 & (1 << 12))
20495 +    result |= 1 << 5;
20496 +  if (regmask16 & (1 << 14))
20497 +    result |= 1 << 6;
20498 +  if (regmask16 & (1 << 15))
20499 +    result |= 1 << 7;
20500 +
20501 +  *regmask8 = result;
20502 +
20503 +  return 0;
20504 +}
20505 +
20506 +#if 0
20507 +struct reg_map
20508 +{
20509 +  const struct reg_entry       *names;
20510 +  int                          nr_regs;
20511 +  struct hash_control          *htab;
20512 +  const char                   *errmsg;
20513 +};
20514 +
20515 +struct reg_map all_reg_maps[] =
20516 +  {
20517 +    { reg_table, AVR32_NR_INTREGS, NULL, N_("integral register expected") },
20518 +    { cr_table,  AVR32_NR_CPREGS,  NULL, N_("coprocessor register expected") },
20519 +  };
20520 +#endif
20521 --- /dev/null
20522 +++ b/opcodes/avr32-asm.h
20523 @@ -0,0 +1,40 @@
20524 +/* Assembler interface for AVR32.
20525 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
20526 +
20527 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20528 +
20529 +   This file is part of libopcodes.
20530 +
20531 +   This program is free software; you can redistribute it and/or
20532 +   modify it under the terms of the GNU General Public License as
20533 +   published by the Free Software Foundation; either version 2 of the
20534 +   License, or (at your option) any later version.
20535 +
20536 +   This program is distributed in the hope that it will be useful, but
20537 +   WITHOUT ANY WARRANTY; without even the implied warranty of
20538 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
20539 +   General Public License for more details.
20540 +
20541 +   You should have received a copy of the GNU General Public License
20542 +   along with this program; if not, write to the Free Software
20543 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20544 +   02111-1307, USA.  */
20545 +#ifndef __OPCODES_AVR32_ASM_H
20546 +#define __OPCODES_AVR32_ASM_H
20547 +
20548 +extern int
20549 +avr32_parse_intreg(const char *str);
20550 +extern int
20551 +avr32_parse_cpreg(const char *str);
20552 +extern int
20553 +avr32_parse_picoreg(const char *str);
20554 +extern unsigned long
20555 +avr32_parse_reglist(char *str, char **endptr);
20556 +extern unsigned long
20557 +avr32_parse_cpreglist(char *str, char **endptr);
20558 +extern unsigned long
20559 +avr32_parse_pico_reglist(char *str, char **endptr);
20560 +extern int
20561 +avr32_make_regmask8(unsigned long regmask16, unsigned long *regmask8);
20562 +
20563 +#endif /* __OPCODES_AVR32_ASM_H */
20564 --- /dev/null
20565 +++ b/opcodes/avr32-dis.c
20566 @@ -0,0 +1,916 @@
20567 +/* Print AVR32 instructions for GDB and objdump.
20568 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
20569 +
20570 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20571 +
20572 +   This file is part of libopcodes.
20573 +
20574 +   This program is free software; you can redistribute it and/or
20575 +   modify it under the terms of the GNU General Public License as
20576 +   published by the Free Software Foundation; either version 2 of the
20577 +   License, or (at your option) any later version.
20578 +
20579 +   This program is distributed in the hope that it will be useful, but
20580 +   WITHOUT ANY WARRANTY; without even the implied warranty of
20581 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
20582 +   General Public License for more details.
20583 +
20584 +   You should have received a copy of the GNU General Public License
20585 +   along with this program; if not, write to the Free Software
20586 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20587 +   02111-1307, USA.  */
20588 +
20589 +#include "sysdep.h"
20590 +#include "dis-asm.h"
20591 +#include "avr32-opc.h"
20592 +#include "opintl.h"
20593 +#include "safe-ctype.h"
20594 +
20595 +/* TODO: Share this with -asm */
20596 +
20597 +/* Structure for a register hash table entry.  */
20598 +struct reg_entry
20599 +{
20600 +  const char   *name;
20601 +  int          number;
20602 +};
20603 +
20604 +#ifndef strneq
20605 +#define strneq(a,b,n)  (strncmp ((a), (b), (n)) == 0)
20606 +#endif
20607 +
20608 +static char avr32_opt_decode_fpu = 0;
20609 +
20610 +static const struct reg_entry reg_table[] =
20611 +  {
20612 +    /* Primary names (used by the disassembler) */
20613 +    { "r0",   0 }, { "r1",   1 }, { "r2",   2 }, { "r3",   3 },
20614 +    { "r4",   4 }, { "r5",   5 }, { "r6",   6 }, { "r7",   7 },
20615 +    { "r8",   8 }, { "r9",   9 }, { "r10", 10 }, { "r11", 11 },
20616 +    { "r12", 12 }, { "sp",  13 }, { "lr",  14 }, { "pc",  15 },
20617 +    /* Alternatives to sp, lr and pc.  */
20618 +    { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
20619 +  };
20620 +#define AVR32_NR_INTREGS (sizeof(reg_table)/sizeof(reg_table[0]))
20621 +
20622 +/* Coprocessor Registers.  */
20623 +static const struct reg_entry cr_table[] =
20624 +  {
20625 +    { "cr0",   0 }, { "cr1",   1 }, { "cr2",   2 }, { "cr3",   3 },
20626 +    { "cr4",   4 }, { "cr5",   5 }, { "cr6",   6 }, { "cr7",   7 },
20627 +    { "cr8",   8 }, { "cr9",   9 }, { "cr10", 10 }, { "cr11", 11 },
20628 +    { "cr12", 12 }, { "cr13", 13 }, { "cr14", 14 }, { "cr15", 15 },
20629 +  };
20630 +#define AVR32_NR_CPREGS (sizeof(cr_table)/sizeof(cr_table[0]))
20631 +
20632 +static const char bparts[4] = { 'b', 'l', 'u', 't' };
20633 +static bfd_vma current_pc;
20634 +
20635 +struct avr32_field_value
20636 +{
20637 +  const struct avr32_ifield *ifield;
20638 +  unsigned long value;
20639 +};
20640 +
20641 +struct avr32_operand
20642 +{
20643 +  int id;
20644 +  int is_pcrel;
20645 +  int align_order;
20646 +  int (*print)(struct avr32_operand *op, struct disassemble_info *info,
20647 +              struct avr32_field_value *ifields);
20648 +};
20649 +
20650 +static signed long
20651 +get_signed_value(const struct avr32_field_value *fv)
20652 +{
20653 +  signed long value = fv->value;
20654 +
20655 +  if (fv->value & (1 << (fv->ifield->bitsize - 1)))
20656 +    value |= (~0UL << fv->ifield->bitsize);
20657 +
20658 +  return value;
20659 +}
20660 +
20661 +static void
20662 +print_reglist_range(unsigned int first, unsigned int last,
20663 +                   const struct reg_entry *reg_names,
20664 +                   int need_comma,
20665 +                   struct disassemble_info *info)
20666 +{
20667 +  if (need_comma)
20668 +    info->fprintf_func(info->stream, ",");
20669 +
20670 +  if (first == last)
20671 +    info->fprintf_func(info->stream, "%s",
20672 +                      reg_names[first].name);
20673 +  else
20674 +    info->fprintf_func(info->stream, "%s-%s",
20675 +                      reg_names[first].name, reg_names[last].name);
20676 +}
20677 +
20678 +static int
20679 +print_intreg(struct avr32_operand *op,
20680 +            struct disassemble_info *info,
20681 +            struct avr32_field_value *ifields)
20682 +{
20683 +  unsigned long regid = ifields[0].value << op->align_order;
20684 +
20685 +  info->fprintf_func(info->stream, "%s",
20686 +                    reg_table[regid].name);
20687 +  return 1;
20688 +}
20689 +
20690 +static int
20691 +print_intreg_predec(struct avr32_operand *op ATTRIBUTE_UNUSED,
20692 +                   struct disassemble_info *info,
20693 +                   struct avr32_field_value *ifields)
20694 +{
20695 +  info->fprintf_func(info->stream, "--%s",
20696 +                    reg_table[ifields[0].value].name);
20697 +  return 1;
20698 +}
20699 +
20700 +static int
20701 +print_intreg_postinc(struct avr32_operand *op ATTRIBUTE_UNUSED,
20702 +                    struct disassemble_info *info,
20703 +                    struct avr32_field_value *ifields)
20704 +{
20705 +  info->fprintf_func(info->stream, "%s++",
20706 +                    reg_table[ifields[0].value].name);
20707 +  return 1;
20708 +}
20709 +
20710 +static int
20711 +print_intreg_lsl(struct avr32_operand *op ATTRIBUTE_UNUSED,
20712 +                struct disassemble_info *info,
20713 +                struct avr32_field_value *ifields)
20714 +{
20715 +  const char *rp = reg_table[ifields[0].value].name;
20716 +  unsigned long sa = ifields[1].value;
20717 +
20718 +  if (sa)
20719 +    info->fprintf_func(info->stream, "%s<<0x%lx", rp, sa);
20720 +  else
20721 +    info->fprintf_func(info->stream, "%s", rp);
20722 +
20723 +  return 2;
20724 +}
20725 +
20726 +static int
20727 +print_intreg_lsr(struct avr32_operand *op ATTRIBUTE_UNUSED,
20728 +                struct disassemble_info *info,
20729 +                struct avr32_field_value *ifields)
20730 +{
20731 +  const char *rp = reg_table[ifields[0].value].name;
20732 +  unsigned long sa = ifields[1].value;
20733 +
20734 +  if (sa)
20735 +    info->fprintf_func(info->stream, "%s>>0x%lx", rp, sa);
20736 +  else
20737 +    info->fprintf_func(info->stream, "%s", rp);
20738 +
20739 +  return 2;
20740 +}
20741 +
20742 +static int
20743 +print_intreg_bpart(struct avr32_operand *op ATTRIBUTE_UNUSED,
20744 +                  struct disassemble_info *info,
20745 +                  struct avr32_field_value *ifields)
20746 +{
20747 +  info->fprintf_func(info->stream, "%s:%c",
20748 +                    reg_table[ifields[0].value].name,
20749 +                    bparts[ifields[1].value]);
20750 +  return 2;
20751 +}
20752 +
20753 +static int
20754 +print_intreg_hpart(struct avr32_operand *op ATTRIBUTE_UNUSED,
20755 +                  struct disassemble_info *info,
20756 +                  struct avr32_field_value *ifields)
20757 +{
20758 +  info->fprintf_func(info->stream, "%s:%c",
20759 +                    reg_table[ifields[0].value].name,
20760 +                    ifields[1].value ? 't' : 'b');
20761 +  return 2;
20762 +}
20763 +
20764 +static int
20765 +print_intreg_sdisp(struct avr32_operand *op,
20766 +                 struct disassemble_info *info,
20767 +                 struct avr32_field_value *ifields)
20768 +{
20769 +  signed long disp;
20770 +
20771 +  disp = get_signed_value(&ifields[1]) << op->align_order;
20772 +
20773 +  info->fprintf_func(info->stream, "%s[%ld]",
20774 +                    reg_table[ifields[0].value].name, disp);
20775 +  return 2;
20776 +}
20777 +
20778 +static int
20779 +print_intreg_udisp(struct avr32_operand *op,
20780 +                  struct disassemble_info *info,
20781 +                  struct avr32_field_value *ifields)
20782 +{
20783 +  info->fprintf_func(info->stream, "%s[0x%lx]",
20784 +                    reg_table[ifields[0].value].name,
20785 +                    ifields[1].value << op->align_order);
20786 +  return 2;
20787 +}
20788 +
20789 +static int
20790 +print_intreg_index(struct avr32_operand *op ATTRIBUTE_UNUSED,
20791 +                  struct disassemble_info *info,
20792 +                  struct avr32_field_value *ifields)
20793 +{
20794 +  const char *rb, *ri;
20795 +  unsigned long sa = ifields[2].value;
20796 +
20797 +  rb = reg_table[ifields[0].value].name;
20798 +  ri = reg_table[ifields[1].value].name;
20799 +
20800 +  if (sa)
20801 +    info->fprintf_func(info->stream, "%s[%s<<0x%lx]", rb, ri, sa);
20802 +  else
20803 +    info->fprintf_func(info->stream, "%s[%s]", rb, ri);
20804 +
20805 +  return 3;
20806 +}
20807 +
20808 +static int
20809 +print_intreg_xindex(struct avr32_operand *op ATTRIBUTE_UNUSED,
20810 +                   struct disassemble_info *info,
20811 +                   struct avr32_field_value *ifields)
20812 +{
20813 +  info->fprintf_func(info->stream, "%s[%s:%c<<2]",
20814 +                    reg_table[ifields[0].value].name,
20815 +                    reg_table[ifields[1].value].name,
20816 +                    bparts[ifields[2].value]);
20817 +  return 3;
20818 +}
20819 +
20820 +static int
20821 +print_jmplabel(struct avr32_operand *op,
20822 +              struct disassemble_info *info,
20823 +              struct avr32_field_value *ifields)
20824 +{
20825 +  bfd_vma address, offset;
20826 +
20827 +  offset = get_signed_value(ifields) << op->align_order;
20828 +  address = (current_pc & (~0UL << op->align_order)) + offset;
20829 +
20830 +  info->print_address_func(address, info);
20831 +
20832 +  return 1;
20833 +}
20834 +
20835 +static int
20836 +print_pc_disp(struct avr32_operand *op,
20837 +             struct disassemble_info *info,
20838 +             struct avr32_field_value *ifields)
20839 +{
20840 +  bfd_vma address, offset;
20841 +
20842 +  offset = ifields[0].value << op->align_order;
20843 +  address = (current_pc & (~0UL << op->align_order)) + offset;
20844 +
20845 +  info->print_address_func(address, info);
20846 +
20847 +  return 1;
20848 +}
20849 +
20850 +static int
20851 +print_sp(struct avr32_operand *op ATTRIBUTE_UNUSED,
20852 +        struct disassemble_info *info,
20853 +        struct avr32_field_value *ifields ATTRIBUTE_UNUSED)
20854 +{
20855 +  info->fprintf_func(info->stream, "sp");
20856 +  return 1;
20857 +}
20858 +
20859 +static int
20860 +print_sp_disp(struct avr32_operand *op,
20861 +             struct disassemble_info *info,
20862 +             struct avr32_field_value *ifields)
20863 +{
20864 +  info->fprintf_func(info->stream, "sp[0x%lx]",
20865 +                    ifields[0].value << op->align_order);
20866 +  return 1;
20867 +}
20868 +
20869 +static int
20870 +print_cpno(struct avr32_operand *op ATTRIBUTE_UNUSED,
20871 +          struct disassemble_info *info,
20872 +          struct avr32_field_value *ifields)
20873 +{
20874 +  info->fprintf_func(info->stream, "cp%lu", ifields[0].value);
20875 +  return 1;
20876 +}
20877 +
20878 +static int
20879 +print_cpreg(struct avr32_operand *op,
20880 +           struct disassemble_info *info,
20881 +           struct avr32_field_value *ifields)
20882 +{
20883 +  info->fprintf_func(info->stream, "cr%lu",
20884 +                    ifields[0].value << op->align_order);
20885 +  return 1;
20886 +}
20887 +
20888 +static int
20889 +print_uconst(struct avr32_operand *op,
20890 +            struct disassemble_info *info,
20891 +            struct avr32_field_value *ifields)
20892 +{
20893 +  info->fprintf_func(info->stream, "0x%lx",
20894 +                    ifields[0].value << op->align_order);
20895 +  return 1;
20896 +}
20897 +
20898 +static int
20899 +print_sconst(struct avr32_operand *op,
20900 +            struct disassemble_info *info,
20901 +            struct avr32_field_value *ifields)
20902 +{
20903 +  info->fprintf_func(info->stream, "%ld",
20904 +                    get_signed_value(ifields) << op->align_order);
20905 +  return 1;
20906 +}
20907 +
20908 +static int
20909 +print_reglist8_head(unsigned long regmask, int *commap,
20910 +                   struct disassemble_info *info)
20911 +{
20912 +  int first = -1, last, i = 0;
20913 +  int need_comma = 0;
20914 +
20915 +  while (i < 12)
20916 +    {
20917 +      if (first == -1 && (regmask & 1))
20918 +       {
20919 +         first = i;
20920 +       }
20921 +      else if (first != -1 && !(regmask & 1))
20922 +       {
20923 +         last = i - 1;
20924 +
20925 +         print_reglist_range(first, last, reg_table, need_comma, info);
20926 +         need_comma = 1;
20927 +         first = -1;
20928 +       }
20929 +
20930 +      if (i < 8)
20931 +       i += 4;
20932 +      else if (i < 10)
20933 +       i += 2;
20934 +      else
20935 +       i++;
20936 +      regmask >>= 1;
20937 +    }
20938 +
20939 +  *commap = need_comma;
20940 +  return first;
20941 +}
20942 +
20943 +static void
20944 +print_reglist8_tail(unsigned long regmask, int first, int need_comma,
20945 +                   struct disassemble_info *info)
20946 +{
20947 +  int last = 11;
20948 +
20949 +  if (regmask & 0x20)
20950 +    {
20951 +      if (first == -1)
20952 +       first = 12;
20953 +      last = 12;
20954 +    }
20955 +
20956 +  if (first != -1)
20957 +    {
20958 +      print_reglist_range(first, last, reg_table, need_comma, info);
20959 +      need_comma = 1;
20960 +      first = -1;
20961 +    }
20962 +
20963 +  if (regmask & 0x40)
20964 +    {
20965 +      if (first == -1)
20966 +       first = 14;
20967 +      last = 14;
20968 +    }
20969 +
20970 +  if (regmask & 0x80)
20971 +    {
20972 +      if (first == -1)
20973 +       first = 15;
20974 +      last = 15;
20975 +    }
20976 +
20977 +  if (first != -1)
20978 +    print_reglist_range(first, last, reg_table, need_comma, info);
20979 +}
20980 +
20981 +static int
20982 +print_reglist8(struct avr32_operand *op ATTRIBUTE_UNUSED,
20983 +              struct disassemble_info *info,
20984 +              struct avr32_field_value *ifields)
20985 +{
20986 +  unsigned long regmask = ifields[0].value;
20987 +  int first, need_comma;
20988 +
20989 +  first = print_reglist8_head(regmask, &need_comma, info);
20990 +  print_reglist8_tail(regmask, first, need_comma, info);
20991 +
20992 +  return 1;
20993 +}
20994 +
20995 +static int
20996 +print_reglist9(struct avr32_operand *op ATTRIBUTE_UNUSED,
20997 +              struct disassemble_info *info,
20998 +              struct avr32_field_value *ifields)
20999 +{
21000 +  unsigned long regmask = ifields[0].value >> 1;
21001 +  int first, last, need_comma;
21002 +
21003 +  first = print_reglist8_head(regmask, &need_comma, info);
21004 +
21005 +  if ((ifields[0].value & 0x101) == 0x101)
21006 +    {
21007 +      if (first != -1)
21008 +       {
21009 +         last = 11;
21010 +
21011 +         print_reglist_range(first, last, reg_table, need_comma, info);
21012 +         need_comma = 1;
21013 +         first = -1;
21014 +       }
21015 +
21016 +      print_reglist_range(15, 15, reg_table, need_comma, info);
21017 +
21018 +      regmask >>= 5;
21019 +
21020 +      if ((regmask & 3) == 0)
21021 +       info->fprintf_func(info->stream, ",r12=0");
21022 +      else if ((regmask & 3) == 1)
21023 +       info->fprintf_func(info->stream, ",r12=1");
21024 +      else
21025 +       info->fprintf_func(info->stream, ",r12=-1");
21026 +    }
21027 +  else
21028 +      print_reglist8_tail(regmask, first, need_comma, info);
21029 +
21030 +  return 1;
21031 +}
21032 +
21033 +static int
21034 +print_reglist16(struct avr32_operand *op ATTRIBUTE_UNUSED,
21035 +               struct disassemble_info *info,
21036 +               struct avr32_field_value *ifields)
21037 +{
21038 +  unsigned long regmask = ifields[0].value;
21039 +  unsigned int i = 0, first, last;
21040 +  int need_comma = 0;
21041 +
21042 +  while (i < 16)
21043 +    {
21044 +      if (regmask & 1)
21045 +       {
21046 +         first = i;
21047 +         while (i < 16)
21048 +           {
21049 +             i++;
21050 +             regmask >>= 1;
21051 +             if (!(regmask & 1))
21052 +               break;
21053 +           }
21054 +         last = i - 1;
21055 +         print_reglist_range(first, last, reg_table, need_comma, info);
21056 +         need_comma = 1;
21057 +       }
21058 +      else
21059 +       {
21060 +         i++;
21061 +         regmask >>= 1;
21062 +       }
21063 +    }
21064 +
21065 +  return 1;
21066 +}
21067 +
21068 +static int
21069 +print_reglist_ldm(struct avr32_operand *op,
21070 +                 struct disassemble_info *info,
21071 +                 struct avr32_field_value *ifields)
21072 +{
21073 +  int rp, w_bit;
21074 +  int i, first, last;
21075 +  unsigned long regmask;
21076 +
21077 +  rp = ifields[0].value;
21078 +  w_bit = ifields[1].value;
21079 +  regmask = ifields[2].value;
21080 +
21081 +  if (regmask & (1 << AVR32_REG_PC) && rp == AVR32_REG_PC)
21082 +    {
21083 +      if (w_bit)
21084 +       info->fprintf_func(info->stream, "sp++");
21085 +      else
21086 +       info->fprintf_func(info->stream, "sp");
21087 +
21088 +      for (i = 0; i < 12; )
21089 +       {
21090 +         if (regmask & (1 << i))
21091 +           {
21092 +             first = i;
21093 +             while (i < 12)
21094 +               {
21095 +                 i++;
21096 +                 if (!(regmask & (1 << i)))
21097 +                   break;
21098 +               }
21099 +             last = i - 1;
21100 +             print_reglist_range(first, last, reg_table, 1, info);
21101 +           }
21102 +         else
21103 +           i++;
21104 +       }
21105 +
21106 +      info->fprintf_func(info->stream, ",pc");
21107 +      if (regmask & (1 << AVR32_REG_LR))
21108 +       info->fprintf_func(info->stream, ",r12=-1");
21109 +      else if (regmask & (1 << AVR32_REG_R12))
21110 +       info->fprintf_func(info->stream, ",r12=1");
21111 +      else
21112 +       info->fprintf_func(info->stream, ",r12=0");
21113 +    }
21114 +  else
21115 +    {
21116 +      if (w_bit)
21117 +       info->fprintf_func(info->stream, "%s++,", reg_table[rp].name);
21118 +      else
21119 +       info->fprintf_func(info->stream, "%s,", reg_table[rp].name);
21120 +
21121 +      print_reglist16(op, info, ifields + 2);
21122 +    }
21123 +
21124 +  return 3;
21125 +}
21126 +
21127 +static int
21128 +print_reglist_cp8(struct avr32_operand *op ATTRIBUTE_UNUSED,
21129 +                 struct disassemble_info *info,
21130 +                 struct avr32_field_value *ifields)
21131 +{
21132 +  unsigned long regmask = ifields[0].value;
21133 +  unsigned int i = 0, first, last, offset = 0;
21134 +  int need_comma = 0;
21135 +
21136 +  if (ifields[1].value)
21137 +    offset = 8;
21138 +
21139 +  while (i < 8)
21140 +    {
21141 +      if (regmask & 1)
21142 +       {
21143 +         first = i;
21144 +         while (i < 8)
21145 +           {
21146 +             i++;
21147 +             regmask >>= 1;
21148 +             if (!(regmask & 1))
21149 +               break;
21150 +           }
21151 +         last = i - 1;
21152 +         print_reglist_range(offset + first, offset + last,
21153 +                             cr_table, need_comma, info);
21154 +         need_comma = 1;
21155 +       }
21156 +      else
21157 +       {
21158 +         i++;
21159 +         regmask >>= 1;
21160 +       }
21161 +    }
21162 +
21163 +  return 2;
21164 +}
21165 +
21166 +static int
21167 +print_reglist_cpd8(struct avr32_operand *op ATTRIBUTE_UNUSED,
21168 +                  struct disassemble_info *info,
21169 +                  struct avr32_field_value *ifields)
21170 +{
21171 +  unsigned long regmask = ifields[0].value;
21172 +  unsigned int i = 0, first, last;
21173 +  int need_comma = 0;
21174 +
21175 +  while (i < 8)
21176 +    {
21177 +      if (regmask & 1)
21178 +       {
21179 +         first = 2 * i;
21180 +         while (i < 8)
21181 +           {
21182 +             i++;
21183 +             regmask >>= 1;
21184 +             if (!(regmask & 1))
21185 +               break;
21186 +           }
21187 +         last = 2 * (i - 1) + 1;
21188 +         print_reglist_range(first, last, cr_table, need_comma, info);
21189 +         need_comma = 1;
21190 +       }
21191 +      else
21192 +       {
21193 +         i++;
21194 +         regmask >>= 1;
21195 +       }
21196 +    }
21197 +
21198 +  return 1;
21199 +}
21200 +
21201 +static int
21202 +print_retval(struct avr32_operand *op ATTRIBUTE_UNUSED,
21203 +            struct disassemble_info *info,
21204 +            struct avr32_field_value *ifields)
21205 +{
21206 +  unsigned long regid = ifields[0].value;
21207 +  const char *retval;
21208 +
21209 +  if (regid < AVR32_REG_SP)
21210 +    retval = reg_table[regid].name;
21211 +  else if (regid == AVR32_REG_SP)
21212 +    retval = "0";
21213 +  else if (regid == AVR32_REG_LR)
21214 +    retval = "-1";
21215 +  else
21216 +    retval = "1";
21217 +
21218 +  info->fprintf_func(info->stream, "%s", retval);
21219 +
21220 +  return 1;
21221 +}
21222 +
21223 +static int
21224 +print_mcall(struct avr32_operand *op,
21225 +           struct disassemble_info *info,
21226 +           struct avr32_field_value *ifields)
21227 +{
21228 +  unsigned long regid = ifields[0].value;
21229 +
21230 +  if (regid == AVR32_REG_PC)
21231 +    print_jmplabel(op, info, ifields + 1);
21232 +  else
21233 +    print_intreg_sdisp(op, info, ifields);
21234 +
21235 +  return 2;
21236 +}
21237 +
21238 +static int
21239 +print_jospinc(struct avr32_operand *op ATTRIBUTE_UNUSED,
21240 +             struct disassemble_info *info,
21241 +             struct avr32_field_value *ifields)
21242 +{
21243 +  signed long value = ifields[0].value;
21244 +
21245 +  if (value >= 4)
21246 +    value -= 8;
21247 +  else
21248 +    value += 1;
21249 +
21250 +  info->fprintf_func(info->stream, "%ld", value);
21251 +
21252 +  return 1;
21253 +}
21254 +
21255 +static int
21256 +print_coh(struct avr32_operand *op ATTRIBUTE_UNUSED,
21257 +         struct disassemble_info *info,
21258 +         struct avr32_field_value *ifields ATTRIBUTE_UNUSED)
21259 +{
21260 +  info->fprintf_func(info->stream, "COH");
21261 +  return 0;
21262 +}
21263 +
21264 +#define OP(name, sgn, pcrel, align, func) \
21265 +  { AVR32_OPERAND_##name, pcrel, align, print_##func }
21266 +
21267 +struct avr32_operand operand[AVR32_NR_OPERANDS] =
21268 +  {
21269 +    OP(INTREG, 0, 0, 0, intreg),
21270 +    OP(INTREG_PREDEC, 0, 0, 0, intreg_predec),
21271 +    OP(INTREG_POSTINC, 0, 0, 0, intreg_postinc),
21272 +    OP(INTREG_LSL, 0, 0, 0, intreg_lsl),
21273 +    OP(INTREG_LSR, 0, 0, 0, intreg_lsr),
21274 +    OP(INTREG_BSEL, 0, 0, 0, intreg_bpart),
21275 +    OP(INTREG_HSEL, 0, 0, 1, intreg_hpart),
21276 +    OP(INTREG_SDISP, 1, 0, 0, intreg_sdisp),
21277 +    OP(INTREG_SDISP_H, 1, 0, 1, intreg_sdisp),
21278 +    OP(INTREG_SDISP_W, 1, 0, 2, intreg_sdisp),
21279 +    OP(INTREG_UDISP, 0, 0, 0, intreg_udisp),
21280 +    OP(INTREG_UDISP_H, 0, 0, 1, intreg_udisp),
21281 +    OP(INTREG_UDISP_W, 0, 0, 2, intreg_udisp),
21282 +    OP(INTREG_INDEX, 0, 0, 0, intreg_index),
21283 +    OP(INTREG_XINDEX, 0, 0, 0, intreg_xindex),
21284 +    OP(DWREG, 0, 0, 1, intreg),
21285 +    OP(PC_UDISP_W, 0, 1, 2, pc_disp),
21286 +    OP(SP, 0, 0, 0, sp),
21287 +    OP(SP_UDISP_W, 0, 0, 2, sp_disp),
21288 +    OP(CPNO, 0, 0, 0, cpno),
21289 +    OP(CPREG, 0, 0, 0, cpreg),
21290 +    OP(CPREG_D, 0, 0, 1, cpreg),
21291 +    OP(UNSIGNED_CONST, 0, 0, 0, uconst),
21292 +    OP(UNSIGNED_CONST_W, 0, 0, 2, uconst),
21293 +    OP(SIGNED_CONST, 1, 0, 0, sconst),
21294 +    OP(SIGNED_CONST_W, 1, 0, 2, sconst),
21295 +    OP(JMPLABEL, 1, 1, 1, jmplabel),
21296 +    OP(UNSIGNED_NUMBER, 0, 0, 0, uconst),
21297 +    OP(UNSIGNED_NUMBER_W, 0, 0, 2, uconst),
21298 +    OP(REGLIST8, 0, 0, 0, reglist8),
21299 +    OP(REGLIST9, 0, 0, 0, reglist9),
21300 +    OP(REGLIST16, 0, 0, 0, reglist16),
21301 +    OP(REGLIST_LDM, 0, 0, 0, reglist_ldm),
21302 +    OP(REGLIST_CP8, 0, 0, 0, reglist_cp8),
21303 +    OP(REGLIST_CPD8, 0, 0, 0, reglist_cpd8),
21304 +    OP(RETVAL, 0, 0, 0, retval),
21305 +    OP(MCALL, 1, 0, 2, mcall),
21306 +    OP(JOSPINC, 0, 0, 0, jospinc),
21307 +    OP(COH, 0, 0, 0, coh),
21308 +  };
21309 +
21310 +static void
21311 +print_opcode(bfd_vma insn_word, const struct avr32_opcode *opc,
21312 +            bfd_vma pc, struct disassemble_info *info)
21313 +{
21314 +  const struct avr32_syntax *syntax = opc->syntax;
21315 +  struct avr32_field_value fields[AVR32_MAX_FIELDS];
21316 +  unsigned int i, next_field = 0, nr_operands;
21317 +
21318 +  for (i = 0; i < opc->nr_fields; i++)
21319 +    {
21320 +      opc->fields[i]->extract(opc->fields[i], &insn_word, &fields[i].value);
21321 +      fields[i].ifield = opc->fields[i];
21322 +    }
21323 +
21324 +  current_pc = pc;
21325 +  info->fprintf_func(info->stream, "%s", syntax->mnemonic->name);
21326 +
21327 +  if (syntax->nr_operands < 0)
21328 +    nr_operands = (unsigned int) -syntax->nr_operands;
21329 +  else
21330 +    nr_operands = (unsigned int) syntax->nr_operands;
21331 +
21332 +  for (i = 0; i < nr_operands; i++)
21333 +    {
21334 +      struct avr32_operand *op = &operand[syntax->operand[i]];
21335 +
21336 +      if (i)
21337 +       info->fprintf_func(info->stream, ",");
21338 +      else
21339 +       info->fprintf_func(info->stream, "\t");
21340 +      next_field += op->print(op, info, &fields[next_field]);
21341 +    }
21342 +}
21343 +
21344 +#define is_fpu_insn(iw) ((iw&0xf9f0e000)==0xe1a00000)
21345 +
21346 +static const struct avr32_opcode *
21347 +find_opcode(bfd_vma insn_word)
21348 +{
21349 +  int i;
21350 +
21351 +  for (i = 0; i < AVR32_NR_OPCODES; i++)
21352 +    {
21353 +      const struct avr32_opcode *opc = &avr32_opc_table[i];
21354 +
21355 +      if ((insn_word & opc->mask) == opc->value)
21356 +      {
21357 +        if (avr32_opt_decode_fpu)
21358 +        {
21359 +          if (is_fpu_insn(insn_word))
21360 +          {
21361 +            if (opc->id != AVR32_OPC_COP)
21362 +              return opc;
21363 +          }
21364 +          else
21365 +            return opc;
21366 +        }
21367 +        else
21368 +       return opc;
21369 +    }
21370 +   }
21371 +
21372 +  return NULL;
21373 +}
21374 +
21375 +static int
21376 +read_insn_word(bfd_vma pc, bfd_vma *valuep,
21377 +              struct disassemble_info *info)
21378 +{
21379 +  bfd_byte b[4];
21380 +  int status;
21381 +
21382 +  status = info->read_memory_func(pc, b, 4, info);
21383 +  if (status)
21384 +    {
21385 +      status = info->read_memory_func(pc, b, 2, info);
21386 +      if (status)
21387 +       {
21388 +         info->memory_error_func(status, pc, info);
21389 +         return -1;
21390 +       }
21391 +      b[3] = b[2] = 0;
21392 +    }
21393 +
21394 +  *valuep =  (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
21395 +  return 0;
21396 +}
21397 +
21398 +/* Parse an individual disassembler option.  */
21399 +
21400 +void
21401 +parse_avr32_disassembler_option (option)
21402 +     char * option;
21403 +{
21404 +  if (option == NULL)
21405 +    return;
21406 +
21407 +  if (!strcmp(option,"decode-fpu"))
21408 +  {
21409 +    avr32_opt_decode_fpu = 1;
21410 +    return;
21411 +  }
21412 +
21413 +  printf("\n%s--",option);
21414 +  /* XXX - should break 'option' at following delimiter.  */
21415 +  fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
21416 +
21417 +  return;
21418 +}
21419 +
21420 +/* Parse the string of disassembler options, spliting it at whitespaces
21421 +   or commas.  (Whitespace separators supported for backwards compatibility).  */
21422 +
21423 +static void
21424 +parse_disassembler_options (char *options)
21425 +{
21426 +  if (options == NULL)
21427 +    return;
21428 +
21429 +  while (*options)
21430 +    {
21431 +      parse_avr32_disassembler_option (options);
21432 +
21433 +      /* Skip forward to next seperator.  */
21434 +      while ((*options) && (! ISSPACE (*options)) && (*options != ','))
21435 +       ++ options;
21436 +      /* Skip forward past seperators.  */
21437 +      while (ISSPACE (*options) || (*options == ','))
21438 +       ++ options;
21439 +    }
21440 +}
21441 +
21442 +int
21443 +print_insn_avr32(bfd_vma pc, struct disassemble_info *info)
21444 +{
21445 +  bfd_vma insn_word;
21446 +  const struct avr32_opcode *opc;
21447 +
21448 +  if (info->disassembler_options)
21449 +    {
21450 +      parse_disassembler_options (info->disassembler_options);
21451 +
21452 +      /* To avoid repeated parsing of these options, we remove them here.  */
21453 +      info->disassembler_options = NULL;
21454 +    }
21455 +
21456 +  info->bytes_per_chunk = 1;
21457 +  info->display_endian = BFD_ENDIAN_BIG;
21458 +
21459 +  if (read_insn_word(pc, &insn_word, info))
21460 +    return -1;
21461 +
21462 +  opc = find_opcode(insn_word);
21463 +  if (opc)
21464 +    {
21465 +      print_opcode(insn_word, opc, pc, info);
21466 +      return opc->size;
21467 +    }
21468 +  else
21469 +    {
21470 +      info->fprintf_func(info->stream, _("*unknown*"));
21471 +      return 2;
21472 +    }
21473 +
21474 +}
21475 +
21476 +void
21477 +print_avr32_disassembler_options (FILE *stream ATTRIBUTE_UNUSED)
21478 +{
21479 +  fprintf(stream, "\n AVR32 Specific Disassembler Options:\n");
21480 +  fprintf(stream, "  -M decode-fpu                  Print FPU instructions instead of 'cop' \n");
21481 +}
21482 +
21483 --- /dev/null
21484 +++ b/opcodes/avr32-opc.c
21485 @@ -0,0 +1,6906 @@
21486 +/* Opcode tables for AVR32.
21487 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
21488 +
21489 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
21490 +
21491 +   This file is part of libopcodes.
21492 +
21493 +   This program is free software; you can redistribute it and/or
21494 +   modify it under the terms of the GNU General Public License as
21495 +   published by the Free Software Foundation; either version 2 of the
21496 +   License, or (at your option) any later version.
21497 +
21498 +   This program is distributed in the hope that it will be useful, but
21499 +   WITHOUT ANY WARRANTY; without even the implied warranty of
21500 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
21501 +   General Public License for more details.
21502 +
21503 +   You should have received a copy of the GNU General Public License
21504 +   along with this program; if not, write to the Free Software
21505 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
21506 +   02111-1307, USA.  */
21507 +
21508 +#include <stdlib.h>
21509 +#include <assert.h>
21510 +
21511 +#include "avr32-opc.h"
21512 +
21513 +#define PICO_CPNO      1
21514 +
21515 +void
21516 +avr32_insert_simple(const struct avr32_ifield *field,
21517 +                   void *buf, unsigned long value)
21518 +{
21519 +  bfd_vma word;
21520 +
21521 +  word = bfd_getb32(buf);
21522 +  word &= ~field->mask;
21523 +  word |= (value << field->shift) & field->mask;
21524 +  bfd_putb32(word, buf);
21525 +}
21526 +
21527 +void
21528 +avr32_insert_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21529 +                  void *buf, unsigned long value)
21530 +{
21531 +  char *opcode = buf;
21532 +
21533 +  opcode[0] = (opcode[0] & 0xe1) | (value & 0x1e);
21534 +  opcode[1] = (opcode[1] & 0xef) | ((value & 1) << 4);
21535 +}
21536 +
21537 +void
21538 +avr32_insert_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21539 +                void *buf, unsigned long value)
21540 +{
21541 +  char *opcode = buf;
21542 +
21543 +  opcode[0] = (opcode[0] & 0xf0) | ((value & 0xf0) >> 4);
21544 +  opcode[1] = ((opcode[1] & 0x0c) | ((value & 0x0f) << 4)
21545 +              | ((value & 0x300) >> 8));
21546 +}
21547 +
21548 +
21549 +void
21550 +avr32_insert_k21(const struct avr32_ifield *field,
21551 +                void *buf, unsigned long value)
21552 +{
21553 +  bfd_vma word;
21554 +  bfd_vma k21;
21555 +
21556 +  word = bfd_getb32(buf);
21557 +  word &= ~field->mask;
21558 +  k21 = ((value & 0xffff) | ((value & 0x10000) << 4)
21559 +        | ((value & 0x1e0000) << 8));
21560 +  assert(!(k21 & ~field->mask));
21561 +  word |= k21;
21562 +  bfd_putb32(word, buf);
21563 +}
21564 +
21565 +void
21566 +avr32_insert_cpop(const struct avr32_ifield *field,
21567 +                 void *buf, unsigned long value)
21568 +{
21569 +  bfd_vma word;
21570 +
21571 +  word = bfd_getb32(buf);
21572 +  word &= ~field->mask;
21573 +  word |= (((value & 0x1e) << 15) | ((value & 0x60) << 20)
21574 +          | ((value & 0x01) << 12));
21575 +  bfd_putb32(word, buf);
21576 +}
21577 +
21578 +void
21579 +avr32_insert_k12cp(const struct avr32_ifield *field,
21580 +                  void *buf, unsigned long value)
21581 +{
21582 +  bfd_vma word;
21583 +
21584 +  word = bfd_getb32(buf);
21585 +  word &= ~field->mask;
21586 +  word |= ((value & 0xf00) << 4) | (value & 0xff);
21587 +  bfd_putb32(word, buf);
21588 +}
21589 +
21590 +void avr32_extract_simple(const struct avr32_ifield *field,
21591 +                         void *buf, unsigned long *value)
21592 +{
21593 +  /* XXX: The disassembler has done any necessary byteswapping already */
21594 +  bfd_vma word = *(bfd_vma *)buf;
21595 +
21596 +  *value = (word & field->mask) >> field->shift;
21597 +}
21598 +
21599 +void avr32_extract_bit5c(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21600 +                        void *buf, unsigned long *value)
21601 +{
21602 +  bfd_vma word = *(bfd_vma *)buf;
21603 +
21604 +  *value = ((word >> 20) & 1) | ((word >> 24) & 0x1e);
21605 +}
21606 +
21607 +void avr32_extract_k10(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21608 +                      void *buf, unsigned long *value)
21609 +{
21610 +  bfd_vma word = *(bfd_vma *)buf;
21611 +
21612 +  *value = ((word >> 8) & 0x300) | ((word >> 20) & 0xff);
21613 +}
21614 +
21615 +void avr32_extract_k21(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21616 +                      void *buf, unsigned long *value)
21617 +{
21618 +  bfd_vma word = *(bfd_vma *)buf;
21619 +
21620 +  *value = ((word & 0xffff) | ((word >> 4) & 0x10000)
21621 +           | ((word >> 8) & 0x1e0000));
21622 +}
21623 +
21624 +void avr32_extract_cpop(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21625 +                       void *buf, unsigned long *value)
21626 +{
21627 +  bfd_vma word = *(bfd_vma *)buf;
21628 +
21629 +  *value = (((word >> 12) & 1) | ((word >> 15) & 0x1e)
21630 +           | ((word >> 20) & 0x60));
21631 +}
21632 +
21633 +void avr32_extract_k12cp(const struct avr32_ifield *field ATTRIBUTE_UNUSED,
21634 +                        void *buf, unsigned long *value)
21635 +{
21636 +  bfd_vma word = *(bfd_vma *)buf;
21637 +
21638 +  *value = ((word >> 4) & 0xf00) | (word & 0xff);
21639 +}
21640 +
21641 +
21642 +#define IFLD(id, bitsz, shift, mask, func) \
21643 +  { AVR32_IFIELD_##id, bitsz, shift, mask, \
21644 +    avr32_insert_##func, avr32_extract_##func }
21645 +
21646 +const struct avr32_ifield avr32_ifield_table[] =
21647 +  {
21648 +    IFLD(RX, 4, 25, 0x1e000000, simple),
21649 +    IFLD(RY, 4, 16, 0x000f0000, simple),
21650 +    IFLD(COND4C, 4, 20, 0x00f00000, simple),
21651 +    IFLD(K8C, 8, 20, 0x0ff00000, simple),
21652 +    IFLD(K7C, 7, 20, 0x07f00000, simple),
21653 +    IFLD(K5C, 5, 20, 0x01f00000, simple),
21654 +    IFLD(K3, 3, 20, 0x00700000, simple),
21655 +    IFLD(RY_DW, 3, 17, 0x000e0000, simple),
21656 +    IFLD(COND4E, 4, 8, 0x00000f00, simple),
21657 +    IFLD(K8E, 8, 0, 0x000000ff, simple),
21658 +    IFLD(BIT5C, 5, 20, 0x1e100000, bit5c),
21659 +    IFLD(COND3, 3, 16, 0x00070000, simple),
21660 +    IFLD(K10, 10, 16, 0x0ff30000, k10),
21661 +    IFLD(POPM, 9, 19, 0x0ff80000, simple),
21662 +    IFLD(K2, 2, 4, 0x00000030, simple),
21663 +    IFLD(RD_E, 4, 0, 0x0000000f, simple),
21664 +    IFLD(RD_DW, 3, 1, 0x0000000e, simple),
21665 +    IFLD(X, 1, 5, 0x00000020, simple),
21666 +    IFLD(Y, 1, 4, 0x00000010, simple),
21667 +    IFLD(X2, 1, 13, 0x00002000, simple),
21668 +    IFLD(Y2, 1, 12, 0x00001000, simple),
21669 +    IFLD(K5E, 5, 0, 0x0000001f, simple),
21670 +    IFLD(PART2, 2, 0, 0x00000003, simple),
21671 +    IFLD(PART1, 1, 0, 0x00000001, simple),
21672 +    IFLD(K16, 16, 0, 0x0000ffff, simple),
21673 +    IFLD(CACHEOP, 5, 11, 0x0000f800, simple),
21674 +    IFLD(K11, 11, 0, 0x000007ff, simple),
21675 +    IFLD(K21, 21, 0, 0x1e10ffff, k21),
21676 +    IFLD(CPOP, 7, 12, 0x060f1000, cpop),
21677 +    IFLD(CPNO, 3, 13, 0x0000e000, simple),
21678 +    IFLD(CRD_RI, 4, 8, 0x00000f00, simple),
21679 +    IFLD(CRX, 4, 4, 0x000000f0, simple),
21680 +    IFLD(CRY, 4, 0, 0x0000000f, simple),
21681 +    IFLD(K7E, 7, 0, 0x0000007f, simple),
21682 +    IFLD(CRD_DW, 3, 9, 0x00000e00, simple),
21683 +    IFLD(PART1_K12, 1, 12, 0x00001000, simple),
21684 +    IFLD(PART2_K12, 2, 12, 0x00003000, simple),
21685 +    IFLD(K12, 12, 0, 0x00000fff, simple),
21686 +    IFLD(S5, 5, 5, 0x000003e0, simple),
21687 +    IFLD(K5E2, 5, 4, 0x000001f0, simple),
21688 +    IFLD(K4, 4, 20, 0x00f00000, simple),
21689 +    IFLD(COND4E2, 4, 4, 0x000000f0, simple),
21690 +    IFLD(K8E2, 8, 4, 0x00000ff0, simple),
21691 +    IFLD(K6, 6, 20, 0x03f00000, simple),
21692 +    IFLD(MEM15, 15, 0, 0x00007fff, simple),
21693 +    IFLD(MEMB5, 5, 15, 0x000f8000, simple),
21694 +    IFLD(W, 1, 25, 0x02000000, simple),
21695 +    /* Coprocessor Multiple High/Low */
21696 +    IFLD(CM_HL, 1, 8, 0x00000100, simple),
21697 +    IFLD(K12CP, 12 ,0, 0x0000f0ff, k12cp),
21698 +    IFLD(K9E, 9 ,0, 0x000001ff, simple),
21699 +    IFLD (FP_RX, 4,  4, 0x000000F0, simple),
21700 +    IFLD (FP_RY, 4,  0, 0x0000000F, simple),
21701 +    IFLD (FP_RD, 4,  8, 0x00000F00, simple),
21702 +    IFLD (FP_RA, 4, 16, 0x000F0000, simple)
21703 +  };
21704 +#undef IFLD
21705 +
21706 +
21707 +struct avr32_opcode avr32_opc_table[] =
21708 +  {
21709 +    {
21710 +      AVR32_OPC_ABS, 2, 0x5c400000, 0xfff00000,
21711 +      &avr32_syntax_table[AVR32_SYNTAX_ABS],
21712 +      BFD_RELOC_UNUSED, 1, -1,
21713 +      {
21714 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21715 +      }
21716 +    },
21717 +    {
21718 +      AVR32_OPC_ACALL, 2, 0xd0000000, 0xf00f0000,
21719 +      &avr32_syntax_table[AVR32_SYNTAX_ACALL],
21720 +      BFD_RELOC_UNUSED, 1, -1,
21721 +      {
21722 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21723 +      },
21724 +    },
21725 +    {
21726 +      AVR32_OPC_ACR, 2, 0x5c000000, 0xfff00000,
21727 +      &avr32_syntax_table[AVR32_SYNTAX_ACR],
21728 +      BFD_RELOC_UNUSED, 1, -1,
21729 +      {
21730 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21731 +      },
21732 +    },
21733 +    {
21734 +      AVR32_OPC_ADC, 4, 0xe0000040, 0xe1f0fff0,
21735 +      &avr32_syntax_table[AVR32_SYNTAX_ADC],
21736 +      BFD_RELOC_UNUSED, 3, -1,
21737 +      {
21738 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21739 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21740 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21741 +      },
21742 +    },
21743 +    {
21744 +      AVR32_OPC_ADD1, 2, 0x00000000, 0xe1f00000,
21745 +      &avr32_syntax_table[AVR32_SYNTAX_ADD1],
21746 +      BFD_RELOC_UNUSED, 2, -1,
21747 +      {
21748 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21749 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21750 +      },
21751 +    },
21752 +    {
21753 +      AVR32_OPC_ADD2, 4, 0xe0000000, 0xe1f0ffc0,
21754 +      &avr32_syntax_table[AVR32_SYNTAX_ADD2],
21755 +      BFD_RELOC_UNUSED, 4, -1,
21756 +      {
21757 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21758 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21759 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21760 +       &avr32_ifield_table[AVR32_IFIELD_K2],
21761 +      },
21762 +    },
21763 +    {
21764 +      AVR32_OPC_ADDABS, 4, 0xe0000e40, 0xe1f0fff0,
21765 +      &avr32_syntax_table[AVR32_SYNTAX_ADDABS],
21766 +      BFD_RELOC_UNUSED, 3, -1,
21767 +      {
21768 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21769 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21770 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21771 +      },
21772 +    },
21773 +    {
21774 +      AVR32_OPC_ADDHH_W, 4, 0xe0000e00, 0xe1f0ffc0,
21775 +      &avr32_syntax_table[AVR32_SYNTAX_ADDHH_W],
21776 +      BFD_RELOC_UNUSED, 5, -1,
21777 +      {
21778 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21779 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21780 +       &avr32_ifield_table[AVR32_IFIELD_X],
21781 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21782 +       &avr32_ifield_table[AVR32_IFIELD_Y],
21783 +      },
21784 +    },
21785 +    {
21786 +      AVR32_OPC_AND1, 2, 0x00600000, 0xe1f00000,
21787 +      &avr32_syntax_table[AVR32_SYNTAX_AND1],
21788 +      BFD_RELOC_UNUSED, 2, -1,
21789 +      {
21790 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21791 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21792 +      },
21793 +    },
21794 +    {
21795 +      AVR32_OPC_AND2, 4, 0xe1e00000, 0xe1f0fe00,
21796 +      &avr32_syntax_table[AVR32_SYNTAX_AND2],
21797 +      BFD_RELOC_UNUSED, 4, -1,
21798 +      {
21799 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21800 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21801 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21802 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
21803 +      },
21804 +    },
21805 +    {
21806 +      AVR32_OPC_AND3, 4, 0xe1e00200, 0xe1f0fe00,
21807 +      &avr32_syntax_table[AVR32_SYNTAX_AND3],
21808 +      BFD_RELOC_UNUSED, 4, -1,
21809 +      {
21810 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21811 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21812 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21813 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
21814 +      },
21815 +    },
21816 +    {
21817 +      AVR32_OPC_ANDH, 4, 0xe4100000, 0xfff00000,
21818 +      &avr32_syntax_table[AVR32_SYNTAX_ANDH],
21819 +      BFD_RELOC_AVR32_16U, 2, 1,
21820 +      {
21821 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21822 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21823 +      },
21824 +    },
21825 +    {
21826 +      AVR32_OPC_ANDH_COH, 4, 0xe6100000, 0xfff00000,
21827 +      &avr32_syntax_table[AVR32_SYNTAX_ANDH_COH],
21828 +      BFD_RELOC_AVR32_16U, 2, 1,
21829 +      {
21830 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21831 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21832 +      },
21833 +    },
21834 +    {
21835 +      AVR32_OPC_ANDL, 4, 0xe0100000, 0xfff00000,
21836 +      &avr32_syntax_table[AVR32_SYNTAX_ANDL],
21837 +      BFD_RELOC_AVR32_16U, 2, 1,
21838 +      {
21839 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21840 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21841 +      },
21842 +    },
21843 +    {
21844 +      AVR32_OPC_ANDL_COH, 4, 0xe2100000, 0xfff00000,
21845 +      &avr32_syntax_table[AVR32_SYNTAX_ANDL_COH],
21846 +      BFD_RELOC_AVR32_16U, 2, 1,
21847 +      {
21848 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21849 +       &avr32_ifield_table[AVR32_IFIELD_K16],
21850 +      },
21851 +    },
21852 +    {
21853 +      AVR32_OPC_ANDN, 2, 0x00800000, 0xe1f00000,
21854 +      &avr32_syntax_table[AVR32_SYNTAX_ANDN],
21855 +      BFD_RELOC_UNUSED, 2, -1,
21856 +      {
21857 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21858 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21859 +      },
21860 +    },
21861 +    {
21862 +      AVR32_OPC_ASR1, 4, 0xe0000840, 0xe1f0fff0,
21863 +      &avr32_syntax_table[AVR32_SYNTAX_ASR1],
21864 +      BFD_RELOC_UNUSED, 3, -1,
21865 +      {
21866 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
21867 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21868 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21869 +      },
21870 +    },
21871 +    {
21872 +      AVR32_OPC_ASR3, 4, 0xe0001400, 0xe1f0ffe0,
21873 +      &avr32_syntax_table[AVR32_SYNTAX_ASR3],
21874 +      BFD_RELOC_UNUSED, 3, -1,
21875 +      {
21876 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21877 +       &avr32_ifield_table[AVR32_IFIELD_RX],
21878 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
21879 +      },
21880 +    },
21881 +    {
21882 +      AVR32_OPC_ASR2, 2, 0xa1400000, 0xe1e00000,
21883 +      &avr32_syntax_table[AVR32_SYNTAX_ASR2],
21884 +      BFD_RELOC_UNUSED, 2, -1,
21885 +      {
21886 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21887 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
21888 +      },
21889 +    },
21890 +    {
21891 +      AVR32_OPC_BLD, 4, 0xedb00000, 0xfff0ffe0,
21892 +      &avr32_syntax_table[AVR32_SYNTAX_BLD],
21893 +      BFD_RELOC_UNUSED, 2, -1,
21894 +      {
21895 +       &avr32_ifield_table[AVR32_IFIELD_RY],
21896 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
21897 +      },
21898 +    },
21899 +    {
21900 +      AVR32_OPC_BREQ1, 2, 0xc0000000, 0xf00f0000,
21901 +      &avr32_syntax_table[AVR32_SYNTAX_BREQ1],
21902 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21903 +      {
21904 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21905 +      },
21906 +    },
21907 +    {
21908 +      AVR32_OPC_BRNE1, 2, 0xc0010000, 0xf00f0000,
21909 +      &avr32_syntax_table[AVR32_SYNTAX_BRNE1],
21910 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21911 +      {
21912 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21913 +      },
21914 +    },
21915 +    {
21916 +      AVR32_OPC_BRCC1, 2, 0xc0020000, 0xf00f0000,
21917 +      &avr32_syntax_table[AVR32_SYNTAX_BRCC1],
21918 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21919 +      {
21920 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21921 +      },
21922 +    },
21923 +    {
21924 +      AVR32_OPC_BRCS1, 2, 0xc0030000, 0xf00f0000,
21925 +      &avr32_syntax_table[AVR32_SYNTAX_BRCS1],
21926 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21927 +      {
21928 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21929 +      },
21930 +    },
21931 +    {
21932 +      AVR32_OPC_BRGE1, 2, 0xc0040000, 0xf00f0000,
21933 +      &avr32_syntax_table[AVR32_SYNTAX_BRGE1],
21934 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21935 +      {
21936 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21937 +      },
21938 +    },
21939 +    {
21940 +      AVR32_OPC_BRLT1, 2, 0xc0050000, 0xf00f0000,
21941 +      &avr32_syntax_table[AVR32_SYNTAX_BRLT1],
21942 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21943 +      {
21944 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21945 +      },
21946 +    },
21947 +    {
21948 +      AVR32_OPC_BRMI1, 2, 0xc0060000, 0xf00f0000,
21949 +      &avr32_syntax_table[AVR32_SYNTAX_BRMI1],
21950 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21951 +      {
21952 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21953 +      },
21954 +    },
21955 +    {
21956 +      AVR32_OPC_BRPL1, 2, 0xc0070000, 0xf00f0000,
21957 +      &avr32_syntax_table[AVR32_SYNTAX_BRPL1],
21958 +      BFD_RELOC_AVR32_9H_PCREL, 1, 0,
21959 +      {
21960 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
21961 +      },
21962 +    },
21963 +    {
21964 +      AVR32_OPC_BREQ2, 4, 0xe0800000, 0xe1ef0000,
21965 +      &avr32_syntax_table[AVR32_SYNTAX_BREQ2],
21966 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21967 +      {
21968 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21969 +      },
21970 +    },
21971 +    {
21972 +      AVR32_OPC_BRNE2, 4, 0xe0810000, 0xe1ef0000,
21973 +      &avr32_syntax_table[AVR32_SYNTAX_BRNE2],
21974 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21975 +      {
21976 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21977 +      },
21978 +    },
21979 +    {
21980 +      AVR32_OPC_BRCC2, 4, 0xe0820000, 0xe1ef0000,
21981 +      &avr32_syntax_table[AVR32_SYNTAX_BRHS2],
21982 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21983 +      {
21984 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21985 +      },
21986 +    },
21987 +    {
21988 +      AVR32_OPC_BRCS2, 4, 0xe0830000, 0xe1ef0000,
21989 +      &avr32_syntax_table[AVR32_SYNTAX_BRLO2],
21990 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21991 +      {
21992 +       &avr32_ifield_table[AVR32_IFIELD_K21],
21993 +      },
21994 +    },
21995 +    {
21996 +      AVR32_OPC_BRGE2, 4, 0xe0840000, 0xe1ef0000,
21997 +      &avr32_syntax_table[AVR32_SYNTAX_BRGE2],
21998 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
21999 +      {
22000 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22001 +      },
22002 +    },
22003 +    {
22004 +      AVR32_OPC_BRLT2, 4, 0xe0850000, 0xe1ef0000,
22005 +      &avr32_syntax_table[AVR32_SYNTAX_BRLT2],
22006 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22007 +      {
22008 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22009 +      },
22010 +    },
22011 +    {
22012 +      AVR32_OPC_BRMI2, 4, 0xe0860000, 0xe1ef0000,
22013 +      &avr32_syntax_table[AVR32_SYNTAX_BRMI2],
22014 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22015 +      {
22016 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22017 +      },
22018 +    },
22019 +    {
22020 +      AVR32_OPC_BRPL2, 4, 0xe0870000, 0xe1ef0000,
22021 +      &avr32_syntax_table[AVR32_SYNTAX_BRPL2],
22022 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22023 +      {
22024 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22025 +      },
22026 +    },
22027 +    {
22028 +      AVR32_OPC_BRLS, 4, 0xe0880000, 0xe1ef0000,
22029 +      &avr32_syntax_table[AVR32_SYNTAX_BRLS],
22030 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22031 +      {
22032 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22033 +      },
22034 +    },
22035 +    {
22036 +      AVR32_OPC_BRGT, 4, 0xe0890000, 0xe1ef0000,
22037 +      &avr32_syntax_table[AVR32_SYNTAX_BRGT],
22038 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22039 +      {
22040 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22041 +      },
22042 +    },
22043 +    {
22044 +      AVR32_OPC_BRLE, 4, 0xe08a0000, 0xe1ef0000,
22045 +      &avr32_syntax_table[AVR32_SYNTAX_BRLE],
22046 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22047 +      {
22048 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22049 +      },
22050 +    },
22051 +    {
22052 +      AVR32_OPC_BRHI, 4, 0xe08b0000, 0xe1ef0000,
22053 +      &avr32_syntax_table[AVR32_SYNTAX_BRHI],
22054 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22055 +      {
22056 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22057 +      },
22058 +    },
22059 +    {
22060 +      AVR32_OPC_BRVS, 4, 0xe08c0000, 0xe1ef0000,
22061 +      &avr32_syntax_table[AVR32_SYNTAX_BRVS],
22062 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22063 +      {
22064 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22065 +      },
22066 +    },
22067 +    {
22068 +      AVR32_OPC_BRVC, 4, 0xe08d0000, 0xe1ef0000,
22069 +      &avr32_syntax_table[AVR32_SYNTAX_BRVC],
22070 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22071 +      {
22072 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22073 +      },
22074 +    },
22075 +    {
22076 +      AVR32_OPC_BRQS, 4, 0xe08e0000, 0xe1ef0000,
22077 +      &avr32_syntax_table[AVR32_SYNTAX_BRQS],
22078 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22079 +      {
22080 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22081 +      },
22082 +    },
22083 +    {
22084 +      AVR32_OPC_BRAL, 4, 0xe08f0000, 0xe1ef0000,
22085 +      &avr32_syntax_table[AVR32_SYNTAX_BRAL],
22086 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
22087 +      {
22088 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22089 +      },
22090 +    },
22091 +    {
22092 +      AVR32_OPC_BREAKPOINT, 2, 0xd6730000, 0xffff0000,
22093 +      &avr32_syntax_table[AVR32_SYNTAX_BREAKPOINT],
22094 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
22095 +    },
22096 +    {
22097 +      AVR32_OPC_BREV, 2, 0x5c900000, 0xfff00000,
22098 +      &avr32_syntax_table[AVR32_SYNTAX_BREV],
22099 +      BFD_RELOC_UNUSED, 1, -1,
22100 +      {
22101 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22102 +      },
22103 +    },
22104 +    {
22105 +      AVR32_OPC_BST, 4, 0xefb00000, 0xfff0ffe0,
22106 +      &avr32_syntax_table[AVR32_SYNTAX_BST],
22107 +      BFD_RELOC_UNUSED, 2, -1,
22108 +      {
22109 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22110 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
22111 +      },
22112 +    },
22113 +    {
22114 +      AVR32_OPC_CACHE, 4, 0xf4100000, 0xfff00000,
22115 +      &avr32_syntax_table[AVR32_SYNTAX_CACHE],
22116 +      BFD_RELOC_UNUSED, 3, -1,
22117 +      {
22118 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22119 +       &avr32_ifield_table[AVR32_IFIELD_K11],
22120 +       &avr32_ifield_table[AVR32_IFIELD_CACHEOP],
22121 +      },
22122 +    },
22123 +    {
22124 +      AVR32_OPC_CASTS_B, 2, 0x5c600000, 0xfff00000,
22125 +      &avr32_syntax_table[AVR32_SYNTAX_CASTS_B],
22126 +      BFD_RELOC_UNUSED, 1, -1,
22127 +      {
22128 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22129 +      },
22130 +    },
22131 +    {
22132 +      AVR32_OPC_CASTS_H, 2, 0x5c800000, 0xfff00000,
22133 +      &avr32_syntax_table[AVR32_SYNTAX_CASTS_H],
22134 +      BFD_RELOC_UNUSED, 1, -1,
22135 +      {
22136 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22137 +      },
22138 +    },
22139 +    {
22140 +      AVR32_OPC_CASTU_B, 2, 0x5c500000, 0xfff00000,
22141 +      &avr32_syntax_table[AVR32_SYNTAX_CASTU_B],
22142 +      BFD_RELOC_UNUSED, 1, -1,
22143 +      {
22144 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22145 +      },
22146 +    },
22147 +    {
22148 +      AVR32_OPC_CASTU_H, 2, 0x5c700000, 0xfff00000,
22149 +      &avr32_syntax_table[AVR32_SYNTAX_CASTU_H],
22150 +      BFD_RELOC_UNUSED, 1, -1,
22151 +      {
22152 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22153 +      },
22154 +    },
22155 +    {
22156 +      AVR32_OPC_CBR, 2, 0xa1c00000, 0xe1e00000,
22157 +      &avr32_syntax_table[AVR32_SYNTAX_CBR],
22158 +      BFD_RELOC_UNUSED, 2, -1,
22159 +      {
22160 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22161 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
22162 +      },
22163 +    },
22164 +    {
22165 +      AVR32_OPC_CLZ, 4, 0xe0001200, 0xe1f0ffff,
22166 +      &avr32_syntax_table[AVR32_SYNTAX_CLZ],
22167 +      BFD_RELOC_UNUSED, 2, -1,
22168 +      {
22169 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22170 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22171 +      },
22172 +    },
22173 +    {
22174 +      AVR32_OPC_COM, 2, 0x5cd00000, 0xfff00000,
22175 +      &avr32_syntax_table[AVR32_SYNTAX_COM],
22176 +      BFD_RELOC_UNUSED, 1, -1,
22177 +      {
22178 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22179 +      },
22180 +    },
22181 +    {
22182 +      AVR32_OPC_COP, 4, 0xe1a00000, 0xf9f00000,
22183 +      &avr32_syntax_table[AVR32_SYNTAX_COP],
22184 +      BFD_RELOC_UNUSED, 5, -1,
22185 +      {
22186 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22187 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22188 +       &avr32_ifield_table[AVR32_IFIELD_CRX],
22189 +       &avr32_ifield_table[AVR32_IFIELD_CRY],
22190 +       &avr32_ifield_table[AVR32_IFIELD_CPOP],
22191 +      },
22192 +    },
22193 +    {
22194 +      AVR32_OPC_CP_B, 4, 0xe0001800, 0xe1f0ffff,
22195 +      &avr32_syntax_table[AVR32_SYNTAX_CP_B],
22196 +      BFD_RELOC_UNUSED, 2, -1,
22197 +      {
22198 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22199 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22200 +      },
22201 +    },
22202 +    {
22203 +      AVR32_OPC_CP_H, 4, 0xe0001900, 0xe1f0ffff,
22204 +      &avr32_syntax_table[AVR32_SYNTAX_CP_H],
22205 +      BFD_RELOC_UNUSED, 2, -1,
22206 +      {
22207 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22208 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22209 +      },
22210 +    },
22211 +    {
22212 +      AVR32_OPC_CP_W1, 2, 0x00300000, 0xe1f00000,
22213 +      &avr32_syntax_table[AVR32_SYNTAX_CP_W1],
22214 +      BFD_RELOC_UNUSED, 2, -1,
22215 +      {
22216 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22217 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22218 +      },
22219 +    },
22220 +    {
22221 +      AVR32_OPC_CP_W2, 2, 0x58000000, 0xfc000000,
22222 +      &avr32_syntax_table[AVR32_SYNTAX_CP_W2],
22223 +      BFD_RELOC_AVR32_6S, 2, 1,
22224 +      {
22225 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22226 +       &avr32_ifield_table[AVR32_IFIELD_K6],
22227 +      },
22228 +    },
22229 +    {
22230 +      AVR32_OPC_CP_W3, 4, 0xe0400000, 0xe1e00000,
22231 +      &avr32_syntax_table[AVR32_SYNTAX_CP_W3],
22232 +      BFD_RELOC_AVR32_21S, 2, 1,
22233 +      {
22234 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22235 +       &avr32_ifield_table[AVR32_IFIELD_K21],
22236 +      },
22237 +    },
22238 +    {
22239 +      AVR32_OPC_CPC1, 4, 0xe0001300, 0xe1f0ffff,
22240 +      &avr32_syntax_table[AVR32_SYNTAX_CPC1],
22241 +      BFD_RELOC_UNUSED, 2, -1,
22242 +      {
22243 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22244 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22245 +      },
22246 +    },
22247 +    {
22248 +      AVR32_OPC_CPC2, 2, 0x5c200000, 0xfff00000,
22249 +      &avr32_syntax_table[AVR32_SYNTAX_CPC2],
22250 +      BFD_RELOC_UNUSED, 1, -1,
22251 +      {
22252 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22253 +      },
22254 +    },
22255 +    {
22256 +      AVR32_OPC_CSRF, 2, 0xd4030000, 0xfe0f0000,
22257 +      &avr32_syntax_table[AVR32_SYNTAX_CSRF],
22258 +      BFD_RELOC_UNUSED, 1, -1,
22259 +      {
22260 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
22261 +      },
22262 +    },
22263 +    {
22264 +      AVR32_OPC_CSRFCZ, 2, 0xd0030000, 0xfe0f0000,
22265 +      &avr32_syntax_table[AVR32_SYNTAX_CSRFCZ],
22266 +      BFD_RELOC_UNUSED, 1, -1,
22267 +      {
22268 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
22269 +      },
22270 +    },
22271 +    {
22272 +      AVR32_OPC_DIVS, 4, 0xe0000c00, 0xe1f0ffc0,
22273 +      &avr32_syntax_table[AVR32_SYNTAX_DIVS],
22274 +      BFD_RELOC_UNUSED, 3, -1,
22275 +      {
22276 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22277 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22278 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22279 +      },
22280 +    },
22281 +    {
22282 +      AVR32_OPC_DIVU, 4, 0xe0000d00, 0xe1f0ffc0,
22283 +      &avr32_syntax_table[AVR32_SYNTAX_DIVU],
22284 +      BFD_RELOC_UNUSED, 3, -1,
22285 +      {
22286 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22287 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22288 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22289 +      },
22290 +    },
22291 +    {
22292 +      AVR32_OPC_EOR1, 2, 0x00500000, 0xe1f00000,
22293 +      &avr32_syntax_table[AVR32_SYNTAX_EOR1],
22294 +      BFD_RELOC_UNUSED, 2, -1,
22295 +      {
22296 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22297 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22298 +      },
22299 +    },
22300 +    {
22301 +      AVR32_OPC_EOR2, 4, 0xe1e02000, 0xe1f0fe00,
22302 +      &avr32_syntax_table[AVR32_SYNTAX_EOR2],
22303 +      BFD_RELOC_UNUSED, 4, -1,
22304 +      {
22305 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22306 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22307 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22308 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
22309 +      }
22310 +    },
22311 +    {
22312 +      AVR32_OPC_EOR3, 4, 0xe1e02200, 0xe1f0fe00,
22313 +      &avr32_syntax_table[AVR32_SYNTAX_EOR3],
22314 +      BFD_RELOC_UNUSED, 4, -1,
22315 +      {
22316 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22317 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22318 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22319 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
22320 +      }
22321 +    },
22322 +    {
22323 +      AVR32_OPC_EORL, 4, 0xec100000, 0xfff00000,
22324 +      &avr32_syntax_table[AVR32_SYNTAX_EORL],
22325 +      BFD_RELOC_AVR32_16U, 2, 1,
22326 +      {
22327 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22328 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22329 +      },
22330 +    },
22331 +    {
22332 +      AVR32_OPC_EORH, 4, 0xee100000, 0xfff00000,
22333 +      &avr32_syntax_table[AVR32_SYNTAX_EORH],
22334 +      BFD_RELOC_AVR32_16U, 2, 1,
22335 +      {
22336 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22337 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22338 +      },
22339 +    },
22340 +    {
22341 +      AVR32_OPC_FRS, 2, 0xd7430000, 0xffff0000,
22342 +      &avr32_syntax_table[AVR32_SYNTAX_FRS],
22343 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
22344 +    },
22345 +    {
22346 +      AVR32_OPC_ICALL, 2, 0x5d100000, 0xfff00000,
22347 +      &avr32_syntax_table[AVR32_SYNTAX_ICALL],
22348 +      BFD_RELOC_UNUSED, 1, -1,
22349 +      {
22350 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22351 +      },
22352 +    },
22353 +    {
22354 +      AVR32_OPC_INCJOSP, 2, 0xd6830000, 0xff8f0000,
22355 +      &avr32_syntax_table[AVR32_SYNTAX_INCJOSP],
22356 +      BFD_RELOC_UNUSED, 1, -1,
22357 +      {
22358 +       &avr32_ifield_table[AVR32_IFIELD_K3],
22359 +      },
22360 +    },
22361 +    {
22362 +      AVR32_OPC_LD_D1, 2, 0xa1010000, 0xe1f10000,
22363 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D1],
22364 +      BFD_RELOC_UNUSED, 2, -1,
22365 +      {
22366 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22367 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22368 +      },
22369 +    },
22370 +    {
22371 +      AVR32_OPC_LD_D2, 2, 0xa1100000, 0xe1f10000,
22372 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D2],
22373 +      BFD_RELOC_UNUSED, 2, -1,
22374 +      {
22375 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22376 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22377 +      },
22378 +    },
22379 +    {
22380 +      AVR32_OPC_LD_D3, 2, 0xa1000000, 0xe1f10000,
22381 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D3],
22382 +      BFD_RELOC_UNUSED, 2, -1,
22383 +      {
22384 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22385 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22386 +      },
22387 +    },
22388 +    {
22389 +      AVR32_OPC_LD_D5, 4, 0xe0000200, 0xe1f0ffc1,
22390 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D5],
22391 +      BFD_RELOC_UNUSED, 4, -1,
22392 +      {
22393 +       &avr32_ifield_table[AVR32_IFIELD_RD_DW],
22394 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22395 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22396 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22397 +      },
22398 +    },
22399 +    {
22400 +      AVR32_OPC_LD_D4, 4, 0xe0e00000, 0xe1f10000,
22401 +      &avr32_syntax_table[AVR32_SYNTAX_LD_D4],
22402 +      BFD_RELOC_AVR32_16S, 3, 2,
22403 +      {
22404 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
22405 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22406 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22407 +      },
22408 +    },
22409 +    {
22410 +      AVR32_OPC_LD_SB2, 4, 0xe0000600, 0xe1f0ffc0,
22411 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SB2],
22412 +      BFD_RELOC_UNUSED, 4, -1,
22413 +      {
22414 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22415 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22416 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22417 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22418 +      },
22419 +    },
22420 +    {
22421 +      AVR32_OPC_LD_SB1, 4, 0xe1200000, 0xe1f00000,
22422 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SB1],
22423 +      BFD_RELOC_AVR32_16S, 3, -1,
22424 +      {
22425 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22426 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22427 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22428 +      },
22429 +    },
22430 +    {
22431 +      AVR32_OPC_LD_UB1, 2, 0x01300000, 0xe1f00000,
22432 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB1],
22433 +      BFD_RELOC_UNUSED, 2, -1,
22434 +      {
22435 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22436 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22437 +      },
22438 +    },
22439 +    {
22440 +      AVR32_OPC_LD_UB2, 2, 0x01700000, 0xe1f00000,
22441 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB2],
22442 +      BFD_RELOC_UNUSED, 2, -1,
22443 +      {
22444 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22445 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22446 +      },
22447 +    },
22448 +    {
22449 +      AVR32_OPC_LD_UB5, 4, 0xe0000700, 0xe1f0ffc0,
22450 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB5],
22451 +      BFD_RELOC_UNUSED, 4, -1,
22452 +      {
22453 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22454 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22455 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22456 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22457 +      },
22458 +    },
22459 +    {
22460 +      AVR32_OPC_LD_UB3, 2, 0x01800000, 0xe1800000,
22461 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB3],
22462 +      BFD_RELOC_AVR32_3U, 3, 2,
22463 +      {
22464 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22465 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22466 +       &avr32_ifield_table[AVR32_IFIELD_K3],
22467 +      },
22468 +    },
22469 +    {
22470 +      AVR32_OPC_LD_UB4, 4, 0xe1300000, 0xe1f00000,
22471 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UB4],
22472 +      BFD_RELOC_AVR32_16S, 3, 2,
22473 +      {
22474 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22475 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22476 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22477 +      },
22478 +    },
22479 +    {
22480 +      AVR32_OPC_LD_SH1, 2, 0x01100000, 0xe1f00000,
22481 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH1],
22482 +      BFD_RELOC_UNUSED, 2, -1,
22483 +      {
22484 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22485 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22486 +      },
22487 +    },
22488 +    {
22489 +      AVR32_OPC_LD_SH2, 2, 0x01500000, 0xe1f00000,
22490 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH2],
22491 +      BFD_RELOC_UNUSED, 2, -1,
22492 +      {
22493 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22494 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22495 +      },
22496 +    },
22497 +    {
22498 +      AVR32_OPC_LD_SH5, 4, 0xe0000400, 0xe1f0ffc0,
22499 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH5],
22500 +      BFD_RELOC_UNUSED, 4, -1,
22501 +      {
22502 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22503 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22504 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22505 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22506 +      },
22507 +    },
22508 +    {
22509 +      AVR32_OPC_LD_SH3, 2, 0x80000000, 0xe1800000,
22510 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH3],
22511 +      BFD_RELOC_AVR32_4UH, 3, 2,
22512 +      {
22513 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22514 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22515 +       &avr32_ifield_table[AVR32_IFIELD_K3],
22516 +      },
22517 +    },
22518 +    {
22519 +      AVR32_OPC_LD_SH4, 4, 0xe1000000, 0xe1f00000,
22520 +      &avr32_syntax_table[AVR32_SYNTAX_LD_SH4],
22521 +      BFD_RELOC_AVR32_16S, 3, 2,
22522 +      {
22523 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22524 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22525 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22526 +      },
22527 +    },
22528 +    {
22529 +      AVR32_OPC_LD_UH1, 2, 0x01200000, 0xe1f00000,
22530 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH1],
22531 +      BFD_RELOC_UNUSED, 2, -1,
22532 +      {
22533 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22534 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22535 +      },
22536 +    },
22537 +    {
22538 +      AVR32_OPC_LD_UH2, 2, 0x01600000, 0xe1f00000,
22539 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH2],
22540 +      BFD_RELOC_UNUSED, 2, -1,
22541 +      {
22542 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22543 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22544 +      },
22545 +    },
22546 +    {
22547 +      AVR32_OPC_LD_UH5, 4, 0xe0000500, 0xe1f0ffc0,
22548 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH5],
22549 +      BFD_RELOC_UNUSED, 4, -1,
22550 +      {
22551 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22552 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22553 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22554 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22555 +      },
22556 +    },
22557 +    {
22558 +      AVR32_OPC_LD_UH3, 2, 0x80800000, 0xe1800000,
22559 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH3],
22560 +      BFD_RELOC_AVR32_4UH, 3, 2,
22561 +      {
22562 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22563 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22564 +       &avr32_ifield_table[AVR32_IFIELD_K3],
22565 +      },
22566 +    },
22567 +    {
22568 +      AVR32_OPC_LD_UH4, 4, 0xe1100000, 0xe1f00000,
22569 +      &avr32_syntax_table[AVR32_SYNTAX_LD_UH4],
22570 +      BFD_RELOC_AVR32_16S, 3, 2,
22571 +      {
22572 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22573 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22574 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22575 +      },
22576 +    },
22577 +    {
22578 +      AVR32_OPC_LD_W1, 2, 0x01000000, 0xe1f00000,
22579 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W1],
22580 +      BFD_RELOC_UNUSED, 2, -1,
22581 +      {
22582 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22583 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22584 +      },
22585 +    },
22586 +    {
22587 +      AVR32_OPC_LD_W2, 2, 0x01400000, 0xe1f00000,
22588 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W2],
22589 +      BFD_RELOC_UNUSED, 2, -1,
22590 +      {
22591 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22592 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22593 +      },
22594 +    },
22595 +    {
22596 +      AVR32_OPC_LD_W5, 4, 0xe0000300, 0xe1f0ffc0,
22597 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W5],
22598 +      BFD_RELOC_UNUSED, 4, -1,
22599 +      {
22600 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22601 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22602 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22603 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22604 +      },
22605 +    },
22606 +    {
22607 +      AVR32_OPC_LD_W6, 4, 0xe0000f80, 0xe1f0ffc0,
22608 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W6],
22609 +      BFD_RELOC_UNUSED, 4, -1,
22610 +      {
22611 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22612 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22613 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22614 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22615 +      },
22616 +    },
22617 +    {
22618 +      AVR32_OPC_LD_W3, 2, 0x60000000, 0xe0000000,
22619 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W3],
22620 +      BFD_RELOC_AVR32_7UW, 3, 2,
22621 +      {
22622 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22623 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22624 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
22625 +      },
22626 +    },
22627 +    {
22628 +      AVR32_OPC_LD_W4, 4, 0xe0f00000, 0xe1f00000,
22629 +      &avr32_syntax_table[AVR32_SYNTAX_LD_W4],
22630 +      BFD_RELOC_AVR32_16S, 3, 2,
22631 +      {
22632 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22633 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22634 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22635 +      },
22636 +    },
22637 +    {
22638 +      AVR32_OPC_LDC_D1, 4, 0xe9a01000, 0xfff01100,
22639 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_D1],
22640 +      BFD_RELOC_AVR32_10UW, 4, 3,
22641 +      {
22642 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22643 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22644 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22645 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22646 +      },
22647 +    },
22648 +    {
22649 +      AVR32_OPC_LDC_D2, 4, 0xefa00050, 0xfff011ff,
22650 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_D2],
22651 +      BFD_RELOC_UNUSED, 3, -1,
22652 +      {
22653 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22654 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22655 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22656 +      },
22657 +    },
22658 +    {
22659 +      AVR32_OPC_LDC_D3, 4, 0xefa01040, 0xfff011c0,
22660 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_D3],
22661 +      BFD_RELOC_UNUSED, 5, -1,
22662 +      {
22663 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22664 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22665 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22666 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22667 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22668 +      },
22669 +    },
22670 +    {
22671 +      AVR32_OPC_LDC_W1, 4, 0xe9a00000, 0xfff01000,
22672 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_W1],
22673 +      BFD_RELOC_AVR32_10UW, 4, 3,
22674 +      {
22675 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22676 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22677 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22678 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22679 +      },
22680 +    },
22681 +    {
22682 +      AVR32_OPC_LDC_W2, 4, 0xefa00040, 0xfff010ff,
22683 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_W2],
22684 +      BFD_RELOC_UNUSED, 3, -1,
22685 +      {
22686 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22687 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22688 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22689 +      },
22690 +    },
22691 +    {
22692 +      AVR32_OPC_LDC_W3, 4, 0xefa01000, 0xfff010c0,
22693 +      &avr32_syntax_table[AVR32_SYNTAX_LDC_W3],
22694 +      BFD_RELOC_UNUSED, 5, -1,
22695 +      {
22696 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22697 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22698 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22699 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22700 +       &avr32_ifield_table[AVR32_IFIELD_K2],
22701 +      },
22702 +    },
22703 +    {
22704 +      AVR32_OPC_LDC0_D, 4, 0xf3a00000, 0xfff00100,
22705 +      &avr32_syntax_table[AVR32_SYNTAX_LDC0_D],
22706 +      BFD_RELOC_AVR32_14UW, 3, 2,
22707 +      {
22708 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
22709 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22710 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
22711 +      },
22712 +    },
22713 +    {
22714 +      AVR32_OPC_LDC0_W, 4, 0xf1a00000, 0xfff00000,
22715 +      &avr32_syntax_table[AVR32_SYNTAX_LDC0_W],
22716 +      BFD_RELOC_AVR32_14UW, 3, 2,
22717 +      {
22718 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
22719 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22720 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
22721 +      },
22722 +    },
22723 +    {
22724 +      AVR32_OPC_LDCM_D, 4, 0xeda00400, 0xfff01f00,
22725 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_D],
22726 +      BFD_RELOC_UNUSED, 3, -1,
22727 +      {
22728 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22729 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22730 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22731 +      },
22732 +    },
22733 +    {
22734 +      AVR32_OPC_LDCM_D_PU, 4, 0xeda01400, 0xfff01f00,
22735 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_D_PU],
22736 +      BFD_RELOC_UNUSED, 3, -1,
22737 +      {
22738 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22739 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22740 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22741 +      },
22742 +    },
22743 +    {
22744 +      AVR32_OPC_LDCM_W, 4, 0xeda00000, 0xfff01e00,
22745 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_W],
22746 +      BFD_RELOC_UNUSED, 4, -1,
22747 +      {
22748 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22749 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22750 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22751 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
22752 +      },
22753 +    },
22754 +    {
22755 +      AVR32_OPC_LDCM_W_PU, 4, 0xeda01000, 0xfff01e00,
22756 +      &avr32_syntax_table[AVR32_SYNTAX_LDCM_W_PU],
22757 +      BFD_RELOC_UNUSED, 4, -1,
22758 +      {
22759 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
22760 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22761 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
22762 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
22763 +      },
22764 +    },
22765 +    {
22766 +      AVR32_OPC_LDDPC, 2, 0x48000000, 0xf8000000,
22767 +      &avr32_syntax_table[AVR32_SYNTAX_LDDPC],
22768 +      BFD_RELOC_AVR32_9UW_PCREL, 2, 1,
22769 +      {
22770 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22771 +       &avr32_ifield_table[AVR32_IFIELD_K7C],
22772 +      },
22773 +    },
22774 +    {
22775 +      AVR32_OPC_LDDPC_EXT, 4, 0xfef00000, 0xfff00000,
22776 +      &avr32_syntax_table[AVR32_SYNTAX_LDDPC_EXT],
22777 +      BFD_RELOC_AVR32_16B_PCREL, 2, 1,
22778 +      {
22779 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22780 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22781 +      },
22782 +    },
22783 +    {
22784 +      AVR32_OPC_LDDSP, 2, 0x40000000, 0xf8000000,
22785 +      &avr32_syntax_table[AVR32_SYNTAX_LDDSP],
22786 +      BFD_RELOC_UNUSED, 2, -1,
22787 +      {
22788 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22789 +       &avr32_ifield_table[AVR32_IFIELD_K7C],
22790 +      },
22791 +    },
22792 +    {
22793 +      AVR32_OPC_LDINS_B, 4, 0xe1d04000, 0xe1f0c000,
22794 +      &avr32_syntax_table[AVR32_SYNTAX_LDINS_B],
22795 +      BFD_RELOC_UNUSED, 4, -1,
22796 +      {
22797 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22798 +       &avr32_ifield_table[AVR32_IFIELD_PART2_K12],
22799 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22800 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22801 +      },
22802 +    },
22803 +    {
22804 +      AVR32_OPC_LDINS_H, 4, 0xe1d00000, 0xe1f0e000,
22805 +      &avr32_syntax_table[AVR32_SYNTAX_LDINS_H],
22806 +      BFD_RELOC_UNUSED, 4, -1,
22807 +      {
22808 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22809 +       &avr32_ifield_table[AVR32_IFIELD_PART1_K12],
22810 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22811 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22812 +      },
22813 +    },
22814 +    {
22815 +      AVR32_OPC_LDM, 4, 0xe1c00000, 0xfdf00000,
22816 +      &avr32_syntax_table[AVR32_SYNTAX_LDM],
22817 +      BFD_RELOC_UNUSED, 3, -1,
22818 +      {
22819 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22820 +       &avr32_ifield_table[AVR32_IFIELD_W],
22821 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22822 +      },
22823 +    },
22824 +    {
22825 +      AVR32_OPC_LDMTS, 4, 0xe5c00000, 0xfff00000,
22826 +      &avr32_syntax_table[AVR32_SYNTAX_LDMTS],
22827 +      BFD_RELOC_UNUSED, 2, -1,
22828 +      {
22829 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22830 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22831 +      },
22832 +    },
22833 +    {
22834 +      AVR32_OPC_LDMTS_PU, 4, 0xe7c00000, 0xfff00000,
22835 +      &avr32_syntax_table[AVR32_SYNTAX_LDMTS_PU],
22836 +      BFD_RELOC_UNUSED, 2, -1,
22837 +      {
22838 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22839 +       &avr32_ifield_table[AVR32_IFIELD_K16],
22840 +      },
22841 +    },
22842 +    {
22843 +      AVR32_OPC_LDSWP_SH, 4, 0xe1d02000, 0xe1f0f000,
22844 +      &avr32_syntax_table[AVR32_SYNTAX_LDSWP_SH],
22845 +      BFD_RELOC_UNUSED, 3, -1,
22846 +      {
22847 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22848 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22849 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22850 +      },
22851 +    },
22852 +    {
22853 +      AVR32_OPC_LDSWP_UH, 4, 0xe1d03000, 0xe1f0f000,
22854 +      &avr32_syntax_table[AVR32_SYNTAX_LDSWP_UH],
22855 +      BFD_RELOC_UNUSED, 3, -1,
22856 +      {
22857 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22858 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22859 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22860 +      },
22861 +    },
22862 +    {
22863 +      AVR32_OPC_LDSWP_W, 4, 0xe1d08000, 0xe1f0f000,
22864 +      &avr32_syntax_table[AVR32_SYNTAX_LDSWP_W],
22865 +      BFD_RELOC_UNUSED, 3, -1,
22866 +      {
22867 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22868 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22869 +       &avr32_ifield_table[AVR32_IFIELD_K12],
22870 +      },
22871 +    },
22872 +    {
22873 +      AVR32_OPC_LSL1, 4, 0xe0000940, 0xe1f0fff0,
22874 +      &avr32_syntax_table[AVR32_SYNTAX_LSL1],
22875 +      BFD_RELOC_UNUSED, 3, -1,
22876 +      {
22877 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22878 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22879 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22880 +      },
22881 +    },
22882 +    {
22883 +      AVR32_OPC_LSL3, 4, 0xe0001500, 0xe1f0ffe0,
22884 +      &avr32_syntax_table[AVR32_SYNTAX_LSL3],
22885 +      BFD_RELOC_UNUSED, 3, -1,
22886 +      {
22887 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22888 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22889 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
22890 +      },
22891 +    },
22892 +    {
22893 +      AVR32_OPC_LSL2, 2, 0xa1600000, 0xe1e00000,
22894 +      &avr32_syntax_table[AVR32_SYNTAX_LSL2],
22895 +      BFD_RELOC_UNUSED, 2, -1,
22896 +      {
22897 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22898 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
22899 +      },
22900 +    },
22901 +    {
22902 +      AVR32_OPC_LSR1, 4, 0xe0000a40, 0xe1f0fff0,
22903 +      &avr32_syntax_table[AVR32_SYNTAX_LSR1],
22904 +      BFD_RELOC_UNUSED, 3, -1,
22905 +      {
22906 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22907 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22908 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22909 +      },
22910 +    },
22911 +    {
22912 +      AVR32_OPC_LSR3, 4, 0xe0001600, 0xe1f0ffe0,
22913 +      &avr32_syntax_table[AVR32_SYNTAX_LSR3],
22914 +      BFD_RELOC_UNUSED, 3, -1,
22915 +      {
22916 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22917 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22918 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
22919 +      },
22920 +    },
22921 +    {
22922 +      AVR32_OPC_LSR2, 2, 0xa1800000, 0xe1e00000,
22923 +      &avr32_syntax_table[AVR32_SYNTAX_LSR2],
22924 +      BFD_RELOC_UNUSED, 2, -1,
22925 +      {
22926 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22927 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
22928 +      },
22929 +    },
22930 +    {
22931 +      AVR32_OPC_MAC, 4, 0xe0000340, 0xe1f0fff0,
22932 +      &avr32_syntax_table[AVR32_SYNTAX_MAC],
22933 +      BFD_RELOC_UNUSED, 3, -1,
22934 +      {
22935 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22936 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22937 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22938 +      },
22939 +    },
22940 +    {
22941 +      AVR32_OPC_MACHH_D, 4, 0xe0000580, 0xe1f0ffc1,
22942 +      &avr32_syntax_table[AVR32_SYNTAX_MACHH_D],
22943 +      BFD_RELOC_UNUSED, 5, -1,
22944 +      {
22945 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22946 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22947 +       &avr32_ifield_table[AVR32_IFIELD_X],
22948 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22949 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22950 +      },
22951 +    },
22952 +    {
22953 +      AVR32_OPC_MACHH_W, 4, 0xe0000480, 0xe1f0ffc0,
22954 +      &avr32_syntax_table[AVR32_SYNTAX_MACHH_W],
22955 +      BFD_RELOC_UNUSED, 5, -1,
22956 +      {
22957 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22958 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22959 +       &avr32_ifield_table[AVR32_IFIELD_X],
22960 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22961 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22962 +      },
22963 +    },
22964 +    {
22965 +      AVR32_OPC_MACS_D, 4, 0xe0000540, 0xe1f0fff1,
22966 +      &avr32_syntax_table[AVR32_SYNTAX_MACS_D],
22967 +      BFD_RELOC_UNUSED, 3, -1,
22968 +      {
22969 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22970 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22971 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22972 +      },
22973 +    },
22974 +    {
22975 +      AVR32_OPC_MACSATHH_W, 4, 0xe0000680, 0xe1f0ffc0,
22976 +      &avr32_syntax_table[AVR32_SYNTAX_MACSATHH_W],
22977 +      BFD_RELOC_UNUSED, 5, -1,
22978 +      {
22979 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22980 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22981 +       &avr32_ifield_table[AVR32_IFIELD_X],
22982 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22983 +       &avr32_ifield_table[AVR32_IFIELD_Y],
22984 +      },
22985 +    },
22986 +    {
22987 +      AVR32_OPC_MACUD, 4, 0xe0000740, 0xe1f0fff1,
22988 +      &avr32_syntax_table[AVR32_SYNTAX_MACUD],
22989 +      BFD_RELOC_UNUSED, 3, -1,
22990 +      {
22991 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
22992 +       &avr32_ifield_table[AVR32_IFIELD_RX],
22993 +       &avr32_ifield_table[AVR32_IFIELD_RY],
22994 +      },
22995 +    },
22996 +    {
22997 +      AVR32_OPC_MACWH_D, 4, 0xe0000c80, 0xe1f0ffe1,
22998 +      &avr32_syntax_table[AVR32_SYNTAX_MACWH_D],
22999 +      BFD_RELOC_UNUSED, 4, -1,
23000 +      {
23001 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23002 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23003 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23004 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23005 +      },
23006 +    },
23007 +    {
23008 +      AVR32_OPC_MAX, 4, 0xe0000c40, 0xe1f0fff0,
23009 +      &avr32_syntax_table[AVR32_SYNTAX_MAX],
23010 +      BFD_RELOC_UNUSED, 3, -1,
23011 +      {
23012 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23013 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23014 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23015 +      },
23016 +    },
23017 +    {
23018 +      AVR32_OPC_MCALL, 4, 0xf0100000, 0xfff00000,
23019 +      &avr32_syntax_table[AVR32_SYNTAX_MCALL],
23020 +      BFD_RELOC_AVR32_18W_PCREL, 2, 1,
23021 +      {
23022 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23023 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23024 +      },
23025 +    },
23026 +    {
23027 +      AVR32_OPC_MFDR, 4, 0xe5b00000, 0xfff0ff00,
23028 +      &avr32_syntax_table[AVR32_SYNTAX_MFDR],
23029 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23030 +      {
23031 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23032 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23033 +      },
23034 +    },
23035 +    {
23036 +      AVR32_OPC_MFSR, 4, 0xe1b00000, 0xfff0ff00,
23037 +      &avr32_syntax_table[AVR32_SYNTAX_MFSR],
23038 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23039 +      {
23040 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23041 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23042 +      },
23043 +    },
23044 +    {
23045 +      AVR32_OPC_MIN, 4, 0xe0000d40, 0xe1f0fff0,
23046 +      &avr32_syntax_table[AVR32_SYNTAX_MIN],
23047 +      BFD_RELOC_UNUSED, 3, -1,
23048 +      {
23049 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23050 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23051 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23052 +      },
23053 +    },
23054 +    {
23055 +      AVR32_OPC_MOV3, 2, 0x00900000, 0xe1f00000,
23056 +      &avr32_syntax_table[AVR32_SYNTAX_MOV3],
23057 +      BFD_RELOC_NONE, 2, -1,
23058 +      {
23059 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23060 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23061 +      },
23062 +    },
23063 +    {
23064 +      AVR32_OPC_MOV1, 2, 0x30000000, 0xf0000000,
23065 +      &avr32_syntax_table[AVR32_SYNTAX_MOV1],
23066 +      BFD_RELOC_AVR32_8S, 2, 1,
23067 +      {
23068 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23069 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
23070 +      },
23071 +    },
23072 +    {
23073 +      AVR32_OPC_MOV2, 4, 0xe0600000, 0xe1e00000,
23074 +      &avr32_syntax_table[AVR32_SYNTAX_MOV2],
23075 +      BFD_RELOC_AVR32_21S, 2, 1,
23076 +      {
23077 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23078 +       &avr32_ifield_table[AVR32_IFIELD_K21],
23079 +      },
23080 +    },
23081 +    {
23082 +      AVR32_OPC_MOVEQ1, 4, 0xe0001700, 0xe1f0ffff,
23083 +      &avr32_syntax_table[AVR32_SYNTAX_MOVEQ1],
23084 +      BFD_RELOC_UNUSED, 2, -1,
23085 +      {
23086 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23087 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23088 +      },
23089 +    },
23090 +    {
23091 +      AVR32_OPC_MOVNE1, 4, 0xe0001710, 0xe1f0ffff,
23092 +      &avr32_syntax_table[AVR32_SYNTAX_MOVNE1],
23093 +      BFD_RELOC_UNUSED, 2, -1,
23094 +      {
23095 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23096 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23097 +      },
23098 +    },
23099 +    {
23100 +      AVR32_OPC_MOVCC1, 4, 0xe0001720, 0xe1f0ffff,
23101 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHS1],
23102 +      BFD_RELOC_UNUSED, 2, -1,
23103 +      {
23104 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23105 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23106 +      },
23107 +    },
23108 +    {
23109 +      AVR32_OPC_MOVCS1, 4, 0xe0001730, 0xe1f0ffff,
23110 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLO1],
23111 +      BFD_RELOC_UNUSED, 2, -1,
23112 +      {
23113 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23114 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23115 +      },
23116 +    },
23117 +    {
23118 +      AVR32_OPC_MOVGE1, 4, 0xe0001740, 0xe1f0ffff,
23119 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGE1],
23120 +      BFD_RELOC_UNUSED, 2, -1,
23121 +      {
23122 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23123 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23124 +      },
23125 +    },
23126 +    {
23127 +      AVR32_OPC_MOVLT1, 4, 0xe0001750, 0xe1f0ffff,
23128 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLT1],
23129 +      BFD_RELOC_UNUSED, 2, -1,
23130 +      {
23131 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23132 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23133 +      },
23134 +    },
23135 +    {
23136 +      AVR32_OPC_MOVMI1, 4, 0xe0001760, 0xe1f0ffff,
23137 +      &avr32_syntax_table[AVR32_SYNTAX_MOVMI1],
23138 +      BFD_RELOC_UNUSED, 2, -1,
23139 +      {
23140 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23141 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23142 +      },
23143 +    },
23144 +    {
23145 +      AVR32_OPC_MOVPL1, 4, 0xe0001770, 0xe1f0ffff,
23146 +      &avr32_syntax_table[AVR32_SYNTAX_MOVPL1],
23147 +      BFD_RELOC_UNUSED, 2, -1,
23148 +      {
23149 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23150 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23151 +      },
23152 +    },
23153 +    {
23154 +      AVR32_OPC_MOVLS1, 4, 0xe0001780, 0xe1f0ffff,
23155 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLS1],
23156 +      BFD_RELOC_UNUSED, 2, -1,
23157 +      {
23158 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23159 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23160 +      },
23161 +    },
23162 +    {
23163 +      AVR32_OPC_MOVGT1, 4, 0xe0001790, 0xe1f0ffff,
23164 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGT1],
23165 +      BFD_RELOC_UNUSED, 2, -1,
23166 +      {
23167 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23168 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23169 +      },
23170 +    },
23171 +    {
23172 +      AVR32_OPC_MOVLE1, 4, 0xe00017a0, 0xe1f0ffff,
23173 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLE1],
23174 +      BFD_RELOC_UNUSED, 2, -1,
23175 +      {
23176 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23177 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23178 +      },
23179 +    },
23180 +    {
23181 +      AVR32_OPC_MOVHI1, 4, 0xe00017b0, 0xe1f0ffff,
23182 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHI1],
23183 +      BFD_RELOC_UNUSED, 2, -1,
23184 +      {
23185 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23186 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23187 +      },
23188 +    },
23189 +    {
23190 +      AVR32_OPC_MOVVS1, 4, 0xe00017c0, 0xe1f0ffff,
23191 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVS1],
23192 +      BFD_RELOC_UNUSED, 2, -1,
23193 +      {
23194 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23195 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23196 +      },
23197 +    },
23198 +    {
23199 +      AVR32_OPC_MOVVC1, 4, 0xe00017d0, 0xe1f0ffff,
23200 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVC1],
23201 +      BFD_RELOC_UNUSED, 2, -1,
23202 +      {
23203 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23204 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23205 +      },
23206 +    },
23207 +    {
23208 +      AVR32_OPC_MOVQS1, 4, 0xe00017e0, 0xe1f0ffff,
23209 +      &avr32_syntax_table[AVR32_SYNTAX_MOVQS1],
23210 +      BFD_RELOC_UNUSED, 2, -1,
23211 +      {
23212 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23213 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23214 +      },
23215 +    },
23216 +    {
23217 +      AVR32_OPC_MOVAL1, 4, 0xe00017f0, 0xe1f0ffff,
23218 +      &avr32_syntax_table[AVR32_SYNTAX_MOVAL1],
23219 +      BFD_RELOC_UNUSED, 2, -1,
23220 +      {
23221 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23222 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23223 +      },
23224 +    },
23225 +    {
23226 +      AVR32_OPC_MOVEQ2, 4, 0xf9b00000, 0xfff0ff00,
23227 +      &avr32_syntax_table[AVR32_SYNTAX_MOVEQ2],
23228 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23229 +      {
23230 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23231 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23232 +      },
23233 +    },
23234 +    {
23235 +      AVR32_OPC_MOVNE2, 4, 0xf9b00100, 0xfff0ff00,
23236 +      &avr32_syntax_table[AVR32_SYNTAX_MOVNE2],
23237 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23238 +      {
23239 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23240 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23241 +      },
23242 +    },
23243 +    {
23244 +      AVR32_OPC_MOVCC2, 4, 0xf9b00200, 0xfff0ff00,
23245 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHS2],
23246 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23247 +      {
23248 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23249 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23250 +      },
23251 +    },
23252 +    {
23253 +      AVR32_OPC_MOVCS2, 4, 0xf9b00300, 0xfff0ff00,
23254 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLO2],
23255 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23256 +      {
23257 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23258 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23259 +      },
23260 +    },
23261 +    {
23262 +      AVR32_OPC_MOVGE2, 4, 0xf9b00400, 0xfff0ff00,
23263 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGE2],
23264 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23265 +      {
23266 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23267 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23268 +      },
23269 +    },
23270 +    {
23271 +      AVR32_OPC_MOVLT2, 4, 0xf9b00500, 0xfff0ff00,
23272 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLT2],
23273 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23274 +      {
23275 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23276 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23277 +      },
23278 +    },
23279 +    {
23280 +      AVR32_OPC_MOVMI2, 4, 0xf9b00600, 0xfff0ff00,
23281 +      &avr32_syntax_table[AVR32_SYNTAX_MOVMI2],
23282 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23283 +      {
23284 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23285 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23286 +      },
23287 +    },
23288 +    {
23289 +      AVR32_OPC_MOVPL2, 4, 0xf9b00700, 0xfff0ff00,
23290 +      &avr32_syntax_table[AVR32_SYNTAX_MOVPL2],
23291 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23292 +      {
23293 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23294 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23295 +      },
23296 +    },
23297 +    {
23298 +      AVR32_OPC_MOVLS2, 4, 0xf9b00800, 0xfff0ff00,
23299 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLS2],
23300 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23301 +      {
23302 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23303 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23304 +      },
23305 +    },
23306 +    {
23307 +      AVR32_OPC_MOVGT2, 4, 0xf9b00900, 0xfff0ff00,
23308 +      &avr32_syntax_table[AVR32_SYNTAX_MOVGT2],
23309 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23310 +      {
23311 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23312 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23313 +      },
23314 +    },
23315 +    {
23316 +      AVR32_OPC_MOVLE2, 4, 0xf9b00a00, 0xfff0ff00,
23317 +      &avr32_syntax_table[AVR32_SYNTAX_MOVLE2],
23318 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23319 +      {
23320 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23321 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23322 +      },
23323 +    },
23324 +    {
23325 +      AVR32_OPC_MOVHI2, 4, 0xf9b00b00, 0xfff0ff00,
23326 +      &avr32_syntax_table[AVR32_SYNTAX_MOVHI2],
23327 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23328 +      {
23329 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23330 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23331 +      },
23332 +    },
23333 +    {
23334 +      AVR32_OPC_MOVVS2, 4, 0xf9b00c00, 0xfff0ff00,
23335 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVS2],
23336 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23337 +      {
23338 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23339 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23340 +      },
23341 +    },
23342 +    {
23343 +      AVR32_OPC_MOVVC2, 4, 0xf9b00d00, 0xfff0ff00,
23344 +      &avr32_syntax_table[AVR32_SYNTAX_MOVVC2],
23345 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23346 +      {
23347 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23348 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23349 +      },
23350 +    },
23351 +    {
23352 +      AVR32_OPC_MOVQS2, 4, 0xf9b00e00, 0xfff0ff00,
23353 +      &avr32_syntax_table[AVR32_SYNTAX_MOVQS2],
23354 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23355 +      {
23356 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23357 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23358 +      },
23359 +    },
23360 +    {
23361 +      AVR32_OPC_MOVAL2, 4, 0xf9b00f00, 0xfff0ff00,
23362 +      &avr32_syntax_table[AVR32_SYNTAX_MOVAL2],
23363 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
23364 +      {
23365 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23366 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23367 +      },
23368 +    },
23369 +    {
23370 +      AVR32_OPC_MTDR, 4, 0xe7b00000, 0xfff0ff00,
23371 +      &avr32_syntax_table[AVR32_SYNTAX_MTDR],
23372 +      BFD_RELOC_AVR32_8S_EXT, 2, 0,
23373 +      {
23374 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23375 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23376 +      },
23377 +    },
23378 +    {
23379 +      AVR32_OPC_MTSR, 4, 0xe3b00000, 0xfff0ff00,
23380 +      &avr32_syntax_table[AVR32_SYNTAX_MTSR],
23381 +      BFD_RELOC_AVR32_8S_EXT, 2, 0,
23382 +      {
23383 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23384 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23385 +      },
23386 +    },
23387 +    {
23388 +      AVR32_OPC_MUL1, 2, 0xa1300000, 0xe1f00000,
23389 +      &avr32_syntax_table[AVR32_SYNTAX_MUL1],
23390 +      BFD_RELOC_UNUSED, 2, -1,
23391 +      {
23392 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23393 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23394 +      },
23395 +    },
23396 +    {
23397 +      AVR32_OPC_MUL2, 4, 0xe0000240, 0xe1f0fff0,
23398 +      &avr32_syntax_table[AVR32_SYNTAX_MUL2],
23399 +      BFD_RELOC_UNUSED, 3, -1,
23400 +      {
23401 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23402 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23403 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23404 +      },
23405 +    },
23406 +    {
23407 +      AVR32_OPC_MUL3, 4, 0xe0001000, 0xe1f0ff00,
23408 +      &avr32_syntax_table[AVR32_SYNTAX_MUL3],
23409 +      BFD_RELOC_AVR32_8S_EXT, 3, 2,
23410 +      {
23411 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23412 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23413 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
23414 +      },
23415 +    },
23416 +    {
23417 +      AVR32_OPC_MULHH_W, 4, 0xe0000780, 0xe1f0ffc0,
23418 +      &avr32_syntax_table[AVR32_SYNTAX_MULHH_W],
23419 +      BFD_RELOC_UNUSED, 5, -1,
23420 +      {
23421 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23422 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23423 +       &avr32_ifield_table[AVR32_IFIELD_X],
23424 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23425 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23426 +      },
23427 +    },
23428 +    {
23429 +      AVR32_OPC_MULNHH_W, 4, 0xe0000180, 0xe1f0ffc0,
23430 +      &avr32_syntax_table[AVR32_SYNTAX_MULNHH_W],
23431 +      BFD_RELOC_UNUSED, 5, -1,
23432 +      {
23433 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23434 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23435 +       &avr32_ifield_table[AVR32_IFIELD_X],
23436 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23437 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23438 +      },
23439 +    },
23440 +    {
23441 +      AVR32_OPC_MULNWH_D, 4, 0xe0000280, 0xe1f0ffe1,
23442 +      &avr32_syntax_table[AVR32_SYNTAX_MULNWH_D],
23443 +      BFD_RELOC_UNUSED, 4, -1,
23444 +      {
23445 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23446 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23447 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23448 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23449 +      },
23450 +    },
23451 +    {
23452 +      AVR32_OPC_MULSD, 4, 0xe0000440, 0xe1f0fff0,
23453 +      &avr32_syntax_table[AVR32_SYNTAX_MULSD],
23454 +      BFD_RELOC_UNUSED, 3, -1,
23455 +      {
23456 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23457 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23458 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23459 +      },
23460 +    },
23461 +    {
23462 +      AVR32_OPC_MULSATHH_H, 4, 0xe0000880, 0xe1f0ffc0,
23463 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_H],
23464 +      BFD_RELOC_UNUSED, 5, -1,
23465 +      {
23466 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23467 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23468 +       &avr32_ifield_table[AVR32_IFIELD_X],
23469 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23470 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23471 +      },
23472 +    },
23473 +    {
23474 +      AVR32_OPC_MULSATHH_W, 4, 0xe0000980, 0xe1f0ffc0,
23475 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATHH_W],
23476 +      BFD_RELOC_UNUSED, 5, -1,
23477 +      {
23478 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23479 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23480 +       &avr32_ifield_table[AVR32_IFIELD_X],
23481 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23482 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23483 +      },
23484 +    },
23485 +    {
23486 +      AVR32_OPC_MULSATRNDHH_H, 4, 0xe0000a80, 0xe1f0ffc0,
23487 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDHH_H],
23488 +      BFD_RELOC_UNUSED, 5, -1,
23489 +      {
23490 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23491 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23492 +       &avr32_ifield_table[AVR32_IFIELD_X],
23493 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23494 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23495 +      },
23496 +    },
23497 +    {
23498 +      AVR32_OPC_MULSATRNDWH_W, 4, 0xe0000b80, 0xe1f0ffe0,
23499 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATRNDWH_W],
23500 +      BFD_RELOC_UNUSED, 4, -1,
23501 +      {
23502 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23503 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23504 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23505 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23506 +      },
23507 +    },
23508 +    {
23509 +      AVR32_OPC_MULSATWH_W, 4, 0xe0000e80, 0xe1f0ffe0,
23510 +      &avr32_syntax_table[AVR32_SYNTAX_MULSATWH_W],
23511 +      BFD_RELOC_UNUSED, 4, -1,
23512 +      {
23513 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23514 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23515 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23516 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23517 +      },
23518 +    },
23519 +    {
23520 +      AVR32_OPC_MULU_D, 4, 0xe0000640, 0xe1f0fff1,
23521 +      &avr32_syntax_table[AVR32_SYNTAX_MULU_D],
23522 +      BFD_RELOC_UNUSED, 3, -1,
23523 +      {
23524 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23525 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23526 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23527 +      },
23528 +    },
23529 +    {
23530 +      AVR32_OPC_MULWH_D, 4, 0xe0000d80, 0xe1f0ffe1,
23531 +      &avr32_syntax_table[AVR32_SYNTAX_MULWH_D],
23532 +      BFD_RELOC_UNUSED, 4, -1,
23533 +      {
23534 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23535 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23536 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23537 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23538 +      },
23539 +    },
23540 +    {
23541 +      AVR32_OPC_MUSFR, 2, 0x5d300000, 0xfff00000,
23542 +      &avr32_syntax_table[AVR32_SYNTAX_MUSFR],
23543 +      BFD_RELOC_UNUSED, 1, -1,
23544 +      {
23545 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23546 +      }
23547 +    },
23548 +    {
23549 +      AVR32_OPC_MUSTR, 2, 0x5d200000, 0xfff00000,
23550 +      &avr32_syntax_table[AVR32_SYNTAX_MUSTR],
23551 +      BFD_RELOC_UNUSED, 1, -1,
23552 +      {
23553 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23554 +      }
23555 +    },
23556 +    {
23557 +      AVR32_OPC_MVCR_D, 4, 0xefa00010, 0xfff111ff,
23558 +      &avr32_syntax_table[AVR32_SYNTAX_MVCR_D],
23559 +      BFD_RELOC_UNUSED, 3, -1,
23560 +      {
23561 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23562 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
23563 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
23564 +      },
23565 +    },
23566 +    {
23567 +      AVR32_OPC_MVCR_W, 4, 0xefa00000, 0xfff010ff,
23568 +      &avr32_syntax_table[AVR32_SYNTAX_MVCR_W],
23569 +      BFD_RELOC_UNUSED, 3, -1,
23570 +      {
23571 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23572 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23573 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
23574 +      },
23575 +    },
23576 +    {
23577 +      AVR32_OPC_MVRC_D, 4, 0xefa00030, 0xfff111ff,
23578 +      &avr32_syntax_table[AVR32_SYNTAX_MVRC_D],
23579 +      BFD_RELOC_UNUSED, 3, -1,
23580 +      {
23581 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23582 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
23583 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
23584 +      },
23585 +    },
23586 +    {
23587 +      AVR32_OPC_MVRC_W, 4, 0xefa00020, 0xfff010ff,
23588 +      &avr32_syntax_table[AVR32_SYNTAX_MVRC_W],
23589 +      BFD_RELOC_UNUSED, 3, -1,
23590 +      {
23591 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
23592 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
23593 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23594 +      },
23595 +    },
23596 +    {
23597 +      AVR32_OPC_NEG, 2, 0x5c300000, 0xfff00000,
23598 +      &avr32_syntax_table[AVR32_SYNTAX_NEG],
23599 +      BFD_RELOC_UNUSED, 1, -1,
23600 +      {
23601 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23602 +      }
23603 +    },
23604 +    {
23605 +      AVR32_OPC_NOP, 2, 0xd7030000, 0xffff0000,
23606 +      &avr32_syntax_table[AVR32_SYNTAX_NOP],
23607 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
23608 +    },
23609 +    {
23610 +      AVR32_OPC_OR1, 2, 0x00400000, 0xe1f00000,
23611 +      &avr32_syntax_table[AVR32_SYNTAX_OR1],
23612 +      BFD_RELOC_UNUSED, 2, -1,
23613 +      {
23614 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23615 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23616 +      },
23617 +    },
23618 +    {
23619 +      AVR32_OPC_OR2, 4, 0xe1e01000, 0xe1f0fe00,
23620 +      &avr32_syntax_table[AVR32_SYNTAX_OR2],
23621 +      BFD_RELOC_UNUSED, 4, -1,
23622 +      {
23623 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23624 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23625 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23626 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
23627 +      },
23628 +    },
23629 +    {
23630 +      AVR32_OPC_OR3, 4, 0xe1e01200, 0xe1f0fe00,
23631 +      &avr32_syntax_table[AVR32_SYNTAX_OR3],
23632 +      BFD_RELOC_UNUSED, 4, -1,
23633 +      {
23634 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23635 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23636 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23637 +       &avr32_ifield_table[AVR32_IFIELD_K5E2],
23638 +      },
23639 +    },
23640 +    {
23641 +      AVR32_OPC_ORH, 4, 0xea100000, 0xfff00000,
23642 +      &avr32_syntax_table[AVR32_SYNTAX_ORH],
23643 +      BFD_RELOC_AVR32_16U, 2, 1,
23644 +      {
23645 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23646 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23647 +      },
23648 +    },
23649 +    {
23650 +      AVR32_OPC_ORL, 4, 0xe8100000, 0xfff00000,
23651 +      &avr32_syntax_table[AVR32_SYNTAX_ORL],
23652 +      BFD_RELOC_AVR32_16U, 2, 1,
23653 +      {
23654 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23655 +       &avr32_ifield_table[AVR32_IFIELD_K16],
23656 +      },
23657 +    },
23658 +    {
23659 +      AVR32_OPC_PABS_SB, 4, 0xe00023e0, 0xfff0fff0,
23660 +      &avr32_syntax_table[AVR32_SYNTAX_PABS_SB],
23661 +      BFD_RELOC_UNUSED, 2, -1,
23662 +      {
23663 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23664 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23665 +      },
23666 +    },
23667 +    {
23668 +      AVR32_OPC_PABS_SH, 4, 0xe00023f0, 0xfff0fff0,
23669 +      &avr32_syntax_table[AVR32_SYNTAX_PABS_SH],
23670 +      BFD_RELOC_UNUSED, 2, -1,
23671 +      {
23672 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23673 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23674 +      },
23675 +    },
23676 +    {
23677 +      AVR32_OPC_PACKSH_SB, 4, 0xe00024d0, 0xe1f0fff0,
23678 +      &avr32_syntax_table[AVR32_SYNTAX_PACKSH_SB],
23679 +      BFD_RELOC_UNUSED, 3, -1,
23680 +      {
23681 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23682 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23683 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23684 +      },
23685 +    },
23686 +    {
23687 +      AVR32_OPC_PACKSH_UB, 4, 0xe00024c0, 0xe1f0fff0,
23688 +      &avr32_syntax_table[AVR32_SYNTAX_PACKSH_UB],
23689 +      BFD_RELOC_UNUSED, 3, -1,
23690 +      {
23691 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23692 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23693 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23694 +      },
23695 +    },
23696 +    {
23697 +      AVR32_OPC_PACKW_SH, 4, 0xe0002470, 0xe1f0fff0,
23698 +      &avr32_syntax_table[AVR32_SYNTAX_PACKW_SH],
23699 +      BFD_RELOC_UNUSED, 3, -1,
23700 +      {
23701 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23702 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23703 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23704 +      },
23705 +    },
23706 +    {
23707 +      AVR32_OPC_PADD_B, 4, 0xe0002300, 0xe1f0fff0,
23708 +      &avr32_syntax_table[AVR32_SYNTAX_PADD_B],
23709 +      BFD_RELOC_UNUSED, 3, -1,
23710 +      {
23711 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23712 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23713 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23714 +      },
23715 +    },
23716 +    {
23717 +      AVR32_OPC_PADD_H, 4, 0xe0002000, 0xe1f0fff0,
23718 +      &avr32_syntax_table[AVR32_SYNTAX_PADD_H],
23719 +      BFD_RELOC_UNUSED, 3, -1,
23720 +      {
23721 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23722 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23723 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23724 +      },
23725 +    },
23726 +    {
23727 +      AVR32_OPC_PADDH_SH, 4, 0xe00020c0, 0xe1f0fff0,
23728 +      &avr32_syntax_table[AVR32_SYNTAX_PADDH_SH],
23729 +      BFD_RELOC_UNUSED, 3, -1,
23730 +      {
23731 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23732 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23733 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23734 +      },
23735 +    },
23736 +    {
23737 +      AVR32_OPC_PADDH_UB, 4, 0xe0002360, 0xe1f0fff0,
23738 +      &avr32_syntax_table[AVR32_SYNTAX_PADDH_UB],
23739 +      BFD_RELOC_UNUSED, 3, -1,
23740 +      {
23741 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23742 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23743 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23744 +      },
23745 +    },
23746 +    {
23747 +      AVR32_OPC_PADDS_SB, 4, 0xe0002320, 0xe1f0fff0,
23748 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_SB],
23749 +      BFD_RELOC_UNUSED, 3, -1,
23750 +      {
23751 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23752 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23753 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23754 +      },
23755 +    },
23756 +    {
23757 +      AVR32_OPC_PADDS_SH, 4, 0xe0002040, 0xe1f0fff0,
23758 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_SH],
23759 +      BFD_RELOC_UNUSED, 3, -1,
23760 +      {
23761 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23762 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23763 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23764 +      },
23765 +    },
23766 +    {
23767 +      AVR32_OPC_PADDS_UB, 4, 0xe0002340, 0xe1f0fff0,
23768 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_UB],
23769 +      BFD_RELOC_UNUSED, 3, -1,
23770 +      {
23771 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23772 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23773 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23774 +      },
23775 +    },
23776 +    {
23777 +      AVR32_OPC_PADDS_UH, 4, 0xe0002080, 0xe1f0fff0,
23778 +      &avr32_syntax_table[AVR32_SYNTAX_PADDS_UH],
23779 +      BFD_RELOC_UNUSED, 3, -1,
23780 +      {
23781 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23782 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23783 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23784 +      },
23785 +    },
23786 +    {
23787 +      AVR32_OPC_PADDSUB_H, 4, 0xe0002100, 0xe1f0ffc0,
23788 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUB_H],
23789 +      BFD_RELOC_UNUSED, 5, -1,
23790 +      {
23791 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23792 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23793 +       &avr32_ifield_table[AVR32_IFIELD_X],
23794 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23795 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23796 +      },
23797 +    },
23798 +    {
23799 +      AVR32_OPC_PADDSUBH_SH, 4, 0xe0002280, 0xe1f0ffc0,
23800 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUBH_SH],
23801 +      BFD_RELOC_UNUSED, 5, -1,
23802 +      {
23803 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23804 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23805 +       &avr32_ifield_table[AVR32_IFIELD_X],
23806 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23807 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23808 +      },
23809 +    },
23810 +    {
23811 +      AVR32_OPC_PADDSUBS_SH, 4, 0xe0002180, 0xe1f0ffc0,
23812 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_SH],
23813 +      BFD_RELOC_UNUSED, 5, -1,
23814 +      {
23815 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23816 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23817 +       &avr32_ifield_table[AVR32_IFIELD_X],
23818 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23819 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23820 +      },
23821 +    },
23822 +    {
23823 +      AVR32_OPC_PADDSUBS_UH, 4, 0xe0002200, 0xe1f0ffc0,
23824 +      &avr32_syntax_table[AVR32_SYNTAX_PADDSUBS_UH],
23825 +      BFD_RELOC_UNUSED, 5, -1,
23826 +      {
23827 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23828 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23829 +       &avr32_ifield_table[AVR32_IFIELD_X],
23830 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23831 +       &avr32_ifield_table[AVR32_IFIELD_Y],
23832 +      },
23833 +    },
23834 +    {
23835 +      AVR32_OPC_PADDX_H, 4, 0xe0002020, 0xe1f0fff0,
23836 +      &avr32_syntax_table[AVR32_SYNTAX_PADDX_H],
23837 +      BFD_RELOC_UNUSED, 3, -1,
23838 +      {
23839 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23840 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23841 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23842 +      },
23843 +    },
23844 +    {
23845 +      AVR32_OPC_PADDXH_SH, 4, 0xe00020e0, 0xe1f0fff0,
23846 +      &avr32_syntax_table[AVR32_SYNTAX_PADDXH_SH],
23847 +      BFD_RELOC_UNUSED, 3, -1,
23848 +      {
23849 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23850 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23851 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23852 +      },
23853 +    },
23854 +    {
23855 +      AVR32_OPC_PADDXS_SH, 4, 0xe0002060, 0xe1f0fff0,
23856 +      &avr32_syntax_table[AVR32_SYNTAX_PADDXS_SH],
23857 +      BFD_RELOC_UNUSED, 3, -1,
23858 +      {
23859 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23860 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23861 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23862 +      },
23863 +    },
23864 +    {
23865 +      AVR32_OPC_PADDXS_UH, 4, 0xe00020a0, 0xe1f0fff0,
23866 +      &avr32_syntax_table[AVR32_SYNTAX_PADDXS_UH],
23867 +      BFD_RELOC_UNUSED, 3, -1,
23868 +      {
23869 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23870 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23871 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23872 +      },
23873 +    },
23874 +    {
23875 +      AVR32_OPC_PASR_B, 4, 0xe0002410, 0xe1f8fff0,
23876 +      &avr32_syntax_table[AVR32_SYNTAX_PASR_B],
23877 +      BFD_RELOC_UNUSED, 3, -1,
23878 +      {
23879 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23880 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23881 +       &avr32_ifield_table[AVR32_IFIELD_COND3],
23882 +      },
23883 +    },
23884 +    {
23885 +      AVR32_OPC_PASR_H, 4, 0xe0002440, 0xe1f0fff0,
23886 +      &avr32_syntax_table[AVR32_SYNTAX_PASR_H],
23887 +      BFD_RELOC_UNUSED, 3, -1,
23888 +      {
23889 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23890 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23891 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23892 +      },
23893 +    },
23894 +    {
23895 +      AVR32_OPC_PAVG_SH, 4, 0xe00023d0, 0xe1f0fff0,
23896 +      &avr32_syntax_table[AVR32_SYNTAX_PAVG_SH],
23897 +      BFD_RELOC_UNUSED, 3, -1,
23898 +      {
23899 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23900 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23901 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23902 +      },
23903 +    },
23904 +    {
23905 +      AVR32_OPC_PAVG_UB, 4, 0xe00023c0, 0xe1f0fff0,
23906 +      &avr32_syntax_table[AVR32_SYNTAX_PAVG_UB],
23907 +      BFD_RELOC_UNUSED, 3, -1,
23908 +      {
23909 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23910 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23911 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23912 +      },
23913 +    },
23914 +    {
23915 +      AVR32_OPC_PLSL_B, 4, 0xe0002420, 0xe1f8fff0,
23916 +      &avr32_syntax_table[AVR32_SYNTAX_PLSL_B],
23917 +      BFD_RELOC_UNUSED, 3, -1,
23918 +      {
23919 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23920 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23921 +       &avr32_ifield_table[AVR32_IFIELD_COND3],
23922 +      },
23923 +    },
23924 +    {
23925 +      AVR32_OPC_PLSL_H, 4, 0xe0002450, 0xe1f0fff0,
23926 +      &avr32_syntax_table[AVR32_SYNTAX_PLSL_H],
23927 +      BFD_RELOC_UNUSED, 3, -1,
23928 +      {
23929 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23930 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23931 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23932 +      },
23933 +    },
23934 +    {
23935 +      AVR32_OPC_PLSR_B, 4, 0xe0002430, 0xe1f8fff0,
23936 +      &avr32_syntax_table[AVR32_SYNTAX_PLSR_B],
23937 +      BFD_RELOC_UNUSED, 3, -1,
23938 +      {
23939 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23940 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23941 +       &avr32_ifield_table[AVR32_IFIELD_COND3],
23942 +      },
23943 +    },
23944 +    {
23945 +      AVR32_OPC_PLSR_H, 4, 0xe0002460, 0xe1f0fff0,
23946 +      &avr32_syntax_table[AVR32_SYNTAX_PLSR_H],
23947 +      BFD_RELOC_UNUSED, 3, -1,
23948 +      {
23949 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23950 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23951 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23952 +      },
23953 +    },
23954 +    {
23955 +      AVR32_OPC_PMAX_SH, 4, 0xe0002390, 0xe1f0fff0,
23956 +      &avr32_syntax_table[AVR32_SYNTAX_PMAX_SH],
23957 +      BFD_RELOC_UNUSED, 3, -1,
23958 +      {
23959 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23960 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23961 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23962 +      },
23963 +    },
23964 +    {
23965 +      AVR32_OPC_PMAX_UB, 4, 0xe0002380, 0xe1f0fff0,
23966 +      &avr32_syntax_table[AVR32_SYNTAX_PMAX_UB],
23967 +      BFD_RELOC_UNUSED, 3, -1,
23968 +      {
23969 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23970 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23971 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23972 +      },
23973 +    },
23974 +    {
23975 +      AVR32_OPC_PMIN_SH, 4, 0xe00023b0, 0xe1f0fff0,
23976 +      &avr32_syntax_table[AVR32_SYNTAX_PMIN_SH],
23977 +      BFD_RELOC_UNUSED, 3, -1,
23978 +      {
23979 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23980 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23981 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23982 +      },
23983 +    },
23984 +    {
23985 +      AVR32_OPC_PMIN_UB, 4, 0xe00023a0, 0xe1f0fff0,
23986 +      &avr32_syntax_table[AVR32_SYNTAX_PMIN_UB],
23987 +      BFD_RELOC_UNUSED, 3, -1,
23988 +      {
23989 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
23990 +       &avr32_ifield_table[AVR32_IFIELD_RX],
23991 +       &avr32_ifield_table[AVR32_IFIELD_RY],
23992 +      },
23993 +    },
23994 +    {
23995 +      AVR32_OPC_POPJC, 2, 0xd7130000, 0xffff0000,
23996 +      &avr32_syntax_table[AVR32_SYNTAX_POPJC],
23997 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
23998 +    },
23999 +    {
24000 +      AVR32_OPC_POPM, 2, 0xd0020000, 0xf0070000,
24001 +      &avr32_syntax_table[AVR32_SYNTAX_POPM],
24002 +      BFD_RELOC_UNUSED, 1, -1,
24003 +      {
24004 +       &avr32_ifield_table[AVR32_IFIELD_POPM],
24005 +      },
24006 +    },
24007 +    {
24008 +      AVR32_OPC_POPM_E, 4, 0xe3cd0000, 0xffff0000,
24009 +      &avr32_syntax_table[AVR32_SYNTAX_POPM_E],
24010 +      BFD_RELOC_UNUSED, 1, -1,
24011 +      {
24012 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24013 +      },
24014 +    },
24015 +    {
24016 +      AVR32_OPC_PREF, 4, 0xf2100000, 0xfff00000,
24017 +      &avr32_syntax_table[AVR32_SYNTAX_PREF],
24018 +      BFD_RELOC_AVR32_16S, 2, -1,
24019 +      {
24020 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24021 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24022 +      },
24023 +    },
24024 +    {
24025 +      AVR32_OPC_PSAD, 4, 0xe0002400, 0xe1f0fff0,
24026 +      &avr32_syntax_table[AVR32_SYNTAX_PSAD],
24027 +      BFD_RELOC_UNUSED, 3, -1,
24028 +      {
24029 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24030 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24031 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24032 +      },
24033 +    },
24034 +    {
24035 +      AVR32_OPC_PSUB_B, 4, 0xe0002310, 0xe1f0fff0,
24036 +      &avr32_syntax_table[AVR32_SYNTAX_PSUB_B],
24037 +      BFD_RELOC_UNUSED, 3, -1,
24038 +      {
24039 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24040 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24041 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24042 +      },
24043 +    },
24044 +    {
24045 +      AVR32_OPC_PSUB_H, 4, 0xe0002010, 0xe1f0fff0,
24046 +      &avr32_syntax_table[AVR32_SYNTAX_PSUB_H],
24047 +      BFD_RELOC_UNUSED, 3, -1,
24048 +      {
24049 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24050 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24051 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24052 +      },
24053 +    },
24054 +    {
24055 +      AVR32_OPC_PSUBADD_H, 4, 0xe0002140, 0xe1f0ffc0,
24056 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADD_H],
24057 +      BFD_RELOC_UNUSED, 5, -1,
24058 +      {
24059 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24060 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24061 +       &avr32_ifield_table[AVR32_IFIELD_X],
24062 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24063 +       &avr32_ifield_table[AVR32_IFIELD_Y],
24064 +      },
24065 +    },
24066 +    {
24067 +      AVR32_OPC_PSUBADDH_SH, 4, 0xe00022c0, 0xe1f0ffc0,
24068 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADDH_SH],
24069 +      BFD_RELOC_UNUSED, 5, -1,
24070 +      {
24071 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24072 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24073 +       &avr32_ifield_table[AVR32_IFIELD_X],
24074 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24075 +       &avr32_ifield_table[AVR32_IFIELD_Y],
24076 +      },
24077 +    },
24078 +    {
24079 +      AVR32_OPC_PSUBADDS_SH, 4, 0xe00021c0, 0xe1f0ffc0,
24080 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_SH],
24081 +      BFD_RELOC_UNUSED, 5, -1,
24082 +      {
24083 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24084 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24085 +       &avr32_ifield_table[AVR32_IFIELD_X],
24086 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24087 +       &avr32_ifield_table[AVR32_IFIELD_Y],
24088 +      },
24089 +    },
24090 +    {
24091 +      AVR32_OPC_PSUBADDS_UH, 4, 0xe0002240, 0xe1f0ffc0,
24092 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBADDS_UH],
24093 +      BFD_RELOC_UNUSED, 5, -1,
24094 +      {
24095 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24096 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24097 +       &avr32_ifield_table[AVR32_IFIELD_X],
24098 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24099 +       &avr32_ifield_table[AVR32_IFIELD_Y],
24100 +      },
24101 +    },
24102 +    {
24103 +      AVR32_OPC_PSUBH_SH, 4, 0xe00020d0, 0xe1f0fff0,
24104 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBH_SH],
24105 +      BFD_RELOC_UNUSED, 3, -1,
24106 +      {
24107 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24108 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24109 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24110 +      },
24111 +    },
24112 +    {
24113 +      AVR32_OPC_PSUBH_UB, 4, 0xe0002370, 0xe1f0fff0,
24114 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBH_UB],
24115 +      BFD_RELOC_UNUSED, 3, -1,
24116 +      {
24117 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24118 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24119 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24120 +      },
24121 +    },
24122 +    {
24123 +      AVR32_OPC_PSUBS_SB, 4, 0xe0002330, 0xe1f0fff0,
24124 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SB],
24125 +      BFD_RELOC_UNUSED, 3, -1,
24126 +      {
24127 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24128 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24129 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24130 +      },
24131 +    },
24132 +    {
24133 +      AVR32_OPC_PSUBS_SH, 4, 0xe0002050, 0xe1f0fff0,
24134 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_SH],
24135 +      BFD_RELOC_UNUSED, 3, -1,
24136 +      {
24137 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24138 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24139 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24140 +      },
24141 +    },
24142 +    {
24143 +      AVR32_OPC_PSUBS_UB, 4, 0xe0002350, 0xe1f0fff0,
24144 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UB],
24145 +      BFD_RELOC_UNUSED, 3, -1,
24146 +      {
24147 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24148 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24149 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24150 +      },
24151 +    },
24152 +    {
24153 +      AVR32_OPC_PSUBS_UH, 4, 0xe0002090, 0xe1f0fff0,
24154 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBS_UH],
24155 +      BFD_RELOC_UNUSED, 3, -1,
24156 +      {
24157 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24158 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24159 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24160 +      },
24161 +    },
24162 +    {
24163 +      AVR32_OPC_PSUBX_H, 4, 0xe0002030, 0xe1f0fff0,
24164 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBX_H],
24165 +      BFD_RELOC_UNUSED, 3, -1,
24166 +      {
24167 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24168 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24169 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24170 +      },
24171 +    },
24172 +    {
24173 +      AVR32_OPC_PSUBXH_SH, 4, 0xe00020f0, 0xe1f0fff0,
24174 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBXH_SH],
24175 +      BFD_RELOC_UNUSED, 3, -1,
24176 +      {
24177 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24178 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24179 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24180 +      },
24181 +    },
24182 +    {
24183 +      AVR32_OPC_PSUBXS_SH, 4, 0xe0002070, 0xe1f0fff0,
24184 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_SH],
24185 +      BFD_RELOC_UNUSED, 3, -1,
24186 +      {
24187 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24188 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24189 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24190 +      },
24191 +    },
24192 +    {
24193 +      AVR32_OPC_PSUBXS_UH, 4, 0xe00020b0, 0xe1f0fff0,
24194 +      &avr32_syntax_table[AVR32_SYNTAX_PSUBXS_UH],
24195 +      BFD_RELOC_UNUSED, 3, -1,
24196 +      {
24197 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24198 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24199 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24200 +      },
24201 +    },
24202 +    {
24203 +      AVR32_OPC_PUNPCKSB_H, 4, 0xe00024a0, 0xe1ffffe0,
24204 +      &avr32_syntax_table[AVR32_SYNTAX_PUNPCKSB_H],
24205 +      BFD_RELOC_UNUSED, 3, -1,
24206 +      {
24207 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24208 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24209 +       &avr32_ifield_table[AVR32_IFIELD_Y],
24210 +      },
24211 +    },
24212 +    {
24213 +      AVR32_OPC_PUNPCKUB_H, 4, 0xe0002480, 0xe1ffffe0,
24214 +      &avr32_syntax_table[AVR32_SYNTAX_PUNPCKUB_H],
24215 +      BFD_RELOC_UNUSED, 3, -1,
24216 +      {
24217 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24218 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24219 +       &avr32_ifield_table[AVR32_IFIELD_Y],
24220 +      },
24221 +    },
24222 +    {
24223 +      AVR32_OPC_PUSHJC, 2, 0xd7230000, 0xffff0000,
24224 +      &avr32_syntax_table[AVR32_SYNTAX_PUSHJC],
24225 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
24226 +    },
24227 +    {
24228 +      AVR32_OPC_PUSHM, 2, 0xd0010000, 0xf00f0000,
24229 +      &avr32_syntax_table[AVR32_SYNTAX_PUSHM],
24230 +      BFD_RELOC_UNUSED, 1, -1,
24231 +      {
24232 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
24233 +      },
24234 +    },
24235 +    {
24236 +      AVR32_OPC_PUSHM_E, 4, 0xebcd0000, 0xffff0000,
24237 +      &avr32_syntax_table[AVR32_SYNTAX_PUSHM_E],
24238 +      BFD_RELOC_UNUSED, 1, -1,
24239 +      {
24240 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24241 +      },
24242 +    },
24243 +    {
24244 +      AVR32_OPC_RCALL1, 2, 0xc00c0000, 0xf00c0000,
24245 +      &avr32_syntax_table[AVR32_SYNTAX_RCALL1],
24246 +      BFD_RELOC_AVR32_11H_PCREL, 1, 0,
24247 +      {
24248 +       &avr32_ifield_table[AVR32_IFIELD_K10],
24249 +      },
24250 +    },
24251 +    {
24252 +      AVR32_OPC_RCALL2, 4, 0xe0a00000, 0xe1ef0000,
24253 +      &avr32_syntax_table[AVR32_SYNTAX_RCALL2],
24254 +      BFD_RELOC_AVR32_22H_PCREL, 1, 0,
24255 +      {
24256 +       &avr32_ifield_table[AVR32_IFIELD_K21],
24257 +      },
24258 +    },
24259 +    {
24260 +      AVR32_OPC_RETEQ, 2, 0x5e000000, 0xfff00000,
24261 +      &avr32_syntax_table[AVR32_SYNTAX_RETEQ],
24262 +      BFD_RELOC_NONE, 1, -1,
24263 +      {
24264 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24265 +      },
24266 +    },
24267 +    {
24268 +      AVR32_OPC_RETNE, 2, 0x5e100000, 0xfff00000,
24269 +      &avr32_syntax_table[AVR32_SYNTAX_RETNE],
24270 +      BFD_RELOC_NONE, 1, -1,
24271 +      {
24272 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24273 +      },
24274 +    },
24275 +    {
24276 +      AVR32_OPC_RETCC, 2, 0x5e200000, 0xfff00000,
24277 +      &avr32_syntax_table[AVR32_SYNTAX_RETHS],
24278 +      BFD_RELOC_NONE, 1, -1,
24279 +      {
24280 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24281 +      },
24282 +    },
24283 +    {
24284 +      AVR32_OPC_RETCS, 2, 0x5e300000, 0xfff00000,
24285 +      &avr32_syntax_table[AVR32_SYNTAX_RETLO],
24286 +      BFD_RELOC_NONE, 1, -1,
24287 +      {
24288 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24289 +      },
24290 +    },
24291 +    {
24292 +      AVR32_OPC_RETGE, 2, 0x5e400000, 0xfff00000,
24293 +      &avr32_syntax_table[AVR32_SYNTAX_RETGE],
24294 +      BFD_RELOC_NONE, 1, -1,
24295 +      {
24296 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24297 +      },
24298 +    },
24299 +    {
24300 +      AVR32_OPC_RETLT, 2, 0x5e500000, 0xfff00000,
24301 +      &avr32_syntax_table[AVR32_SYNTAX_RETLT],
24302 +      BFD_RELOC_NONE, 1, -1,
24303 +      {
24304 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24305 +      },
24306 +    },
24307 +    {
24308 +      AVR32_OPC_RETMI, 2, 0x5e600000, 0xfff00000,
24309 +      &avr32_syntax_table[AVR32_SYNTAX_RETMI],
24310 +      BFD_RELOC_NONE, 1, -1,
24311 +      {
24312 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24313 +      },
24314 +    },
24315 +    {
24316 +      AVR32_OPC_RETPL, 2, 0x5e700000, 0xfff00000,
24317 +      &avr32_syntax_table[AVR32_SYNTAX_RETPL],
24318 +      BFD_RELOC_NONE, 1, -1,
24319 +      {
24320 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24321 +      },
24322 +    },
24323 +    {
24324 +      AVR32_OPC_RETLS, 2, 0x5e800000, 0xfff00000,
24325 +      &avr32_syntax_table[AVR32_SYNTAX_RETLS],
24326 +      BFD_RELOC_NONE, 1, -1,
24327 +      {
24328 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24329 +      },
24330 +    },
24331 +    {
24332 +      AVR32_OPC_RETGT, 2, 0x5e900000, 0xfff00000,
24333 +      &avr32_syntax_table[AVR32_SYNTAX_RETGT],
24334 +      BFD_RELOC_NONE, 1, -1,
24335 +      {
24336 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24337 +      },
24338 +    },
24339 +    {
24340 +      AVR32_OPC_RETLE, 2, 0x5ea00000, 0xfff00000,
24341 +      &avr32_syntax_table[AVR32_SYNTAX_RETLE],
24342 +      BFD_RELOC_NONE, 1, -1,
24343 +      {
24344 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24345 +      },
24346 +    },
24347 +    {
24348 +      AVR32_OPC_RETHI, 2, 0x5eb00000, 0xfff00000,
24349 +      &avr32_syntax_table[AVR32_SYNTAX_RETHI],
24350 +      BFD_RELOC_NONE, 1, -1,
24351 +      {
24352 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24353 +      },
24354 +    },
24355 +    {
24356 +      AVR32_OPC_RETVS, 2, 0x5ec00000, 0xfff00000,
24357 +      &avr32_syntax_table[AVR32_SYNTAX_RETVS],
24358 +      BFD_RELOC_NONE, 1, -1,
24359 +      {
24360 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24361 +      },
24362 +    },
24363 +    {
24364 +      AVR32_OPC_RETVC, 2, 0x5ed00000, 0xfff00000,
24365 +      &avr32_syntax_table[AVR32_SYNTAX_RETVC],
24366 +      BFD_RELOC_NONE, 1, -1,
24367 +      {
24368 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24369 +      },
24370 +    },
24371 +    {
24372 +      AVR32_OPC_RETQS, 2, 0x5ee00000, 0xfff00000,
24373 +      &avr32_syntax_table[AVR32_SYNTAX_RETQS],
24374 +      BFD_RELOC_NONE, 1, -1,
24375 +      {
24376 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24377 +      },
24378 +    },
24379 +    {
24380 +      AVR32_OPC_RETAL, 2, 0x5ef00000, 0xfff00000,
24381 +      &avr32_syntax_table[AVR32_SYNTAX_RETAL],
24382 +      BFD_RELOC_NONE, 1, -1,
24383 +      {
24384 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24385 +      },
24386 +    },
24387 +    {
24388 +      AVR32_OPC_RETD, 2, 0xd6230000, 0xffff0000,
24389 +      &avr32_syntax_table[AVR32_SYNTAX_RETD],
24390 +      BFD_RELOC_NONE, 0, -1, { NULL },
24391 +    },
24392 +    {
24393 +      AVR32_OPC_RETE, 2, 0xd6030000, 0xffff0000,
24394 +      &avr32_syntax_table[AVR32_SYNTAX_RETE],
24395 +      BFD_RELOC_NONE, 0, -1, { NULL },
24396 +    },
24397 +    {
24398 +      AVR32_OPC_RETJ, 2, 0xd6330000, 0xffff0000,
24399 +      &avr32_syntax_table[AVR32_SYNTAX_RETJ],
24400 +      BFD_RELOC_NONE, 0, -1, { NULL },
24401 +    },
24402 +    {
24403 +      AVR32_OPC_RETS, 2, 0xd6130000, 0xffff0000,
24404 +      &avr32_syntax_table[AVR32_SYNTAX_RETS],
24405 +      BFD_RELOC_NONE, 0, -1, { NULL },
24406 +    },
24407 +    {
24408 +      AVR32_OPC_RJMP, 2, 0xc0080000, 0xf00c0000,
24409 +      &avr32_syntax_table[AVR32_SYNTAX_RJMP],
24410 +      BFD_RELOC_AVR32_11H_PCREL, 1, 0,
24411 +      {
24412 +       &avr32_ifield_table[AVR32_IFIELD_K10],
24413 +      },
24414 +    },
24415 +    {
24416 +      AVR32_OPC_ROL, 2, 0x5cf00000, 0xfff00000,
24417 +      &avr32_syntax_table[AVR32_SYNTAX_ROL],
24418 +      BFD_RELOC_UNUSED, 1, -1,
24419 +      {
24420 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24421 +      }
24422 +    },
24423 +    {
24424 +      AVR32_OPC_ROR, 2, 0x5d000000, 0xfff00000,
24425 +      &avr32_syntax_table[AVR32_SYNTAX_ROR],
24426 +      BFD_RELOC_UNUSED, 1, -1,
24427 +      {
24428 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24429 +      }
24430 +    },
24431 +    {
24432 +      AVR32_OPC_RSUB1, 2, 0x00200000, 0xe1f00000,
24433 +      &avr32_syntax_table[AVR32_SYNTAX_RSUB1],
24434 +      BFD_RELOC_UNUSED, 2, -1,
24435 +      {
24436 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24437 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24438 +      },
24439 +    },
24440 +    {
24441 +      AVR32_OPC_RSUB2, 4, 0xe0001100, 0xe1f0ff00,
24442 +      &avr32_syntax_table[AVR32_SYNTAX_RSUB2],
24443 +      BFD_RELOC_AVR32_8S_EXT, 3, 2,
24444 +      {
24445 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24446 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24447 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24448 +      },
24449 +    },
24450 +    {
24451 +      AVR32_OPC_SATADD_H, 4, 0xe00002c0, 0xe1f0fff0,
24452 +      &avr32_syntax_table[AVR32_SYNTAX_SATADD_H],
24453 +      BFD_RELOC_UNUSED, 3, -1,
24454 +      {
24455 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24456 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24457 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24458 +      },
24459 +    },
24460 +    {
24461 +      AVR32_OPC_SATADD_W, 4, 0xe00000c0, 0xe1f0fff0,
24462 +      &avr32_syntax_table[AVR32_SYNTAX_SATADD_W],
24463 +      BFD_RELOC_UNUSED, 3, -1,
24464 +      {
24465 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24466 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24467 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24468 +      },
24469 +    },
24470 +    {
24471 +      AVR32_OPC_SATRNDS, 4, 0xf3b00000, 0xfff0fc00,
24472 +      &avr32_syntax_table[AVR32_SYNTAX_SATRNDS],
24473 +      BFD_RELOC_UNUSED, 3, -1,
24474 +      {
24475 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24476 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24477 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24478 +      },
24479 +    },
24480 +    {
24481 +      AVR32_OPC_SATRNDU, 4, 0xf3b00400, 0xfff0fc00,
24482 +      &avr32_syntax_table[AVR32_SYNTAX_SATRNDU],
24483 +      BFD_RELOC_UNUSED, 3, -1,
24484 +      {
24485 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24486 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24487 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24488 +      },
24489 +    },
24490 +    {
24491 +      AVR32_OPC_SATS, 4, 0xf1b00000, 0xfff0fc00,
24492 +      &avr32_syntax_table[AVR32_SYNTAX_SATS],
24493 +      BFD_RELOC_UNUSED, 3, -1,
24494 +      {
24495 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24496 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24497 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24498 +      },
24499 +    },
24500 +    {
24501 +      AVR32_OPC_SATSUB_H, 4, 0xe00003c0, 0xe1f0fff0,
24502 +      &avr32_syntax_table[AVR32_SYNTAX_SATSUB_H],
24503 +      BFD_RELOC_UNUSED, 3, -1,
24504 +      {
24505 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24506 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24507 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24508 +      },
24509 +    },
24510 +    {
24511 +      AVR32_OPC_SATSUB_W1, 4, 0xe00001c0, 0xe1f0fff0,
24512 +      &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W1],
24513 +      BFD_RELOC_UNUSED, 3, -1,
24514 +      {
24515 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24516 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24517 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24518 +      },
24519 +    },
24520 +    {
24521 +      AVR32_OPC_SATSUB_W2, 4, 0xe0d00000, 0xe1f00000,
24522 +      &avr32_syntax_table[AVR32_SYNTAX_SATSUB_W2],
24523 +      BFD_RELOC_UNUSED, 3, -1,
24524 +      {
24525 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24526 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24527 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24528 +      },
24529 +    },
24530 +    {
24531 +      AVR32_OPC_SATU, 4, 0xf1b00400, 0xfff0fc00,
24532 +      &avr32_syntax_table[AVR32_SYNTAX_SATU],
24533 +      BFD_RELOC_UNUSED, 3, -1,
24534 +      {
24535 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24536 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
24537 +       &avr32_ifield_table[AVR32_IFIELD_S5],
24538 +      },
24539 +    },
24540 +    {
24541 +      AVR32_OPC_SBC, 4, 0xe0000140, 0xe1f0fff0,
24542 +      &avr32_syntax_table[AVR32_SYNTAX_SBC],
24543 +      BFD_RELOC_UNUSED, 3, -1,
24544 +      {
24545 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24546 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24547 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24548 +      },
24549 +    },
24550 +    {
24551 +      AVR32_OPC_SBR, 2, 0xa1a00000, 0xe1e00000,
24552 +      &avr32_syntax_table[AVR32_SYNTAX_SBR],
24553 +      BFD_RELOC_UNUSED, 2, -1,
24554 +      {
24555 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24556 +       &avr32_ifield_table[AVR32_IFIELD_BIT5C],
24557 +      },
24558 +    },
24559 +    {
24560 +      AVR32_OPC_SCALL, 2, 0xd7330000, 0xffff0000,
24561 +      &avr32_syntax_table[AVR32_SYNTAX_SCALL],
24562 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
24563 +    },
24564 +    {
24565 +      AVR32_OPC_SCR, 2, 0x5c100000, 0xfff00000,
24566 +      &avr32_syntax_table[AVR32_SYNTAX_SCR],
24567 +      BFD_RELOC_UNUSED, 1, -1,
24568 +      {
24569 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24570 +      },
24571 +    },
24572 +    {
24573 +      AVR32_OPC_SLEEP, 4, 0xe9b00000, 0xffffff00,
24574 +      &avr32_syntax_table[AVR32_SYNTAX_SLEEP],
24575 +      BFD_RELOC_AVR32_8S_EXT, 1, 0,
24576 +      {
24577 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24578 +      },
24579 +    },
24580 +    {
24581 +      AVR32_OPC_SREQ, 2, 0x5f000000, 0xfff00000,
24582 +      &avr32_syntax_table[AVR32_SYNTAX_SREQ],
24583 +      BFD_RELOC_UNUSED, 1, -1,
24584 +      {
24585 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24586 +      },
24587 +    },
24588 +    {
24589 +      AVR32_OPC_SRNE, 2, 0x5f100000, 0xfff00000,
24590 +      &avr32_syntax_table[AVR32_SYNTAX_SRNE],
24591 +      BFD_RELOC_UNUSED, 1, -1,
24592 +      {
24593 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24594 +      },
24595 +    },
24596 +    {
24597 +      AVR32_OPC_SRCC, 2, 0x5f200000, 0xfff00000,
24598 +      &avr32_syntax_table[AVR32_SYNTAX_SRHS],
24599 +      BFD_RELOC_UNUSED, 1, -1,
24600 +      {
24601 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24602 +      },
24603 +    },
24604 +    {
24605 +      AVR32_OPC_SRCS, 2, 0x5f300000, 0xfff00000,
24606 +      &avr32_syntax_table[AVR32_SYNTAX_SRLO],
24607 +      BFD_RELOC_UNUSED, 1, -1,
24608 +      {
24609 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24610 +      },
24611 +    },
24612 +    {
24613 +      AVR32_OPC_SRGE, 2, 0x5f400000, 0xfff00000,
24614 +      &avr32_syntax_table[AVR32_SYNTAX_SRGE],
24615 +      BFD_RELOC_UNUSED, 1, -1,
24616 +      {
24617 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24618 +      },
24619 +    },
24620 +    {
24621 +      AVR32_OPC_SRLT, 2, 0x5f500000, 0xfff00000,
24622 +      &avr32_syntax_table[AVR32_SYNTAX_SRLT],
24623 +      BFD_RELOC_UNUSED, 1, -1,
24624 +      {
24625 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24626 +      },
24627 +    },
24628 +    {
24629 +      AVR32_OPC_SRMI, 2, 0x5f600000, 0xfff00000,
24630 +      &avr32_syntax_table[AVR32_SYNTAX_SRMI],
24631 +      BFD_RELOC_UNUSED, 1, -1,
24632 +      {
24633 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24634 +      },
24635 +    },
24636 +    {
24637 +      AVR32_OPC_SRPL, 2, 0x5f700000, 0xfff00000,
24638 +      &avr32_syntax_table[AVR32_SYNTAX_SRPL],
24639 +      BFD_RELOC_UNUSED, 1, -1,
24640 +      {
24641 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24642 +      },
24643 +    },
24644 +    {
24645 +      AVR32_OPC_SRLS, 2, 0x5f800000, 0xfff00000,
24646 +      &avr32_syntax_table[AVR32_SYNTAX_SRLS],
24647 +      BFD_RELOC_UNUSED, 1, -1,
24648 +      {
24649 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24650 +      },
24651 +    },
24652 +    {
24653 +      AVR32_OPC_SRGT, 2, 0x5f900000, 0xfff00000,
24654 +      &avr32_syntax_table[AVR32_SYNTAX_SRGT],
24655 +      BFD_RELOC_UNUSED, 1, -1,
24656 +      {
24657 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24658 +      },
24659 +    },
24660 +    {
24661 +      AVR32_OPC_SRLE, 2, 0x5fa00000, 0xfff00000,
24662 +      &avr32_syntax_table[AVR32_SYNTAX_SRLE],
24663 +      BFD_RELOC_UNUSED, 1, -1,
24664 +      {
24665 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24666 +      },
24667 +    },
24668 +    {
24669 +      AVR32_OPC_SRHI, 2, 0x5fb00000, 0xfff00000,
24670 +      &avr32_syntax_table[AVR32_SYNTAX_SRHI],
24671 +      BFD_RELOC_UNUSED, 1, -1,
24672 +      {
24673 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24674 +      },
24675 +    },
24676 +    {
24677 +      AVR32_OPC_SRVS, 2, 0x5fc00000, 0xfff00000,
24678 +      &avr32_syntax_table[AVR32_SYNTAX_SRVS],
24679 +      BFD_RELOC_UNUSED, 1, -1,
24680 +      {
24681 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24682 +      },
24683 +    },
24684 +    {
24685 +      AVR32_OPC_SRVC, 2, 0x5fd00000, 0xfff00000,
24686 +      &avr32_syntax_table[AVR32_SYNTAX_SRVC],
24687 +      BFD_RELOC_UNUSED, 1, -1,
24688 +      {
24689 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24690 +      },
24691 +    },
24692 +    {
24693 +      AVR32_OPC_SRQS, 2, 0x5fe00000, 0xfff00000,
24694 +      &avr32_syntax_table[AVR32_SYNTAX_SRQS],
24695 +      BFD_RELOC_UNUSED, 1, -1,
24696 +      {
24697 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24698 +      },
24699 +    },
24700 +    {
24701 +      AVR32_OPC_SRAL, 2, 0x5ff00000, 0xfff00000,
24702 +      &avr32_syntax_table[AVR32_SYNTAX_SRAL],
24703 +      BFD_RELOC_UNUSED, 1, -1,
24704 +      {
24705 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24706 +      },
24707 +    },
24708 +    {
24709 +      AVR32_OPC_SSRF, 2, 0xd2030000, 0xfe0f0000,
24710 +      &avr32_syntax_table[AVR32_SYNTAX_SSRF],
24711 +      BFD_RELOC_UNUSED, 1, -1,
24712 +      {
24713 +       &avr32_ifield_table[AVR32_IFIELD_K5C],
24714 +      },
24715 +    },
24716 +    {
24717 +      AVR32_OPC_ST_B1, 2, 0x00c00000, 0xe1f00000,
24718 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B1],
24719 +      BFD_RELOC_UNUSED, 2, -1,
24720 +      {
24721 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24722 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24723 +      },
24724 +    },
24725 +    {
24726 +      AVR32_OPC_ST_B2, 2, 0x00f00000, 0xe1f00000,
24727 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B2],
24728 +      BFD_RELOC_UNUSED, 2, -1,
24729 +      {
24730 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24731 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24732 +      },
24733 +    },
24734 +    {
24735 +      AVR32_OPC_ST_B5, 4, 0xe0000b00, 0xe1f0ffc0,
24736 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B5],
24737 +      BFD_RELOC_UNUSED, 4, -1,
24738 +      {
24739 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24740 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24741 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24742 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24743 +      },
24744 +    },
24745 +    {
24746 +      AVR32_OPC_ST_B3, 2, 0xa0800000, 0xe1800000,
24747 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B3],
24748 +      BFD_RELOC_AVR32_3U, 3, 1,
24749 +      {
24750 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24751 +       &avr32_ifield_table[AVR32_IFIELD_K3],
24752 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24753 +      },
24754 +    },
24755 +    {
24756 +      AVR32_OPC_ST_B4, 4, 0xe1600000, 0xe1f00000,
24757 +      &avr32_syntax_table[AVR32_SYNTAX_ST_B4],
24758 +      BFD_RELOC_AVR32_16S, 3, 1,
24759 +      {
24760 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24761 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24762 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24763 +      },
24764 +    },
24765 +    {
24766 +      AVR32_OPC_ST_D1, 2, 0xa1200000, 0xe1f10000,
24767 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D1],
24768 +      BFD_RELOC_UNUSED, 2, -1,
24769 +      {
24770 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24771 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24772 +      },
24773 +    },
24774 +    {
24775 +      AVR32_OPC_ST_D2, 2, 0xa1210000, 0xe1f10000,
24776 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D2],
24777 +      BFD_RELOC_UNUSED, 2, -1,
24778 +      {
24779 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24780 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24781 +      },
24782 +    },
24783 +    {
24784 +      AVR32_OPC_ST_D3, 2, 0xa1110000, 0xe1f10000,
24785 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D3],
24786 +      BFD_RELOC_UNUSED, 2, -1,
24787 +      {
24788 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24789 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24790 +      },
24791 +    },
24792 +    {
24793 +      AVR32_OPC_ST_D5, 4, 0xe0000800, 0xe1f0ffc1,
24794 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D5],
24795 +      BFD_RELOC_UNUSED, 4, -1,
24796 +      {
24797 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24798 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24799 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24800 +       &avr32_ifield_table[AVR32_IFIELD_RD_DW],
24801 +      },
24802 +    },
24803 +    {
24804 +      AVR32_OPC_ST_D4, 4, 0xe0e10000, 0xe1f10000,
24805 +      &avr32_syntax_table[AVR32_SYNTAX_ST_D4],
24806 +      BFD_RELOC_AVR32_16S, 3, 1,
24807 +      {
24808 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24809 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24810 +       &avr32_ifield_table[AVR32_IFIELD_RY_DW],
24811 +      },
24812 +    },
24813 +    {
24814 +      AVR32_OPC_ST_H1, 2, 0x00b00000, 0xe1f00000,
24815 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H1],
24816 +      BFD_RELOC_UNUSED, 2, -1,
24817 +      {
24818 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24819 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24820 +      },
24821 +    },
24822 +    {
24823 +      AVR32_OPC_ST_H2, 2, 0x00e00000, 0xe1f00000,
24824 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H2],
24825 +      BFD_RELOC_UNUSED, 2, -1,
24826 +      {
24827 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24828 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24829 +      },
24830 +    },
24831 +    {
24832 +      AVR32_OPC_ST_H5, 4, 0xe0000a00, 0xe1f0ffc0,
24833 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H5],
24834 +      BFD_RELOC_UNUSED, 4, -1,
24835 +      {
24836 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24837 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24838 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24839 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24840 +      },
24841 +    },
24842 +    {
24843 +      AVR32_OPC_ST_H3, 2, 0xa0000000, 0xe1800000,
24844 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H3],
24845 +      BFD_RELOC_AVR32_4UH, 3, 1,
24846 +      {
24847 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24848 +       &avr32_ifield_table[AVR32_IFIELD_K3],
24849 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24850 +      },
24851 +    },
24852 +    {
24853 +      AVR32_OPC_ST_H4, 4, 0xe1500000, 0xe1f00000,
24854 +      &avr32_syntax_table[AVR32_SYNTAX_ST_H4],
24855 +      BFD_RELOC_AVR32_16S, 3, 1,
24856 +      {
24857 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24858 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24859 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24860 +      },
24861 +    },
24862 +    {
24863 +      AVR32_OPC_ST_W1, 2, 0x00a00000, 0xe1f00000,
24864 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W1],
24865 +      BFD_RELOC_UNUSED, 2, -1,
24866 +      {
24867 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24868 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24869 +      },
24870 +    },
24871 +    {
24872 +      AVR32_OPC_ST_W2, 2, 0x00d00000, 0xe1f00000,
24873 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W2],
24874 +      BFD_RELOC_UNUSED, 2, -1,
24875 +      {
24876 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24877 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24878 +      },
24879 +    },
24880 +    {
24881 +      AVR32_OPC_ST_W5, 4, 0xe0000900, 0xe1f0ffc0,
24882 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W5],
24883 +      BFD_RELOC_UNUSED, 4, -1,
24884 +      {
24885 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24886 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24887 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24888 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24889 +      },
24890 +    },
24891 +    {
24892 +      AVR32_OPC_ST_W3, 2, 0x81000000, 0xe1000000,
24893 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W3],
24894 +      BFD_RELOC_AVR32_6UW, 3, 1,
24895 +      {
24896 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24897 +       &avr32_ifield_table[AVR32_IFIELD_K4],
24898 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24899 +      },
24900 +    },
24901 +    {
24902 +      AVR32_OPC_ST_W4, 4, 0xe1400000, 0xe1f00000,
24903 +      &avr32_syntax_table[AVR32_SYNTAX_ST_W4],
24904 +      BFD_RELOC_AVR32_16S, 3, 1,
24905 +      {
24906 +       &avr32_ifield_table[AVR32_IFIELD_RX],
24907 +       &avr32_ifield_table[AVR32_IFIELD_K16],
24908 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24909 +      },
24910 +    },
24911 +    {
24912 +      AVR32_OPC_STC_D1, 4, 0xeba01000, 0xfff01100,
24913 +      &avr32_syntax_table[AVR32_SYNTAX_STC_D1],
24914 +      BFD_RELOC_AVR32_10UW, 4, 2,
24915 +      {
24916 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24917 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24918 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24919 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24920 +      },
24921 +    },
24922 +    {
24923 +      AVR32_OPC_STC_D2, 4, 0xefa00070, 0xfff011f0,
24924 +      &avr32_syntax_table[AVR32_SYNTAX_STC_D2],
24925 +      BFD_RELOC_UNUSED, 3, -1,
24926 +      {
24927 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24928 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24929 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24930 +      },
24931 +    },
24932 +    {
24933 +      AVR32_OPC_STC_D3, 4, 0xefa010c0, 0xfff011c0,
24934 +      &avr32_syntax_table[AVR32_SYNTAX_STC_D3],
24935 +      BFD_RELOC_UNUSED, 5, -1,
24936 +      {
24937 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24938 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24939 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24940 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24941 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24942 +      },
24943 +    },
24944 +    {
24945 +      AVR32_OPC_STC_W1, 4, 0xeba00000, 0xfff01000,
24946 +      &avr32_syntax_table[AVR32_SYNTAX_STC_W1],
24947 +      BFD_RELOC_AVR32_10UW, 4, 2,
24948 +      {
24949 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24950 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24951 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
24952 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24953 +      },
24954 +    },
24955 +    {
24956 +      AVR32_OPC_STC_W2, 4, 0xefa00060, 0xfff010ff,
24957 +      &avr32_syntax_table[AVR32_SYNTAX_STC_W2],
24958 +      BFD_RELOC_UNUSED, 3, -1,
24959 +      {
24960 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24961 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24962 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24963 +      },
24964 +    },
24965 +    {
24966 +      AVR32_OPC_STC_W3, 4, 0xefa01080, 0xfff010c0,
24967 +      &avr32_syntax_table[AVR32_SYNTAX_STC_W3],
24968 +      BFD_RELOC_UNUSED, 5, -1,
24969 +      {
24970 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
24971 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24972 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
24973 +       &avr32_ifield_table[AVR32_IFIELD_K2],
24974 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24975 +      },
24976 +    },
24977 +    {
24978 +      AVR32_OPC_STC0_D, 4, 0xf7a00000, 0xfff00100,
24979 +      &avr32_syntax_table[AVR32_SYNTAX_STC0_D],
24980 +      BFD_RELOC_AVR32_14UW, 3, 1,
24981 +      {
24982 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24983 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
24984 +       &avr32_ifield_table[AVR32_IFIELD_CRD_DW],
24985 +      },
24986 +    },
24987 +    {
24988 +      AVR32_OPC_STC0_W, 4, 0xf5a00000, 0xfff00000,
24989 +      &avr32_syntax_table[AVR32_SYNTAX_STC0_W],
24990 +      BFD_RELOC_AVR32_14UW, 3, 1,
24991 +      {
24992 +       &avr32_ifield_table[AVR32_IFIELD_RY],
24993 +       &avr32_ifield_table[AVR32_IFIELD_K12CP],
24994 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
24995 +      },
24996 +    },
24997 +    {
24998 +      AVR32_OPC_STCM_D, 4, 0xeda00500, 0xfff01f00,
24999 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_D],
25000 +      BFD_RELOC_UNUSED, 3, -1,
25001 +      {
25002 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
25003 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25004 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25005 +      },
25006 +    },
25007 +    {
25008 +      AVR32_OPC_STCM_D_PU, 4, 0xeda01500, 0xfff01f00,
25009 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_D_PU],
25010 +      BFD_RELOC_UNUSED, 3, -1,
25011 +      {
25012 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
25013 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25014 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25015 +      },
25016 +    },
25017 +    {
25018 +      AVR32_OPC_STCM_W, 4, 0xeda00200, 0xfff01e00,
25019 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_W],
25020 +      BFD_RELOC_UNUSED, 4, -1,
25021 +      {
25022 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
25023 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25024 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25025 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
25026 +      },
25027 +    },
25028 +    {
25029 +      AVR32_OPC_STCM_W_PU, 4, 0xeda01200, 0xfff01e00,
25030 +      &avr32_syntax_table[AVR32_SYNTAX_STCM_W_PU],
25031 +      BFD_RELOC_UNUSED, 4, -1,
25032 +      {
25033 +       &avr32_ifield_table[AVR32_IFIELD_CPNO],
25034 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25035 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25036 +       &avr32_ifield_table[AVR32_IFIELD_CM_HL],
25037 +      },
25038 +    },
25039 +    {
25040 +      AVR32_OPC_STCOND, 4, 0xe1700000, 0xe1f00000,
25041 +      &avr32_syntax_table[AVR32_SYNTAX_STCOND],
25042 +      BFD_RELOC_UNUSED, 3, -1,
25043 +      {
25044 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25045 +       &avr32_ifield_table[AVR32_IFIELD_K16],
25046 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25047 +      },
25048 +    },
25049 +    {
25050 +      AVR32_OPC_STDSP, 2, 0x50000000, 0xf8000000,
25051 +      &avr32_syntax_table[AVR32_SYNTAX_STDSP],
25052 +      BFD_RELOC_UNUSED, 2, -1,
25053 +      {
25054 +       &avr32_ifield_table[AVR32_IFIELD_K7C],
25055 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25056 +      },
25057 +    },
25058 +    {
25059 +      AVR32_OPC_STHH_W2, 4, 0xe1e08000, 0xe1f0c0c0,
25060 +      &avr32_syntax_table[AVR32_SYNTAX_STHH_W2],
25061 +      BFD_RELOC_UNUSED, 7, -1,
25062 +      {
25063 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
25064 +       &avr32_ifield_table[AVR32_IFIELD_CRD_RI],
25065 +       &avr32_ifield_table[AVR32_IFIELD_K2],
25066 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25067 +       &avr32_ifield_table[AVR32_IFIELD_X2],
25068 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25069 +       &avr32_ifield_table[AVR32_IFIELD_Y2],
25070 +      },
25071 +    },
25072 +    {
25073 +      AVR32_OPC_STHH_W1, 4, 0xe1e0c000, 0xe1f0c000,
25074 +      &avr32_syntax_table[AVR32_SYNTAX_STHH_W1],
25075 +      BFD_RELOC_AVR32_STHH_W, 6, 1,
25076 +      {
25077 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
25078 +       &avr32_ifield_table[AVR32_IFIELD_K8E2],
25079 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25080 +       &avr32_ifield_table[AVR32_IFIELD_X2],
25081 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25082 +       &avr32_ifield_table[AVR32_IFIELD_Y2],
25083 +      },
25084 +    },
25085 +    {
25086 +      AVR32_OPC_STM, 4, 0xe9c00000, 0xfff00000,
25087 +      &avr32_syntax_table[AVR32_SYNTAX_STM],
25088 +      BFD_RELOC_UNUSED, 2, -1,
25089 +      {
25090 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25091 +       &avr32_ifield_table[AVR32_IFIELD_K16],
25092 +      },
25093 +    },
25094 +    {
25095 +      AVR32_OPC_STM_PU, 4, 0xebc00000, 0xfff00000,
25096 +      &avr32_syntax_table[AVR32_SYNTAX_STM_PU],
25097 +      BFD_RELOC_UNUSED, 2, -1,
25098 +      {
25099 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25100 +       &avr32_ifield_table[AVR32_IFIELD_K16],
25101 +      },
25102 +    },
25103 +    {
25104 +      AVR32_OPC_STMTS, 4, 0xedc00000, 0xfff00000,
25105 +      &avr32_syntax_table[AVR32_SYNTAX_STMTS],
25106 +      BFD_RELOC_UNUSED, 2, -1,
25107 +      {
25108 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25109 +       &avr32_ifield_table[AVR32_IFIELD_K16],
25110 +      },
25111 +    },
25112 +    {
25113 +      AVR32_OPC_STMTS_PU, 4, 0xefc00000, 0xfff00000,
25114 +      &avr32_syntax_table[AVR32_SYNTAX_STMTS_PU],
25115 +      BFD_RELOC_UNUSED, 2, -1,
25116 +      {
25117 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25118 +       &avr32_ifield_table[AVR32_IFIELD_K16],
25119 +      },
25120 +    },
25121 +    {
25122 +      AVR32_OPC_STSWP_H, 4, 0xe1d09000, 0xe1f0f000,
25123 +      &avr32_syntax_table[AVR32_SYNTAX_STSWP_H],
25124 +      BFD_RELOC_UNUSED, 3, -1,
25125 +      {
25126 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25127 +       &avr32_ifield_table[AVR32_IFIELD_K12],
25128 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25129 +      },
25130 +    },
25131 +    {
25132 +      AVR32_OPC_STSWP_W, 4, 0xe1d0a000, 0xe1f0f000,
25133 +      &avr32_syntax_table[AVR32_SYNTAX_STSWP_W],
25134 +      BFD_RELOC_UNUSED, 3, -1,
25135 +      {
25136 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25137 +       &avr32_ifield_table[AVR32_IFIELD_K12],
25138 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25139 +      },
25140 +    },
25141 +    {
25142 +      AVR32_OPC_SUB1, 2, 0x00100000, 0xe1f00000,
25143 +      &avr32_syntax_table[AVR32_SYNTAX_SUB1],
25144 +      BFD_RELOC_UNUSED, 2, -1,
25145 +      {
25146 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25147 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25148 +      },
25149 +    },
25150 +    {
25151 +      AVR32_OPC_SUB2, 4, 0xe0000100, 0xe1f0ffc0,
25152 +      &avr32_syntax_table[AVR32_SYNTAX_SUB2],
25153 +      BFD_RELOC_UNUSED, 4, -1,
25154 +      {
25155 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
25156 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25157 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25158 +       &avr32_ifield_table[AVR32_IFIELD_K2],
25159 +      },
25160 +    },
25161 +    {
25162 +      AVR32_OPC_SUB5, 4, 0xe0c00000, 0xe1f00000,
25163 +      &avr32_syntax_table[AVR32_SYNTAX_SUB5],
25164 +      BFD_RELOC_AVR32_SUB5, 3, 2,
25165 +      {
25166 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25167 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25168 +       &avr32_ifield_table[AVR32_IFIELD_K16],
25169 +      },
25170 +    },
25171 +    {
25172 +      AVR32_OPC_SUB3_SP, 2, 0x200d0000, 0xf00f0000,
25173 +      &avr32_syntax_table[AVR32_SYNTAX_SUB3_SP],
25174 +      BFD_RELOC_AVR32_10SW, 2, 1,
25175 +      {
25176 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25177 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
25178 +      },
25179 +    },
25180 +    {
25181 +      AVR32_OPC_SUB3, 2, 0x20000000, 0xf0000000,
25182 +      &avr32_syntax_table[AVR32_SYNTAX_SUB3],
25183 +      BFD_RELOC_AVR32_8S, 2, 1,
25184 +      {
25185 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25186 +       &avr32_ifield_table[AVR32_IFIELD_K8C],
25187 +      },
25188 +    },
25189 +    {
25190 +      AVR32_OPC_SUB4, 4, 0xe0200000, 0xe1e00000,
25191 +      &avr32_syntax_table[AVR32_SYNTAX_SUB4],
25192 +      BFD_RELOC_AVR32_21S, 2, 1,
25193 +      {
25194 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25195 +       &avr32_ifield_table[AVR32_IFIELD_K21],
25196 +      },
25197 +    },
25198 +    {
25199 +      AVR32_OPC_SUBEQ, 4, 0xf7b00000, 0xfff0ff00,
25200 +      &avr32_syntax_table[AVR32_SYNTAX_SUBEQ],
25201 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25202 +      {
25203 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25204 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25205 +      },
25206 +    },
25207 +    {
25208 +      AVR32_OPC_SUBNE, 4, 0xf7b00100, 0xfff0ff00,
25209 +      &avr32_syntax_table[AVR32_SYNTAX_SUBNE],
25210 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25211 +      {
25212 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25213 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25214 +      },
25215 +    },
25216 +    {
25217 +      AVR32_OPC_SUBCC, 4, 0xf7b00200, 0xfff0ff00,
25218 +      &avr32_syntax_table[AVR32_SYNTAX_SUBHS],
25219 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25220 +      {
25221 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25222 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25223 +      },
25224 +    },
25225 +    {
25226 +      AVR32_OPC_SUBCS, 4, 0xf7b00300, 0xfff0ff00,
25227 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLO],
25228 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25229 +      {
25230 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25231 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25232 +      },
25233 +    },
25234 +    {
25235 +      AVR32_OPC_SUBGE, 4, 0xf7b00400, 0xfff0ff00,
25236 +      &avr32_syntax_table[AVR32_SYNTAX_SUBGE],
25237 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25238 +      {
25239 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25240 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25241 +      },
25242 +    },
25243 +    {
25244 +      AVR32_OPC_SUBLT, 4, 0xf7b00500, 0xfff0ff00,
25245 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLT],
25246 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25247 +      {
25248 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25249 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25250 +      },
25251 +    },
25252 +    {
25253 +      AVR32_OPC_SUBMI, 4, 0xf7b00600, 0xfff0ff00,
25254 +      &avr32_syntax_table[AVR32_SYNTAX_SUBMI],
25255 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25256 +      {
25257 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25258 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25259 +      },
25260 +    },
25261 +    {
25262 +      AVR32_OPC_SUBPL, 4, 0xf7b00700, 0xfff0ff00,
25263 +      &avr32_syntax_table[AVR32_SYNTAX_SUBPL],
25264 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25265 +      {
25266 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25267 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25268 +      },
25269 +    },
25270 +    {
25271 +      AVR32_OPC_SUBLS, 4, 0xf7b00800, 0xfff0ff00,
25272 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLS],
25273 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25274 +      {
25275 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25276 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25277 +      },
25278 +    },
25279 +    {
25280 +      AVR32_OPC_SUBGT, 4, 0xf7b00900, 0xfff0ff00,
25281 +      &avr32_syntax_table[AVR32_SYNTAX_SUBGT],
25282 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25283 +      {
25284 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25285 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25286 +      },
25287 +    },
25288 +    {
25289 +      AVR32_OPC_SUBLE, 4, 0xf7b00a00, 0xfff0ff00,
25290 +      &avr32_syntax_table[AVR32_SYNTAX_SUBLE],
25291 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25292 +      {
25293 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25294 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25295 +      },
25296 +    },
25297 +    {
25298 +      AVR32_OPC_SUBHI, 4, 0xf7b00b00, 0xfff0ff00,
25299 +      &avr32_syntax_table[AVR32_SYNTAX_SUBHI],
25300 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25301 +      {
25302 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25303 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25304 +      },
25305 +    },
25306 +    {
25307 +      AVR32_OPC_SUBVS, 4, 0xf7b00c00, 0xfff0ff00,
25308 +      &avr32_syntax_table[AVR32_SYNTAX_SUBVS],
25309 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25310 +      {
25311 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25312 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25313 +      },
25314 +    },
25315 +    {
25316 +      AVR32_OPC_SUBVC, 4, 0xf7b00d00, 0xfff0ff00,
25317 +      &avr32_syntax_table[AVR32_SYNTAX_SUBVC],
25318 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25319 +      {
25320 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25321 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25322 +      },
25323 +    },
25324 +    {
25325 +      AVR32_OPC_SUBQS, 4, 0xf7b00e00, 0xfff0ff00,
25326 +      &avr32_syntax_table[AVR32_SYNTAX_SUBQS],
25327 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25328 +      {
25329 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25330 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25331 +      },
25332 +    },
25333 +    {
25334 +      AVR32_OPC_SUBAL, 4, 0xf7b00f00, 0xfff0ff00,
25335 +      &avr32_syntax_table[AVR32_SYNTAX_SUBAL],
25336 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25337 +      {
25338 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25339 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25340 +      },
25341 +    },
25342 +    {
25343 +      AVR32_OPC_SUBFEQ, 4, 0xf5b00000, 0xfff0ff00,
25344 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFEQ],
25345 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25346 +      {
25347 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25348 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25349 +      },
25350 +    },
25351 +    {
25352 +      AVR32_OPC_SUBFNE, 4, 0xf5b00100, 0xfff0ff00,
25353 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFNE],
25354 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25355 +      {
25356 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25357 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25358 +      },
25359 +    },
25360 +    {
25361 +      AVR32_OPC_SUBFCC, 4, 0xf5b00200, 0xfff0ff00,
25362 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFHS],
25363 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25364 +      {
25365 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25366 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25367 +      },
25368 +    },
25369 +    {
25370 +      AVR32_OPC_SUBFCS, 4, 0xf5b00300, 0xfff0ff00,
25371 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLO],
25372 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25373 +      {
25374 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25375 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25376 +      },
25377 +    },
25378 +    {
25379 +      AVR32_OPC_SUBFGE, 4, 0xf5b00400, 0xfff0ff00,
25380 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFGE],
25381 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25382 +      {
25383 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25384 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25385 +      },
25386 +    },
25387 +    {
25388 +      AVR32_OPC_SUBFLT, 4, 0xf5b00500, 0xfff0ff00,
25389 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLT],
25390 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25391 +      {
25392 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25393 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25394 +      },
25395 +    },
25396 +    {
25397 +      AVR32_OPC_SUBFMI, 4, 0xf5b00600, 0xfff0ff00,
25398 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFMI],
25399 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25400 +      {
25401 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25402 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25403 +      },
25404 +    },
25405 +    {
25406 +      AVR32_OPC_SUBFPL, 4, 0xf5b00700, 0xfff0ff00,
25407 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFPL],
25408 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25409 +      {
25410 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25411 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25412 +      },
25413 +    },
25414 +    {
25415 +      AVR32_OPC_SUBFLS, 4, 0xf5b00800, 0xfff0ff00,
25416 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLS],
25417 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25418 +      {
25419 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25420 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25421 +      },
25422 +    },
25423 +    {
25424 +      AVR32_OPC_SUBFGT, 4, 0xf5b00900, 0xfff0ff00,
25425 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFGT],
25426 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25427 +      {
25428 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25429 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25430 +      },
25431 +    },
25432 +    {
25433 +      AVR32_OPC_SUBFLE, 4, 0xf5b00a00, 0xfff0ff00,
25434 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFLE],
25435 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25436 +      {
25437 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25438 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25439 +      },
25440 +    },
25441 +    {
25442 +      AVR32_OPC_SUBFHI, 4, 0xf5b00b00, 0xfff0ff00,
25443 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFHI],
25444 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25445 +      {
25446 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25447 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25448 +      },
25449 +    },
25450 +    {
25451 +      AVR32_OPC_SUBFVS, 4, 0xf5b00c00, 0xfff0ff00,
25452 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFVS],
25453 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25454 +      {
25455 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25456 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25457 +      },
25458 +    },
25459 +    {
25460 +      AVR32_OPC_SUBFVC, 4, 0xf5b00d00, 0xfff0ff00,
25461 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFVC],
25462 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25463 +      {
25464 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25465 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25466 +      },
25467 +    },
25468 +    {
25469 +      AVR32_OPC_SUBFQS, 4, 0xf5b00e00, 0xfff0ff00,
25470 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFQS],
25471 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25472 +      {
25473 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25474 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25475 +      },
25476 +    },
25477 +    {
25478 +      AVR32_OPC_SUBFAL, 4, 0xf5b00f00, 0xfff0ff00,
25479 +      &avr32_syntax_table[AVR32_SYNTAX_SUBFAL],
25480 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,
25481 +      {
25482 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25483 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25484 +      },
25485 +    },
25486 +    {
25487 +      AVR32_OPC_SUBHH_W, 4, 0xe0000f00, 0xe1f0ffc0,
25488 +      &avr32_syntax_table[AVR32_SYNTAX_SUBHH_W],
25489 +      BFD_RELOC_UNUSED, 5, -1,
25490 +      {
25491 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
25492 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25493 +       &avr32_ifield_table[AVR32_IFIELD_X],
25494 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25495 +       &avr32_ifield_table[AVR32_IFIELD_Y],
25496 +      },
25497 +    },
25498 +    {
25499 +      AVR32_OPC_SWAP_B, 2, 0x5cb00000, 0xfff00000,
25500 +      &avr32_syntax_table[AVR32_SYNTAX_SWAP_B],
25501 +      BFD_RELOC_UNUSED, 1, -1,
25502 +      {
25503 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25504 +      }
25505 +    },
25506 +    {
25507 +      AVR32_OPC_SWAP_BH, 2, 0x5cc00000, 0xfff00000,
25508 +      &avr32_syntax_table[AVR32_SYNTAX_SWAP_BH],
25509 +      BFD_RELOC_UNUSED, 1, -1,
25510 +      {
25511 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25512 +      }
25513 +    },
25514 +    {
25515 +      AVR32_OPC_SWAP_H, 2, 0x5ca00000, 0xfff00000,
25516 +      &avr32_syntax_table[AVR32_SYNTAX_SWAP_H],
25517 +      BFD_RELOC_UNUSED, 1, -1,
25518 +      {
25519 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25520 +      }
25521 +    },
25522 +    {
25523 +      AVR32_OPC_SYNC, 4, 0xebb00000, 0xffffff00,
25524 +      &avr32_syntax_table[AVR32_SYNTAX_SYNC],
25525 +      BFD_RELOC_AVR32_8S_EXT, 1, 0,
25526 +      {
25527 +       &avr32_ifield_table[AVR32_IFIELD_K8E],
25528 +      }
25529 +    },
25530 +    {
25531 +      AVR32_OPC_TLBR, 2, 0xd6430000, 0xffff0000,
25532 +      &avr32_syntax_table[AVR32_SYNTAX_TLBR],
25533 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25534 +    },
25535 +    {
25536 +      AVR32_OPC_TLBS, 2, 0xd6530000, 0xffff0000,
25537 +      &avr32_syntax_table[AVR32_SYNTAX_TLBS],
25538 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25539 +    },
25540 +    {
25541 +      AVR32_OPC_TLBW, 2, 0xd6630000, 0xffff0000,
25542 +      &avr32_syntax_table[AVR32_SYNTAX_TLBW],
25543 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25544 +    },
25545 +    {
25546 +      AVR32_OPC_TNBZ, 2, 0x5ce00000, 0xfff00000,
25547 +      &avr32_syntax_table[AVR32_SYNTAX_TNBZ],
25548 +      BFD_RELOC_UNUSED, 1, -1,
25549 +      {
25550 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25551 +      }
25552 +    },
25553 +    {
25554 +      AVR32_OPC_TST, 2, 0x00700000, 0xe1f00000,
25555 +      &avr32_syntax_table[AVR32_SYNTAX_TST],
25556 +      BFD_RELOC_UNUSED, 2, -1,
25557 +      {
25558 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25559 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25560 +      },
25561 +    },
25562 +    {
25563 +      AVR32_OPC_XCHG, 4, 0xe0000b40, 0xe1f0fff0,
25564 +      &avr32_syntax_table[AVR32_SYNTAX_XCHG],
25565 +      BFD_RELOC_UNUSED, 3, -1,
25566 +      {
25567 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],
25568 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25569 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25570 +      },
25571 +    },
25572 +    {
25573 +      AVR32_OPC_MEMC, 4, 0xf6100000, 0xfff00000,
25574 +      &avr32_syntax_table[AVR32_SYNTAX_MEMC],
25575 +      BFD_RELOC_AVR32_15S, 2, 0,
25576 +      {
25577 +       &avr32_ifield_table[AVR32_IFIELD_MEM15],
25578 +       &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25579 +      },
25580 +    },
25581 +    {
25582 +      AVR32_OPC_MEMS, 4, 0xf8100000, 0xfff00000,
25583 +      &avr32_syntax_table[AVR32_SYNTAX_MEMS],
25584 +      BFD_RELOC_AVR32_15S, 2, 0,
25585 +      {
25586 +       &avr32_ifield_table[AVR32_IFIELD_MEM15],
25587 +       &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25588 +      },
25589 +    },
25590 +    {
25591 +      AVR32_OPC_MEMT, 4, 0xfa100000, 0xfff00000,
25592 +      &avr32_syntax_table[AVR32_SYNTAX_MEMT],
25593 +      BFD_RELOC_AVR32_15S, 2, 0,
25594 +      {
25595 +       &avr32_ifield_table[AVR32_IFIELD_MEM15],
25596 +       &avr32_ifield_table[AVR32_IFIELD_MEMB5],
25597 +      },
25598 +    },
25599 +    {
25600 +      AVR32_OPC_BFEXTS, 4, 0xe1d0b000, 0xe1f0fc00,
25601 +      &avr32_syntax_table[AVR32_SYNTAX_BFEXTS],
25602 +      BFD_RELOC_UNUSED, 4, -1,
25603 +      {
25604 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25605 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25606 +       &avr32_ifield_table[AVR32_IFIELD_S5],
25607 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
25608 +      },
25609 +    },
25610 +    {
25611 +      AVR32_OPC_BFEXTU, 4, 0xe1d0c000, 0xe1f0fc00,
25612 +      &avr32_syntax_table[AVR32_SYNTAX_BFEXTU],
25613 +      BFD_RELOC_UNUSED, 4, -1,
25614 +      {
25615 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25616 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25617 +       &avr32_ifield_table[AVR32_IFIELD_S5],
25618 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
25619 +      },
25620 +    },
25621 +    {
25622 +      AVR32_OPC_BFINS, 4, 0xe1d0d000, 0xe1f0fc00,
25623 +      &avr32_syntax_table[AVR32_SYNTAX_BFINS],
25624 +      BFD_RELOC_UNUSED, 4, -1,
25625 +      {
25626 +       &avr32_ifield_table[AVR32_IFIELD_RX],
25627 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25628 +       &avr32_ifield_table[AVR32_IFIELD_S5],
25629 +       &avr32_ifield_table[AVR32_IFIELD_K5E],
25630 +      },
25631 +    },
25632 +#define AVR32_OPCODE_RSUBCOND(cond_name, cond_field)                    \
25633 +    {                                                                   \
25634 +      AVR32_OPC_RSUB ## cond_name , 4,                                  \
25635 +      0xfbb00000 | (cond_field << 8), 0xfff0ff00,                       \
25636 +      &avr32_syntax_table[AVR32_SYNTAX_RSUB ## cond_name ],             \
25637 +      BFD_RELOC_AVR32_8S_EXT, 2, 1,                                     \
25638 +      {                                                                 \
25639 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25640 +       &avr32_ifield_table[AVR32_IFIELD_K8E],                          \
25641 +      },                                                                \
25642 +    },
25643 +
25644 +    AVR32_OPCODE_RSUBCOND (EQ, 0)
25645 +    AVR32_OPCODE_RSUBCOND (NE, 1)
25646 +    AVR32_OPCODE_RSUBCOND (CC, 2)
25647 +    AVR32_OPCODE_RSUBCOND (CS, 3)
25648 +    AVR32_OPCODE_RSUBCOND (GE, 4)
25649 +    AVR32_OPCODE_RSUBCOND (LT, 5)
25650 +    AVR32_OPCODE_RSUBCOND (MI, 6)
25651 +    AVR32_OPCODE_RSUBCOND (PL, 7)
25652 +    AVR32_OPCODE_RSUBCOND (LS, 8)
25653 +    AVR32_OPCODE_RSUBCOND (GT, 9)
25654 +    AVR32_OPCODE_RSUBCOND (LE, 10)
25655 +    AVR32_OPCODE_RSUBCOND (HI, 11)
25656 +    AVR32_OPCODE_RSUBCOND (VS, 12)
25657 +    AVR32_OPCODE_RSUBCOND (VC, 13)
25658 +    AVR32_OPCODE_RSUBCOND (QS, 14)
25659 +    AVR32_OPCODE_RSUBCOND (AL, 15)
25660 +
25661 +#define AVR32_OPCODE_OP3_COND(op_name, op_field, cond_name, cond_field) \
25662 +    {                                                                   \
25663 +      AVR32_OPC_ ## op_name ## cond_name , 4,                           \
25664 +      0xe1d0e000 | (cond_field << 8) | (op_field << 4), 0xe1f0fff0,     \
25665 +      &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ],      \
25666 +      BFD_RELOC_UNUSED, 3, -1,                                          \
25667 +      {                                                                 \
25668 +       &avr32_ifield_table[AVR32_IFIELD_RD_E],                         \
25669 +       &avr32_ifield_table[AVR32_IFIELD_RX],                           \
25670 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25671 +      },                                                                \
25672 +    },
25673 +
25674 +    AVR32_OPCODE_OP3_COND (ADD, 0, EQ, 0)
25675 +    AVR32_OPCODE_OP3_COND (ADD, 0, NE, 1)
25676 +    AVR32_OPCODE_OP3_COND (ADD, 0, CC, 2)
25677 +    AVR32_OPCODE_OP3_COND (ADD, 0, CS, 3)
25678 +    AVR32_OPCODE_OP3_COND (ADD, 0, GE, 4)
25679 +    AVR32_OPCODE_OP3_COND (ADD, 0, LT, 5)
25680 +    AVR32_OPCODE_OP3_COND (ADD, 0, MI, 6)
25681 +    AVR32_OPCODE_OP3_COND (ADD, 0, PL, 7)
25682 +    AVR32_OPCODE_OP3_COND (ADD, 0, LS, 8)
25683 +    AVR32_OPCODE_OP3_COND (ADD, 0, GT, 9)
25684 +    AVR32_OPCODE_OP3_COND (ADD, 0, LE, 10)
25685 +    AVR32_OPCODE_OP3_COND (ADD, 0, HI, 11)
25686 +    AVR32_OPCODE_OP3_COND (ADD, 0, VS, 12)
25687 +    AVR32_OPCODE_OP3_COND (ADD, 0, VC, 13)
25688 +    AVR32_OPCODE_OP3_COND (ADD, 0, QS, 14)
25689 +    AVR32_OPCODE_OP3_COND (ADD, 0, AL, 15)
25690 +
25691 +    AVR32_OPCODE_OP3_COND (SUB2, 1, EQ, 0)
25692 +    AVR32_OPCODE_OP3_COND (SUB2, 1, NE, 1)
25693 +    AVR32_OPCODE_OP3_COND (SUB2, 1, CC, 2)
25694 +    AVR32_OPCODE_OP3_COND (SUB2, 1, CS, 3)
25695 +    AVR32_OPCODE_OP3_COND (SUB2, 1, GE, 4)
25696 +    AVR32_OPCODE_OP3_COND (SUB2, 1, LT, 5)
25697 +    AVR32_OPCODE_OP3_COND (SUB2, 1, MI, 6)
25698 +    AVR32_OPCODE_OP3_COND (SUB2, 1, PL, 7)
25699 +    AVR32_OPCODE_OP3_COND (SUB2, 1, LS, 8)
25700 +    AVR32_OPCODE_OP3_COND (SUB2, 1, GT, 9)
25701 +    AVR32_OPCODE_OP3_COND (SUB2, 1, LE, 10)
25702 +    AVR32_OPCODE_OP3_COND (SUB2, 1, HI, 11)
25703 +    AVR32_OPCODE_OP3_COND (SUB2, 1, VS, 12)
25704 +    AVR32_OPCODE_OP3_COND (SUB2, 1, VC, 13)
25705 +    AVR32_OPCODE_OP3_COND (SUB2, 1, QS, 14)
25706 +    AVR32_OPCODE_OP3_COND (SUB2, 1, AL, 15)
25707 +
25708 +    AVR32_OPCODE_OP3_COND (AND, 2, EQ, 0)
25709 +    AVR32_OPCODE_OP3_COND (AND, 2, NE, 1)
25710 +    AVR32_OPCODE_OP3_COND (AND, 2, CC, 2)
25711 +    AVR32_OPCODE_OP3_COND (AND, 2, CS, 3)
25712 +    AVR32_OPCODE_OP3_COND (AND, 2, GE, 4)
25713 +    AVR32_OPCODE_OP3_COND (AND, 2, LT, 5)
25714 +    AVR32_OPCODE_OP3_COND (AND, 2, MI, 6)
25715 +    AVR32_OPCODE_OP3_COND (AND, 2, PL, 7)
25716 +    AVR32_OPCODE_OP3_COND (AND, 2, LS, 8)
25717 +    AVR32_OPCODE_OP3_COND (AND, 2, GT, 9)
25718 +    AVR32_OPCODE_OP3_COND (AND, 2, LE, 10)
25719 +    AVR32_OPCODE_OP3_COND (AND, 2, HI, 11)
25720 +    AVR32_OPCODE_OP3_COND (AND, 2, VS, 12)
25721 +    AVR32_OPCODE_OP3_COND (AND, 2, VC, 13)
25722 +    AVR32_OPCODE_OP3_COND (AND, 2, QS, 14)
25723 +    AVR32_OPCODE_OP3_COND (AND, 2, AL, 15)
25724 +
25725 +    AVR32_OPCODE_OP3_COND (OR, 3, EQ, 0)
25726 +    AVR32_OPCODE_OP3_COND (OR, 3, NE, 1)
25727 +    AVR32_OPCODE_OP3_COND (OR, 3, CC, 2)
25728 +    AVR32_OPCODE_OP3_COND (OR, 3, CS, 3)
25729 +    AVR32_OPCODE_OP3_COND (OR, 3, GE, 4)
25730 +    AVR32_OPCODE_OP3_COND (OR, 3, LT, 5)
25731 +    AVR32_OPCODE_OP3_COND (OR, 3, MI, 6)
25732 +    AVR32_OPCODE_OP3_COND (OR, 3, PL, 7)
25733 +    AVR32_OPCODE_OP3_COND (OR, 3, LS, 8)
25734 +    AVR32_OPCODE_OP3_COND (OR, 3, GT, 9)
25735 +    AVR32_OPCODE_OP3_COND (OR, 3, LE, 10)
25736 +    AVR32_OPCODE_OP3_COND (OR, 3, HI, 11)
25737 +    AVR32_OPCODE_OP3_COND (OR, 3, VS, 12)
25738 +    AVR32_OPCODE_OP3_COND (OR, 3, VC, 13)
25739 +    AVR32_OPCODE_OP3_COND (OR, 3, QS, 14)
25740 +    AVR32_OPCODE_OP3_COND (OR, 3, AL, 15)
25741 +
25742 +    AVR32_OPCODE_OP3_COND (EOR, 4, EQ, 0)
25743 +    AVR32_OPCODE_OP3_COND (EOR, 4, NE, 1)
25744 +    AVR32_OPCODE_OP3_COND (EOR, 4, CC, 2)
25745 +    AVR32_OPCODE_OP3_COND (EOR, 4, CS, 3)
25746 +    AVR32_OPCODE_OP3_COND (EOR, 4, GE, 4)
25747 +    AVR32_OPCODE_OP3_COND (EOR, 4, LT, 5)
25748 +    AVR32_OPCODE_OP3_COND (EOR, 4, MI, 6)
25749 +    AVR32_OPCODE_OP3_COND (EOR, 4, PL, 7)
25750 +    AVR32_OPCODE_OP3_COND (EOR, 4, LS, 8)
25751 +    AVR32_OPCODE_OP3_COND (EOR, 4, GT, 9)
25752 +    AVR32_OPCODE_OP3_COND (EOR, 4, LE, 10)
25753 +    AVR32_OPCODE_OP3_COND (EOR, 4, HI, 11)
25754 +    AVR32_OPCODE_OP3_COND (EOR, 4, VS, 12)
25755 +    AVR32_OPCODE_OP3_COND (EOR, 4, VC, 13)
25756 +    AVR32_OPCODE_OP3_COND (EOR, 4, QS, 14)
25757 +    AVR32_OPCODE_OP3_COND (EOR, 4, AL, 15)
25758 +
25759 +#define AVR32_OPCODE_LD_COND(op_name, op_field, cond_name, cond_field)  \
25760 +    {                                                                   \
25761 +      AVR32_OPC_ ## op_name ## cond_name , 4,                           \
25762 +      0xe1f00000 | (cond_field << 12) | (op_field  << 9), 0xe1f0fe00,   \
25763 +      &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ],      \
25764 +      BFD_RELOC_UNUSED, 3, -1,                                          \
25765 +      {                                                                 \
25766 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25767 +       &avr32_ifield_table[AVR32_IFIELD_RX],                           \
25768 +       &avr32_ifield_table[AVR32_IFIELD_K9E],                          \
25769 +      },                                                                \
25770 +    },
25771 +
25772 +#define AVR32_OPCODE_ST_COND(op_name, op_field, cond_name, cond_field)  \
25773 +    {                                                                   \
25774 +      AVR32_OPC_ ## op_name ## cond_name , 4,                           \
25775 +      0xe1f00000 | (cond_field << 12) | (op_field  << 9), 0xe1f0fe00,   \
25776 +      &avr32_syntax_table[AVR32_SYNTAX_ ## op_name ## cond_name ],      \
25777 +      BFD_RELOC_UNUSED, 3, -1,                                          \
25778 +      {                                                                 \
25779 +       &avr32_ifield_table[AVR32_IFIELD_RX],                           \
25780 +       &avr32_ifield_table[AVR32_IFIELD_K9E],                          \
25781 +       &avr32_ifield_table[AVR32_IFIELD_RY],                           \
25782 +      },                                                                \
25783 +    },
25784 +
25785 +    AVR32_OPCODE_LD_COND (LD_W, 0, EQ, 0)
25786 +    AVR32_OPCODE_LD_COND (LD_W, 0, NE, 1)
25787 +    AVR32_OPCODE_LD_COND (LD_W, 0, CC, 2)
25788 +    AVR32_OPCODE_LD_COND (LD_W, 0, CS, 3)
25789 +    AVR32_OPCODE_LD_COND (LD_W, 0, GE, 4)
25790 +    AVR32_OPCODE_LD_COND (LD_W, 0, LT, 5)
25791 +    AVR32_OPCODE_LD_COND (LD_W, 0, MI, 6)
25792 +    AVR32_OPCODE_LD_COND (LD_W, 0, PL, 7)
25793 +    AVR32_OPCODE_LD_COND (LD_W, 0, LS, 8)
25794 +    AVR32_OPCODE_LD_COND (LD_W, 0, GT, 9)
25795 +    AVR32_OPCODE_LD_COND (LD_W, 0, LE, 10)
25796 +    AVR32_OPCODE_LD_COND (LD_W, 0, HI, 11)
25797 +    AVR32_OPCODE_LD_COND (LD_W, 0, VS, 12)
25798 +    AVR32_OPCODE_LD_COND (LD_W, 0, VC, 13)
25799 +    AVR32_OPCODE_LD_COND (LD_W, 0, QS, 14)
25800 +    AVR32_OPCODE_LD_COND (LD_W, 0, AL, 15)
25801 +
25802 +    AVR32_OPCODE_LD_COND (LD_SH, 1, EQ, 0)
25803 +    AVR32_OPCODE_LD_COND (LD_SH, 1, NE, 1)
25804 +    AVR32_OPCODE_LD_COND (LD_SH, 1, CC, 2)
25805 +    AVR32_OPCODE_LD_COND (LD_SH, 1, CS, 3)
25806 +    AVR32_OPCODE_LD_COND (LD_SH, 1, GE, 4)
25807 +    AVR32_OPCODE_LD_COND (LD_SH, 1, LT, 5)
25808 +    AVR32_OPCODE_LD_COND (LD_SH, 1, MI, 6)
25809 +    AVR32_OPCODE_LD_COND (LD_SH, 1, PL, 7)
25810 +    AVR32_OPCODE_LD_COND (LD_SH, 1, LS, 8)
25811 +    AVR32_OPCODE_LD_COND (LD_SH, 1, GT, 9)
25812 +    AVR32_OPCODE_LD_COND (LD_SH, 1, LE, 10)
25813 +    AVR32_OPCODE_LD_COND (LD_SH, 1, HI, 11)
25814 +    AVR32_OPCODE_LD_COND (LD_SH, 1, VS, 12)
25815 +    AVR32_OPCODE_LD_COND (LD_SH, 1, VC, 13)
25816 +    AVR32_OPCODE_LD_COND (LD_SH, 1, QS, 14)
25817 +    AVR32_OPCODE_LD_COND (LD_SH, 1, AL, 15)
25818 +
25819 +    AVR32_OPCODE_LD_COND (LD_UH, 2, EQ, 0)
25820 +    AVR32_OPCODE_LD_COND (LD_UH, 2, NE, 1)
25821 +    AVR32_OPCODE_LD_COND (LD_UH, 2, CC, 2)
25822 +    AVR32_OPCODE_LD_COND (LD_UH, 2, CS, 3)
25823 +    AVR32_OPCODE_LD_COND (LD_UH, 2, GE, 4)
25824 +    AVR32_OPCODE_LD_COND (LD_UH, 2, LT, 5)
25825 +    AVR32_OPCODE_LD_COND (LD_UH, 2, MI, 6)
25826 +    AVR32_OPCODE_LD_COND (LD_UH, 2, PL, 7)
25827 +    AVR32_OPCODE_LD_COND (LD_SH, 2, LS, 8)
25828 +    AVR32_OPCODE_LD_COND (LD_SH, 2, GT, 9)
25829 +    AVR32_OPCODE_LD_COND (LD_SH, 2, LE, 10)
25830 +    AVR32_OPCODE_LD_COND (LD_SH, 2, HI, 11)
25831 +    AVR32_OPCODE_LD_COND (LD_SH, 2, VS, 12)
25832 +    AVR32_OPCODE_LD_COND (LD_SH, 2, VC, 13)
25833 +    AVR32_OPCODE_LD_COND (LD_SH, 2, QS, 14)
25834 +    AVR32_OPCODE_LD_COND (LD_SH, 2, AL, 15)
25835 +
25836 +    AVR32_OPCODE_LD_COND (LD_SB, 3, EQ, 0)
25837 +    AVR32_OPCODE_LD_COND (LD_SB, 3, NE, 1)
25838 +    AVR32_OPCODE_LD_COND (LD_SB, 3, CC, 2)
25839 +    AVR32_OPCODE_LD_COND (LD_SB, 3, CS, 3)
25840 +    AVR32_OPCODE_LD_COND (LD_SB, 3, GE, 4)
25841 +    AVR32_OPCODE_LD_COND (LD_SB, 3, LT, 5)
25842 +    AVR32_OPCODE_LD_COND (LD_SB, 3, MI, 6)
25843 +    AVR32_OPCODE_LD_COND (LD_SB, 3, PL, 7)
25844 +    AVR32_OPCODE_LD_COND (LD_SB, 3, LS, 8)
25845 +    AVR32_OPCODE_LD_COND (LD_SB, 3, GT, 9)
25846 +    AVR32_OPCODE_LD_COND (LD_SB, 3, LE, 10)
25847 +    AVR32_OPCODE_LD_COND (LD_SB, 3, HI, 11)
25848 +    AVR32_OPCODE_LD_COND (LD_SB, 3, VS, 12)
25849 +    AVR32_OPCODE_LD_COND (LD_SB, 3, VC, 13)
25850 +    AVR32_OPCODE_LD_COND (LD_SB, 3, QS, 14)
25851 +    AVR32_OPCODE_LD_COND (LD_SB, 3, AL, 15)
25852 +
25853 +    AVR32_OPCODE_LD_COND (LD_UB, 4, EQ, 0)
25854 +    AVR32_OPCODE_LD_COND (LD_UB, 4, NE, 1)
25855 +    AVR32_OPCODE_LD_COND (LD_UB, 4, CC, 2)
25856 +    AVR32_OPCODE_LD_COND (LD_UB, 4, CS, 3)
25857 +    AVR32_OPCODE_LD_COND (LD_UB, 4, GE, 4)
25858 +    AVR32_OPCODE_LD_COND (LD_UB, 4, LT, 5)
25859 +    AVR32_OPCODE_LD_COND (LD_UB, 4, MI, 6)
25860 +    AVR32_OPCODE_LD_COND (LD_UB, 4, PL, 7)
25861 +    AVR32_OPCODE_LD_COND (LD_UB, 4, LS, 8)
25862 +    AVR32_OPCODE_LD_COND (LD_UB, 4, GT, 9)
25863 +    AVR32_OPCODE_LD_COND (LD_UB, 4, LE, 10)
25864 +    AVR32_OPCODE_LD_COND (LD_UB, 4, HI, 11)
25865 +    AVR32_OPCODE_LD_COND (LD_UB, 4, VS, 12)
25866 +    AVR32_OPCODE_LD_COND (LD_UB, 4, VC, 13)
25867 +    AVR32_OPCODE_LD_COND (LD_UB, 4, QS, 14)
25868 +    AVR32_OPCODE_LD_COND (LD_UB, 4, AL, 15)
25869 +
25870 +    AVR32_OPCODE_ST_COND (ST_W, 5, EQ, 0)
25871 +    AVR32_OPCODE_ST_COND (ST_W, 5, NE, 1)
25872 +    AVR32_OPCODE_ST_COND (ST_W, 5, CC, 2)
25873 +    AVR32_OPCODE_ST_COND (ST_W, 5, CS, 3)
25874 +    AVR32_OPCODE_ST_COND (ST_W, 5, GE, 4)
25875 +    AVR32_OPCODE_ST_COND (ST_W, 5, LT, 5)
25876 +    AVR32_OPCODE_ST_COND (ST_W, 5, MI, 6)
25877 +    AVR32_OPCODE_ST_COND (ST_W, 5, PL, 7)
25878 +    AVR32_OPCODE_ST_COND (ST_W, 5, LS, 8)
25879 +    AVR32_OPCODE_ST_COND (ST_W, 5, GT, 9)
25880 +    AVR32_OPCODE_ST_COND (ST_W, 5, LE, 10)
25881 +    AVR32_OPCODE_ST_COND (ST_W, 5, HI, 11)
25882 +    AVR32_OPCODE_ST_COND (ST_W, 5, VS, 12)
25883 +    AVR32_OPCODE_ST_COND (ST_W, 5, VC, 13)
25884 +    AVR32_OPCODE_ST_COND (ST_W, 5, QS, 14)
25885 +    AVR32_OPCODE_ST_COND (ST_W, 5, AL, 15)
25886 +
25887 +    AVR32_OPCODE_ST_COND (ST_H, 6, EQ, 0)
25888 +    AVR32_OPCODE_ST_COND (ST_H, 6, NE, 1)
25889 +    AVR32_OPCODE_ST_COND (ST_H, 6, CC, 2)
25890 +    AVR32_OPCODE_ST_COND (ST_H, 6, CS, 3)
25891 +    AVR32_OPCODE_ST_COND (ST_H, 6, GE, 4)
25892 +    AVR32_OPCODE_ST_COND (ST_H, 6, LT, 5)
25893 +    AVR32_OPCODE_ST_COND (ST_H, 6, MI, 6)
25894 +    AVR32_OPCODE_ST_COND (ST_H, 6, PL, 7)
25895 +    AVR32_OPCODE_ST_COND (ST_H, 6, LS, 8)
25896 +    AVR32_OPCODE_ST_COND (ST_H, 6, GT, 9)
25897 +    AVR32_OPCODE_ST_COND (ST_H, 6, LE, 10)
25898 +    AVR32_OPCODE_ST_COND (ST_H, 6, HI, 11)
25899 +    AVR32_OPCODE_ST_COND (ST_H, 6, VS, 12)
25900 +    AVR32_OPCODE_ST_COND (ST_H, 6, VC, 13)
25901 +    AVR32_OPCODE_ST_COND (ST_H, 6, QS, 14)
25902 +    AVR32_OPCODE_ST_COND (ST_H, 6, AL, 15)
25903 +
25904 +    AVR32_OPCODE_ST_COND (ST_B, 7, EQ, 0)
25905 +    AVR32_OPCODE_ST_COND (ST_B, 7, NE, 1)
25906 +    AVR32_OPCODE_ST_COND (ST_B, 7, CC, 2)
25907 +    AVR32_OPCODE_ST_COND (ST_B, 7, CS, 3)
25908 +    AVR32_OPCODE_ST_COND (ST_B, 7, GE, 4)
25909 +    AVR32_OPCODE_ST_COND (ST_B, 7, LT, 5)
25910 +    AVR32_OPCODE_ST_COND (ST_B, 7, MI, 6)
25911 +    AVR32_OPCODE_ST_COND (ST_B, 7, PL, 7)
25912 +    AVR32_OPCODE_ST_COND (ST_B, 7, LS, 8)
25913 +    AVR32_OPCODE_ST_COND (ST_B, 7, GT, 9)
25914 +    AVR32_OPCODE_ST_COND (ST_B, 7, LE, 10)
25915 +    AVR32_OPCODE_ST_COND (ST_B, 7, HI, 11)
25916 +    AVR32_OPCODE_ST_COND (ST_B, 7, VS, 12)
25917 +    AVR32_OPCODE_ST_COND (ST_B, 7, VC, 13)
25918 +    AVR32_OPCODE_ST_COND (ST_B, 7, QS, 14)
25919 +    AVR32_OPCODE_ST_COND (ST_B, 7, AL, 15)
25920 +
25921 +    {
25922 +      AVR32_OPC_MOVH, 4, 0xfc100000, 0xfff00000,
25923 +      &avr32_syntax_table[AVR32_SYNTAX_MOVH],
25924 +      BFD_RELOC_AVR32_16U,  2, 1,
25925 +      {
25926 +       &avr32_ifield_table[AVR32_IFIELD_RY],
25927 +       &avr32_ifield_table[AVR32_IFIELD_K16],
25928 +      },
25929 +    },
25930 +    {
25931 +      AVR32_OPC_SSCALL, 2, 0xd7530000, 0xffff0000,
25932 +      &avr32_syntax_table[AVR32_SYNTAX_SSCALL],
25933 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25934 +    },
25935 +    {
25936 +      AVR32_OPC_RETSS, 2, 0xd7630000, 0xffff0000,
25937 +      &avr32_syntax_table[AVR32_SYNTAX_RETSS],
25938 +      BFD_RELOC_UNUSED, 0, -1, { NULL },
25939 +    },
25940 +
25941 +  {
25942 +    AVR32_OPC_FMAC_S, 4, 0xE1A00000, 0xFFF0F000,
25943 +    &avr32_syntax_table[AVR32_SYNTAX_FMAC_S],
25944 +    BFD_RELOC_UNUSED, 4, -1,
25945 +    {
25946 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25947 +      &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25948 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25949 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25950 +    }
25951 +  },
25952 +  {
25953 +    AVR32_OPC_FNMAC_S, 4, 0xE1A01000, 0xFFF0F000,
25954 +    &avr32_syntax_table[AVR32_SYNTAX_FNMAC_S],
25955 +    BFD_RELOC_UNUSED, 4, -1,
25956 +    {
25957 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25958 +      &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25959 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25960 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25961 +    }
25962 +  },
25963 +  {
25964 +    AVR32_OPC_FMSC_S, 4, 0xE3A00000, 0xFFF0F000,
25965 +    &avr32_syntax_table[AVR32_SYNTAX_FMSC_S],
25966 +    BFD_RELOC_UNUSED, 4, -1,
25967 +    {
25968 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25969 +      &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25970 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25971 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25972 +    }
25973 +  },
25974 +  {
25975 +    AVR32_OPC_FNMSC_S, 4, 0xE3A01000, 0xFFF0F000,
25976 +    &avr32_syntax_table[AVR32_SYNTAX_FNMSC_S],
25977 +    BFD_RELOC_UNUSED, 4, -1,
25978 +    {
25979 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25980 +      &avr32_ifield_table[AVR32_IFIELD_FP_RA],
25981 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25982 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25983 +    }
25984 +  },
25985 +  {
25986 +    AVR32_OPC_FMUL_S, 4, 0xE5A20000, 0xFFFFF000,
25987 +    &avr32_syntax_table[AVR32_SYNTAX_FMUL_S],
25988 +    BFD_RELOC_UNUSED, 3, -1,
25989 +    {
25990 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
25991 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
25992 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
25993 +    }
25994 +  },
25995 +  {
25996 +    AVR32_OPC_FNMUL_S, 4, 0xE5A30000, 0xFFFFF000,
25997 +    &avr32_syntax_table[AVR32_SYNTAX_FNMUL_S],
25998 +    BFD_RELOC_UNUSED, 3, -1,
25999 +    {
26000 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26001 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
26002 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26003 +    }
26004 +  },
26005 +  {
26006 +    AVR32_OPC_FADD_S, 4, 0xE5A00000, 0xFFFFF000,
26007 +    &avr32_syntax_table[AVR32_SYNTAX_FADD_S],
26008 +    BFD_RELOC_UNUSED, 3, -1,
26009 +    {
26010 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26011 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
26012 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26013 +    }
26014 +  },
26015 +  {
26016 +    AVR32_OPC_FSUB_S, 4, 0xE5A10000, 0xFFFFF000,
26017 +    &avr32_syntax_table[AVR32_SYNTAX_FSUB_S],
26018 +    BFD_RELOC_UNUSED, 3, -1,
26019 +    {
26020 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26021 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
26022 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26023 +    }
26024 +  },
26025 +  {
26026 +    AVR32_OPC_FCASTRS_SW, 4, 0xE5AB0000, 0xFFFFF0F0,
26027 +    &avr32_syntax_table[AVR32_SYNTAX_FCASTRS_SW],
26028 +    BFD_RELOC_UNUSED, 2, -1,
26029 +    {
26030 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26031 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26032 +    }
26033 +  },
26034 +  {
26035 +    AVR32_OPC_FCASTRS_UW, 4, 0xE5A90000, 0xFFFFF0F0,
26036 +    &avr32_syntax_table[AVR32_SYNTAX_FCASTRS_UW],
26037 +    BFD_RELOC_UNUSED, 2, -1,
26038 +    {
26039 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26040 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26041 +    }
26042 +  },
26043 +  {
26044 +    AVR32_OPC_FCASTSW_S, 4, 0xE5A60000, 0xFFFFF0F0,
26045 +    &avr32_syntax_table[AVR32_SYNTAX_FCASTSW_S],
26046 +    BFD_RELOC_UNUSED, 2, -1,
26047 +    {
26048 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26049 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26050 +    }
26051 +  },
26052 +  {
26053 +    AVR32_OPC_FCASTUW_S, 4, 0xE5A40000, 0xFFFFF0F0,
26054 +    &avr32_syntax_table[AVR32_SYNTAX_FCASTUW_S],
26055 +    BFD_RELOC_UNUSED, 2, -1,
26056 +    {
26057 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26058 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26059 +    }
26060 +  },
26061 +  {
26062 +    AVR32_OPC_FCMP_S, 4, 0xE5AC0000, 0xFFFFFF00,
26063 +    &avr32_syntax_table[AVR32_SYNTAX_FCMP_S],
26064 +    BFD_RELOC_UNUSED, 2, -1,
26065 +    {
26066 +      &avr32_ifield_table[AVR32_IFIELD_FP_RX],
26067 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26068 +    }
26069 +  },
26070 +  {
26071 +    AVR32_OPC_FCHK_S, 4, 0xE5AD0000, 0xFFFFFFF0,
26072 +    &avr32_syntax_table[AVR32_SYNTAX_FCHK_S],
26073 +    BFD_RELOC_UNUSED, 1, -1,
26074 +    {
26075 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26076 +    }
26077 +  },
26078 +  {
26079 +    AVR32_OPC_FRCPA_S, 4, 0xE5AE0000, 0xFFFFF0F0,
26080 +    &avr32_syntax_table[AVR32_SYNTAX_FRCPA_S],
26081 +    BFD_RELOC_UNUSED, 2, -1,
26082 +    {
26083 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26084 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26085 +    }
26086 +  },
26087 +  {
26088 +    AVR32_OPC_FRSQRTA_S, 4, 0xE5AF0000, 0xFFFFF0F0,
26089 +    &avr32_syntax_table[AVR32_SYNTAX_FRSQRTA_S],
26090 +    BFD_RELOC_UNUSED, 2, -1,
26091 +    {
26092 +      &avr32_ifield_table[AVR32_IFIELD_FP_RD],
26093 +      &avr32_ifield_table[AVR32_IFIELD_FP_RY]
26094 +    }
26095 +  }
26096 +
26097 +};
26098 +
26099 +
26100 +const struct avr32_alias avr32_alias_table[] =
26101 +  {
26102 +    {
26103 +      AVR32_ALIAS_PICOSVMAC0,
26104 +      &avr32_opc_table[AVR32_OPC_COP],
26105 +      {
26106 +       { 0, PICO_CPNO },
26107 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26108 +       { 0, 0x0c },
26109 +      },
26110 +    },
26111 +    {
26112 +      AVR32_ALIAS_PICOSVMAC1,
26113 +      &avr32_opc_table[AVR32_OPC_COP],
26114 +      {
26115 +       { 0, PICO_CPNO },
26116 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26117 +       { 0, 0x0d },
26118 +      },
26119 +    },
26120 +    {
26121 +      AVR32_ALIAS_PICOSVMAC2,
26122 +      &avr32_opc_table[AVR32_OPC_COP],
26123 +      {
26124 +       { 0, PICO_CPNO },
26125 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26126 +       { 0, 0x0e },
26127 +      },
26128 +    },
26129 +    {
26130 +      AVR32_ALIAS_PICOSVMAC3,
26131 +      &avr32_opc_table[AVR32_OPC_COP],
26132 +      {
26133 +       { 0, PICO_CPNO },
26134 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26135 +       { 0, 0x0f },
26136 +      },
26137 +    },
26138 +    {
26139 +      AVR32_ALIAS_PICOSVMUL0,
26140 +      &avr32_opc_table[AVR32_OPC_COP],
26141 +      {
26142 +       { 0, PICO_CPNO },
26143 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26144 +       { 0, 0x08 },
26145 +      },
26146 +    },
26147 +    {
26148 +      AVR32_ALIAS_PICOSVMUL1,
26149 +      &avr32_opc_table[AVR32_OPC_COP],
26150 +      {
26151 +       { 0, PICO_CPNO },
26152 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26153 +       { 0, 0x09 },
26154 +      },
26155 +    },
26156 +    {
26157 +      AVR32_ALIAS_PICOSVMUL2,
26158 +      &avr32_opc_table[AVR32_OPC_COP],
26159 +      {
26160 +       { 0, PICO_CPNO },
26161 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26162 +       { 0, 0x0a },
26163 +      },
26164 +    },
26165 +    {
26166 +      AVR32_ALIAS_PICOSVMUL3,
26167 +      &avr32_opc_table[AVR32_OPC_COP],
26168 +      {
26169 +       { 0, PICO_CPNO },
26170 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26171 +       { 0, 0x0b },
26172 +      },
26173 +    },
26174 +    {
26175 +      AVR32_ALIAS_PICOVMAC0,
26176 +      &avr32_opc_table[AVR32_OPC_COP],
26177 +      {
26178 +       { 0, PICO_CPNO },
26179 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26180 +       { 0, 0x04 },
26181 +      },
26182 +    },
26183 +    {
26184 +      AVR32_ALIAS_PICOVMAC1,
26185 +      &avr32_opc_table[AVR32_OPC_COP],
26186 +      {
26187 +       { 0, PICO_CPNO },
26188 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26189 +       { 0, 0x05 },
26190 +      },
26191 +    },
26192 +    {
26193 +      AVR32_ALIAS_PICOVMAC2,
26194 +      &avr32_opc_table[AVR32_OPC_COP],
26195 +      {
26196 +       { 0, PICO_CPNO },
26197 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26198 +       { 0, 0x06 },
26199 +      },
26200 +    },
26201 +    {
26202 +      AVR32_ALIAS_PICOVMAC3,
26203 +      &avr32_opc_table[AVR32_OPC_COP],
26204 +      {
26205 +       { 0, PICO_CPNO },
26206 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26207 +       { 0, 0x07 },
26208 +      },
26209 +    },
26210 +    {
26211 +      AVR32_ALIAS_PICOVMUL0,
26212 +      &avr32_opc_table[AVR32_OPC_COP],
26213 +      {
26214 +       { 0, PICO_CPNO },
26215 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26216 +       { 0, 0x00 },
26217 +      },
26218 +    },
26219 +    {
26220 +      AVR32_ALIAS_PICOVMUL1,
26221 +      &avr32_opc_table[AVR32_OPC_COP],
26222 +      {
26223 +       { 0, PICO_CPNO },
26224 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26225 +       { 0, 0x01 },
26226 +      },
26227 +    },
26228 +    {
26229 +      AVR32_ALIAS_PICOVMUL2,
26230 +      &avr32_opc_table[AVR32_OPC_COP],
26231 +      {
26232 +       { 0, PICO_CPNO },
26233 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26234 +       { 0, 0x02 },
26235 +      },
26236 +    },
26237 +    {
26238 +      AVR32_ALIAS_PICOVMUL3,
26239 +      &avr32_opc_table[AVR32_OPC_COP],
26240 +      {
26241 +       { 0, PICO_CPNO },
26242 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26243 +       { 0, 0x03 },
26244 +      },
26245 +    },
26246 +    {
26247 +      AVR32_ALIAS_PICOLD_D1,
26248 +      &avr32_opc_table[AVR32_OPC_LDC_D1],
26249 +      {
26250 +       { 0, PICO_CPNO },
26251 +       { 1, 0 }, { 1, 1 },
26252 +      },
26253 +    },
26254 +    {
26255 +      AVR32_ALIAS_PICOLD_D2,
26256 +      &avr32_opc_table[AVR32_OPC_LDC_D2],
26257 +      {
26258 +       { 0, PICO_CPNO },
26259 +       { 1, 0 }, { 1, 1 },
26260 +      },
26261 +    },
26262 +    {
26263 +      AVR32_ALIAS_PICOLD_D3,
26264 +      &avr32_opc_table[AVR32_OPC_LDC_D3],
26265 +      {
26266 +       { 0, PICO_CPNO },
26267 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
26268 +      },
26269 +    },
26270 +    {
26271 +      AVR32_ALIAS_PICOLD_W1,
26272 +      &avr32_opc_table[AVR32_OPC_LDC_W1],
26273 +      {
26274 +       { 0, PICO_CPNO },
26275 +       { 1, 0 }, { 1, 1 },
26276 +      },
26277 +    },
26278 +    {
26279 +      AVR32_ALIAS_PICOLD_W2,
26280 +      &avr32_opc_table[AVR32_OPC_LDC_W2],
26281 +      {
26282 +       { 0, PICO_CPNO },
26283 +       { 1, 0 }, { 1, 1 },
26284 +      },
26285 +    },
26286 +    {
26287 +      AVR32_ALIAS_PICOLD_W3,
26288 +      &avr32_opc_table[AVR32_OPC_LDC_W3],
26289 +      {
26290 +       { 0, PICO_CPNO },
26291 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
26292 +      },
26293 +    },
26294 +    {
26295 +      AVR32_ALIAS_PICOLDM_D,
26296 +      &avr32_opc_table[AVR32_OPC_LDCM_D],
26297 +      {
26298 +       { 0, PICO_CPNO },
26299 +       { 1, 0 }, { 1, 1 },
26300 +      },
26301 +    },
26302 +    {
26303 +      AVR32_ALIAS_PICOLDM_D_PU,
26304 +      &avr32_opc_table[AVR32_OPC_LDCM_D_PU],
26305 +      {
26306 +       { 0, PICO_CPNO },
26307 +       { 1, 0 }, { 1, 1 },
26308 +      },
26309 +    },
26310 +    {
26311 +      AVR32_ALIAS_PICOLDM_W,
26312 +      &avr32_opc_table[AVR32_OPC_LDCM_W],
26313 +      {
26314 +       { 0, PICO_CPNO },
26315 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26316 +      },
26317 +    },
26318 +    {
26319 +      AVR32_ALIAS_PICOLDM_W_PU,
26320 +      &avr32_opc_table[AVR32_OPC_LDCM_W_PU],
26321 +      {
26322 +       { 0, PICO_CPNO },
26323 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26324 +      },
26325 +    },
26326 +    {
26327 +      AVR32_ALIAS_PICOMV_D1,
26328 +      &avr32_opc_table[AVR32_OPC_MVCR_D],
26329 +      {
26330 +       { 0, PICO_CPNO },
26331 +       { 1, 0 }, { 1, 1 },
26332 +      },
26333 +    },
26334 +    {
26335 +      AVR32_ALIAS_PICOMV_D2,
26336 +      &avr32_opc_table[AVR32_OPC_MVRC_D],
26337 +      {
26338 +       { 0, PICO_CPNO },
26339 +       { 1, 0 }, { 1, 1 },
26340 +      },
26341 +    },
26342 +    {
26343 +      AVR32_ALIAS_PICOMV_W1,
26344 +      &avr32_opc_table[AVR32_OPC_MVCR_W],
26345 +      {
26346 +       { 0, PICO_CPNO },
26347 +       { 1, 0 }, { 1, 1 },
26348 +      },
26349 +    },
26350 +    {
26351 +      AVR32_ALIAS_PICOMV_W2,
26352 +      &avr32_opc_table[AVR32_OPC_MVRC_W],
26353 +      {
26354 +       { 0, PICO_CPNO },
26355 +       { 1, 0 }, { 1, 1 },
26356 +      },
26357 +    },
26358 +    {
26359 +      AVR32_ALIAS_PICOST_D1,
26360 +      &avr32_opc_table[AVR32_OPC_STC_D1],
26361 +      {
26362 +       { 0, PICO_CPNO },
26363 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26364 +      },
26365 +    },
26366 +    {
26367 +      AVR32_ALIAS_PICOST_D2,
26368 +      &avr32_opc_table[AVR32_OPC_STC_D2],
26369 +      {
26370 +       { 0, PICO_CPNO },
26371 +       { 1, 0 }, { 1, 1 },
26372 +      },
26373 +    },
26374 +    {
26375 +      AVR32_ALIAS_PICOST_D3,
26376 +      &avr32_opc_table[AVR32_OPC_STC_D3],
26377 +      {
26378 +       { 0, PICO_CPNO },
26379 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
26380 +      },
26381 +    },
26382 +    {
26383 +      AVR32_ALIAS_PICOST_W1,
26384 +      &avr32_opc_table[AVR32_OPC_STC_W1],
26385 +      {
26386 +       { 0, PICO_CPNO },
26387 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26388 +      },
26389 +    },
26390 +    {
26391 +      AVR32_ALIAS_PICOST_W2,
26392 +      &avr32_opc_table[AVR32_OPC_STC_W2],
26393 +      {
26394 +       { 0, PICO_CPNO },
26395 +       { 1, 0 }, { 1, 1 },
26396 +      },
26397 +    },
26398 +    {
26399 +      AVR32_ALIAS_PICOST_W3,
26400 +      &avr32_opc_table[AVR32_OPC_STC_W3],
26401 +      {
26402 +       { 0, PICO_CPNO },
26403 +       { 1, 0 }, { 1, 1 }, { 1, 2 }, { 1, 3 },
26404 +      },
26405 +    },
26406 +    {
26407 +      AVR32_ALIAS_PICOSTM_D,
26408 +      &avr32_opc_table[AVR32_OPC_STCM_D],
26409 +      {
26410 +       { 0, PICO_CPNO },
26411 +       { 1, 0 }, { 1, 1 },
26412 +      },
26413 +    },
26414 +    {
26415 +      AVR32_ALIAS_PICOSTM_D_PU,
26416 +      &avr32_opc_table[AVR32_OPC_STCM_D_PU],
26417 +      {
26418 +       { 0, PICO_CPNO },
26419 +       { 1, 0 }, { 1, 1 },
26420 +      },
26421 +    },
26422 +    {
26423 +      AVR32_ALIAS_PICOSTM_W,
26424 +      &avr32_opc_table[AVR32_OPC_STCM_W],
26425 +      {
26426 +       { 0, PICO_CPNO },
26427 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26428 +      },
26429 +    },
26430 +    {
26431 +      AVR32_ALIAS_PICOSTM_W_PU,
26432 +      &avr32_opc_table[AVR32_OPC_STCM_W_PU],
26433 +      {
26434 +       { 0, PICO_CPNO },
26435 +       { 1, 0 }, { 1, 1 }, { 1, 2 },
26436 +      },
26437 +    },
26438 +  };
26439 +
26440 +
26441 +#define SYNTAX_NORMAL0(id, mne, opc, arch)                     \
26442 +  {                                                    \
26443 +    AVR32_SYNTAX_##id, arch,                   \
26444 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26445 +    AVR32_PARSER_NORMAL,                                       \
26446 +    { &avr32_opc_table[AVR32_OPC_##opc], },            \
26447 +    NULL, 0, { }                                       \
26448 +  }
26449 +#define SYNTAX_NORMAL1(id, mne, opc, op0, arch)                \
26450 +  {                                                    \
26451 +    AVR32_SYNTAX_##id, arch,                   \
26452 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26453 +    AVR32_PARSER_NORMAL,                                       \
26454 +    { &avr32_opc_table[AVR32_OPC_##opc], },            \
26455 +    NULL, 1,                                           \
26456 +    {                                                  \
26457 +      AVR32_OPERAND_##op0,                             \
26458 +    }                                                  \
26459 +  }
26460 +#define SYNTAX_NORMALM1(id, mne, opc, op0, arch)               \
26461 +  {                                                    \
26462 +    AVR32_SYNTAX_##id, arch,                   \
26463 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26464 +    AVR32_PARSER_NORMAL,                                       \
26465 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26466 +    NULL, -1,                                          \
26467 +    {                                                  \
26468 +      AVR32_OPERAND_##op0,                             \
26469 +    }                                                  \
26470 +  }
26471 +#define SYNTAX_NORMAL2(id, mne, opc, op0, op1, arch)           \
26472 +  {                                                    \
26473 +    AVR32_SYNTAX_##id, arch,                   \
26474 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26475 +    AVR32_PARSER_NORMAL,                                       \
26476 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26477 +    NULL, 2,                                           \
26478 +    {                                                  \
26479 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26480 +    }                                                  \
26481 +  }
26482 +#define SYNTAX_NORMALM2(id, mne, opc, op0, op1, arch)          \
26483 +  {                                                    \
26484 +    AVR32_SYNTAX_##id, arch,                   \
26485 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26486 +    AVR32_PARSER_NORMAL,                                       \
26487 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26488 +    NULL, -2,                                          \
26489 +    {                                                  \
26490 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26491 +    }                                                  \
26492 +  }
26493 +#define SYNTAX_NORMAL3(id, mne, opc, op0, op1, op2, arch)      \
26494 +  {                                                    \
26495 +    AVR32_SYNTAX_##id, arch,                   \
26496 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26497 +    AVR32_PARSER_NORMAL,                                       \
26498 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26499 +    NULL, 3,                                           \
26500 +    {                                                  \
26501 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26502 +      AVR32_OPERAND_##op2,                             \
26503 +    }                                                  \
26504 +  }
26505 +#define SYNTAX_NORMALM3(id, mne, opc, op0, op1, op2, arch)     \
26506 +  {                                                    \
26507 +    AVR32_SYNTAX_##id, arch,                   \
26508 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26509 +    AVR32_PARSER_NORMAL,                                       \
26510 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26511 +    NULL, -3,                                          \
26512 +    {                                                  \
26513 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26514 +      AVR32_OPERAND_##op2,                             \
26515 +    }                                                  \
26516 +  }
26517 +#define SYNTAX_NORMAL4(id, mne, opc, op0, op1, op2, op3, arch)\
26518 +  {                                                    \
26519 +    AVR32_SYNTAX_##id, arch,                   \
26520 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26521 +    AVR32_PARSER_NORMAL,                                       \
26522 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26523 +    NULL, 4,                                           \
26524 +    {                                                  \
26525 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26526 +      AVR32_OPERAND_##op2, AVR32_OPERAND_##op3,                \
26527 +    }                                                  \
26528 +  }
26529 +#define SYNTAX_NORMAL5(id, mne, opc, op0, op1, op2, op3, op4, arch)    \
26530 +  {                                                            \
26531 +    AVR32_SYNTAX_##id, arch,                           \
26532 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],               \
26533 +    AVR32_PARSER_NORMAL,                                               \
26534 +    { &avr32_opc_table[AVR32_OPC_##opc], },                            \
26535 +    NULL, 5,                                                   \
26536 +    {                                                          \
26537 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                        \
26538 +      AVR32_OPERAND_##op2, AVR32_OPERAND_##op3,                        \
26539 +      AVR32_OPERAND_##op4,                                     \
26540 +    }                                                          \
26541 +  }
26542 +
26543 +#define SYNTAX_NORMAL_C1(id, mne, opc, nxt, op0, arch) \
26544 +  {                                                    \
26545 +    AVR32_SYNTAX_##id, arch,                   \
26546 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26547 +    AVR32_PARSER_NORMAL,                                       \
26548 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26549 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], 1,                \
26550 +    {                                                  \
26551 +      AVR32_OPERAND_##op0,                             \
26552 +    }                                                  \
26553 +  }
26554 +#define SYNTAX_NORMAL_CM1(id, mne, opc, nxt, op0, arch)        \
26555 +  {                                                    \
26556 +    AVR32_SYNTAX_##id, arch,                   \
26557 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26558 +    AVR32_PARSER_NORMAL,                                       \
26559 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26560 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], -1,       \
26561 +    {                                                  \
26562 +      AVR32_OPERAND_##op0,                             \
26563 +    }                                                  \
26564 +  }
26565 +#define SYNTAX_NORMAL_C2(id, mne, opc, nxt, op0, op1, arch)    \
26566 +  {                                                    \
26567 +    AVR32_SYNTAX_##id, arch,                   \
26568 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26569 +    AVR32_PARSER_NORMAL,                                       \
26570 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26571 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], 2,                \
26572 +    {                                                  \
26573 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26574 +    }                                                  \
26575 +  }
26576 +#define SYNTAX_NORMAL_CM2(id, mne, opc, nxt, op0, op1, arch)   \
26577 +  {                                                    \
26578 +    AVR32_SYNTAX_##id, arch,                   \
26579 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],       \
26580 +    AVR32_PARSER_NORMAL,                                       \
26581 +    { &avr32_opc_table[AVR32_OPC_##opc], },                    \
26582 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], -2,       \
26583 +    {                                                  \
26584 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                \
26585 +    }                                                  \
26586 +  }
26587 +#define SYNTAX_NORMAL_C3(id, mne, opc, nxt, op0, op1, op2, arch)       \
26588 +  {                                                            \
26589 +    AVR32_SYNTAX_##id, arch,                           \
26590 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],               \
26591 +    AVR32_PARSER_NORMAL,                                               \
26592 +    { &avr32_opc_table[AVR32_OPC_##opc], },                            \
26593 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], 3,                        \
26594 +    {                                                          \
26595 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                        \
26596 +      AVR32_OPERAND_##op2,                                     \
26597 +    }                                                          \
26598 +  }
26599 +#define SYNTAX_NORMAL_CM3(id, mne, opc, nxt, op0, op1, op2, arch)      \
26600 +  {                                                            \
26601 +    AVR32_SYNTAX_##id, arch,                           \
26602 +    &avr32_mnemonic_table[AVR32_MNEMONIC_##mne],               \
26603 +    AVR32_PARSER_NORMAL,                                               \
26604 +    { &avr32_opc_table[AVR32_OPC_##opc], },                            \
26605 +    &avr32_syntax_table[AVR32_SYNTAX_##nxt], -3,               \
26606 +    {                                                          \
26607 +      AVR32_OPERAND_##op0, AVR32_OPERAND_##op1,                        \
26608 +      AVR32_OPERAND_##op2,                                     \
26609 +    }                                                          \
26610 +  }
26611 +
26612 +
26613 +const struct avr32_syntax avr32_syntax_table[] =
26614 +  {
26615 +    SYNTAX_NORMAL1(ABS, ABS, ABS, INTREG, AVR32_V1),
26616 +    SYNTAX_NORMAL1(ACALL, ACALL, ACALL, UNSIGNED_CONST_W, AVR32_V1),
26617 +    SYNTAX_NORMAL1(ACR, ACR, ACR, INTREG,AVR32_V1),
26618 +    SYNTAX_NORMAL3(ADC, ADC, ADC, INTREG, INTREG, INTREG, AVR32_V1),
26619 +    SYNTAX_NORMAL_C2(ADD1, ADD, ADD1, ADD2, INTREG, INTREG, AVR32_V1),
26620 +    SYNTAX_NORMAL3(ADD2, ADD, ADD2, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26621 +    SYNTAX_NORMAL3(ADDABS, ADDABS, ADDABS, INTREG, INTREG, INTREG, AVR32_V1),
26622 +    SYNTAX_NORMAL3(ADDHH_W, ADDHH_W, ADDHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26623 +    SYNTAX_NORMAL_C2(AND1, AND, AND1, AND2, INTREG, INTREG, AVR32_V1),
26624 +    SYNTAX_NORMAL_C3(AND2, AND, AND2, AND3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26625 +    SYNTAX_NORMAL3(AND3, AND, AND3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26626 +    SYNTAX_NORMAL_C2(ANDH, ANDH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, AVR32_V1),
26627 +    SYNTAX_NORMAL3(ANDH_COH, ANDH, ANDH_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1),
26628 +    SYNTAX_NORMAL_C2(ANDL, ANDL, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, AVR32_V1),
26629 +    SYNTAX_NORMAL3(ANDL_COH, ANDL, ANDL_COH, INTREG, UNSIGNED_CONST, COH, AVR32_V1),
26630 +    SYNTAX_NORMAL2(ANDN, ANDN, ANDN, INTREG, INTREG, AVR32_V1),
26631 +    SYNTAX_NORMAL_C3(ASR1, ASR, ASR1, ASR3, INTREG, INTREG, INTREG, AVR32_V1),
26632 +    SYNTAX_NORMAL_C3(ASR3, ASR, ASR3, ASR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26633 +    SYNTAX_NORMAL2(ASR2, ASR, ASR2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26634 +    SYNTAX_NORMAL4(BFEXTS, BFEXTS, BFEXTS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26635 +    SYNTAX_NORMAL4(BFEXTU, BFEXTU, BFEXTU, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26636 +    SYNTAX_NORMAL4(BFINS, BFINS, BFINS, INTREG, INTREG, UNSIGNED_NUMBER, UNSIGNED_NUMBER, AVR32_V1),
26637 +    SYNTAX_NORMAL2(BLD, BLD, BLD, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26638 +    SYNTAX_NORMAL_C1(BREQ1, BREQ, BREQ1, BREQ2, JMPLABEL, AVR32_V1),
26639 +    SYNTAX_NORMAL_C1(BRNE1, BRNE, BRNE1, BRNE2, JMPLABEL, AVR32_V1),
26640 +    SYNTAX_NORMAL_C1(BRCC1, BRCC, BRCC1, BRCC2, JMPLABEL, AVR32_V1),
26641 +    SYNTAX_NORMAL_C1(BRCS1, BRCS, BRCS1, BRCS2, JMPLABEL, AVR32_V1),
26642 +    SYNTAX_NORMAL_C1(BRGE1, BRGE, BRGE1, BRGE2, JMPLABEL, AVR32_V1),
26643 +    SYNTAX_NORMAL_C1(BRLT1, BRLT, BRLT1, BRLT2, JMPLABEL, AVR32_V1),
26644 +    SYNTAX_NORMAL_C1(BRMI1, BRMI, BRMI1, BRMI2, JMPLABEL, AVR32_V1),
26645 +    SYNTAX_NORMAL_C1(BRPL1, BRPL, BRPL1, BRPL2, JMPLABEL, AVR32_V1),
26646 +    SYNTAX_NORMAL_C1(BRHS1, BRHS, BRCC1, BRHS2, JMPLABEL, AVR32_V1),
26647 +    SYNTAX_NORMAL_C1(BRLO1, BRLO, BRCS1, BRLO2, JMPLABEL, AVR32_V1),
26648 +    SYNTAX_NORMAL1(BREQ2, BREQ, BREQ2, JMPLABEL, AVR32_V1),
26649 +    SYNTAX_NORMAL1(BRNE2, BRNE, BRNE2, JMPLABEL, AVR32_V1),
26650 +    SYNTAX_NORMAL1(BRCC2, BRCC, BRCC2, JMPLABEL, AVR32_V1),
26651 +    SYNTAX_NORMAL1(BRCS2, BRCS, BRCS2, JMPLABEL, AVR32_V1),
26652 +    SYNTAX_NORMAL1(BRGE2, BRGE, BRGE2, JMPLABEL, AVR32_V1),
26653 +    SYNTAX_NORMAL1(BRLT2, BRLT, BRLT2, JMPLABEL, AVR32_V1),
26654 +    SYNTAX_NORMAL1(BRMI2, BRMI, BRMI2, JMPLABEL, AVR32_V1),
26655 +    SYNTAX_NORMAL1(BRPL2, BRPL, BRPL2, JMPLABEL, AVR32_V1),
26656 +    SYNTAX_NORMAL1(BRLS, BRLS, BRLS, JMPLABEL, AVR32_V1),
26657 +    SYNTAX_NORMAL1(BRGT, BRGT, BRGT, JMPLABEL, AVR32_V1),
26658 +    SYNTAX_NORMAL1(BRLE, BRLE, BRLE, JMPLABEL, AVR32_V1),
26659 +    SYNTAX_NORMAL1(BRHI, BRHI, BRHI, JMPLABEL, AVR32_V1),
26660 +    SYNTAX_NORMAL1(BRVS, BRVS, BRVS, JMPLABEL, AVR32_V1),
26661 +    SYNTAX_NORMAL1(BRVC, BRVC, BRVC, JMPLABEL, AVR32_V1),
26662 +    SYNTAX_NORMAL1(BRQS, BRQS, BRQS, JMPLABEL, AVR32_V1),
26663 +    SYNTAX_NORMAL1(BRAL, BRAL, BRAL, JMPLABEL, AVR32_V1),
26664 +    SYNTAX_NORMAL1(BRHS2, BRHS, BRCC2, JMPLABEL, AVR32_V1),
26665 +    SYNTAX_NORMAL1(BRLO2, BRLO, BRCS2, JMPLABEL, AVR32_V1),
26666 +    SYNTAX_NORMAL0(BREAKPOINT, BREAKPOINT, BREAKPOINT, AVR32_V1),
26667 +    SYNTAX_NORMAL1(BREV, BREV, BREV, INTREG, AVR32_V1),
26668 +    SYNTAX_NORMAL2(BST, BST, BST, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26669 +    SYNTAX_NORMAL2(CACHE, CACHE, CACHE, INTREG_SDISP, UNSIGNED_NUMBER, AVR32_V1),
26670 +    SYNTAX_NORMAL1(CASTS_B, CASTS_B, CASTS_B, INTREG, AVR32_V1),
26671 +    SYNTAX_NORMAL1(CASTS_H, CASTS_H, CASTS_H, INTREG, AVR32_V1),
26672 +    SYNTAX_NORMAL1(CASTU_B, CASTU_B, CASTU_B, INTREG, AVR32_V1),
26673 +    SYNTAX_NORMAL1(CASTU_H, CASTU_H, CASTU_H, INTREG, AVR32_V1),
26674 +    SYNTAX_NORMAL2(CBR, CBR, CBR, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26675 +    SYNTAX_NORMAL2(CLZ, CLZ, CLZ, INTREG, INTREG, AVR32_V1),
26676 +    SYNTAX_NORMAL1(COM, COM, COM, INTREG, AVR32_V1),
26677 +    SYNTAX_NORMAL5(COP, COP, COP, CPNO, CPREG, CPREG, CPREG, UNSIGNED_NUMBER, AVR32_V1),
26678 +    SYNTAX_NORMAL2(CP_B, CP_B, CP_B, INTREG, INTREG, AVR32_V1),
26679 +    SYNTAX_NORMAL2(CP_H, CP_H, CP_H, INTREG, INTREG, AVR32_V1),
26680 +    SYNTAX_NORMAL_C2(CP_W1, CP_W, CP_W1, CP_W2, INTREG, INTREG, AVR32_V1),
26681 +    SYNTAX_NORMAL_C2(CP_W2, CP_W, CP_W2, CP_W3, INTREG, SIGNED_CONST, AVR32_V1),
26682 +    SYNTAX_NORMAL2(CP_W3, CP_W, CP_W3, INTREG, SIGNED_CONST, AVR32_V1),
26683 +    SYNTAX_NORMAL_C2(CPC1, CPC, CPC1, CPC2, INTREG, INTREG, AVR32_V1),
26684 +    SYNTAX_NORMAL1(CPC2, CPC, CPC2, INTREG, AVR32_V1),
26685 +    SYNTAX_NORMAL1(CSRF, CSRF, CSRF, UNSIGNED_NUMBER, AVR32_V1),
26686 +    SYNTAX_NORMAL1(CSRFCZ, CSRFCZ, CSRFCZ, UNSIGNED_NUMBER, AVR32_V1),
26687 +    SYNTAX_NORMAL3(DIVS, DIVS, DIVS, INTREG, INTREG, INTREG, AVR32_V1),
26688 +    SYNTAX_NORMAL3(DIVU, DIVU, DIVU, INTREG, INTREG, INTREG, AVR32_V1),
26689 +    SYNTAX_NORMAL_C2(EOR1, EOR, EOR1, EOR2, INTREG, INTREG, AVR32_V1),
26690 +    SYNTAX_NORMAL_C3(EOR2, EOR, EOR2, EOR3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26691 +    SYNTAX_NORMAL3(EOR3, EOR, EOR3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26692 +    SYNTAX_NORMAL2(EORL, EORL, EORL, INTREG, UNSIGNED_CONST, AVR32_V1),
26693 +    SYNTAX_NORMAL2(EORH, EORH, EORH, INTREG, UNSIGNED_CONST, AVR32_V1),
26694 +    SYNTAX_NORMAL0(FRS, FRS, FRS, AVR32_V1),
26695 +    SYNTAX_NORMAL0(SSCALL, SSCALL, SSCALL, AVR32_V3),
26696 +    SYNTAX_NORMAL0(RETSS, RETSS, RETSS, AVR32_V3),
26697 +    SYNTAX_NORMAL1(ICALL, ICALL, ICALL, INTREG, AVR32_V1),
26698 +    SYNTAX_NORMAL1(INCJOSP, INCJOSP, INCJOSP, JOSPINC, AVR32_V1),
26699 +    SYNTAX_NORMAL_C2(LD_D1, LD_D, LD_D1, LD_D2, DWREG, INTREG_POSTINC, AVR32_V1),
26700 +    SYNTAX_NORMAL_C2(LD_D2, LD_D, LD_D2, LD_D3, DWREG, INTREG_PREDEC, AVR32_V1),
26701 +    SYNTAX_NORMAL_C2(LD_D3, LD_D, LD_D3, LD_D5, DWREG, INTREG, AVR32_V1),
26702 +    SYNTAX_NORMAL_C2(LD_D5, LD_D, LD_D5, LD_D4, DWREG, INTREG_INDEX, AVR32_V1),
26703 +    SYNTAX_NORMAL2(LD_D4, LD_D, LD_D4, DWREG, INTREG_SDISP, AVR32_V1),
26704 +    SYNTAX_NORMAL_C2(LD_SB2, LD_SB, LD_SB2, LD_SB1, INTREG, INTREG_INDEX, AVR32_V1),
26705 +    SYNTAX_NORMAL2(LD_SB1, LD_SB, LD_SB1, INTREG, INTREG_SDISP, AVR32_V1),
26706 +    SYNTAX_NORMAL_C2(LD_UB1, LD_UB, LD_UB1, LD_UB2, INTREG, INTREG_POSTINC, AVR32_V1),
26707 +    SYNTAX_NORMAL_C2(LD_UB2, LD_UB, LD_UB2, LD_UB5, INTREG, INTREG_PREDEC, AVR32_V1),
26708 +    SYNTAX_NORMAL_C2(LD_UB5, LD_UB, LD_UB5, LD_UB3, INTREG, INTREG_INDEX, AVR32_V1),
26709 +    SYNTAX_NORMAL_C2(LD_UB3, LD_UB, LD_UB3, LD_UB4, INTREG, INTREG_UDISP, AVR32_V1),
26710 +    SYNTAX_NORMAL2(LD_UB4, LD_UB, LD_UB4, INTREG, INTREG_SDISP, AVR32_V1),
26711 +    SYNTAX_NORMAL_C2(LD_SH1, LD_SH, LD_SH1, LD_SH2, INTREG, INTREG_POSTINC, AVR32_V1),
26712 +    SYNTAX_NORMAL_C2(LD_SH2, LD_SH, LD_SH2, LD_SH5, INTREG, INTREG_PREDEC, AVR32_V1),
26713 +    SYNTAX_NORMAL_C2(LD_SH5, LD_SH, LD_SH5, LD_SH3, INTREG, INTREG_INDEX, AVR32_V1),
26714 +    SYNTAX_NORMAL_C2(LD_SH3, LD_SH, LD_SH3, LD_SH4, INTREG, INTREG_UDISP_H, AVR32_V1),
26715 +    SYNTAX_NORMAL2(LD_SH4, LD_SH, LD_SH4, INTREG, INTREG_SDISP, AVR32_V1),
26716 +    SYNTAX_NORMAL_C2(LD_UH1, LD_UH, LD_UH1, LD_UH2, INTREG, INTREG_POSTINC, AVR32_V1),
26717 +    SYNTAX_NORMAL_C2(LD_UH2, LD_UH, LD_UH2, LD_UH5, INTREG, INTREG_PREDEC, AVR32_V1),
26718 +    SYNTAX_NORMAL_C2(LD_UH5, LD_UH, LD_UH5, LD_UH3, INTREG, INTREG_INDEX, AVR32_V1),
26719 +    SYNTAX_NORMAL_C2(LD_UH3, LD_UH, LD_UH3, LD_UH4, INTREG, INTREG_UDISP_H, AVR32_V1),
26720 +    SYNTAX_NORMAL2(LD_UH4, LD_UH, LD_UH4, INTREG, INTREG_SDISP, AVR32_V1),
26721 +    SYNTAX_NORMAL_C2(LD_W1, LD_W, LD_W1, LD_W2, INTREG, INTREG_POSTINC, AVR32_V1),
26722 +    SYNTAX_NORMAL_C2(LD_W2, LD_W, LD_W2, LD_W5, INTREG, INTREG_PREDEC, AVR32_V1),
26723 +    SYNTAX_NORMAL_C2(LD_W5, LD_W, LD_W5, LD_W6, INTREG, INTREG_INDEX, AVR32_V1),
26724 +    SYNTAX_NORMAL_C2(LD_W6, LD_W, LD_W6, LD_W3, INTREG, INTREG_XINDEX, AVR32_V1),
26725 +    SYNTAX_NORMAL_C2(LD_W3, LD_W, LD_W3, LD_W4, INTREG, INTREG_UDISP_W, AVR32_V1),
26726 +    SYNTAX_NORMAL2(LD_W4, LD_W, LD_W4, INTREG, INTREG_SDISP, AVR32_V1),
26727 +    SYNTAX_NORMAL3(LDC_D1, LDC_D, LDC_D1, CPNO, CPREG_D, INTREG_UDISP_W, AVR32_V1),
26728 +    SYNTAX_NORMAL_C3(LDC_D2, LDC_D, LDC_D2, LDC_D1, CPNO, CPREG_D, INTREG_PREDEC, AVR32_V1),
26729 +    SYNTAX_NORMAL_C3(LDC_D3, LDC_D, LDC_D3, LDC_D2, CPNO, CPREG_D, INTREG_INDEX, AVR32_V1),
26730 +    SYNTAX_NORMAL3(LDC_W1, LDC_W, LDC_W1, CPNO, CPREG, INTREG_UDISP_W, AVR32_V1),
26731 +    SYNTAX_NORMAL_C3(LDC_W2, LDC_W, LDC_W2, LDC_W1, CPNO, CPREG, INTREG_PREDEC, AVR32_V1),
26732 +    SYNTAX_NORMAL_C3(LDC_W3, LDC_W, LDC_W3, LDC_W2, CPNO, CPREG, INTREG_INDEX, AVR32_V1),
26733 +    SYNTAX_NORMAL2(LDC0_D, LDC0_D, LDC0_D, CPREG_D, INTREG_UDISP_W, AVR32_V1),
26734 +    SYNTAX_NORMAL2(LDC0_W, LDC0_W, LDC0_W, CPREG, INTREG_UDISP_W, AVR32_V1),
26735 +    SYNTAX_NORMAL_CM3(LDCM_D, LDCM_D, LDCM_D, LDCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1),
26736 +    SYNTAX_NORMALM3(LDCM_D_PU, LDCM_D, LDCM_D_PU, CPNO, INTREG_POSTINC, REGLIST_CPD8, AVR32_V1),
26737 +    SYNTAX_NORMAL_CM3(LDCM_W, LDCM_W, LDCM_W, LDCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1),
26738 +    SYNTAX_NORMALM3(LDCM_W_PU, LDCM_W, LDCM_W_PU, CPNO, INTREG_POSTINC, REGLIST_CP8, AVR32_V1),
26739 +    SYNTAX_NORMAL2(LDDPC, LDDPC, LDDPC, INTREG, PC_UDISP_W, AVR32_V1),
26740 +    SYNTAX_NORMAL2(LDDPC_EXT, LDDPC, LDDPC_EXT, INTREG, SIGNED_CONST, AVR32_V1),
26741 +    SYNTAX_NORMAL2(LDDSP, LDDSP, LDDSP, INTREG, SP_UDISP_W, AVR32_V1),
26742 +    SYNTAX_NORMAL2(LDINS_B, LDINS_B, LDINS_B, INTREG_BSEL, INTREG_SDISP, AVR32_V1),
26743 +    SYNTAX_NORMAL2(LDINS_H, LDINS_H, LDINS_H, INTREG_HSEL, INTREG_SDISP_H, AVR32_V1),
26744 +    SYNTAX_NORMALM1(LDM, LDM, LDM, REGLIST_LDM, AVR32_V1),
26745 +    SYNTAX_NORMAL_CM2(LDMTS, LDMTS, LDMTS, LDMTS_PU, INTREG, REGLIST16, AVR32_V1),
26746 +    SYNTAX_NORMALM2(LDMTS_PU, LDMTS, LDMTS_PU, INTREG_POSTINC, REGLIST16, AVR32_V1),
26747 +    SYNTAX_NORMAL2(LDSWP_SH, LDSWP_SH, LDSWP_SH, INTREG, INTREG_SDISP_H, AVR32_V1),
26748 +    SYNTAX_NORMAL2(LDSWP_UH, LDSWP_UH, LDSWP_UH, INTREG, INTREG_SDISP_H, AVR32_V1),
26749 +    SYNTAX_NORMAL2(LDSWP_W, LDSWP_W, LDSWP_W, INTREG, INTREG_SDISP_W, AVR32_V1),
26750 +    SYNTAX_NORMAL_C3(LSL1, LSL, LSL1, LSL3, INTREG, INTREG, INTREG, AVR32_V1),
26751 +    SYNTAX_NORMAL_C3(LSL3, LSL, LSL3, LSL2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26752 +    SYNTAX_NORMAL2(LSL2, LSL, LSL2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26753 +    SYNTAX_NORMAL_C3(LSR1, LSR, LSR1, LSR3, INTREG, INTREG, INTREG, AVR32_V1),
26754 +    SYNTAX_NORMAL_C3(LSR3, LSR, LSR3, LSR2, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26755 +    SYNTAX_NORMAL2(LSR2, LSR, LSR2, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26756 +    SYNTAX_NORMAL3(MAC, MAC, MAC, INTREG, INTREG, INTREG, AVR32_V1),
26757 +    SYNTAX_NORMAL3(MACHH_D, MACHH_D, MACHH_D, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26758 +    SYNTAX_NORMAL3(MACHH_W, MACHH_W, MACHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26759 +    SYNTAX_NORMAL3(MACS_D, MACS_D, MACS_D, INTREG, INTREG, INTREG, AVR32_V1),
26760 +    SYNTAX_NORMAL3(MACSATHH_W, MACSATHH_W, MACSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26761 +    SYNTAX_NORMAL3(MACUD, MACU_D, MACUD, INTREG, INTREG, INTREG, AVR32_V1),
26762 +    SYNTAX_NORMAL3(MACWH_D, MACWH_D, MACWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26763 +    SYNTAX_NORMAL3(MAX, MAX, MAX, INTREG, INTREG, INTREG, AVR32_V1),
26764 +    SYNTAX_NORMAL1(MCALL, MCALL, MCALL, MCALL, AVR32_V1),
26765 +    SYNTAX_NORMAL2(MFDR, MFDR, MFDR, INTREG, UNSIGNED_CONST_W, AVR32_V1),
26766 +    SYNTAX_NORMAL2(MFSR, MFSR, MFSR, INTREG, UNSIGNED_CONST_W, AVR32_V1),
26767 +    SYNTAX_NORMAL3(MIN, MIN, MIN, INTREG, INTREG, INTREG, AVR32_V1),
26768 +    SYNTAX_NORMAL_C2(MOV3, MOV, MOV3, MOV1, INTREG, INTREG, AVR32_V1),
26769 +    SYNTAX_NORMAL_C2(MOV1, MOV, MOV1, MOV2, INTREG, SIGNED_CONST, AVR32_V1),
26770 +    SYNTAX_NORMAL2(MOV2, MOV, MOV2,INTREG, SIGNED_CONST, AVR32_V1),
26771 +    SYNTAX_NORMAL_C2(MOVEQ1, MOVEQ, MOVEQ1, MOVEQ2, INTREG, INTREG, AVR32_V1),
26772 +    SYNTAX_NORMAL_C2(MOVNE1, MOVNE, MOVNE1, MOVNE2, INTREG, INTREG, AVR32_V1),
26773 +    SYNTAX_NORMAL_C2(MOVCC1, MOVCC, MOVCC1, MOVCC2, INTREG, INTREG, AVR32_V1),
26774 +    SYNTAX_NORMAL_C2(MOVCS1, MOVCS, MOVCS1, MOVCS2, INTREG, INTREG, AVR32_V1),
26775 +    SYNTAX_NORMAL_C2(MOVGE1, MOVGE, MOVGE1, MOVGE2, INTREG, INTREG, AVR32_V1),
26776 +    SYNTAX_NORMAL_C2(MOVLT1, MOVLT, MOVLT1, MOVLT2, INTREG, INTREG, AVR32_V1),
26777 +    SYNTAX_NORMAL_C2(MOVMI1, MOVMI, MOVMI1, MOVMI2, INTREG, INTREG, AVR32_V1),
26778 +    SYNTAX_NORMAL_C2(MOVPL1, MOVPL, MOVPL1, MOVPL2, INTREG, INTREG, AVR32_V1),
26779 +    SYNTAX_NORMAL_C2(MOVLS1, MOVLS, MOVLS1, MOVLS2, INTREG, INTREG, AVR32_V1),
26780 +    SYNTAX_NORMAL_C2(MOVGT1, MOVGT, MOVGT1, MOVGT2, INTREG, INTREG, AVR32_V1),
26781 +    SYNTAX_NORMAL_C2(MOVLE1, MOVLE, MOVLE1, MOVLE2, INTREG, INTREG, AVR32_V1),
26782 +    SYNTAX_NORMAL_C2(MOVHI1, MOVHI, MOVHI1, MOVHI2, INTREG, INTREG, AVR32_V1),
26783 +    SYNTAX_NORMAL_C2(MOVVS1, MOVVS, MOVVS1, MOVVS2, INTREG, INTREG, AVR32_V1),
26784 +    SYNTAX_NORMAL_C2(MOVVC1, MOVVC, MOVVC1, MOVVC2, INTREG, INTREG, AVR32_V1),
26785 +    SYNTAX_NORMAL_C2(MOVQS1, MOVQS, MOVQS1, MOVQS2, INTREG, INTREG, AVR32_V1),
26786 +    SYNTAX_NORMAL_C2(MOVAL1, MOVAL, MOVAL1, MOVAL2, INTREG, INTREG, AVR32_V1),
26787 +    SYNTAX_NORMAL_C2(MOVHS1, MOVHS, MOVCC1, MOVHS2, INTREG, INTREG, AVR32_V1),
26788 +    SYNTAX_NORMAL_C2(MOVLO1, MOVLO, MOVCS1, MOVLO2, INTREG, INTREG, AVR32_V1),
26789 +    SYNTAX_NORMAL2(MOVEQ2, MOVEQ, MOVEQ2, INTREG, SIGNED_CONST, AVR32_V1),
26790 +    SYNTAX_NORMAL2(MOVNE2, MOVNE, MOVNE2, INTREG, SIGNED_CONST, AVR32_V1),
26791 +    SYNTAX_NORMAL2(MOVCC2, MOVCC, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1),
26792 +    SYNTAX_NORMAL2(MOVCS2, MOVCS, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1),
26793 +    SYNTAX_NORMAL2(MOVGE2, MOVGE, MOVGE2, INTREG, SIGNED_CONST, AVR32_V1),
26794 +    SYNTAX_NORMAL2(MOVLT2, MOVLT, MOVLT2, INTREG, SIGNED_CONST, AVR32_V1),
26795 +    SYNTAX_NORMAL2(MOVMI2, MOVMI, MOVMI2, INTREG, SIGNED_CONST, AVR32_V1),
26796 +    SYNTAX_NORMAL2(MOVPL2, MOVPL, MOVPL2, INTREG, SIGNED_CONST, AVR32_V1),
26797 +    SYNTAX_NORMAL2(MOVLS2, MOVLS, MOVLS2, INTREG, SIGNED_CONST, AVR32_V1),
26798 +    SYNTAX_NORMAL2(MOVGT2, MOVGT, MOVGT2, INTREG, SIGNED_CONST, AVR32_V1),
26799 +    SYNTAX_NORMAL2(MOVLE2, MOVLE, MOVLE2, INTREG, SIGNED_CONST, AVR32_V1),
26800 +    SYNTAX_NORMAL2(MOVHI2, MOVHI, MOVHI2, INTREG, SIGNED_CONST, AVR32_V1),
26801 +    SYNTAX_NORMAL2(MOVVS2, MOVVS, MOVVS2, INTREG, SIGNED_CONST, AVR32_V1),
26802 +    SYNTAX_NORMAL2(MOVVC2, MOVVC, MOVVC2, INTREG, SIGNED_CONST, AVR32_V1),
26803 +    SYNTAX_NORMAL2(MOVQS2, MOVQS, MOVQS2, INTREG, SIGNED_CONST, AVR32_V1),
26804 +    SYNTAX_NORMAL2(MOVAL2, MOVAL, MOVAL2, INTREG, SIGNED_CONST, AVR32_V1),
26805 +    SYNTAX_NORMAL2(MOVHS2, MOVHS, MOVCC2, INTREG, SIGNED_CONST, AVR32_V1),
26806 +    SYNTAX_NORMAL2(MOVLO2, MOVLO, MOVCS2, INTREG, SIGNED_CONST, AVR32_V1),
26807 +    SYNTAX_NORMAL2(MTDR, MTDR, MTDR, UNSIGNED_CONST_W, INTREG, AVR32_V1),
26808 +    SYNTAX_NORMAL2(MTSR, MTSR, MTSR, UNSIGNED_CONST_W, INTREG, AVR32_V1),
26809 +    SYNTAX_NORMAL_C2(MUL1, MUL, MUL1, MUL2, INTREG, INTREG, AVR32_V1),
26810 +    SYNTAX_NORMAL_C3(MUL2, MUL, MUL2, MUL3, INTREG, INTREG, INTREG, AVR32_V1),
26811 +    SYNTAX_NORMAL3(MUL3, MUL, MUL3, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
26812 +    SYNTAX_NORMAL3(MULHH_W, MULHH_W, MULHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26813 +    SYNTAX_NORMAL3(MULNHH_W, MULNHH_W, MULNHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26814 +    SYNTAX_NORMAL3(MULNWH_D, MULNWH_D, MULNWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26815 +    SYNTAX_NORMAL3(MULSD, MULS_D, MULSD, INTREG, INTREG, INTREG, AVR32_V1),
26816 +    SYNTAX_NORMAL3(MULSATHH_H, MULSATHH_H, MULSATHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26817 +    SYNTAX_NORMAL3(MULSATHH_W, MULSATHH_W, MULSATHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26818 +    SYNTAX_NORMAL3(MULSATRNDHH_H, MULSATRNDHH_H, MULSATRNDHH_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
26819 +    SYNTAX_NORMAL3(MULSATRNDWH_W, MULSATRNDWH_W, MULSATRNDWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26820 +    SYNTAX_NORMAL3(MULSATWH_W, MULSATWH_W, MULSATWH_W, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26821 +    SYNTAX_NORMAL3(MULU_D, MULU_D, MULU_D, INTREG, INTREG, INTREG, AVR32_V1),
26822 +    SYNTAX_NORMAL3(MULWH_D, MULWH_D, MULWH_D, INTREG, INTREG, INTREG_HSEL, AVR32_DSP),
26823 +    SYNTAX_NORMAL1(MUSFR, MUSFR, MUSFR, INTREG, AVR32_V1),
26824 +    SYNTAX_NORMAL1(MUSTR, MUSTR, MUSTR, INTREG, AVR32_V1),
26825 +    SYNTAX_NORMAL3(MVCR_D, MVCR_D, MVCR_D, CPNO, DWREG, CPREG_D, AVR32_V1),
26826 +    SYNTAX_NORMAL3(MVCR_W, MVCR_W, MVCR_W, CPNO, INTREG, CPREG, AVR32_V1),
26827 +    SYNTAX_NORMAL3(MVRC_D, MVRC_D, MVRC_D, CPNO, CPREG_D, DWREG, AVR32_V1),
26828 +    SYNTAX_NORMAL3(MVRC_W, MVRC_W, MVRC_W, CPNO, CPREG, INTREG, AVR32_V1),
26829 +    SYNTAX_NORMAL1(NEG, NEG, NEG, INTREG, AVR32_V1),
26830 +    SYNTAX_NORMAL0(NOP, NOP, NOP, AVR32_V1),
26831 +    SYNTAX_NORMAL_C2(OR1, OR, OR1, OR2, INTREG, INTREG, AVR32_V1),
26832 +    SYNTAX_NORMAL_C3(OR2, OR, OR2, OR3, INTREG, INTREG, INTREG_LSL, AVR32_V1),
26833 +    SYNTAX_NORMAL3(OR3, OR, OR3, INTREG, INTREG, INTREG_LSR, AVR32_V1),
26834 +    SYNTAX_NORMAL2(ORH, ORH, ORH, INTREG, UNSIGNED_CONST, AVR32_V1),
26835 +    SYNTAX_NORMAL2(ORL, ORL, ORL, INTREG, UNSIGNED_CONST, AVR32_V1),
26836 +    SYNTAX_NORMAL2(PABS_SB, PABS_SB, PABS_SB, INTREG, INTREG, AVR32_SIMD),
26837 +    SYNTAX_NORMAL2(PABS_SH, PABS_SH, PABS_SH, INTREG, INTREG, AVR32_SIMD),
26838 +    SYNTAX_NORMAL3(PACKSH_SB, PACKSH_SB, PACKSH_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26839 +    SYNTAX_NORMAL3(PACKSH_UB, PACKSH_UB, PACKSH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26840 +    SYNTAX_NORMAL3(PACKW_SH, PACKW_SH, PACKW_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26841 +    SYNTAX_NORMAL3(PADD_B, PADD_B, PADD_B, INTREG, INTREG, INTREG, AVR32_SIMD),
26842 +    SYNTAX_NORMAL3(PADD_H, PADD_H, PADD_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26843 +    SYNTAX_NORMAL3(PADDH_SH, PADDH_SH, PADDH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26844 +    SYNTAX_NORMAL3(PADDH_UB, PADDH_UB, PADDH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26845 +    SYNTAX_NORMAL3(PADDS_SB, PADDS_SB, PADDS_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26846 +    SYNTAX_NORMAL3(PADDS_SH, PADDS_SH, PADDS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26847 +    SYNTAX_NORMAL3(PADDS_UB, PADDS_UB, PADDS_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26848 +    SYNTAX_NORMAL3(PADDS_UH, PADDS_UH, PADDS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26849 +    SYNTAX_NORMAL3(PADDSUB_H, PADDSUB_H, PADDSUB_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26850 +    SYNTAX_NORMAL3(PADDSUBH_SH, PADDSUBH_SH, PADDSUBH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26851 +    SYNTAX_NORMAL3(PADDSUBS_SH, PADDSUBS_SH, PADDSUBS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26852 +    SYNTAX_NORMAL3(PADDSUBS_UH, PADDSUBS_UH, PADDSUBS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26853 +    SYNTAX_NORMAL3(PADDX_H, PADDX_H, PADDX_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26854 +    SYNTAX_NORMAL3(PADDXH_SH, PADDXH_SH, PADDXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26855 +    SYNTAX_NORMAL3(PADDXS_SH, PADDXS_SH, PADDXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26856 +    SYNTAX_NORMAL3(PADDXS_UH, PADDXS_UH, PADDXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26857 +    SYNTAX_NORMAL3(PASR_B, PASR_B, PASR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26858 +    SYNTAX_NORMAL3(PASR_H, PASR_H, PASR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26859 +    SYNTAX_NORMAL3(PAVG_SH, PAVG_SH, PAVG_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26860 +    SYNTAX_NORMAL3(PAVG_UB, PAVG_UB, PAVG_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26861 +    SYNTAX_NORMAL3(PLSL_B, PLSL_B, PLSL_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26862 +    SYNTAX_NORMAL3(PLSL_H, PLSL_H, PLSL_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26863 +    SYNTAX_NORMAL3(PLSR_B, PLSR_B, PLSR_B, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26864 +    SYNTAX_NORMAL3(PLSR_H, PLSR_H, PLSR_H, INTREG, INTREG, UNSIGNED_NUMBER, AVR32_SIMD),
26865 +    SYNTAX_NORMAL3(PMAX_SH, PMAX_SH, PMAX_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26866 +    SYNTAX_NORMAL3(PMAX_UB, PMAX_UB, PMAX_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26867 +    SYNTAX_NORMAL3(PMIN_SH, PMIN_SH, PMIN_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26868 +    SYNTAX_NORMAL3(PMIN_UB, PMIN_UB, PMIN_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26869 +    SYNTAX_NORMAL0(POPJC, POPJC, POPJC, AVR32_V1),
26870 +    SYNTAX_NORMAL_CM1(POPM, POPM, POPM, POPM_E, REGLIST9, AVR32_V1),
26871 +    SYNTAX_NORMALM1(POPM_E, POPM, POPM_E, REGLIST16, AVR32_V1),
26872 +    SYNTAX_NORMAL1(PREF, PREF, PREF, INTREG_SDISP, AVR32_V1),
26873 +    SYNTAX_NORMAL3(PSAD, PSAD, PSAD, INTREG, INTREG, INTREG, AVR32_SIMD),
26874 +    SYNTAX_NORMAL3(PSUB_B, PSUB_B, PSUB_B, INTREG, INTREG, INTREG, AVR32_SIMD),
26875 +    SYNTAX_NORMAL3(PSUB_H, PSUB_H, PSUB_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26876 +    SYNTAX_NORMAL3(PSUBADD_H, PSUBADD_H, PSUBADD_H, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26877 +    SYNTAX_NORMAL3(PSUBADDH_SH, PSUBADDH_SH, PSUBADDH_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26878 +    SYNTAX_NORMAL3(PSUBADDS_SH, PSUBADDS_SH, PSUBADDS_SH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26879 +    SYNTAX_NORMAL3(PSUBADDS_UH, PSUBADDS_UH, PSUBADDS_UH, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_SIMD),
26880 +    SYNTAX_NORMAL3(PSUBH_SH, PSUBH_SH, PSUBH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26881 +    SYNTAX_NORMAL3(PSUBH_UB, PSUBH_UB, PSUBH_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26882 +    SYNTAX_NORMAL3(PSUBS_SB, PSUBS_SB, PSUBS_SB, INTREG, INTREG, INTREG, AVR32_SIMD),
26883 +    SYNTAX_NORMAL3(PSUBS_SH, PSUBS_SH, PSUBS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26884 +    SYNTAX_NORMAL3(PSUBS_UB, PSUBS_UB, PSUBS_UB, INTREG, INTREG, INTREG, AVR32_SIMD),
26885 +    SYNTAX_NORMAL3(PSUBS_UH, PSUBS_UH, PSUBS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26886 +    SYNTAX_NORMAL3(PSUBX_H, PSUBX_H, PSUBX_H, INTREG, INTREG, INTREG, AVR32_SIMD),
26887 +    SYNTAX_NORMAL3(PSUBXH_SH, PSUBXH_SH, PSUBXH_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26888 +    SYNTAX_NORMAL3(PSUBXS_SH, PSUBXS_SH, PSUBXS_SH, INTREG, INTREG, INTREG, AVR32_SIMD),
26889 +    SYNTAX_NORMAL3(PSUBXS_UH, PSUBXS_UH, PSUBXS_UH, INTREG, INTREG, INTREG, AVR32_SIMD),
26890 +    SYNTAX_NORMAL2(PUNPCKSB_H, PUNPCKSB_H, PUNPCKSB_H, INTREG, INTREG_HSEL, AVR32_SIMD),
26891 +    SYNTAX_NORMAL2(PUNPCKUB_H, PUNPCKUB_H, PUNPCKUB_H, INTREG, INTREG_HSEL, AVR32_SIMD),
26892 +    SYNTAX_NORMAL0(PUSHJC, PUSHJC, PUSHJC, AVR32_V1),
26893 +    SYNTAX_NORMAL_CM1(PUSHM, PUSHM, PUSHM, PUSHM_E, REGLIST8, AVR32_V1),
26894 +    SYNTAX_NORMALM1(PUSHM_E, PUSHM, PUSHM_E, REGLIST16, AVR32_V1),
26895 +    SYNTAX_NORMAL_C1(RCALL1, RCALL, RCALL1, RCALL2, JMPLABEL, AVR32_V1),
26896 +    SYNTAX_NORMAL1(RCALL2, RCALL, RCALL2, JMPLABEL, AVR32_V1),
26897 +    SYNTAX_NORMAL1(RETEQ, RETEQ, RETEQ, RETVAL, AVR32_V1),
26898 +    SYNTAX_NORMAL1(RETNE, RETNE, RETNE, RETVAL, AVR32_V1),
26899 +    SYNTAX_NORMAL1(RETCC, RETCC, RETCC, RETVAL, AVR32_V1),
26900 +    SYNTAX_NORMAL1(RETCS, RETCS, RETCS, RETVAL, AVR32_V1),
26901 +    SYNTAX_NORMAL1(RETGE, RETGE, RETGE, RETVAL, AVR32_V1),
26902 +    SYNTAX_NORMAL1(RETLT, RETLT, RETLT, RETVAL, AVR32_V1),
26903 +    SYNTAX_NORMAL1(RETMI, RETMI, RETMI, RETVAL, AVR32_V1),
26904 +    SYNTAX_NORMAL1(RETPL, RETPL, RETPL, RETVAL, AVR32_V1),
26905 +    SYNTAX_NORMAL1(RETLS, RETLS, RETLS, RETVAL, AVR32_V1),
26906 +    SYNTAX_NORMAL1(RETGT, RETGT, RETGT, RETVAL, AVR32_V1),
26907 +    SYNTAX_NORMAL1(RETLE, RETLE, RETLE, RETVAL, AVR32_V1),
26908 +    SYNTAX_NORMAL1(RETHI, RETHI, RETHI, RETVAL, AVR32_V1),
26909 +    SYNTAX_NORMAL1(RETVS, RETVS, RETVS, RETVAL, AVR32_V1),
26910 +    SYNTAX_NORMAL1(RETVC, RETVC, RETVC, RETVAL, AVR32_V1),
26911 +    SYNTAX_NORMAL1(RETQS, RETQS, RETQS, RETVAL, AVR32_V1),
26912 +    SYNTAX_NORMAL1(RETAL, RETAL, RETAL, RETVAL, AVR32_V1),
26913 +    SYNTAX_NORMAL1(RETHS, RETHS, RETCC, RETVAL, AVR32_V1),
26914 +    SYNTAX_NORMAL1(RETLO, RETLO, RETCS, RETVAL, AVR32_V1),
26915 +    SYNTAX_NORMAL0(RETD, RETD, RETD, AVR32_V1),
26916 +    SYNTAX_NORMAL0(RETE, RETE, RETE, AVR32_V1),
26917 +    SYNTAX_NORMAL0(RETJ, RETJ, RETJ, AVR32_V1),
26918 +    SYNTAX_NORMAL0(RETS, RETS, RETS, AVR32_V1),
26919 +    SYNTAX_NORMAL1(RJMP, RJMP, RJMP, JMPLABEL, AVR32_V1),
26920 +    SYNTAX_NORMAL1(ROL, ROL, ROL, INTREG, AVR32_V1),
26921 +    SYNTAX_NORMAL1(ROR, ROR, ROR, INTREG, AVR32_V1),
26922 +    SYNTAX_NORMAL_C2(RSUB1, RSUB, RSUB1, RSUB2, INTREG, INTREG, AVR32_V1),
26923 +    SYNTAX_NORMAL3(RSUB2, RSUB, RSUB2, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
26924 +    SYNTAX_NORMAL3(SATADD_H, SATADD_H, SATADD_H, INTREG, INTREG, INTREG,  AVR32_DSP),
26925 +    SYNTAX_NORMAL3(SATADD_W, SATADD_W, SATADD_W, INTREG, INTREG, INTREG, AVR32_DSP),
26926 +    SYNTAX_NORMAL2(SATRNDS, SATRNDS, SATRNDS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26927 +    SYNTAX_NORMAL2(SATRNDU, SATRNDU, SATRNDU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26928 +    SYNTAX_NORMAL2(SATS, SATS, SATS, INTREG_LSR, UNSIGNED_NUMBER, AVR32_DSP),
26929 +    SYNTAX_NORMAL3(SATSUB_H, SATSUB_H, SATSUB_H, INTREG, INTREG, INTREG, AVR32_DSP),
26930 +    SYNTAX_NORMAL_C3(SATSUB_W1, SATSUB_W, SATSUB_W1, SATSUB_W2, INTREG, INTREG, INTREG, AVR32_DSP),
26931 +    SYNTAX_NORMAL3(SATSUB_W2, SATSUB_W, SATSUB_W2, INTREG, INTREG, SIGNED_CONST, AVR32_DSP),
26932 +    SYNTAX_NORMAL2(SATU, SATU, SATU, INTREG_LSR, UNSIGNED_NUMBER, AVR32_V1),
26933 +    SYNTAX_NORMAL3(SBC, SBC, SBC, INTREG, INTREG, INTREG, AVR32_V1),
26934 +    SYNTAX_NORMAL2(SBR, SBR, SBR, INTREG, UNSIGNED_NUMBER, AVR32_V1),
26935 +    SYNTAX_NORMAL0(SCALL, SCALL, SCALL, AVR32_V1),
26936 +    SYNTAX_NORMAL1(SCR, SCR, SCR, INTREG, AVR32_V1),
26937 +    SYNTAX_NORMAL1(SLEEP, SLEEP, SLEEP, UNSIGNED_CONST, AVR32_V1),
26938 +    SYNTAX_NORMAL1(SREQ, SREQ, SREQ, INTREG, AVR32_V1),
26939 +    SYNTAX_NORMAL1(SRNE, SRNE, SRNE, INTREG, AVR32_V1),
26940 +    SYNTAX_NORMAL1(SRCC, SRCC, SRCC, INTREG, AVR32_V1),
26941 +    SYNTAX_NORMAL1(SRCS, SRCS, SRCS, INTREG, AVR32_V1),
26942 +    SYNTAX_NORMAL1(SRGE, SRGE, SRGE, INTREG, AVR32_V1),
26943 +    SYNTAX_NORMAL1(SRLT, SRLT, SRLT, INTREG, AVR32_V1),
26944 +    SYNTAX_NORMAL1(SRMI, SRMI, SRMI, INTREG, AVR32_V1),
26945 +    SYNTAX_NORMAL1(SRPL, SRPL, SRPL, INTREG, AVR32_V1),
26946 +    SYNTAX_NORMAL1(SRLS, SRLS, SRLS, INTREG, AVR32_V1),
26947 +    SYNTAX_NORMAL1(SRGT, SRGT, SRGT, INTREG, AVR32_V1),
26948 +    SYNTAX_NORMAL1(SRLE, SRLE, SRLE, INTREG, AVR32_V1),
26949 +    SYNTAX_NORMAL1(SRHI, SRHI, SRHI, INTREG, AVR32_V1),
26950 +    SYNTAX_NORMAL1(SRVS, SRVS, SRVS, INTREG, AVR32_V1),
26951 +    SYNTAX_NORMAL1(SRVC, SRVC, SRVC, INTREG, AVR32_V1),
26952 +    SYNTAX_NORMAL1(SRQS, SRQS, SRQS, INTREG, AVR32_V1),
26953 +    SYNTAX_NORMAL1(SRAL, SRAL, SRAL, INTREG, AVR32_V1),
26954 +    SYNTAX_NORMAL1(SRHS, SRHS, SRCC, INTREG, AVR32_V1),
26955 +    SYNTAX_NORMAL1(SRLO, SRLO, SRCS, INTREG, AVR32_V1),
26956 +    SYNTAX_NORMAL1(SSRF, SSRF, SSRF, UNSIGNED_NUMBER, AVR32_V1),
26957 +    SYNTAX_NORMAL_C2(ST_B1, ST_B, ST_B1, ST_B2, INTREG_POSTINC, INTREG, AVR32_V1),
26958 +    SYNTAX_NORMAL_C2(ST_B2, ST_B, ST_B2, ST_B5, INTREG_PREDEC, INTREG, AVR32_V1),
26959 +    SYNTAX_NORMAL_C2(ST_B5, ST_B, ST_B5, ST_B3, INTREG_INDEX, INTREG, AVR32_V1),
26960 +    SYNTAX_NORMAL_C2(ST_B3, ST_B, ST_B3, ST_B4, INTREG_UDISP, INTREG, AVR32_V1),
26961 +    SYNTAX_NORMAL2(ST_B4, ST_B, ST_B4, INTREG_SDISP, INTREG, AVR32_V1),
26962 +    SYNTAX_NORMAL_C2(ST_D1, ST_D, ST_D1, ST_D2, INTREG_POSTINC, DWREG, AVR32_V1),
26963 +    SYNTAX_NORMAL_C2(ST_D2, ST_D, ST_D2, ST_D3, INTREG_PREDEC, DWREG, AVR32_V1),
26964 +    SYNTAX_NORMAL_C2(ST_D3, ST_D, ST_D3, ST_D5, INTREG, DWREG, AVR32_V1),
26965 +    SYNTAX_NORMAL_C2(ST_D5, ST_D, ST_D5, ST_D4, INTREG_INDEX, DWREG, AVR32_V1),
26966 +    SYNTAX_NORMAL2(ST_D4, ST_D, ST_D4, INTREG_SDISP, DWREG, AVR32_V1),
26967 +    SYNTAX_NORMAL_C2(ST_H1, ST_H, ST_H1, ST_H2, INTREG_POSTINC, INTREG, AVR32_V1),
26968 +    SYNTAX_NORMAL_C2(ST_H2, ST_H, ST_H2, ST_H5, INTREG_PREDEC, INTREG, AVR32_V1),
26969 +    SYNTAX_NORMAL_C2(ST_H5, ST_H, ST_H5, ST_H3, INTREG_INDEX, INTREG, AVR32_V1),
26970 +    SYNTAX_NORMAL_C2(ST_H3, ST_H, ST_H3, ST_H4, INTREG_UDISP_H, INTREG, AVR32_V1),
26971 +    SYNTAX_NORMAL2(ST_H4, ST_H, ST_H4, INTREG_SDISP, INTREG, AVR32_V1),
26972 +    SYNTAX_NORMAL_C2(ST_W1, ST_W, ST_W1, ST_W2, INTREG_POSTINC, INTREG, AVR32_V1),
26973 +    SYNTAX_NORMAL_C2(ST_W2, ST_W, ST_W2, ST_W5, INTREG_PREDEC, INTREG, AVR32_V1),
26974 +    SYNTAX_NORMAL_C2(ST_W5, ST_W, ST_W5, ST_W3, INTREG_INDEX, INTREG, AVR32_V1),
26975 +    SYNTAX_NORMAL_C2(ST_W3, ST_W, ST_W3, ST_W4, INTREG_UDISP_W, INTREG, AVR32_V1),
26976 +    SYNTAX_NORMAL2(ST_W4, ST_W, ST_W4, INTREG_SDISP, INTREG, AVR32_V1),
26977 +    SYNTAX_NORMAL3(STC_D1, STC_D, STC_D1, CPNO, INTREG_UDISP_W, CPREG_D, AVR32_V1),
26978 +    SYNTAX_NORMAL_C3(STC_D2, STC_D, STC_D2, STC_D1, CPNO, INTREG_POSTINC, CPREG_D, AVR32_V1),
26979 +    SYNTAX_NORMAL_C3(STC_D3, STC_D, STC_D3, STC_D2, CPNO, INTREG_INDEX, CPREG_D, AVR32_V1),
26980 +    SYNTAX_NORMAL3(STC_W1, STC_W, STC_W1, CPNO, INTREG_UDISP_W, CPREG, AVR32_V1),
26981 +    SYNTAX_NORMAL_C3(STC_W2, STC_W, STC_W2, STC_W1, CPNO, INTREG_POSTINC, CPREG, AVR32_V1),
26982 +    SYNTAX_NORMAL_C3(STC_W3, STC_W, STC_W3, STC_W2, CPNO, INTREG_INDEX, CPREG, AVR32_V1),
26983 +    SYNTAX_NORMAL2(STC0_D, STC0_D, STC0_D, INTREG_UDISP_W, CPREG_D, AVR32_V1),
26984 +    SYNTAX_NORMAL2(STC0_W, STC0_W, STC0_W, INTREG_UDISP_W, CPREG, AVR32_V1),
26985 +    SYNTAX_NORMAL_CM3(STCM_D, STCM_D, STCM_D, STCM_D_PU, CPNO, INTREG, REGLIST_CPD8, AVR32_V1),
26986 +    SYNTAX_NORMALM3(STCM_D_PU, STCM_D, STCM_D_PU, CPNO, INTREG_PREDEC, REGLIST_CPD8, AVR32_V1),
26987 +    SYNTAX_NORMAL_CM3(STCM_W, STCM_W, STCM_W, STCM_W_PU, CPNO, INTREG, REGLIST_CP8, AVR32_V1),
26988 +    SYNTAX_NORMALM3(STCM_W_PU, STCM_W, STCM_W_PU, CPNO, INTREG_PREDEC, REGLIST_CP8, AVR32_V1),
26989 +    SYNTAX_NORMAL2(STCOND, STCOND, STCOND, INTREG_SDISP, INTREG, AVR32_V1),
26990 +    SYNTAX_NORMAL2(STDSP, STDSP, STDSP, SP_UDISP_W, INTREG, AVR32_V1),
26991 +    SYNTAX_NORMAL_C3(STHH_W2, STHH_W, STHH_W2, STHH_W1, INTREG_INDEX, INTREG_HSEL, INTREG_HSEL, AVR32_V1),
26992 +    SYNTAX_NORMAL3(STHH_W1, STHH_W, STHH_W1, INTREG_UDISP_W, INTREG_HSEL, INTREG_HSEL, AVR32_V1),
26993 +    SYNTAX_NORMAL_CM2(STM, STM, STM, STM_PU, INTREG, REGLIST16, AVR32_V1),
26994 +    SYNTAX_NORMALM2(STM_PU, STM, STM_PU, INTREG_PREDEC, REGLIST16, AVR32_V1),
26995 +    SYNTAX_NORMAL_CM2(STMTS, STMTS, STMTS, STMTS_PU, INTREG, REGLIST16, AVR32_V1),
26996 +    SYNTAX_NORMALM2(STMTS_PU, STMTS, STMTS_PU, INTREG_PREDEC, REGLIST16, AVR32_V1),
26997 +    SYNTAX_NORMAL2(STSWP_H, STSWP_H, STSWP_H, INTREG_SDISP_H, INTREG, AVR32_V1),
26998 +    SYNTAX_NORMAL2(STSWP_W, STSWP_W, STSWP_W, INTREG_SDISP_W, INTREG, AVR32_V1),
26999 +    SYNTAX_NORMAL_C2(SUB1, SUB, SUB1, SUB2, INTREG, INTREG, AVR32_V1),
27000 +    SYNTAX_NORMAL_C3(SUB2, SUB, SUB2, SUB5, INTREG, INTREG, INTREG_LSL, AVR32_V1),
27001 +    SYNTAX_NORMAL_C3(SUB5, SUB, SUB5, SUB3_SP, INTREG, INTREG, SIGNED_CONST, AVR32_V1),
27002 +    SYNTAX_NORMAL_C2(SUB3_SP, SUB, SUB3_SP, SUB3, SP, SIGNED_CONST_W, AVR32_V1),
27003 +    SYNTAX_NORMAL_C2(SUB3, SUB, SUB3, SUB4, INTREG, SIGNED_CONST, AVR32_V1),
27004 +    SYNTAX_NORMAL2(SUB4, SUB, SUB4, INTREG, SIGNED_CONST, AVR32_V1),
27005 +    SYNTAX_NORMAL_C2(SUBEQ, SUBEQ, SUBEQ, SUB2EQ, INTREG, SIGNED_CONST, AVR32_V1),
27006 +    SYNTAX_NORMAL_C2(SUBNE, SUBNE, SUBNE, SUB2NE, INTREG, SIGNED_CONST, AVR32_V1),
27007 +    SYNTAX_NORMAL_C2(SUBCC, SUBCC, SUBCC, SUB2CC, INTREG, SIGNED_CONST, AVR32_V1),
27008 +    SYNTAX_NORMAL_C2(SUBCS, SUBCS, SUBCS, SUB2CS, INTREG, SIGNED_CONST, AVR32_V1),
27009 +    SYNTAX_NORMAL_C2(SUBGE, SUBGE, SUBGE, SUB2GE, INTREG, SIGNED_CONST, AVR32_V1),
27010 +    SYNTAX_NORMAL_C2(SUBLT, SUBLT, SUBLT, SUB2LT, INTREG, SIGNED_CONST, AVR32_V1),
27011 +    SYNTAX_NORMAL_C2(SUBMI, SUBMI, SUBMI, SUB2MI, INTREG, SIGNED_CONST, AVR32_V1),
27012 +    SYNTAX_NORMAL_C2(SUBPL, SUBPL, SUBPL, SUB2PL, INTREG, SIGNED_CONST, AVR32_V1),
27013 +    SYNTAX_NORMAL_C2(SUBLS, SUBLS, SUBLS, SUB2LS, INTREG, SIGNED_CONST, AVR32_V1),
27014 +    SYNTAX_NORMAL_C2(SUBGT, SUBGT, SUBGT, SUB2GT, INTREG, SIGNED_CONST, AVR32_V1),
27015 +    SYNTAX_NORMAL_C2(SUBLE, SUBLE, SUBLE, SUB2LE, INTREG, SIGNED_CONST, AVR32_V1),
27016 +    SYNTAX_NORMAL_C2(SUBHI, SUBHI, SUBHI, SUB2HI, INTREG, SIGNED_CONST, AVR32_V1),
27017 +    SYNTAX_NORMAL_C2(SUBVS, SUBVS, SUBVS, SUB2VS, INTREG, SIGNED_CONST, AVR32_V1),
27018 +    SYNTAX_NORMAL_C2(SUBVC, SUBVC, SUBVC, SUB2VC, INTREG, SIGNED_CONST, AVR32_V1),
27019 +    SYNTAX_NORMAL_C2(SUBQS, SUBQS, SUBQS, SUB2QS, INTREG, SIGNED_CONST, AVR32_V1),
27020 +    SYNTAX_NORMAL_C2(SUBAL, SUBAL, SUBAL, SUB2AL, INTREG, SIGNED_CONST, AVR32_V1),
27021 +    SYNTAX_NORMAL_C2(SUBHS, SUBHS, SUBCC, SUB2CC, INTREG, SIGNED_CONST, AVR32_V1),
27022 +    SYNTAX_NORMAL_C2(SUBLO, SUBLO, SUBCS, SUB2CS, INTREG, SIGNED_CONST, AVR32_V1),
27023 +    SYNTAX_NORMAL2(SUBFEQ, SUBFEQ, SUBFEQ, INTREG, SIGNED_CONST, AVR32_V1),
27024 +    SYNTAX_NORMAL2(SUBFNE, SUBFNE, SUBFNE, INTREG, SIGNED_CONST, AVR32_V1),
27025 +    SYNTAX_NORMAL2(SUBFCC, SUBFCC, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1),
27026 +    SYNTAX_NORMAL2(SUBFCS, SUBFCS, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1),
27027 +    SYNTAX_NORMAL2(SUBFGE, SUBFGE, SUBFGE, INTREG, SIGNED_CONST, AVR32_V1),
27028 +    SYNTAX_NORMAL2(SUBFLT, SUBFLT, SUBFLT, INTREG, SIGNED_CONST, AVR32_V1),
27029 +    SYNTAX_NORMAL2(SUBFMI, SUBFMI, SUBFMI, INTREG, SIGNED_CONST, AVR32_V1),
27030 +    SYNTAX_NORMAL2(SUBFPL, SUBFPL, SUBFPL, INTREG, SIGNED_CONST, AVR32_V1),
27031 +    SYNTAX_NORMAL2(SUBFLS, SUBFLS, SUBFLS, INTREG, SIGNED_CONST, AVR32_V1),
27032 +    SYNTAX_NORMAL2(SUBFGT, SUBFGT, SUBFGT, INTREG, SIGNED_CONST, AVR32_V1),
27033 +    SYNTAX_NORMAL2(SUBFLE, SUBFLE, SUBFLE, INTREG, SIGNED_CONST, AVR32_V1),
27034 +    SYNTAX_NORMAL2(SUBFHI, SUBFHI, SUBFHI, INTREG, SIGNED_CONST, AVR32_V1),
27035 +    SYNTAX_NORMAL2(SUBFVS, SUBFVS, SUBFVS, INTREG, SIGNED_CONST, AVR32_V1),
27036 +    SYNTAX_NORMAL2(SUBFVC, SUBFVC, SUBFVC, INTREG, SIGNED_CONST, AVR32_V1),
27037 +    SYNTAX_NORMAL2(SUBFQS, SUBFQS, SUBFQS, INTREG, SIGNED_CONST, AVR32_V1),
27038 +    SYNTAX_NORMAL2(SUBFAL, SUBFAL, SUBFAL, INTREG, SIGNED_CONST, AVR32_V1),
27039 +    SYNTAX_NORMAL2(SUBFHS, SUBFHS, SUBFCC, INTREG, SIGNED_CONST, AVR32_V1),
27040 +    SYNTAX_NORMAL2(SUBFLO, SUBFLO, SUBFCS, INTREG, SIGNED_CONST, AVR32_V1),
27041 +    SYNTAX_NORMAL3(SUBHH_W, SUBHH_W, SUBHH_W, INTREG, INTREG_HSEL, INTREG_HSEL, AVR32_DSP),
27042 +    SYNTAX_NORMAL1(SWAP_B, SWAP_B, SWAP_B, INTREG, AVR32_V1),
27043 +    SYNTAX_NORMAL1(SWAP_BH, SWAP_BH, SWAP_BH, INTREG, AVR32_V1),
27044 +    SYNTAX_NORMAL1(SWAP_H, SWAP_H, SWAP_H, INTREG, AVR32_V1),
27045 +    SYNTAX_NORMAL1(SYNC, SYNC, SYNC, UNSIGNED_CONST, AVR32_V1),
27046 +    SYNTAX_NORMAL0(TLBR, TLBR, TLBR, AVR32_V1),
27047 +    SYNTAX_NORMAL0(TLBS, TLBS, TLBS, AVR32_V1),
27048 +    SYNTAX_NORMAL0(TLBW, TLBW, TLBW, AVR32_V1),
27049 +    SYNTAX_NORMAL1(TNBZ, TNBZ, TNBZ, INTREG, AVR32_V1),
27050 +    SYNTAX_NORMAL2(TST, TST, TST, INTREG, INTREG, AVR32_V1),
27051 +    SYNTAX_NORMAL3(XCHG, XCHG, XCHG, INTREG, INTREG, INTREG, AVR32_V1),
27052 +    SYNTAX_NORMAL2(MEMC, MEMC, MEMC, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
27053 +    SYNTAX_NORMAL2(MEMS, MEMS, MEMS, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
27054 +    SYNTAX_NORMAL2(MEMT, MEMT, MEMT, SIGNED_CONST_W, UNSIGNED_NUMBER, AVR32_RMW),
27055 +  SYNTAX_NORMAL4 (FMAC_S,  FMAC_S,  FMAC_S,  INTREG, INTREG, INTREG, INTREG,
27056 +                  AVR32_V3FP),
27057 +  SYNTAX_NORMAL4 (FNMAC_S, FNMAC_S, FNMAC_S, INTREG, INTREG, INTREG, INTREG,
27058 +                  AVR32_V3FP),
27059 +  SYNTAX_NORMAL4 (FMSC_S,  FMSC_S,  FMSC_S,  INTREG, INTREG, INTREG, INTREG,
27060 +                  AVR32_V3FP),
27061 +  SYNTAX_NORMAL4 (FNMSC_S, FNMSC_S, FNMSC_S, INTREG, INTREG, INTREG, INTREG,
27062 +                  AVR32_V3FP),
27063 +  SYNTAX_NORMAL3 (FMUL_S,  FMUL_S,  FMUL_S,  INTREG, INTREG, INTREG, AVR32_V3FP),
27064 +  SYNTAX_NORMAL3 (FNMUL_S, FNMUL_S, FNMUL_S, INTREG, INTREG, INTREG, AVR32_V3FP),
27065 +  SYNTAX_NORMAL3 (FADD_S,  FADD_S,  FADD_S,  INTREG, INTREG, INTREG, AVR32_V3FP),
27066 +  SYNTAX_NORMAL3 (FSUB_S,  FSUB_S,  FSUB_S,  INTREG, INTREG, INTREG, AVR32_V3FP),
27067 +  SYNTAX_NORMAL2 (FCASTRS_SW, FCASTRS_SW, FCASTRS_SW, INTREG, INTREG, AVR32_V3FP),
27068 +  SYNTAX_NORMAL2 (FCASTRS_UW, FCASTRS_UW, FCASTRS_UW, INTREG, INTREG, AVR32_V3FP),
27069 +  SYNTAX_NORMAL2 (FCASTSW_S,  FCASTSW_S,  FCASTSW_S,  INTREG, INTREG, AVR32_V3FP),
27070 +  SYNTAX_NORMAL2 (FCASTUW_S,  FCASTUW_S,  FCASTUW_S,  INTREG, INTREG, AVR32_V3FP),
27071 +  SYNTAX_NORMAL2 (FCMP_S, FCMP_S, FCMP_S, INTREG, INTREG, AVR32_V3FP),
27072 +  SYNTAX_NORMAL1 (FCHK_S, FCHK_S, FCHK_S, INTREG, AVR32_V3FP),
27073 +  SYNTAX_NORMAL2 (FRCPA_S,   FRCPA_S,   FRCPA_S,   INTREG, INTREG, AVR32_V3FP),
27074 +  SYNTAX_NORMAL2 (FRSQRTA_S, FRSQRTA_S, FRSQRTA_S, INTREG, INTREG, AVR32_V3FP),
27075 +    {
27076 +      AVR32_SYNTAX_LDA_W,
27077 +      AVR32_V1, NULL, AVR32_PARSER_LDA,
27078 +      { NULL }, NULL,
27079 +      2,
27080 +      {
27081 +       AVR32_OPERAND_INTREG,
27082 +       AVR32_OPERAND_SIGNED_CONST,
27083 +      },
27084 +    },
27085 +    {
27086 +      AVR32_SYNTAX_CALL,
27087 +      AVR32_V1, NULL, AVR32_PARSER_CALL,
27088 +      { NULL }, NULL,
27089 +      1,
27090 +      {
27091 +       AVR32_OPERAND_JMPLABEL,
27092 +      },
27093 +    },
27094 +    {
27095 +      AVR32_SYNTAX_PICOSVMAC0,
27096 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
27097 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC0] },
27098 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC1], 4,
27099 +      {
27100 +       AVR32_OPERAND_PICO_OUT0,
27101 +       AVR32_OPERAND_PICO_IN,
27102 +       AVR32_OPERAND_PICO_IN,
27103 +       AVR32_OPERAND_PICO_IN,
27104 +      },
27105 +    },
27106 +    {
27107 +      AVR32_SYNTAX_PICOSVMAC1,
27108 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
27109 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC1] },
27110 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC2], 4,
27111 +      {
27112 +       AVR32_OPERAND_PICO_OUT1,
27113 +       AVR32_OPERAND_PICO_IN,
27114 +       AVR32_OPERAND_PICO_IN,
27115 +       AVR32_OPERAND_PICO_IN,
27116 +      },
27117 +    },
27118 +    {
27119 +      AVR32_SYNTAX_PICOSVMAC2,
27120 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
27121 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC2] },
27122 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMAC3], 4,
27123 +      {
27124 +       AVR32_OPERAND_PICO_OUT2,
27125 +       AVR32_OPERAND_PICO_IN,
27126 +       AVR32_OPERAND_PICO_IN,
27127 +       AVR32_OPERAND_PICO_IN,
27128 +      },
27129 +    },
27130 +    {
27131 +      AVR32_SYNTAX_PICOSVMAC3,
27132 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMAC], AVR32_PARSER_ALIAS,
27133 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMAC3] },
27134 +      NULL, 4,
27135 +      {
27136 +       AVR32_OPERAND_PICO_OUT3,
27137 +       AVR32_OPERAND_PICO_IN,
27138 +       AVR32_OPERAND_PICO_IN,
27139 +       AVR32_OPERAND_PICO_IN,
27140 +      },
27141 +    },
27142 +    {
27143 +      AVR32_SYNTAX_PICOSVMUL0,
27144 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
27145 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL0] },
27146 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL1], 4,
27147 +      {
27148 +       AVR32_OPERAND_PICO_OUT0,
27149 +       AVR32_OPERAND_PICO_IN,
27150 +       AVR32_OPERAND_PICO_IN,
27151 +       AVR32_OPERAND_PICO_IN,
27152 +      },
27153 +    },
27154 +    {
27155 +      AVR32_SYNTAX_PICOSVMUL1,
27156 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
27157 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL1] },
27158 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL2], 4,
27159 +      {
27160 +       AVR32_OPERAND_PICO_OUT1,
27161 +       AVR32_OPERAND_PICO_IN,
27162 +       AVR32_OPERAND_PICO_IN,
27163 +       AVR32_OPERAND_PICO_IN,
27164 +      },
27165 +    },
27166 +    {
27167 +      AVR32_SYNTAX_PICOSVMUL2,
27168 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
27169 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL2] },
27170 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSVMUL3], 4,
27171 +      {
27172 +       AVR32_OPERAND_PICO_OUT2,
27173 +       AVR32_OPERAND_PICO_IN,
27174 +       AVR32_OPERAND_PICO_IN,
27175 +       AVR32_OPERAND_PICO_IN,
27176 +      },
27177 +    },
27178 +    {
27179 +      AVR32_SYNTAX_PICOSVMUL3,
27180 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSVMUL], AVR32_PARSER_ALIAS,
27181 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSVMUL3] },
27182 +      NULL, 4,
27183 +      {
27184 +       AVR32_OPERAND_PICO_OUT3,
27185 +       AVR32_OPERAND_PICO_IN,
27186 +       AVR32_OPERAND_PICO_IN,
27187 +       AVR32_OPERAND_PICO_IN,
27188 +      },
27189 +    },
27190 +    {
27191 +      AVR32_SYNTAX_PICOVMAC0,
27192 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27193 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC0] },
27194 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC1], 4,
27195 +      {
27196 +       AVR32_OPERAND_PICO_OUT0,
27197 +       AVR32_OPERAND_PICO_IN,
27198 +       AVR32_OPERAND_PICO_IN,
27199 +       AVR32_OPERAND_PICO_IN,
27200 +      },
27201 +    },
27202 +    {
27203 +      AVR32_SYNTAX_PICOVMAC1,
27204 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27205 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC1] },
27206 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC2], 4,
27207 +      {
27208 +       AVR32_OPERAND_PICO_OUT1,
27209 +       AVR32_OPERAND_PICO_IN,
27210 +       AVR32_OPERAND_PICO_IN,
27211 +       AVR32_OPERAND_PICO_IN,
27212 +      },
27213 +    },
27214 +    {
27215 +      AVR32_SYNTAX_PICOVMAC2,
27216 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27217 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC2] },
27218 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMAC3], 4,
27219 +      {
27220 +       AVR32_OPERAND_PICO_OUT2,
27221 +       AVR32_OPERAND_PICO_IN,
27222 +       AVR32_OPERAND_PICO_IN,
27223 +       AVR32_OPERAND_PICO_IN,
27224 +      },
27225 +    },
27226 +    {
27227 +      AVR32_SYNTAX_PICOVMAC3,
27228 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMAC], AVR32_PARSER_ALIAS,
27229 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMAC3] },
27230 +      NULL, 4,
27231 +      {
27232 +       AVR32_OPERAND_PICO_OUT3,
27233 +       AVR32_OPERAND_PICO_IN,
27234 +       AVR32_OPERAND_PICO_IN,
27235 +       AVR32_OPERAND_PICO_IN,
27236 +      },
27237 +    },
27238 +    {
27239 +      AVR32_SYNTAX_PICOVMUL0,
27240 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27241 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL0] },
27242 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL1], 4,
27243 +      {
27244 +       AVR32_OPERAND_PICO_OUT0,
27245 +       AVR32_OPERAND_PICO_IN,
27246 +       AVR32_OPERAND_PICO_IN,
27247 +       AVR32_OPERAND_PICO_IN,
27248 +      },
27249 +    },
27250 +    {
27251 +      AVR32_SYNTAX_PICOVMUL1,
27252 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27253 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL1] },
27254 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL2], 4,
27255 +      {
27256 +       AVR32_OPERAND_PICO_OUT1,
27257 +       AVR32_OPERAND_PICO_IN,
27258 +       AVR32_OPERAND_PICO_IN,
27259 +       AVR32_OPERAND_PICO_IN,
27260 +      },
27261 +    },
27262 +    {
27263 +      AVR32_SYNTAX_PICOVMUL2,
27264 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27265 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL2] },
27266 +      &avr32_syntax_table[AVR32_SYNTAX_PICOVMUL3], 4,
27267 +      {
27268 +       AVR32_OPERAND_PICO_OUT2,
27269 +       AVR32_OPERAND_PICO_IN,
27270 +       AVR32_OPERAND_PICO_IN,
27271 +       AVR32_OPERAND_PICO_IN,
27272 +      },
27273 +    },
27274 +    {
27275 +      AVR32_SYNTAX_PICOVMUL3,
27276 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOVMUL], AVR32_PARSER_ALIAS,
27277 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOVMUL3] },
27278 +      NULL, 4,
27279 +      {
27280 +       AVR32_OPERAND_PICO_OUT3,
27281 +       AVR32_OPERAND_PICO_IN,
27282 +       AVR32_OPERAND_PICO_IN,
27283 +       AVR32_OPERAND_PICO_IN,
27284 +      },
27285 +    },
27286 +    {
27287 +      AVR32_SYNTAX_PICOLD_D2,
27288 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
27289 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D2] },
27290 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_D3], 2,
27291 +      {
27292 +       AVR32_OPERAND_PICO_REG_D,
27293 +       AVR32_OPERAND_INTREG_PREDEC,
27294 +      },
27295 +    },
27296 +    {
27297 +      AVR32_SYNTAX_PICOLD_D3,
27298 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
27299 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D3] },
27300 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_D1], 2,
27301 +      {
27302 +       AVR32_OPERAND_PICO_REG_D,
27303 +       AVR32_OPERAND_INTREG_INDEX,
27304 +      },
27305 +    },
27306 +    {
27307 +      AVR32_SYNTAX_PICOLD_D1,
27308 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_D], AVR32_PARSER_ALIAS,
27309 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_D1] },
27310 +      NULL, 2,
27311 +      {
27312 +       AVR32_OPERAND_PICO_REG_D,
27313 +       AVR32_OPERAND_INTREG_UDISP_W,
27314 +      },
27315 +    },
27316 +    {
27317 +      AVR32_SYNTAX_PICOLD_W2,
27318 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
27319 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W2] },
27320 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_W3], 2,
27321 +      {
27322 +       AVR32_OPERAND_PICO_REG_W,
27323 +       AVR32_OPERAND_INTREG_PREDEC,
27324 +      },
27325 +    },
27326 +    {
27327 +      AVR32_SYNTAX_PICOLD_W3,
27328 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
27329 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W3] },
27330 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLD_W1], 2,
27331 +      {
27332 +       AVR32_OPERAND_PICO_REG_W,
27333 +       AVR32_OPERAND_INTREG_INDEX,
27334 +      },
27335 +    },
27336 +    {
27337 +      AVR32_SYNTAX_PICOLD_W1,
27338 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLD_W], AVR32_PARSER_ALIAS,
27339 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLD_W1] },
27340 +      NULL, 2,
27341 +      {
27342 +       AVR32_OPERAND_PICO_REG_W,
27343 +       AVR32_OPERAND_INTREG_UDISP_W,
27344 +      },
27345 +    },
27346 +    {
27347 +      AVR32_SYNTAX_PICOLDM_D,
27348 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_D], AVR32_PARSER_ALIAS,
27349 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_D] },
27350 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLDM_D_PU], -2,
27351 +      {
27352 +       AVR32_OPERAND_INTREG,
27353 +       AVR32_OPERAND_PICO_REGLIST_D,
27354 +      },
27355 +    },
27356 +    {
27357 +      AVR32_SYNTAX_PICOLDM_D_PU,
27358 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_D], AVR32_PARSER_ALIAS,
27359 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_D_PU] },
27360 +      NULL, -2,
27361 +      {
27362 +       AVR32_OPERAND_INTREG_POSTINC,
27363 +       AVR32_OPERAND_PICO_REGLIST_D,
27364 +      },
27365 +    },
27366 +    {
27367 +      AVR32_SYNTAX_PICOLDM_W,
27368 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_W], AVR32_PARSER_ALIAS,
27369 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_W] },
27370 +      &avr32_syntax_table[AVR32_SYNTAX_PICOLDM_W_PU], -2,
27371 +      {
27372 +       AVR32_OPERAND_INTREG,
27373 +       AVR32_OPERAND_PICO_REGLIST_W,
27374 +      },
27375 +    },
27376 +    {
27377 +      AVR32_SYNTAX_PICOLDM_W_PU,
27378 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOLDM_W], AVR32_PARSER_ALIAS,
27379 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOLDM_W_PU] },
27380 +      NULL, -2,
27381 +      {
27382 +       AVR32_OPERAND_INTREG_POSTINC,
27383 +       AVR32_OPERAND_PICO_REGLIST_W,
27384 +      },
27385 +    },
27386 +    {
27387 +      AVR32_SYNTAX_PICOMV_D1,
27388 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_D], AVR32_PARSER_ALIAS,
27389 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_D1] },
27390 +      &avr32_syntax_table[AVR32_SYNTAX_PICOMV_D2], 2,
27391 +      {
27392 +       AVR32_OPERAND_DWREG,
27393 +       AVR32_OPERAND_PICO_REG_D,
27394 +      },
27395 +    },
27396 +    {
27397 +      AVR32_SYNTAX_PICOMV_D2,
27398 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_D], AVR32_PARSER_ALIAS,
27399 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_D2] },
27400 +      NULL, 2,
27401 +      {
27402 +       AVR32_OPERAND_PICO_REG_D,
27403 +       AVR32_OPERAND_DWREG,
27404 +      },
27405 +    },
27406 +    {
27407 +      AVR32_SYNTAX_PICOMV_W1,
27408 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_W], AVR32_PARSER_ALIAS,
27409 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_W1] },
27410 +      &avr32_syntax_table[AVR32_SYNTAX_PICOMV_W2], 2,
27411 +      {
27412 +       AVR32_OPERAND_INTREG,
27413 +       AVR32_OPERAND_PICO_REG_W,
27414 +      },
27415 +    },
27416 +    {
27417 +      AVR32_SYNTAX_PICOMV_W2,
27418 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOMV_W], AVR32_PARSER_ALIAS,
27419 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOMV_W2] },
27420 +      NULL, 2,
27421 +      {
27422 +       AVR32_OPERAND_PICO_REG_W,
27423 +       AVR32_OPERAND_INTREG,
27424 +      },
27425 +    },
27426 +    {
27427 +      AVR32_SYNTAX_PICOST_D2,
27428 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
27429 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D2] },
27430 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_D3], 2,
27431 +      {
27432 +       AVR32_OPERAND_INTREG_POSTINC,
27433 +       AVR32_OPERAND_PICO_REG_D,
27434 +      },
27435 +    },
27436 +    {
27437 +      AVR32_SYNTAX_PICOST_D3,
27438 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
27439 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D3] },
27440 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_D1], 2,
27441 +      {
27442 +       AVR32_OPERAND_INTREG_INDEX,
27443 +       AVR32_OPERAND_PICO_REG_D,
27444 +      },
27445 +    },
27446 +    {
27447 +      AVR32_SYNTAX_PICOST_D1,
27448 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_D], AVR32_PARSER_ALIAS,
27449 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_D1] },
27450 +      NULL, 2,
27451 +      {
27452 +       AVR32_OPERAND_INTREG_UDISP_W,
27453 +       AVR32_OPERAND_PICO_REG_D,
27454 +      },
27455 +    },
27456 +    {
27457 +      AVR32_SYNTAX_PICOST_W2,
27458 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
27459 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W2] },
27460 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_W3], 2,
27461 +      {
27462 +       AVR32_OPERAND_INTREG_POSTINC,
27463 +       AVR32_OPERAND_PICO_REG_W,
27464 +      },
27465 +    },
27466 +    {
27467 +      AVR32_SYNTAX_PICOST_W3,
27468 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
27469 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W3] },
27470 +      &avr32_syntax_table[AVR32_SYNTAX_PICOST_W1], 2,
27471 +      {
27472 +       AVR32_OPERAND_INTREG_INDEX,
27473 +       AVR32_OPERAND_PICO_REG_W,
27474 +      },
27475 +    },
27476 +    {
27477 +      AVR32_SYNTAX_PICOST_W1,
27478 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOST_W], AVR32_PARSER_ALIAS,
27479 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOST_W1] },
27480 +      NULL, 2,
27481 +      {
27482 +       AVR32_OPERAND_INTREG_UDISP_W,
27483 +       AVR32_OPERAND_PICO_REG_W,
27484 +      },
27485 +    },
27486 +    {
27487 +      AVR32_SYNTAX_PICOSTM_D,
27488 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_D], AVR32_PARSER_ALIAS,
27489 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_D] },
27490 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSTM_D_PU], -2,
27491 +      {
27492 +       AVR32_OPERAND_INTREG,
27493 +       AVR32_OPERAND_PICO_REGLIST_D,
27494 +      },
27495 +    },
27496 +    {
27497 +      AVR32_SYNTAX_PICOSTM_D_PU,
27498 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_D], AVR32_PARSER_ALIAS,
27499 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_D_PU] },
27500 +      NULL, -2,
27501 +      {
27502 +       AVR32_OPERAND_INTREG_PREDEC,
27503 +       AVR32_OPERAND_PICO_REGLIST_D,
27504 +      },
27505 +    },
27506 +    {
27507 +      AVR32_SYNTAX_PICOSTM_W,
27508 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_W], AVR32_PARSER_ALIAS,
27509 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_W] },
27510 +      &avr32_syntax_table[AVR32_SYNTAX_PICOSTM_W_PU], -2,
27511 +      {
27512 +       AVR32_OPERAND_INTREG,
27513 +       AVR32_OPERAND_PICO_REGLIST_W,
27514 +      },
27515 +    },
27516 +    {
27517 +      AVR32_SYNTAX_PICOSTM_W_PU,
27518 +      AVR32_PICO, &avr32_mnemonic_table[AVR32_MNEMONIC_PICOSTM_W], AVR32_PARSER_ALIAS,
27519 +      { .alias = &avr32_alias_table[AVR32_ALIAS_PICOSTM_W_PU] },
27520 +      NULL, -2,
27521 +      {
27522 +       AVR32_OPERAND_INTREG_PREDEC,
27523 +       AVR32_OPERAND_PICO_REGLIST_W,
27524 +      },
27525 +    },
27526 +    SYNTAX_NORMAL2(RSUBEQ, RSUBEQ, RSUBEQ, INTREG, SIGNED_CONST, AVR32_V1),
27527 +    SYNTAX_NORMAL2(RSUBNE, RSUBNE, RSUBNE, INTREG, SIGNED_CONST, AVR32_V2),
27528 +    SYNTAX_NORMAL2(RSUBCC, RSUBCC, RSUBCC, INTREG, SIGNED_CONST, AVR32_V2),
27529 +    SYNTAX_NORMAL2(RSUBCS, RSUBCS, RSUBCS, INTREG, SIGNED_CONST, AVR32_V2),
27530 +    SYNTAX_NORMAL2(RSUBGE, RSUBGE, RSUBGE, INTREG, SIGNED_CONST, AVR32_V2),
27531 +    SYNTAX_NORMAL2(RSUBLT, RSUBLT, RSUBLT, INTREG, SIGNED_CONST, AVR32_V2),
27532 +    SYNTAX_NORMAL2(RSUBMI, RSUBMI, RSUBMI, INTREG, SIGNED_CONST, AVR32_V2),
27533 +    SYNTAX_NORMAL2(RSUBPL, RSUBPL, RSUBPL, INTREG, SIGNED_CONST, AVR32_V2),
27534 +    SYNTAX_NORMAL2(RSUBLS, RSUBLS, RSUBLS, INTREG, SIGNED_CONST, AVR32_V2),
27535 +    SYNTAX_NORMAL2(RSUBGT, RSUBGT, RSUBGT, INTREG, SIGNED_CONST, AVR32_V2),
27536 +    SYNTAX_NORMAL2(RSUBLE, RSUBLE, RSUBLE, INTREG, SIGNED_CONST, AVR32_V2),
27537 +    SYNTAX_NORMAL2(RSUBHI, RSUBHI, RSUBHI, INTREG, SIGNED_CONST, AVR32_V2),
27538 +    SYNTAX_NORMAL2(RSUBVS, RSUBVS, RSUBVS, INTREG, SIGNED_CONST, AVR32_V2),
27539 +    SYNTAX_NORMAL2(RSUBVC, RSUBVC, RSUBVC, INTREG, SIGNED_CONST, AVR32_V2),
27540 +    SYNTAX_NORMAL2(RSUBQS, RSUBQS, RSUBQS, INTREG, SIGNED_CONST, AVR32_V2),
27541 +    SYNTAX_NORMAL2(RSUBAL, RSUBAL, RSUBAL, INTREG, SIGNED_CONST, AVR32_V2),
27542 +    SYNTAX_NORMAL2(RSUBHS, RSUBHS, RSUBCC, INTREG, SIGNED_CONST, AVR32_V2),
27543 +    SYNTAX_NORMAL2(RSUBLO, RSUBLO, RSUBCS, INTREG, SIGNED_CONST, AVR32_V2),
27544 +    SYNTAX_NORMAL3(ADDEQ, ADDEQ, ADDEQ, INTREG, INTREG, INTREG, AVR32_V2),
27545 +    SYNTAX_NORMAL3(ADDNE, ADDNE, ADDNE, INTREG, INTREG, INTREG, AVR32_V2),
27546 +    SYNTAX_NORMAL3(ADDCC, ADDCC, ADDCC, INTREG, INTREG, INTREG, AVR32_V2),
27547 +    SYNTAX_NORMAL3(ADDCS, ADDCS, ADDCS, INTREG, INTREG, INTREG, AVR32_V2),
27548 +    SYNTAX_NORMAL3(ADDGE, ADDGE, ADDGE, INTREG, INTREG, INTREG, AVR32_V2),
27549 +    SYNTAX_NORMAL3(ADDLT, ADDLT, ADDLT, INTREG, INTREG, INTREG, AVR32_V2),
27550 +    SYNTAX_NORMAL3(ADDMI, ADDMI, ADDMI, INTREG, INTREG, INTREG, AVR32_V2),
27551 +    SYNTAX_NORMAL3(ADDPL, ADDPL, ADDPL, INTREG, INTREG, INTREG, AVR32_V2),
27552 +    SYNTAX_NORMAL3(ADDLS, ADDLS, ADDLS, INTREG, INTREG, INTREG, AVR32_V2),
27553 +    SYNTAX_NORMAL3(ADDGT, ADDGT, ADDGT, INTREG, INTREG, INTREG, AVR32_V2),
27554 +    SYNTAX_NORMAL3(ADDLE, ADDLE, ADDLE, INTREG, INTREG, INTREG, AVR32_V2),
27555 +    SYNTAX_NORMAL3(ADDHI, ADDHI, ADDHI, INTREG, INTREG, INTREG, AVR32_V2),
27556 +    SYNTAX_NORMAL3(ADDVS, ADDVS, ADDVS, INTREG, INTREG, INTREG, AVR32_V2),
27557 +    SYNTAX_NORMAL3(ADDVC, ADDVC, ADDVC, INTREG, INTREG, INTREG, AVR32_V2),
27558 +    SYNTAX_NORMAL3(ADDQS, ADDQS, ADDQS, INTREG, INTREG, INTREG, AVR32_V2),
27559 +    SYNTAX_NORMAL3(ADDAL, ADDAL, ADDAL, INTREG, INTREG, INTREG, AVR32_V2),
27560 +    SYNTAX_NORMAL3(ADDHS, ADDHS, ADDCC, INTREG, INTREG, INTREG, AVR32_V2),
27561 +    SYNTAX_NORMAL3(ADDLO, ADDLO, ADDCS, INTREG, INTREG, INTREG, AVR32_V2),
27562 +    SYNTAX_NORMAL3(SUB2EQ, SUBEQ, SUB2EQ, INTREG, INTREG, INTREG, AVR32_V2),
27563 +    SYNTAX_NORMAL3(SUB2NE, SUBNE, SUB2NE, INTREG, INTREG, INTREG, AVR32_V2),
27564 +    SYNTAX_NORMAL3(SUB2CC, SUBCC, SUB2CC, INTREG, INTREG, INTREG, AVR32_V2),
27565 +    SYNTAX_NORMAL3(SUB2CS, SUBCS, SUB2CS, INTREG, INTREG, INTREG, AVR32_V2),
27566 +    SYNTAX_NORMAL3(SUB2GE, SUBGE, SUB2GE, INTREG, INTREG, INTREG, AVR32_V2),
27567 +    SYNTAX_NORMAL3(SUB2LT, SUBLT, SUB2LT, INTREG, INTREG, INTREG, AVR32_V2),
27568 +    SYNTAX_NORMAL3(SUB2MI, SUBMI, SUB2MI, INTREG, INTREG, INTREG, AVR32_V2),
27569 +    SYNTAX_NORMAL3(SUB2PL, SUBPL, SUB2PL, INTREG, INTREG, INTREG, AVR32_V2),
27570 +    SYNTAX_NORMAL3(SUB2LS, SUBLS, SUB2LS, INTREG, INTREG, INTREG, AVR32_V2),
27571 +    SYNTAX_NORMAL3(SUB2GT, SUBGT, SUB2GT, INTREG, INTREG, INTREG, AVR32_V2),
27572 +    SYNTAX_NORMAL3(SUB2LE, SUBLE, SUB2LE, INTREG, INTREG, INTREG, AVR32_V2),
27573 +    SYNTAX_NORMAL3(SUB2HI, SUBHI, SUB2HI, INTREG, INTREG, INTREG, AVR32_V2),
27574 +    SYNTAX_NORMAL3(SUB2VS, SUBVS, SUB2VS, INTREG, INTREG, INTREG, AVR32_V2),
27575 +    SYNTAX_NORMAL3(SUB2VC, SUBVC, SUB2VC, INTREG, INTREG, INTREG, AVR32_V2),
27576 +    SYNTAX_NORMAL3(SUB2QS, SUBQS, SUB2QS, INTREG, INTREG, INTREG, AVR32_V2),
27577 +    SYNTAX_NORMAL3(SUB2AL, SUBAL, SUB2AL, INTREG, INTREG, INTREG, AVR32_V2),
27578 +    SYNTAX_NORMAL3(SUB2HS, SUBHS, SUB2CC, INTREG, INTREG, INTREG, AVR32_V2),
27579 +    SYNTAX_NORMAL3(SUB2LO, SUBLO, SUB2CS, INTREG, INTREG, INTREG, AVR32_V2),
27580 +    SYNTAX_NORMAL3(ANDEQ, ANDEQ, ANDEQ, INTREG, INTREG, INTREG, AVR32_V2),
27581 +    SYNTAX_NORMAL3(ANDNE, ANDNE, ANDNE, INTREG, INTREG, INTREG, AVR32_V2),
27582 +    SYNTAX_NORMAL3(ANDCC, ANDCC, ANDCC, INTREG, INTREG, INTREG, AVR32_V2),
27583 +    SYNTAX_NORMAL3(ANDCS, ANDCS, ANDCS, INTREG, INTREG, INTREG, AVR32_V2),
27584 +    SYNTAX_NORMAL3(ANDGE, ANDGE, ANDGE, INTREG, INTREG, INTREG, AVR32_V2),
27585 +    SYNTAX_NORMAL3(ANDLT, ANDLT, ANDLT, INTREG, INTREG, INTREG, AVR32_V2),
27586 +    SYNTAX_NORMAL3(ANDMI, ANDMI, ANDMI, INTREG, INTREG, INTREG, AVR32_V2),
27587 +    SYNTAX_NORMAL3(ANDPL, ANDPL, ANDPL, INTREG, INTREG, INTREG, AVR32_V2),
27588 +    SYNTAX_NORMAL3(ANDLS, ANDLS, ANDLS, INTREG, INTREG, INTREG, AVR32_V2),
27589 +    SYNTAX_NORMAL3(ANDGT, ANDGT, ANDGT, INTREG, INTREG, INTREG, AVR32_V2),
27590 +    SYNTAX_NORMAL3(ANDLE, ANDLE, ANDLE, INTREG, INTREG, INTREG, AVR32_V2),
27591 +    SYNTAX_NORMAL3(ANDHI, ANDHI, ANDHI, INTREG, INTREG, INTREG, AVR32_V2),
27592 +    SYNTAX_NORMAL3(ANDVS, ANDVS, ANDVS, INTREG, INTREG, INTREG, AVR32_V2),
27593 +    SYNTAX_NORMAL3(ANDVC, ANDVC, ANDVC, INTREG, INTREG, INTREG, AVR32_V2),
27594 +    SYNTAX_NORMAL3(ANDQS, ANDQS, ANDQS, INTREG, INTREG, INTREG, AVR32_V2),
27595 +    SYNTAX_NORMAL3(ANDAL, ANDAL, ANDAL, INTREG, INTREG, INTREG, AVR32_V2),
27596 +    SYNTAX_NORMAL3(ANDHS, ANDHS, ANDCC, INTREG, INTREG, INTREG, AVR32_V2),
27597 +    SYNTAX_NORMAL3(ANDLO, ANDLO, ANDCS, INTREG, INTREG, INTREG, AVR32_V2),
27598 +    SYNTAX_NORMAL3(OREQ, OREQ, OREQ, INTREG, INTREG, INTREG, AVR32_V2),
27599 +    SYNTAX_NORMAL3(ORNE, ORNE, ORNE, INTREG, INTREG, INTREG, AVR32_V2),
27600 +    SYNTAX_NORMAL3(ORCC, ORCC, ORCC, INTREG, INTREG, INTREG, AVR32_V2),
27601 +    SYNTAX_NORMAL3(ORCS, ORCS, ORCS, INTREG, INTREG, INTREG, AVR32_V2),
27602 +    SYNTAX_NORMAL3(ORGE, ORGE, ORGE, INTREG, INTREG, INTREG, AVR32_V2),
27603 +    SYNTAX_NORMAL3(ORLT, ORLT, ORLT, INTREG, INTREG, INTREG, AVR32_V2),
27604 +    SYNTAX_NORMAL3(ORMI, ORMI, ORMI, INTREG, INTREG, INTREG, AVR32_V2),
27605 +    SYNTAX_NORMAL3(ORPL, ORPL, ORPL, INTREG, INTREG, INTREG, AVR32_V2),
27606 +    SYNTAX_NORMAL3(ORLS, ORLS, ORLS, INTREG, INTREG, INTREG, AVR32_V2),
27607 +    SYNTAX_NORMAL3(ORGT, ORGT, ORGT, INTREG, INTREG, INTREG, AVR32_V2),
27608 +    SYNTAX_NORMAL3(ORLE, ORLE, ORLE, INTREG, INTREG, INTREG, AVR32_V2),
27609 +    SYNTAX_NORMAL3(ORHI, ORHI, ORHI, INTREG, INTREG, INTREG, AVR32_V2),
27610 +    SYNTAX_NORMAL3(ORVS, ORVS, ORVS, INTREG, INTREG, INTREG, AVR32_V2),
27611 +    SYNTAX_NORMAL3(ORVC, ORVC, ORVC, INTREG, INTREG, INTREG, AVR32_V2),
27612 +    SYNTAX_NORMAL3(ORQS, ORQS, ORQS, INTREG, INTREG, INTREG, AVR32_V2),
27613 +    SYNTAX_NORMAL3(ORAL, ORAL, ORAL, INTREG, INTREG, INTREG, AVR32_V2),
27614 +    SYNTAX_NORMAL3(ORHS, ORHS, ORCC, INTREG, INTREG, INTREG, AVR32_V2),
27615 +    SYNTAX_NORMAL3(ORLO, ORLO, ORCS, INTREG, INTREG, INTREG, AVR32_V2),
27616 +    SYNTAX_NORMAL3(EOREQ, EOREQ, EOREQ, INTREG, INTREG, INTREG, AVR32_V2),
27617 +    SYNTAX_NORMAL3(EORNE, EORNE, EORNE, INTREG, INTREG, INTREG, AVR32_V2),
27618 +    SYNTAX_NORMAL3(EORCC, EORCC, EORCC, INTREG, INTREG, INTREG, AVR32_V2),
27619 +    SYNTAX_NORMAL3(EORCS, EORCS, EORCS, INTREG, INTREG, INTREG, AVR32_V2),
27620 +    SYNTAX_NORMAL3(EORGE, EORGE, EORGE, INTREG, INTREG, INTREG, AVR32_V2),
27621 +    SYNTAX_NORMAL3(EORLT, EORLT, EORLT, INTREG, INTREG, INTREG, AVR32_V2),
27622 +    SYNTAX_NORMAL3(EORMI, EORMI, EORMI, INTREG, INTREG, INTREG, AVR32_V2),
27623 +    SYNTAX_NORMAL3(EORPL, EORPL, EORPL, INTREG, INTREG, INTREG, AVR32_V2),
27624 +    SYNTAX_NORMAL3(EORLS, EORLS, EORLS, INTREG, INTREG, INTREG, AVR32_V2),
27625 +    SYNTAX_NORMAL3(EORGT, EORGT, EORGT, INTREG, INTREG, INTREG, AVR32_V2),
27626 +    SYNTAX_NORMAL3(EORLE, EORLE, EORLE, INTREG, INTREG, INTREG, AVR32_V2),
27627 +    SYNTAX_NORMAL3(EORHI, EORHI, EORHI, INTREG, INTREG, INTREG, AVR32_V2),
27628 +    SYNTAX_NORMAL3(EORVS, EORVS, EORVS, INTREG, INTREG, INTREG, AVR32_V2),
27629 +    SYNTAX_NORMAL3(EORVC, EORVC, EORVC, INTREG, INTREG, INTREG, AVR32_V2),
27630 +    SYNTAX_NORMAL3(EORQS, EORQS, EORQS, INTREG, INTREG, INTREG, AVR32_V2),
27631 +    SYNTAX_NORMAL3(EORAL, EORAL, EORAL, INTREG, INTREG, INTREG, AVR32_V2),
27632 +    SYNTAX_NORMAL3(EORHS, EORHS, EORCC, INTREG, INTREG, INTREG, AVR32_V2),
27633 +    SYNTAX_NORMAL3(EORLO, EORLO, EORCS, INTREG, INTREG, INTREG, AVR32_V2),
27634 +    SYNTAX_NORMAL2(LD_WEQ, LD_WEQ, LD_WEQ, INTREG, INTREG_UDISP_W, AVR32_V2),
27635 +    SYNTAX_NORMAL2(LD_WNE, LD_WNE, LD_WNE, INTREG, INTREG_UDISP_W, AVR32_V2),
27636 +    SYNTAX_NORMAL2(LD_WCC, LD_WCC, LD_WCC, INTREG, INTREG_UDISP_W, AVR32_V2),
27637 +    SYNTAX_NORMAL2(LD_WCS, LD_WCS, LD_WCS, INTREG, INTREG_UDISP_W, AVR32_V2),
27638 +    SYNTAX_NORMAL2(LD_WGE, LD_WGE, LD_WGE, INTREG, INTREG_UDISP_W, AVR32_V2),
27639 +    SYNTAX_NORMAL2(LD_WLT, LD_WLT, LD_WLT, INTREG, INTREG_UDISP_W, AVR32_V2),
27640 +    SYNTAX_NORMAL2(LD_WMI, LD_WMI, LD_WMI, INTREG, INTREG_UDISP_W, AVR32_V2),
27641 +    SYNTAX_NORMAL2(LD_WPL, LD_WPL, LD_WPL, INTREG, INTREG_UDISP_W, AVR32_V2),
27642 +    SYNTAX_NORMAL2(LD_WLS, LD_WLS, LD_WLS, INTREG, INTREG_UDISP_W, AVR32_V2),
27643 +    SYNTAX_NORMAL2(LD_WGT, LD_WGT, LD_WGT, INTREG, INTREG_UDISP_W, AVR32_V2),
27644 +    SYNTAX_NORMAL2(LD_WLE, LD_WLE, LD_WLE, INTREG, INTREG_UDISP_W, AVR32_V2),
27645 +    SYNTAX_NORMAL2(LD_WHI, LD_WHI, LD_WHI, INTREG, INTREG_UDISP_W, AVR32_V2),
27646 +    SYNTAX_NORMAL2(LD_WVS, LD_WVS, LD_WVS, INTREG, INTREG_UDISP_W, AVR32_V2),
27647 +    SYNTAX_NORMAL2(LD_WVC, LD_WVC, LD_WVC, INTREG, INTREG_UDISP_W, AVR32_V2),
27648 +    SYNTAX_NORMAL2(LD_WQS, LD_WQS, LD_WQS, INTREG, INTREG_UDISP_W, AVR32_V2),
27649 +    SYNTAX_NORMAL2(LD_WAL, LD_WAL, LD_WAL, INTREG, INTREG_UDISP_W, AVR32_V2),
27650 +    SYNTAX_NORMAL2(LD_WHS, LD_WHS, LD_WCC, INTREG, INTREG_UDISP_W, AVR32_V2),
27651 +    SYNTAX_NORMAL2(LD_WLO, LD_WLO, LD_WCS, INTREG, INTREG_UDISP_W, AVR32_V2),
27652 +    SYNTAX_NORMAL2(LD_SHEQ, LD_SHEQ, LD_SHEQ, INTREG, INTREG_UDISP_H, AVR32_V2),
27653 +    SYNTAX_NORMAL2(LD_SHNE, LD_SHNE, LD_SHNE, INTREG, INTREG_UDISP_H, AVR32_V2),
27654 +    SYNTAX_NORMAL2(LD_SHCC, LD_SHCC, LD_SHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27655 +    SYNTAX_NORMAL2(LD_SHCS, LD_SHCS, LD_SHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27656 +    SYNTAX_NORMAL2(LD_SHGE, LD_SHGE, LD_SHGE, INTREG, INTREG_UDISP_H, AVR32_V2),
27657 +    SYNTAX_NORMAL2(LD_SHLT, LD_SHLT, LD_SHLT, INTREG, INTREG_UDISP_H, AVR32_V2),
27658 +    SYNTAX_NORMAL2(LD_SHMI, LD_SHMI, LD_SHMI, INTREG, INTREG_UDISP_H, AVR32_V2),
27659 +    SYNTAX_NORMAL2(LD_SHPL, LD_SHPL, LD_SHPL, INTREG, INTREG_UDISP_H, AVR32_V2),
27660 +    SYNTAX_NORMAL2(LD_SHLS, LD_SHLS, LD_SHLS, INTREG, INTREG_UDISP_H, AVR32_V2),
27661 +    SYNTAX_NORMAL2(LD_SHGT, LD_SHGT, LD_SHGT, INTREG, INTREG_UDISP_H, AVR32_V2),
27662 +    SYNTAX_NORMAL2(LD_SHLE, LD_SHLE, LD_SHLE, INTREG, INTREG_UDISP_H, AVR32_V2),
27663 +    SYNTAX_NORMAL2(LD_SHHI, LD_SHHI, LD_SHHI, INTREG, INTREG_UDISP_H, AVR32_V2),
27664 +    SYNTAX_NORMAL2(LD_SHVS, LD_SHVS, LD_SHVS, INTREG, INTREG_UDISP_H, AVR32_V2),
27665 +    SYNTAX_NORMAL2(LD_SHVC, LD_SHVC, LD_SHVC, INTREG, INTREG_UDISP_H, AVR32_V2),
27666 +    SYNTAX_NORMAL2(LD_SHQS, LD_SHQS, LD_SHQS, INTREG, INTREG_UDISP_H, AVR32_V2),
27667 +    SYNTAX_NORMAL2(LD_SHAL, LD_SHAL, LD_SHAL, INTREG, INTREG_UDISP_H, AVR32_V2),
27668 +    SYNTAX_NORMAL2(LD_SHHS, LD_SHHS, LD_SHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27669 +    SYNTAX_NORMAL2(LD_SHLO, LD_SHLO, LD_SHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27670 +    SYNTAX_NORMAL2(LD_UHEQ, LD_UHEQ, LD_UHEQ, INTREG, INTREG_UDISP_H, AVR32_V2),
27671 +    SYNTAX_NORMAL2(LD_UHNE, LD_UHNE, LD_UHNE, INTREG, INTREG_UDISP_H, AVR32_V2),
27672 +    SYNTAX_NORMAL2(LD_UHCC, LD_UHCC, LD_UHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27673 +    SYNTAX_NORMAL2(LD_UHCS, LD_UHCS, LD_UHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27674 +    SYNTAX_NORMAL2(LD_UHGE, LD_UHGE, LD_UHGE, INTREG, INTREG_UDISP_H, AVR32_V2),
27675 +    SYNTAX_NORMAL2(LD_UHLT, LD_UHLT, LD_UHLT, INTREG, INTREG_UDISP_H, AVR32_V2),
27676 +    SYNTAX_NORMAL2(LD_UHMI, LD_UHMI, LD_UHMI, INTREG, INTREG_UDISP_H, AVR32_V2),
27677 +    SYNTAX_NORMAL2(LD_UHPL, LD_UHPL, LD_UHPL, INTREG, INTREG_UDISP_H, AVR32_V2),
27678 +    SYNTAX_NORMAL2(LD_UHLS, LD_UHLS, LD_UHLS, INTREG, INTREG_UDISP_H, AVR32_V2),
27679 +    SYNTAX_NORMAL2(LD_UHGT, LD_UHGT, LD_UHGT, INTREG, INTREG_UDISP_H, AVR32_V2),
27680 +    SYNTAX_NORMAL2(LD_UHLE, LD_UHLE, LD_UHLE, INTREG, INTREG_UDISP_H, AVR32_V2),
27681 +    SYNTAX_NORMAL2(LD_UHHI, LD_UHHI, LD_UHHI, INTREG, INTREG_UDISP_H, AVR32_V2),
27682 +    SYNTAX_NORMAL2(LD_UHVS, LD_UHVS, LD_UHVS, INTREG, INTREG_UDISP_H, AVR32_V2),
27683 +    SYNTAX_NORMAL2(LD_UHVC, LD_UHVC, LD_UHVC, INTREG, INTREG_UDISP_H, AVR32_V2),
27684 +    SYNTAX_NORMAL2(LD_UHQS, LD_UHQS, LD_UHQS, INTREG, INTREG_UDISP_H, AVR32_V2),
27685 +    SYNTAX_NORMAL2(LD_UHAL, LD_UHAL, LD_UHAL, INTREG, INTREG_UDISP_H, AVR32_V2),
27686 +    SYNTAX_NORMAL2(LD_UHHS, LD_UHHS, LD_UHCC, INTREG, INTREG_UDISP_H, AVR32_V2),
27687 +    SYNTAX_NORMAL2(LD_UHLO, LD_UHLO, LD_UHCS, INTREG, INTREG_UDISP_H, AVR32_V2),
27688 +    SYNTAX_NORMAL2(LD_SBEQ, LD_SBEQ, LD_SBEQ, INTREG, INTREG_UDISP, AVR32_V2),
27689 +    SYNTAX_NORMAL2(LD_SBNE, LD_SBNE, LD_SBNE, INTREG, INTREG_UDISP, AVR32_V2),
27690 +    SYNTAX_NORMAL2(LD_SBCC, LD_SBCC, LD_SBCC, INTREG, INTREG_UDISP, AVR32_V2),
27691 +    SYNTAX_NORMAL2(LD_SBCS, LD_SBCS, LD_SBCS, INTREG, INTREG_UDISP, AVR32_V2),
27692 +    SYNTAX_NORMAL2(LD_SBGE, LD_SBGE, LD_SBGE, INTREG, INTREG_UDISP, AVR32_V2),
27693 +    SYNTAX_NORMAL2(LD_SBLT, LD_SBLT, LD_SBLT, INTREG, INTREG_UDISP, AVR32_V2),
27694 +    SYNTAX_NORMAL2(LD_SBMI, LD_SBMI, LD_SBMI, INTREG, INTREG_UDISP, AVR32_V2),
27695 +    SYNTAX_NORMAL2(LD_SBPL, LD_SBPL, LD_SBPL, INTREG, INTREG_UDISP, AVR32_V2),
27696 +    SYNTAX_NORMAL2(LD_SBLS, LD_SBLS, LD_SBLS, INTREG, INTREG_UDISP, AVR32_V2),
27697 +    SYNTAX_NORMAL2(LD_SBGT, LD_SBGT, LD_SBGT, INTREG, INTREG_UDISP, AVR32_V2),
27698 +    SYNTAX_NORMAL2(LD_SBLE, LD_SBLE, LD_SBLE, INTREG, INTREG_UDISP, AVR32_V2),
27699 +    SYNTAX_NORMAL2(LD_SBHI, LD_SBHI, LD_SBHI, INTREG, INTREG_UDISP, AVR32_V2),
27700 +    SYNTAX_NORMAL2(LD_SBVS, LD_SBVS, LD_SBVS, INTREG, INTREG_UDISP, AVR32_V2),
27701 +    SYNTAX_NORMAL2(LD_SBVC, LD_SBVC, LD_SBVC, INTREG, INTREG_UDISP, AVR32_V2),
27702 +    SYNTAX_NORMAL2(LD_SBQS, LD_SBQS, LD_SBQS, INTREG, INTREG_UDISP, AVR32_V2),
27703 +    SYNTAX_NORMAL2(LD_SBAL, LD_SBAL, LD_SBAL, INTREG, INTREG_UDISP, AVR32_V2),
27704 +    SYNTAX_NORMAL2(LD_SBHS, LD_SBHS, LD_SBCC, INTREG, INTREG_UDISP, AVR32_V2),
27705 +    SYNTAX_NORMAL2(LD_SBLO, LD_SBLO, LD_SBCS, INTREG, INTREG_UDISP, AVR32_V2),
27706 +    SYNTAX_NORMAL2(LD_UBEQ, LD_UBEQ, LD_UBEQ, INTREG, INTREG_UDISP, AVR32_V2),
27707 +    SYNTAX_NORMAL2(LD_UBNE, LD_UBNE, LD_UBNE, INTREG, INTREG_UDISP, AVR32_V2),
27708 +    SYNTAX_NORMAL2(LD_UBCC, LD_UBCC, LD_UBCC, INTREG, INTREG_UDISP, AVR32_V2),
27709 +    SYNTAX_NORMAL2(LD_UBCS, LD_UBCS, LD_UBCS, INTREG, INTREG_UDISP, AVR32_V2),
27710 +    SYNTAX_NORMAL2(LD_UBGE, LD_UBGE, LD_UBGE, INTREG, INTREG_UDISP, AVR32_V2),
27711 +    SYNTAX_NORMAL2(LD_UBLT, LD_UBLT, LD_UBLT, INTREG, INTREG_UDISP, AVR32_V2),
27712 +    SYNTAX_NORMAL2(LD_UBMI, LD_UBMI, LD_UBMI, INTREG, INTREG_UDISP, AVR32_V2),
27713 +    SYNTAX_NORMAL2(LD_UBPL, LD_UBPL, LD_UBPL, INTREG, INTREG_UDISP, AVR32_V2),
27714 +    SYNTAX_NORMAL2(LD_UBLS, LD_UBLS, LD_UBLS, INTREG, INTREG_UDISP, AVR32_V2),
27715 +    SYNTAX_NORMAL2(LD_UBGT, LD_UBGT, LD_UBGT, INTREG, INTREG_UDISP, AVR32_V2),
27716 +    SYNTAX_NORMAL2(LD_UBLE, LD_UBLE, LD_UBLE, INTREG, INTREG_UDISP, AVR32_V2),
27717 +    SYNTAX_NORMAL2(LD_UBHI, LD_UBHI, LD_UBHI, INTREG, INTREG_UDISP, AVR32_V2),
27718 +    SYNTAX_NORMAL2(LD_UBVS, LD_UBVS, LD_UBVS, INTREG, INTREG_UDISP, AVR32_V2),
27719 +    SYNTAX_NORMAL2(LD_UBVC, LD_UBVC, LD_UBVC, INTREG, INTREG_UDISP, AVR32_V2),
27720 +    SYNTAX_NORMAL2(LD_UBQS, LD_UBQS, LD_UBQS, INTREG, INTREG_UDISP, AVR32_V2),
27721 +    SYNTAX_NORMAL2(LD_UBAL, LD_UBAL, LD_UBAL, INTREG, INTREG_UDISP, AVR32_V2),
27722 +    SYNTAX_NORMAL2(LD_UBHS, LD_UBHS, LD_UBCC, INTREG, INTREG_UDISP, AVR32_V2),
27723 +    SYNTAX_NORMAL2(LD_UBLO, LD_UBLO, LD_UBCS, INTREG, INTREG_UDISP, AVR32_V2),
27724 +    SYNTAX_NORMAL2(ST_WEQ, ST_WEQ, ST_WEQ, INTREG_UDISP_W, INTREG, AVR32_V2),
27725 +    SYNTAX_NORMAL2(ST_WNE, ST_WNE, ST_WNE, INTREG_UDISP_W, INTREG, AVR32_V2),
27726 +    SYNTAX_NORMAL2(ST_WCC, ST_WCC, ST_WCC, INTREG_UDISP_W, INTREG, AVR32_V2),
27727 +    SYNTAX_NORMAL2(ST_WCS, ST_WCS, ST_WCS, INTREG_UDISP_W, INTREG, AVR32_V2),
27728 +    SYNTAX_NORMAL2(ST_WGE, ST_WGE, ST_WGE, INTREG_UDISP_W, INTREG, AVR32_V2),
27729 +    SYNTAX_NORMAL2(ST_WLT, ST_WLT, ST_WLT, INTREG_UDISP_W, INTREG, AVR32_V2),
27730 +    SYNTAX_NORMAL2(ST_WMI, ST_WMI, ST_WMI, INTREG_UDISP_W, INTREG, AVR32_V2),
27731 +    SYNTAX_NORMAL2(ST_WPL, ST_WPL, ST_WPL, INTREG_UDISP_W, INTREG, AVR32_V2),
27732 +    SYNTAX_NORMAL2(ST_WLS, ST_WLS, ST_WLS, INTREG_UDISP_W, INTREG, AVR32_V2),
27733 +    SYNTAX_NORMAL2(ST_WGT, ST_WGT, ST_WGT, INTREG_UDISP_W, INTREG, AVR32_V2),
27734 +    SYNTAX_NORMAL2(ST_WLE, ST_WLE, ST_WLE, INTREG_UDISP_W, INTREG, AVR32_V2),
27735 +    SYNTAX_NORMAL2(ST_WHI, ST_WHI, ST_WHI, INTREG_UDISP_W, INTREG, AVR32_V2),
27736 +    SYNTAX_NORMAL2(ST_WVS, ST_WVS, ST_WVS, INTREG_UDISP_W, INTREG, AVR32_V2),
27737 +    SYNTAX_NORMAL2(ST_WVC, ST_WVC, ST_WVC, INTREG_UDISP_W, INTREG, AVR32_V2),
27738 +    SYNTAX_NORMAL2(ST_WQS, ST_WQS, ST_WQS, INTREG_UDISP_W, INTREG, AVR32_V2),
27739 +    SYNTAX_NORMAL2(ST_WAL, ST_WAL, ST_WAL, INTREG_UDISP_W, INTREG, AVR32_V2),
27740 +    SYNTAX_NORMAL2(ST_WHS, ST_WHS, ST_WCC, INTREG_UDISP_W, INTREG, AVR32_V2),
27741 +    SYNTAX_NORMAL2(ST_WLO, ST_WLO, ST_WCS, INTREG_UDISP_W, INTREG, AVR32_V2),
27742 +    SYNTAX_NORMAL2(ST_HEQ, ST_HEQ, ST_HEQ, INTREG_UDISP_H, INTREG, AVR32_V2),
27743 +    SYNTAX_NORMAL2(ST_HNE, ST_HNE, ST_HNE, INTREG_UDISP_H, INTREG, AVR32_V2),
27744 +    SYNTAX_NORMAL2(ST_HCC, ST_HCC, ST_HCC, INTREG_UDISP_H, INTREG, AVR32_V2),
27745 +    SYNTAX_NORMAL2(ST_HCS, ST_HCS, ST_HCS, INTREG_UDISP_H, INTREG, AVR32_V2),
27746 +    SYNTAX_NORMAL2(ST_HGE, ST_HGE, ST_HGE, INTREG_UDISP_H, INTREG, AVR32_V2),
27747 +    SYNTAX_NORMAL2(ST_HLT, ST_HLT, ST_HLT, INTREG_UDISP_H, INTREG, AVR32_V2),
27748 +    SYNTAX_NORMAL2(ST_HMI, ST_HMI, ST_HMI, INTREG_UDISP_H, INTREG, AVR32_V2),
27749 +    SYNTAX_NORMAL2(ST_HPL, ST_HPL, ST_HPL, INTREG_UDISP_H, INTREG, AVR32_V2),
27750 +    SYNTAX_NORMAL2(ST_HLS, ST_HLS, ST_HLS, INTREG_UDISP_H, INTREG, AVR32_V2),
27751 +    SYNTAX_NORMAL2(ST_HGT, ST_HGT, ST_HGT, INTREG_UDISP_H, INTREG, AVR32_V2),
27752 +    SYNTAX_NORMAL2(ST_HLE, ST_HLE, ST_HLE, INTREG_UDISP_H, INTREG, AVR32_V2),
27753 +    SYNTAX_NORMAL2(ST_HHI, ST_HHI, ST_HHI, INTREG_UDISP_H, INTREG, AVR32_V2),
27754 +    SYNTAX_NORMAL2(ST_HVS, ST_HVS, ST_HVS, INTREG_UDISP_H, INTREG, AVR32_V2),
27755 +    SYNTAX_NORMAL2(ST_HVC, ST_HVC, ST_HVC, INTREG_UDISP_H, INTREG, AVR32_V2),
27756 +    SYNTAX_NORMAL2(ST_HQS, ST_HQS, ST_HQS, INTREG_UDISP_H, INTREG, AVR32_V2),
27757 +    SYNTAX_NORMAL2(ST_HAL, ST_HAL, ST_HAL, INTREG_UDISP_H, INTREG, AVR32_V2),
27758 +    SYNTAX_NORMAL2(ST_HHS, ST_HHS, ST_HCC, INTREG_UDISP_H, INTREG, AVR32_V2),
27759 +    SYNTAX_NORMAL2(ST_HLO, ST_HLO, ST_HCS, INTREG_UDISP_H, INTREG, AVR32_V2),
27760 +    SYNTAX_NORMAL2(ST_BEQ, ST_BEQ, ST_BEQ, INTREG_UDISP, INTREG, AVR32_V2),
27761 +    SYNTAX_NORMAL2(ST_BNE, ST_BNE, ST_BNE, INTREG_UDISP, INTREG, AVR32_V2),
27762 +    SYNTAX_NORMAL2(ST_BCC, ST_BCC, ST_BCC, INTREG_UDISP, INTREG, AVR32_V2),
27763 +    SYNTAX_NORMAL2(ST_BCS, ST_BCS, ST_BCS, INTREG_UDISP, INTREG, AVR32_V2),
27764 +    SYNTAX_NORMAL2(ST_BGE, ST_BGE, ST_BGE, INTREG_UDISP, INTREG, AVR32_V2),
27765 +    SYNTAX_NORMAL2(ST_BLT, ST_BLT, ST_BLT, INTREG_UDISP, INTREG, AVR32_V2),
27766 +    SYNTAX_NORMAL2(ST_BMI, ST_BMI, ST_BMI, INTREG_UDISP, INTREG, AVR32_V2),
27767 +    SYNTAX_NORMAL2(ST_BPL, ST_BPL, ST_BPL, INTREG_UDISP, INTREG, AVR32_V2),
27768 +    SYNTAX_NORMAL2(ST_BLS, ST_BLS, ST_BLS, INTREG_UDISP, INTREG, AVR32_V2),
27769 +    SYNTAX_NORMAL2(ST_BGT, ST_BGT, ST_BGT, INTREG_UDISP, INTREG, AVR32_V2),
27770 +    SYNTAX_NORMAL2(ST_BLE, ST_BLE, ST_BLE, INTREG_UDISP, INTREG, AVR32_V2),
27771 +    SYNTAX_NORMAL2(ST_BHI, ST_BHI, ST_BHI, INTREG_UDISP, INTREG, AVR32_V2),
27772 +    SYNTAX_NORMAL2(ST_BVS, ST_BVS, ST_BVS, INTREG_UDISP, INTREG, AVR32_V2),
27773 +    SYNTAX_NORMAL2(ST_BVC, ST_BVC, ST_BVC, INTREG_UDISP, INTREG, AVR32_V2),
27774 +    SYNTAX_NORMAL2(ST_BQS, ST_BQS, ST_BQS, INTREG_UDISP, INTREG, AVR32_V2),
27775 +    SYNTAX_NORMAL2(ST_BAL, ST_BAL, ST_BAL, INTREG_UDISP, INTREG, AVR32_V2),
27776 +    SYNTAX_NORMAL2(ST_BHS, ST_BHS, ST_BCC, INTREG_UDISP, INTREG, AVR32_V2),
27777 +    SYNTAX_NORMAL2(ST_BLO, ST_BLO, ST_BCS, INTREG_UDISP, INTREG, AVR32_V2),
27778 +    SYNTAX_NORMAL2(MOVH, MOVH, MOVH, INTREG, UNSIGNED_CONST, AVR32_V2),
27779 +
27780 +  };
27781 +
27782 +#define NORMAL_MNEMONIC(name, syntax, str)             \
27783 +  {                                                    \
27784 +    AVR32_MNEMONIC_##name, str,                                \
27785 +    &avr32_syntax_table[AVR32_SYNTAX_##syntax],                \
27786 +  }
27787 +#define FP_MNEMONIC(name, syntax, str)                 \
27788 +  NORMAL_MNEMONIC(name##_S, syntax##_S, str ".s"),     \
27789 +  NORMAL_MNEMONIC(name##_D, syntax##_D, str ".d")
27790 +
27791 +const struct avr32_mnemonic avr32_mnemonic_table[] =
27792 +  {
27793 +    NORMAL_MNEMONIC(ABS, ABS, "abs"),
27794 +    NORMAL_MNEMONIC(ACALL, ACALL, "acall"),
27795 +    NORMAL_MNEMONIC(ACR, ACR, "acr"),
27796 +    NORMAL_MNEMONIC(ADC, ADC, "adc"),
27797 +    NORMAL_MNEMONIC(ADD, ADD1, "add"),
27798 +    NORMAL_MNEMONIC(ADDABS, ADDABS, "addabs"),
27799 +    NORMAL_MNEMONIC(ADDHH_W, ADDHH_W, "addhh.w"),
27800 +    NORMAL_MNEMONIC(AND, AND1, "and"),
27801 +    NORMAL_MNEMONIC(ANDH, ANDH, "andh"),
27802 +    NORMAL_MNEMONIC(ANDL, ANDL, "andl"),
27803 +    NORMAL_MNEMONIC(ANDN, ANDN, "andn"),
27804 +    NORMAL_MNEMONIC(ASR, ASR1, "asr"),
27805 +    NORMAL_MNEMONIC(BFEXTS, BFEXTS, "bfexts"),
27806 +    NORMAL_MNEMONIC(BFEXTU, BFEXTU, "bfextu"),
27807 +    NORMAL_MNEMONIC(BFINS, BFINS, "bfins"),
27808 +    NORMAL_MNEMONIC(BLD, BLD, "bld"),
27809 +    NORMAL_MNEMONIC(BREQ, BREQ1, "breq"),
27810 +    NORMAL_MNEMONIC(BRNE, BRNE1, "brne"),
27811 +    NORMAL_MNEMONIC(BRCC, BRCC1, "brcc"),
27812 +    NORMAL_MNEMONIC(BRCS, BRCS1, "brcs"),
27813 +    NORMAL_MNEMONIC(BRGE, BRGE1, "brge"),
27814 +    NORMAL_MNEMONIC(BRLT, BRLT1, "brlt"),
27815 +    NORMAL_MNEMONIC(BRMI, BRMI1, "brmi"),
27816 +    NORMAL_MNEMONIC(BRPL, BRPL1, "brpl"),
27817 +    NORMAL_MNEMONIC(BRHS, BRHS1, "brhs"),
27818 +    NORMAL_MNEMONIC(BRLO, BRLO1, "brlo"),
27819 +    NORMAL_MNEMONIC(BRLS, BRLS, "brls"),
27820 +    NORMAL_MNEMONIC(BRGT, BRGT, "brgt"),
27821 +    NORMAL_MNEMONIC(BRLE, BRLE, "brle"),
27822 +    NORMAL_MNEMONIC(BRHI, BRHI, "brhi"),
27823 +    NORMAL_MNEMONIC(BRVS, BRVS, "brvs"),
27824 +    NORMAL_MNEMONIC(BRVC, BRVC, "brvc"),
27825 +    NORMAL_MNEMONIC(BRQS, BRQS, "brqs"),
27826 +    NORMAL_MNEMONIC(BRAL, BRAL, "bral"),
27827 +    NORMAL_MNEMONIC(BREAKPOINT, BREAKPOINT, "breakpoint"),
27828 +    NORMAL_MNEMONIC(BREV, BREV, "brev"),
27829 +    NORMAL_MNEMONIC(BST, BST, "bst"),
27830 +    NORMAL_MNEMONIC(CACHE, CACHE, "cache"),
27831 +    NORMAL_MNEMONIC(CASTS_B, CASTS_B, "casts.b"),
27832 +    NORMAL_MNEMONIC(CASTS_H, CASTS_H, "casts.h"),
27833 +    NORMAL_MNEMONIC(CASTU_B, CASTU_B, "castu.b"),
27834 +    NORMAL_MNEMONIC(CASTU_H, CASTU_H, "castu.h"),
27835 +    NORMAL_MNEMONIC(CBR, CBR, "cbr"),
27836 +    NORMAL_MNEMONIC(CLZ, CLZ, "clz"),
27837 +    NORMAL_MNEMONIC(COM, COM, "com"),
27838 +    NORMAL_MNEMONIC(COP, COP, "cop"),
27839 +    NORMAL_MNEMONIC(CP_B, CP_B, "cp.b"),
27840 +    NORMAL_MNEMONIC(CP_H, CP_H, "cp.h"),
27841 +    NORMAL_MNEMONIC(CP_W, CP_W1, "cp.w"),
27842 +    NORMAL_MNEMONIC(CP, CP_W1, "cp"),
27843 +    NORMAL_MNEMONIC(CPC, CPC1, "cpc"),
27844 +    NORMAL_MNEMONIC(CSRF, CSRF, "csrf"),
27845 +    NORMAL_MNEMONIC(CSRFCZ, CSRFCZ, "csrfcz"),
27846 +    NORMAL_MNEMONIC(DIVS, DIVS, "divs"),
27847 +    NORMAL_MNEMONIC(DIVU, DIVU, "divu"),
27848 +    NORMAL_MNEMONIC(EOR, EOR1, "eor"),
27849 +    NORMAL_MNEMONIC(EORL, EORL, "eorl"),
27850 +    NORMAL_MNEMONIC(EORH, EORH, "eorh"),
27851 +    NORMAL_MNEMONIC(FRS, FRS, "frs"),
27852 +    NORMAL_MNEMONIC(SSCALL, SSCALL, "sscall"),
27853 +    NORMAL_MNEMONIC(RETSS, RETSS, "retss"),
27854 +    NORMAL_MNEMONIC(ICALL, ICALL, "icall"),
27855 +    NORMAL_MNEMONIC(INCJOSP, INCJOSP, "incjosp"),
27856 +    NORMAL_MNEMONIC(LD_D, LD_D1, "ld.d"),
27857 +    NORMAL_MNEMONIC(LD_SB, LD_SB2, "ld.sb"),
27858 +    NORMAL_MNEMONIC(LD_UB, LD_UB1, "ld.ub"),
27859 +    NORMAL_MNEMONIC(LD_SH, LD_SH1, "ld.sh"),
27860 +    NORMAL_MNEMONIC(LD_UH, LD_UH1, "ld.uh"),
27861 +    NORMAL_MNEMONIC(LD_W, LD_W1, "ld.w"),
27862 +    NORMAL_MNEMONIC(LDC_D, LDC_D3, "ldc.d"),
27863 +    NORMAL_MNEMONIC(LDC_W, LDC_W3, "ldc.w"),
27864 +    NORMAL_MNEMONIC(LDC0_D, LDC0_D, "ldc0.d"),
27865 +    NORMAL_MNEMONIC(LDC0_W, LDC0_W, "ldc0.w"),
27866 +    NORMAL_MNEMONIC(LDCM_D, LDCM_D, "ldcm.d"),
27867 +    NORMAL_MNEMONIC(LDCM_W, LDCM_W, "ldcm.w"),
27868 +    NORMAL_MNEMONIC(LDDPC, LDDPC, "lddpc"),
27869 +    NORMAL_MNEMONIC(LDDSP, LDDSP, "lddsp"),
27870 +    NORMAL_MNEMONIC(LDINS_B, LDINS_B, "ldins.b"),
27871 +    NORMAL_MNEMONIC(LDINS_H, LDINS_H, "ldins.h"),
27872 +    NORMAL_MNEMONIC(LDM, LDM, "ldm"),
27873 +    NORMAL_MNEMONIC(LDMTS, LDMTS, "ldmts"),
27874 +    NORMAL_MNEMONIC(LDSWP_SH, LDSWP_SH, "ldswp.sh"),
27875 +    NORMAL_MNEMONIC(LDSWP_UH, LDSWP_UH, "ldswp.uh"),
27876 +    NORMAL_MNEMONIC(LDSWP_W, LDSWP_W, "ldswp.w"),
27877 +    NORMAL_MNEMONIC(LSL, LSL1, "lsl"),
27878 +    NORMAL_MNEMONIC(LSR, LSR1, "lsr"),
27879 +    NORMAL_MNEMONIC(MAC, MAC, "mac"),
27880 +    NORMAL_MNEMONIC(MACHH_D, MACHH_D, "machh.d"),
27881 +    NORMAL_MNEMONIC(MACHH_W, MACHH_W, "machh.w"),
27882 +    NORMAL_MNEMONIC(MACS_D, MACS_D, "macs.d"),
27883 +    NORMAL_MNEMONIC(MACSATHH_W, MACSATHH_W, "macsathh.w"),
27884 +    NORMAL_MNEMONIC(MACU_D, MACUD, "macu.d"),
27885 +    NORMAL_MNEMONIC(MACWH_D, MACWH_D, "macwh.d"),
27886 +    NORMAL_MNEMONIC(MAX, MAX, "max"),
27887 +    NORMAL_MNEMONIC(MCALL, MCALL, "mcall"),
27888 +    NORMAL_MNEMONIC(MFDR, MFDR, "mfdr"),
27889 +    NORMAL_MNEMONIC(MFSR, MFSR, "mfsr"),
27890 +    NORMAL_MNEMONIC(MIN, MIN, "min"),
27891 +    NORMAL_MNEMONIC(MOV, MOV3, "mov"),
27892 +    NORMAL_MNEMONIC(MOVEQ, MOVEQ1, "moveq"),
27893 +    NORMAL_MNEMONIC(MOVNE, MOVNE1, "movne"),
27894 +    NORMAL_MNEMONIC(MOVCC, MOVCC1, "movcc"),
27895 +    NORMAL_MNEMONIC(MOVCS, MOVCS1, "movcs"),
27896 +    NORMAL_MNEMONIC(MOVGE, MOVGE1, "movge"),
27897 +    NORMAL_MNEMONIC(MOVLT, MOVLT1, "movlt"),
27898 +    NORMAL_MNEMONIC(MOVMI, MOVMI1, "movmi"),
27899 +    NORMAL_MNEMONIC(MOVPL, MOVPL1, "movpl"),
27900 +    NORMAL_MNEMONIC(MOVLS, MOVLS1, "movls"),
27901 +    NORMAL_MNEMONIC(MOVGT, MOVGT1, "movgt"),
27902 +    NORMAL_MNEMONIC(MOVLE, MOVLE1, "movle"),
27903 +    NORMAL_MNEMONIC(MOVHI, MOVHI1, "movhi"),
27904 +    NORMAL_MNEMONIC(MOVVS, MOVVS1, "movvs"),
27905 +    NORMAL_MNEMONIC(MOVVC, MOVVC1, "movvc"),
27906 +    NORMAL_MNEMONIC(MOVQS, MOVQS1, "movqs"),
27907 +    NORMAL_MNEMONIC(MOVAL, MOVAL1, "moval"),
27908 +    NORMAL_MNEMONIC(MOVHS, MOVHS1, "movhs"),
27909 +    NORMAL_MNEMONIC(MOVLO, MOVLO1, "movlo"),
27910 +    NORMAL_MNEMONIC(MTDR, MTDR, "mtdr"),
27911 +    NORMAL_MNEMONIC(MTSR, MTSR, "mtsr"),
27912 +    NORMAL_MNEMONIC(MUL, MUL1, "mul"),
27913 +    NORMAL_MNEMONIC(MULHH_W, MULHH_W, "mulhh.w"),
27914 +    NORMAL_MNEMONIC(MULNHH_W, MULNHH_W, "mulnhh.w"),
27915 +    NORMAL_MNEMONIC(MULNWH_D, MULNWH_D, "mulnwh.d"),
27916 +    NORMAL_MNEMONIC(MULS_D, MULSD, "muls.d"),
27917 +    NORMAL_MNEMONIC(MULSATHH_H, MULSATHH_H, "mulsathh.h"),
27918 +    NORMAL_MNEMONIC(MULSATHH_W, MULSATHH_W, "mulsathh.w"),
27919 +    NORMAL_MNEMONIC(MULSATRNDHH_H, MULSATRNDHH_H, "mulsatrndhh.h"),
27920 +    NORMAL_MNEMONIC(MULSATRNDWH_W, MULSATRNDWH_W, "mulsatrndwh.w"),
27921 +    NORMAL_MNEMONIC(MULSATWH_W, MULSATWH_W, "mulsatwh.w"),
27922 +    NORMAL_MNEMONIC(MULU_D, MULU_D, "mulu.d"),
27923 +    NORMAL_MNEMONIC(MULWH_D, MULWH_D, "mulwh.d"),
27924 +    NORMAL_MNEMONIC(MUSFR, MUSFR, "musfr"),
27925 +    NORMAL_MNEMONIC(MUSTR, MUSTR, "mustr"),
27926 +    NORMAL_MNEMONIC(MVCR_D, MVCR_D, "mvcr.d"),
27927 +    NORMAL_MNEMONIC(MVCR_W, MVCR_W, "mvcr.w"),
27928 +    NORMAL_MNEMONIC(MVRC_D, MVRC_D, "mvrc.d"),
27929 +    NORMAL_MNEMONIC(MVRC_W, MVRC_W, "mvrc.w"),
27930 +    NORMAL_MNEMONIC(NEG, NEG, "neg"),
27931 +    NORMAL_MNEMONIC(NOP, NOP, "nop"),
27932 +    NORMAL_MNEMONIC(OR, OR1, "or"),
27933 +    NORMAL_MNEMONIC(ORH, ORH, "orh"),
27934 +    NORMAL_MNEMONIC(ORL, ORL, "orl"),
27935 +    NORMAL_MNEMONIC(PABS_SB, PABS_SB, "pabs.sb"),
27936 +    NORMAL_MNEMONIC(PABS_SH, PABS_SH, "pabs.sh"),
27937 +    NORMAL_MNEMONIC(PACKSH_SB, PACKSH_SB, "packsh.sb"),
27938 +    NORMAL_MNEMONIC(PACKSH_UB, PACKSH_UB, "packsh.ub"),
27939 +    NORMAL_MNEMONIC(PACKW_SH, PACKW_SH, "packw.sh"),
27940 +    NORMAL_MNEMONIC(PADD_B, PADD_B, "padd.b"),
27941 +    NORMAL_MNEMONIC(PADD_H, PADD_H, "padd.h"),
27942 +    NORMAL_MNEMONIC(PADDH_SH, PADDH_SH, "paddh.sh"),
27943 +    NORMAL_MNEMONIC(PADDH_UB, PADDH_UB, "paddh.ub"),
27944 +    NORMAL_MNEMONIC(PADDS_SB, PADDS_SB, "padds.sb"),
27945 +    NORMAL_MNEMONIC(PADDS_SH, PADDS_SH, "padds.sh"),
27946 +    NORMAL_MNEMONIC(PADDS_UB, PADDS_UB, "padds.ub"),
27947 +    NORMAL_MNEMONIC(PADDS_UH, PADDS_UH, "padds.uh"),
27948 +    NORMAL_MNEMONIC(PADDSUB_H, PADDSUB_H, "paddsub.h"),
27949 +    NORMAL_MNEMONIC(PADDSUBH_SH, PADDSUBH_SH, "paddsubh.sh"),
27950 +    NORMAL_MNEMONIC(PADDSUBS_SH, PADDSUBS_SH, "paddsubs.sh"),
27951 +    NORMAL_MNEMONIC(PADDSUBS_UH, PADDSUBS_UH, "paddsubs.uh"),
27952 +    NORMAL_MNEMONIC(PADDX_H, PADDX_H, "paddx.h"),
27953 +    NORMAL_MNEMONIC(PADDXH_SH, PADDXH_SH, "paddxh.sh"),
27954 +    NORMAL_MNEMONIC(PADDXS_SH, PADDXS_SH, "paddxs.sh"),
27955 +    NORMAL_MNEMONIC(PADDXS_UH, PADDXS_UH, "paddxs.uh"),
27956 +    NORMAL_MNEMONIC(PASR_B, PASR_B, "pasr.b"),
27957 +    NORMAL_MNEMONIC(PASR_H, PASR_H, "pasr.h"),
27958 +    NORMAL_MNEMONIC(PAVG_SH, PAVG_SH, "pavg.sh"),
27959 +    NORMAL_MNEMONIC(PAVG_UB, PAVG_UB, "pavg.ub"),
27960 +    NORMAL_MNEMONIC(PLSL_B, PLSL_B, "plsl.b"),
27961 +    NORMAL_MNEMONIC(PLSL_H, PLSL_H, "plsl.h"),
27962 +    NORMAL_MNEMONIC(PLSR_B, PLSR_B, "plsr.b"),
27963 +    NORMAL_MNEMONIC(PLSR_H, PLSR_H, "plsr.h"),
27964 +    NORMAL_MNEMONIC(PMAX_SH, PMAX_SH, "pmax.sh"),
27965 +    NORMAL_MNEMONIC(PMAX_UB, PMAX_UB, "pmax.ub"),
27966 +    NORMAL_MNEMONIC(PMIN_SH, PMIN_SH, "pmin.sh"),
27967 +    NORMAL_MNEMONIC(PMIN_UB, PMIN_UB, "pmin.ub"),
27968 +    NORMAL_MNEMONIC(POPJC, POPJC, "popjc"),
27969 +    NORMAL_MNEMONIC(POPM, POPM, "popm"),
27970 +    NORMAL_MNEMONIC(PREF, PREF, "pref"),
27971 +    NORMAL_MNEMONIC(PSAD, PSAD, "psad"),
27972 +    NORMAL_MNEMONIC(PSUB_B, PSUB_B, "psub.b"),
27973 +    NORMAL_MNEMONIC(PSUB_H, PSUB_H, "psub.h"),
27974 +    NORMAL_MNEMONIC(PSUBADD_H, PSUBADD_H, "psubadd.h"),
27975 +    NORMAL_MNEMONIC(PSUBADDH_SH, PSUBADDH_SH, "psubaddh.sh"),
27976 +    NORMAL_MNEMONIC(PSUBADDS_SH, PSUBADDS_SH, "psubadds.sh"),
27977 +    NORMAL_MNEMONIC(PSUBADDS_UH, PSUBADDS_UH, "psubadds.uh"),
27978 +    NORMAL_MNEMONIC(PSUBH_SH, PSUBH_SH, "psubh.sh"),
27979 +    NORMAL_MNEMONIC(PSUBH_UB, PSUBH_UB, "psubh.ub"),
27980 +    NORMAL_MNEMONIC(PSUBS_SB, PSUBS_SB, "psubs.sb"),
27981 +    NORMAL_MNEMONIC(PSUBS_SH, PSUBS_SH, "psubs.sh"),
27982 +    NORMAL_MNEMONIC(PSUBS_UB, PSUBS_UB, "psubs.ub"),
27983 +    NORMAL_MNEMONIC(PSUBS_UH, PSUBS_UH, "psubs.uh"),
27984 +    NORMAL_MNEMONIC(PSUBX_H, PSUBX_H, "psubx.h"),
27985 +    NORMAL_MNEMONIC(PSUBXH_SH, PSUBXH_SH, "psubxh.sh"),
27986 +    NORMAL_MNEMONIC(PSUBXS_SH, PSUBXS_SH, "psubxs.sh"),
27987 +    NORMAL_MNEMONIC(PSUBXS_UH, PSUBXS_UH, "psubxs.uh"),
27988 +    NORMAL_MNEMONIC(PUNPCKSB_H, PUNPCKSB_H, "punpcksb.h"),
27989 +    NORMAL_MNEMONIC(PUNPCKUB_H, PUNPCKUB_H, "punpckub.h"),
27990 +    NORMAL_MNEMONIC(PUSHJC, PUSHJC, "pushjc"),
27991 +    NORMAL_MNEMONIC(PUSHM, PUSHM, "pushm"),
27992 +    NORMAL_MNEMONIC(RCALL, RCALL1, "rcall"),
27993 +    NORMAL_MNEMONIC(RETEQ, RETEQ, "reteq"),
27994 +    NORMAL_MNEMONIC(RETNE, RETNE, "retne"),
27995 +    NORMAL_MNEMONIC(RETCC, RETCC, "retcc"),
27996 +    NORMAL_MNEMONIC(RETCS, RETCS, "retcs"),
27997 +    NORMAL_MNEMONIC(RETGE, RETGE, "retge"),
27998 +    NORMAL_MNEMONIC(RETLT, RETLT, "retlt"),
27999 +    NORMAL_MNEMONIC(RETMI, RETMI, "retmi"),
28000 +    NORMAL_MNEMONIC(RETPL, RETPL, "retpl"),
28001 +    NORMAL_MNEMONIC(RETLS, RETLS, "retls"),
28002 +    NORMAL_MNEMONIC(RETGT, RETGT, "retgt"),
28003 +    NORMAL_MNEMONIC(RETLE, RETLE, "retle"),
28004 +    NORMAL_MNEMONIC(RETHI, RETHI, "rethi"),
28005 +    NORMAL_MNEMONIC(RETVS, RETVS, "retvs"),
28006 +    NORMAL_MNEMONIC(RETVC, RETVC, "retvc"),
28007 +    NORMAL_MNEMONIC(RETQS, RETQS, "retqs"),
28008 +    NORMAL_MNEMONIC(RETAL, RETAL, "retal"),
28009 +    NORMAL_MNEMONIC(RETHS, RETHS, "reths"),
28010 +    NORMAL_MNEMONIC(RETLO, RETLO, "retlo"),
28011 +    NORMAL_MNEMONIC(RET, RETAL, "ret"),
28012 +    NORMAL_MNEMONIC(RETD, RETD, "retd"),
28013 +    NORMAL_MNEMONIC(RETE, RETE, "rete"),
28014 +    NORMAL_MNEMONIC(RETJ, RETJ, "retj"),
28015 +    NORMAL_MNEMONIC(RETS, RETS, "rets"),
28016 +    NORMAL_MNEMONIC(RJMP, RJMP, "rjmp"),
28017 +    NORMAL_MNEMONIC(ROL, ROL, "rol"),
28018 +    NORMAL_MNEMONIC(ROR, ROR, "ror"),
28019 +    NORMAL_MNEMONIC(RSUB, RSUB1, "rsub"),
28020 +    NORMAL_MNEMONIC(SATADD_H, SATADD_H, "satadd.h"),
28021 +    NORMAL_MNEMONIC(SATADD_W, SATADD_W, "satadd.w"),
28022 +    NORMAL_MNEMONIC(SATRNDS, SATRNDS, "satrnds"),
28023 +    NORMAL_MNEMONIC(SATRNDU, SATRNDU, "satrndu"),
28024 +    NORMAL_MNEMONIC(SATS, SATS, "sats"),
28025 +    NORMAL_MNEMONIC(SATSUB_H, SATSUB_H, "satsub.h"),
28026 +    NORMAL_MNEMONIC(SATSUB_W, SATSUB_W1, "satsub.w"),
28027 +    NORMAL_MNEMONIC(SATU, SATU, "satu"),
28028 +    NORMAL_MNEMONIC(SBC, SBC, "sbc"),
28029 +    NORMAL_MNEMONIC(SBR, SBR, "sbr"),
28030 +    NORMAL_MNEMONIC(SCALL, SCALL, "scall"),
28031 +    NORMAL_MNEMONIC(SCR, SCR, "scr"),
28032 +    NORMAL_MNEMONIC(SLEEP, SLEEP, "sleep"),
28033 +    NORMAL_MNEMONIC(SREQ, SREQ, "sreq"),
28034 +    NORMAL_MNEMONIC(SRNE, SRNE, "srne"),
28035 +    NORMAL_MNEMONIC(SRCC, SRCC, "srcc"),
28036 +    NORMAL_MNEMONIC(SRCS, SRCS, "srcs"),
28037 +    NORMAL_MNEMONIC(SRGE, SRGE, "srge"),
28038 +    NORMAL_MNEMONIC(SRLT, SRLT, "srlt"),
28039 +    NORMAL_MNEMONIC(SRMI, SRMI, "srmi"),
28040 +    NORMAL_MNEMONIC(SRPL, SRPL, "srpl"),
28041 +    NORMAL_MNEMONIC(SRLS, SRLS, "srls"),
28042 +    NORMAL_MNEMONIC(SRGT, SRGT, "srgt"),
28043 +    NORMAL_MNEMONIC(SRLE, SRLE, "srle"),
28044 +    NORMAL_MNEMONIC(SRHI, SRHI, "srhi"),
28045 +    NORMAL_MNEMONIC(SRVS, SRVS, "srvs"),
28046 +    NORMAL_MNEMONIC(SRVC, SRVC, "srvc"),
28047 +    NORMAL_MNEMONIC(SRQS, SRQS, "srqs"),
28048 +    NORMAL_MNEMONIC(SRAL, SRAL, "sral"),
28049 +    NORMAL_MNEMONIC(SRHS, SRHS, "srhs"),
28050 +    NORMAL_MNEMONIC(SRLO, SRLO, "srlo"),
28051 +    NORMAL_MNEMONIC(SSRF, SSRF, "ssrf"),
28052 +    NORMAL_MNEMONIC(ST_B, ST_B1, "st.b"),
28053 +    NORMAL_MNEMONIC(ST_D, ST_D1, "st.d"),
28054 +    NORMAL_MNEMONIC(ST_H, ST_H1, "st.h"),
28055 +    NORMAL_MNEMONIC(ST_W, ST_W1, "st.w"),
28056 +    NORMAL_MNEMONIC(STC_D, STC_D3, "stc.d"),
28057 +    NORMAL_MNEMONIC(STC_W, STC_W3, "stc.w"),
28058 +    NORMAL_MNEMONIC(STC0_D, STC0_D, "stc0.d"),
28059 +    NORMAL_MNEMONIC(STC0_W, STC0_W, "stc0.w"),
28060 +    NORMAL_MNEMONIC(STCM_D, STCM_D, "stcm.d"),
28061 +    NORMAL_MNEMONIC(STCM_W, STCM_W, "stcm.w"),
28062 +    NORMAL_MNEMONIC(STCOND, STCOND, "stcond"),
28063 +    NORMAL_MNEMONIC(STDSP, STDSP, "stdsp"),
28064 +    NORMAL_MNEMONIC(STHH_W, STHH_W2, "sthh.w"),
28065 +    NORMAL_MNEMONIC(STM, STM, "stm"),
28066 +    NORMAL_MNEMONIC(STMTS, STMTS, "stmts"),
28067 +    NORMAL_MNEMONIC(STSWP_H, STSWP_H, "stswp.h"),
28068 +    NORMAL_MNEMONIC(STSWP_W, STSWP_W, "stswp.w"),
28069 +    NORMAL_MNEMONIC(SUB, SUB1, "sub"),
28070 +    NORMAL_MNEMONIC(SUBEQ, SUBEQ, "subeq"),
28071 +    NORMAL_MNEMONIC(SUBNE, SUBNE, "subne"),
28072 +    NORMAL_MNEMONIC(SUBCC, SUBCC, "subcc"),
28073 +    NORMAL_MNEMONIC(SUBCS, SUBCS, "subcs"),
28074 +    NORMAL_MNEMONIC(SUBGE, SUBGE, "subge"),
28075 +    NORMAL_MNEMONIC(SUBLT, SUBLT, "sublt"),
28076 +    NORMAL_MNEMONIC(SUBMI, SUBMI, "submi"),
28077 +    NORMAL_MNEMONIC(SUBPL, SUBPL, "subpl"),
28078 +    NORMAL_MNEMONIC(SUBLS, SUBLS, "subls"),
28079 +    NORMAL_MNEMONIC(SUBGT, SUBGT, "subgt"),
28080 +    NORMAL_MNEMONIC(SUBLE, SUBLE, "suble"),
28081 +    NORMAL_MNEMONIC(SUBHI, SUBHI, "subhi"),
28082 +    NORMAL_MNEMONIC(SUBVS, SUBVS, "subvs"),
28083 +    NORMAL_MNEMONIC(SUBVC, SUBVC, "subvc"),
28084 +    NORMAL_MNEMONIC(SUBQS, SUBQS, "subqs"),
28085 +    NORMAL_MNEMONIC(SUBAL, SUBAL, "subal"),
28086 +    NORMAL_MNEMONIC(SUBHS, SUBHS, "subhs"),
28087 +    NORMAL_MNEMONIC(SUBLO, SUBLO, "sublo"),
28088 +    NORMAL_MNEMONIC(SUBFEQ, SUBFEQ, "subfeq"),
28089 +    NORMAL_MNEMONIC(SUBFNE, SUBFNE, "subfne"),
28090 +    NORMAL_MNEMONIC(SUBFCC, SUBFCC, "subfcc"),
28091 +    NORMAL_MNEMONIC(SUBFCS, SUBFCS, "subfcs"),
28092 +    NORMAL_MNEMONIC(SUBFGE, SUBFGE, "subfge"),
28093 +    NORMAL_MNEMONIC(SUBFLT, SUBFLT, "subflt"),
28094 +    NORMAL_MNEMONIC(SUBFMI, SUBFMI, "subfmi"),
28095 +    NORMAL_MNEMONIC(SUBFPL, SUBFPL, "subfpl"),
28096 +    NORMAL_MNEMONIC(SUBFLS, SUBFLS, "subfls"),
28097 +    NORMAL_MNEMONIC(SUBFGT, SUBFGT, "subfgt"),
28098 +    NORMAL_MNEMONIC(SUBFLE, SUBFLE, "subfle"),
28099 +    NORMAL_MNEMONIC(SUBFHI, SUBFHI, "subfhi"),
28100 +    NORMAL_MNEMONIC(SUBFVS, SUBFVS, "subfvs"),
28101 +    NORMAL_MNEMONIC(SUBFVC, SUBFVC, "subfvc"),
28102 +    NORMAL_MNEMONIC(SUBFQS, SUBFQS, "subfqs"),
28103 +    NORMAL_MNEMONIC(SUBFAL, SUBFAL, "subfal"),
28104 +    NORMAL_MNEMONIC(SUBFHS, SUBFHS, "subfhs"),
28105 +    NORMAL_MNEMONIC(SUBFLO, SUBFLO, "subflo"),
28106 +    NORMAL_MNEMONIC(SUBHH_W, SUBHH_W, "subhh.w"),
28107 +    NORMAL_MNEMONIC(SWAP_B, SWAP_B, "swap.b"),
28108 +    NORMAL_MNEMONIC(SWAP_BH, SWAP_BH, "swap.bh"),
28109 +    NORMAL_MNEMONIC(SWAP_H, SWAP_H, "swap.h"),
28110 +    NORMAL_MNEMONIC(SYNC, SYNC, "sync"),
28111 +    NORMAL_MNEMONIC(TLBR, TLBR, "tlbr"),
28112 +    NORMAL_MNEMONIC(TLBS, TLBS, "tlbs"),
28113 +    NORMAL_MNEMONIC(TLBW, TLBW, "tlbw"),
28114 +    NORMAL_MNEMONIC(TNBZ, TNBZ, "tnbz"),
28115 +    NORMAL_MNEMONIC(TST, TST, "tst"),
28116 +    NORMAL_MNEMONIC(XCHG, XCHG, "xchg"),
28117 +    NORMAL_MNEMONIC(MEMC, MEMC, "memc"),
28118 +    NORMAL_MNEMONIC(MEMS, MEMS, "mems"),
28119 +    NORMAL_MNEMONIC(MEMT, MEMT, "memt"),
28120 +  NORMAL_MNEMONIC (FMAC_S,     FMAC_S,     "fmac.s"),
28121 +  NORMAL_MNEMONIC (FNMAC_S,    FNMAC_S,    "fnmac.s"),
28122 +  NORMAL_MNEMONIC (FMSC_S,     FMSC_S,     "fmsc.s"),
28123 +  NORMAL_MNEMONIC (FNMSC_S,    FNMSC_S,    "fnmsc.s"),
28124 +  NORMAL_MNEMONIC (FMUL_S,     FMUL_S,     "fmul.s"),
28125 +  NORMAL_MNEMONIC (FNMUL_S,    FNMUL_S,    "fnmul.s"),
28126 +  NORMAL_MNEMONIC (FADD_S,     FADD_S,     "fadd.s"),
28127 +  NORMAL_MNEMONIC (FSUB_S,     FSUB_S,     "fsub.s"),
28128 +  NORMAL_MNEMONIC (FCASTRS_SW, FCASTRS_SW, "fcastrs.sw"),
28129 +  NORMAL_MNEMONIC (FCASTRS_UW, FCASTRS_UW, "fcastrs.uw"),
28130 +  NORMAL_MNEMONIC (FCASTSW_S,  FCASTSW_S,  "fcastsw.s"),
28131 +  NORMAL_MNEMONIC (FCASTUW_S,  FCASTUW_S,  "fcastuw.s"),
28132 +  NORMAL_MNEMONIC (FCMP_S,     FCMP_S,     "fcmp.s"),
28133 +  NORMAL_MNEMONIC (FCHK_S,     FCHK_S,     "fchk.s"),
28134 +  NORMAL_MNEMONIC (FRCPA_S,    FRCPA_S,    "frcpa.s"),
28135 +  NORMAL_MNEMONIC (FRSQRTA_S,  FRSQRTA_S,  "frsqrta.s"),
28136 +    NORMAL_MNEMONIC(LDA_W, LDA_W, "lda.w"),
28137 +    NORMAL_MNEMONIC(CALL, CALL, "call"),
28138 +    NORMAL_MNEMONIC(PICOSVMAC, PICOSVMAC0, "picosvmac"),
28139 +    NORMAL_MNEMONIC(PICOSVMUL, PICOSVMUL0, "picosvmul"),
28140 +    NORMAL_MNEMONIC(PICOVMAC, PICOVMAC0, "picovmac"),
28141 +    NORMAL_MNEMONIC(PICOVMUL, PICOVMUL0, "picovmul"),
28142 +    NORMAL_MNEMONIC(PICOLD_D, PICOLD_D2, "picold.d"),
28143 +    NORMAL_MNEMONIC(PICOLD_W, PICOLD_W2, "picold.w"),
28144 +    NORMAL_MNEMONIC(PICOLDM_D, PICOLDM_D, "picoldm.d"),
28145 +    NORMAL_MNEMONIC(PICOLDM_W, PICOLDM_W, "picoldm.w"),
28146 +    NORMAL_MNEMONIC(PICOMV_D, PICOMV_D1, "picomv.d"),
28147 +    NORMAL_MNEMONIC(PICOMV_W, PICOMV_W1, "picomv.w"),
28148 +    NORMAL_MNEMONIC(PICOST_D, PICOST_D2, "picost.d"),
28149 +    NORMAL_MNEMONIC(PICOST_W, PICOST_W2, "picost.w"),
28150 +    NORMAL_MNEMONIC(PICOSTM_D, PICOSTM_D, "picostm.d"),
28151 +    NORMAL_MNEMONIC(PICOSTM_W, PICOSTM_W, "picostm.w"),
28152 +    NORMAL_MNEMONIC(RSUBEQ, RSUBEQ, "rsubeq"),
28153 +    NORMAL_MNEMONIC(RSUBNE, RSUBNE, "rsubne"),
28154 +    NORMAL_MNEMONIC(RSUBCC, RSUBCC, "rsubcc"),
28155 +    NORMAL_MNEMONIC(RSUBCS, RSUBCS, "rsubcs"),
28156 +    NORMAL_MNEMONIC(RSUBGE, RSUBGE, "rsubge"),
28157 +    NORMAL_MNEMONIC(RSUBLT, RSUBLT, "rsublt"),
28158 +    NORMAL_MNEMONIC(RSUBMI, RSUBMI, "rsubmi"),
28159 +    NORMAL_MNEMONIC(RSUBPL, RSUBPL, "rsubpl"),
28160 +    NORMAL_MNEMONIC(RSUBLS, RSUBLS, "rsubls"),
28161 +    NORMAL_MNEMONIC(RSUBGT, RSUBGT, "rsubgt"),
28162 +    NORMAL_MNEMONIC(RSUBLE, RSUBLE, "rsuble"),
28163 +    NORMAL_MNEMONIC(RSUBHI, RSUBHI, "rsubhi"),
28164 +    NORMAL_MNEMONIC(RSUBVS, RSUBVS, "rsubvs"),
28165 +    NORMAL_MNEMONIC(RSUBVC, RSUBVC, "rsubvc"),
28166 +    NORMAL_MNEMONIC(RSUBQS, RSUBQS, "rsubqs"),
28167 +    NORMAL_MNEMONIC(RSUBAL, RSUBAL, "rsubal"),
28168 +    NORMAL_MNEMONIC(RSUBHS, RSUBHS, "rsubhs"),
28169 +    NORMAL_MNEMONIC(RSUBLO, RSUBLO, "rsublo"),
28170 +    NORMAL_MNEMONIC(ADDEQ, ADDEQ, "addeq"),
28171 +    NORMAL_MNEMONIC(ADDNE, ADDNE, "addne"),
28172 +    NORMAL_MNEMONIC(ADDCC, ADDCC, "addcc"),
28173 +    NORMAL_MNEMONIC(ADDCS, ADDCS, "addcs"),
28174 +    NORMAL_MNEMONIC(ADDGE, ADDGE, "addge"),
28175 +    NORMAL_MNEMONIC(ADDLT, ADDLT, "addlt"),
28176 +    NORMAL_MNEMONIC(ADDMI, ADDMI, "addmi"),
28177 +    NORMAL_MNEMONIC(ADDPL, ADDPL, "addpl"),
28178 +    NORMAL_MNEMONIC(ADDLS, ADDLS, "addls"),
28179 +    NORMAL_MNEMONIC(ADDGT, ADDGT, "addgt"),
28180 +    NORMAL_MNEMONIC(ADDLE, ADDLE, "addle"),
28181 +    NORMAL_MNEMONIC(ADDHI, ADDHI, "addhi"),
28182 +    NORMAL_MNEMONIC(ADDVS, ADDVS, "addvs"),
28183 +    NORMAL_MNEMONIC(ADDVC, ADDVC, "addvc"),
28184 +    NORMAL_MNEMONIC(ADDQS, ADDQS, "addqs"),
28185 +    NORMAL_MNEMONIC(ADDAL, ADDAL, "addal"),
28186 +    NORMAL_MNEMONIC(ADDHS, ADDHS, "addhs"),
28187 +    NORMAL_MNEMONIC(ADDLO, ADDLO, "addlo"),
28188 +    NORMAL_MNEMONIC(ANDEQ, ANDEQ, "andeq"),
28189 +    NORMAL_MNEMONIC(ANDNE, ANDNE, "andne"),
28190 +    NORMAL_MNEMONIC(ANDCC, ANDCC, "andcc"),
28191 +    NORMAL_MNEMONIC(ANDCS, ANDCS, "andcs"),
28192 +    NORMAL_MNEMONIC(ANDGE, ANDGE, "andge"),
28193 +    NORMAL_MNEMONIC(ANDLT, ANDLT, "andlt"),
28194 +    NORMAL_MNEMONIC(ANDMI, ANDMI, "andmi"),
28195 +    NORMAL_MNEMONIC(ANDPL, ANDPL, "andpl"),
28196 +    NORMAL_MNEMONIC(ANDLS, ANDLS, "andls"),
28197 +    NORMAL_MNEMONIC(ANDGT, ANDGT, "andgt"),
28198 +    NORMAL_MNEMONIC(ANDLE, ANDLE, "andle"),
28199 +    NORMAL_MNEMONIC(ANDHI, ANDHI, "andhi"),
28200 +    NORMAL_MNEMONIC(ANDVS, ANDVS, "andvs"),
28201 +    NORMAL_MNEMONIC(ANDVC, ANDVC, "andvc"),
28202 +    NORMAL_MNEMONIC(ANDQS, ANDQS, "andqs"),
28203 +    NORMAL_MNEMONIC(ANDAL, ANDAL, "andal"),
28204 +    NORMAL_MNEMONIC(ANDHS, ANDHS, "andhs"),
28205 +    NORMAL_MNEMONIC(ANDLO, ANDLO, "andlo"),
28206 +    NORMAL_MNEMONIC(OREQ, OREQ, "oreq"),
28207 +    NORMAL_MNEMONIC(ORNE, ORNE, "orne"),
28208 +    NORMAL_MNEMONIC(ORCC, ORCC, "orcc"),
28209 +    NORMAL_MNEMONIC(ORCS, ORCS, "orcs"),
28210 +    NORMAL_MNEMONIC(ORGE, ORGE, "orge"),
28211 +    NORMAL_MNEMONIC(ORLT, ORLT, "orlt"),
28212 +    NORMAL_MNEMONIC(ORMI, ORMI, "ormi"),
28213 +    NORMAL_MNEMONIC(ORPL, ORPL, "orpl"),
28214 +    NORMAL_MNEMONIC(ORLS, ORLS, "orls"),
28215 +    NORMAL_MNEMONIC(ORGT, ORGT, "orgt"),
28216 +    NORMAL_MNEMONIC(ORLE, ORLE, "orle"),
28217 +    NORMAL_MNEMONIC(ORHI, ORHI, "orhi"),
28218 +    NORMAL_MNEMONIC(ORVS, ORVS, "orvs"),
28219 +    NORMAL_MNEMONIC(ORVC, ORVC, "orvc"),
28220 +    NORMAL_MNEMONIC(ORQS, ORQS, "orqs"),
28221 +    NORMAL_MNEMONIC(ORAL, ORAL, "oral"),
28222 +    NORMAL_MNEMONIC(ORHS, ORHS, "orhs"),
28223 +    NORMAL_MNEMONIC(ORLO, ORLO, "orlo"),
28224 +    NORMAL_MNEMONIC(EOREQ, EOREQ, "eoreq"),
28225 +    NORMAL_MNEMONIC(EORNE, EORNE, "eorne"),
28226 +    NORMAL_MNEMONIC(EORCC, EORCC, "eorcc"),
28227 +    NORMAL_MNEMONIC(EORCS, EORCS, "eorcs"),
28228 +    NORMAL_MNEMONIC(EORGE, EORGE, "eorge"),
28229 +    NORMAL_MNEMONIC(EORLT, EORLT, "eorlt"),
28230 +    NORMAL_MNEMONIC(EORMI, EORMI, "eormi"),
28231 +    NORMAL_MNEMONIC(EORPL, EORPL, "eorpl"),
28232 +    NORMAL_MNEMONIC(EORLS, EORLS, "eorls"),
28233 +    NORMAL_MNEMONIC(EORGT, EORGT, "eorgt"),
28234 +    NORMAL_MNEMONIC(EORLE, EORLE, "eorle"),
28235 +    NORMAL_MNEMONIC(EORHI, EORHI, "eorhi"),
28236 +    NORMAL_MNEMONIC(EORVS, EORVS, "eorvs"),
28237 +    NORMAL_MNEMONIC(EORVC, EORVC, "eorvc"),
28238 +    NORMAL_MNEMONIC(EORQS, EORQS, "eorqs"),
28239 +    NORMAL_MNEMONIC(EORAL, EORAL, "eoral"),
28240 +    NORMAL_MNEMONIC(EORHS, EORHS, "eorhs"),
28241 +    NORMAL_MNEMONIC(EORLO, EORLO, "eorlo"),
28242 +    NORMAL_MNEMONIC(LD_WEQ, LD_WEQ, "ld.weq"),
28243 +    NORMAL_MNEMONIC(LD_WNE, LD_WNE, "ld.wne"),
28244 +    NORMAL_MNEMONIC(LD_WCC, LD_WCC, "ld.wcc"),
28245 +    NORMAL_MNEMONIC(LD_WCS, LD_WCS, "ld.wcs"),
28246 +    NORMAL_MNEMONIC(LD_WGE, LD_WGE, "ld.wge"),
28247 +    NORMAL_MNEMONIC(LD_WLT, LD_WLT, "ld.wlt"),
28248 +    NORMAL_MNEMONIC(LD_WMI, LD_WMI, "ld.wmi"),
28249 +    NORMAL_MNEMONIC(LD_WPL, LD_WPL, "ld.wpl"),
28250 +    NORMAL_MNEMONIC(LD_WLS, LD_WLS, "ld.wls"),
28251 +    NORMAL_MNEMONIC(LD_WGT, LD_WGT, "ld.wgt"),
28252 +    NORMAL_MNEMONIC(LD_WLE, LD_WLE, "ld.wle"),
28253 +    NORMAL_MNEMONIC(LD_WHI, LD_WHI, "ld.whi"),
28254 +    NORMAL_MNEMONIC(LD_WVS, LD_WVS, "ld.wvs"),
28255 +    NORMAL_MNEMONIC(LD_WVC, LD_WVC, "ld.wvc"),
28256 +    NORMAL_MNEMONIC(LD_WQS, LD_WQS, "ld.wqs"),
28257 +    NORMAL_MNEMONIC(LD_WAL, LD_WAL, "ld.wal"),
28258 +    NORMAL_MNEMONIC(LD_WHS, LD_WHS, "ld.whs"),
28259 +    NORMAL_MNEMONIC(LD_WLO, LD_WLO, "ld.wlo"),
28260 +    NORMAL_MNEMONIC(LD_SHEQ, LD_SHEQ, "ld.sheq"),
28261 +    NORMAL_MNEMONIC(LD_SHNE, LD_SHNE, "ld.shne"),
28262 +    NORMAL_MNEMONIC(LD_SHCC, LD_SHCC, "ld.shcc"),
28263 +    NORMAL_MNEMONIC(LD_SHCS, LD_SHCS, "ld.shcs"),
28264 +    NORMAL_MNEMONIC(LD_SHGE, LD_SHGE, "ld.shge"),
28265 +    NORMAL_MNEMONIC(LD_SHLT, LD_SHLT, "ld.shlt"),
28266 +    NORMAL_MNEMONIC(LD_SHMI, LD_SHMI, "ld.shmi"),
28267 +    NORMAL_MNEMONIC(LD_SHPL, LD_SHPL, "ld.shpl"),
28268 +    NORMAL_MNEMONIC(LD_SHLS, LD_SHLS, "ld.shls"),
28269 +    NORMAL_MNEMONIC(LD_SHGT, LD_SHGT, "ld.shgt"),
28270 +    NORMAL_MNEMONIC(LD_SHLE, LD_SHLE, "ld.shle"),
28271 +    NORMAL_MNEMONIC(LD_SHHI, LD_SHHI, "ld.shhi"),
28272 +    NORMAL_MNEMONIC(LD_SHVS, LD_SHVS, "ld.shvs"),
28273 +    NORMAL_MNEMONIC(LD_SHVC, LD_SHVC, "ld.shvc"),
28274 +    NORMAL_MNEMONIC(LD_SHQS, LD_SHQS, "ld.shqs"),
28275 +    NORMAL_MNEMONIC(LD_SHAL, LD_SHAL, "ld.shal"),
28276 +    NORMAL_MNEMONIC(LD_SHHS, LD_SHHS, "ld.shhs"),
28277 +    NORMAL_MNEMONIC(LD_SHLO, LD_SHLO, "ld.shlo"),
28278 +    NORMAL_MNEMONIC(LD_UHEQ, LD_UHEQ, "ld.uheq"),
28279 +    NORMAL_MNEMONIC(LD_UHNE, LD_UHNE, "ld.uhne"),
28280 +    NORMAL_MNEMONIC(LD_UHCC, LD_UHCC, "ld.uhcc"),
28281 +    NORMAL_MNEMONIC(LD_UHCS, LD_UHCS, "ld.uhcs"),
28282 +    NORMAL_MNEMONIC(LD_UHGE, LD_UHGE, "ld.uhge"),
28283 +    NORMAL_MNEMONIC(LD_UHLT, LD_UHLT, "ld.uhlt"),
28284 +    NORMAL_MNEMONIC(LD_UHMI, LD_UHMI, "ld.uhmi"),
28285 +    NORMAL_MNEMONIC(LD_UHPL, LD_UHPL, "ld.uhpl"),
28286 +    NORMAL_MNEMONIC(LD_UHLS, LD_UHLS, "ld.uhls"),
28287 +    NORMAL_MNEMONIC(LD_UHGT, LD_UHGT, "ld.uhgt"),
28288 +    NORMAL_MNEMONIC(LD_UHLE, LD_UHLE, "ld.uhle"),
28289 +    NORMAL_MNEMONIC(LD_UHHI, LD_UHHI, "ld.uhhi"),
28290 +    NORMAL_MNEMONIC(LD_UHVS, LD_UHVS, "ld.uhvs"),
28291 +    NORMAL_MNEMONIC(LD_UHVC, LD_UHVC, "ld.uhvc"),
28292 +    NORMAL_MNEMONIC(LD_UHQS, LD_UHQS, "ld.uhqs"),
28293 +    NORMAL_MNEMONIC(LD_UHAL, LD_UHAL, "ld.uhal"),
28294 +    NORMAL_MNEMONIC(LD_UHHS, LD_UHHS, "ld.uhhs"),
28295 +    NORMAL_MNEMONIC(LD_UHLO, LD_UHLO, "ld.uhlo"),
28296 +    NORMAL_MNEMONIC(LD_SBEQ, LD_SBEQ, "ld.sbeq"),
28297 +    NORMAL_MNEMONIC(LD_SBNE, LD_SBNE, "ld.sbne"),
28298 +    NORMAL_MNEMONIC(LD_SBCC, LD_SBCC, "ld.sbcc"),
28299 +    NORMAL_MNEMONIC(LD_SBCS, LD_SBCS, "ld.sbcs"),
28300 +    NORMAL_MNEMONIC(LD_SBGE, LD_SBGE, "ld.sbge"),
28301 +    NORMAL_MNEMONIC(LD_SBLT, LD_SBLT, "ld.sblt"),
28302 +    NORMAL_MNEMONIC(LD_SBMI, LD_SBMI, "ld.sbmi"),
28303 +    NORMAL_MNEMONIC(LD_SBPL, LD_SBPL, "ld.sbpl"),
28304 +    NORMAL_MNEMONIC(LD_SBLS, LD_SBLS, "ld.sbls"),
28305 +    NORMAL_MNEMONIC(LD_SBGT, LD_SBGT, "ld.sbgt"),
28306 +    NORMAL_MNEMONIC(LD_SBLE, LD_SBLE, "ld.sble"),
28307 +    NORMAL_MNEMONIC(LD_SBHI, LD_SBHI, "ld.sbhi"),
28308 +    NORMAL_MNEMONIC(LD_SBVS, LD_SBVS, "ld.sbvs"),
28309 +    NORMAL_MNEMONIC(LD_SBVC, LD_SBVC, "ld.sbvc"),
28310 +    NORMAL_MNEMONIC(LD_SBQS, LD_SBQS, "ld.sbqs"),
28311 +    NORMAL_MNEMONIC(LD_SBAL, LD_SBAL, "ld.sbal"),
28312 +    NORMAL_MNEMONIC(LD_SBHS, LD_SBHS, "ld.sbhs"),
28313 +    NORMAL_MNEMONIC(LD_SBLO, LD_SBLO, "ld.sblo"),
28314 +    NORMAL_MNEMONIC(LD_UBEQ, LD_UBEQ, "ld.ubeq"),
28315 +    NORMAL_MNEMONIC(LD_UBNE, LD_UBNE, "ld.ubne"),
28316 +    NORMAL_MNEMONIC(LD_UBCC, LD_UBCC, "ld.ubcc"),
28317 +    NORMAL_MNEMONIC(LD_UBCS, LD_UBCS, "ld.ubcs"),
28318 +    NORMAL_MNEMONIC(LD_UBGE, LD_UBGE, "ld.ubge"),
28319 +    NORMAL_MNEMONIC(LD_UBLT, LD_UBLT, "ld.ublt"),
28320 +    NORMAL_MNEMONIC(LD_UBMI, LD_UBMI, "ld.ubmi"),
28321 +    NORMAL_MNEMONIC(LD_UBPL, LD_UBPL, "ld.ubpl"),
28322 +    NORMAL_MNEMONIC(LD_UBLS, LD_UBLS, "ld.ubls"),
28323 +    NORMAL_MNEMONIC(LD_UBGT, LD_UBGT, "ld.ubgt"),
28324 +    NORMAL_MNEMONIC(LD_UBLE, LD_UBLE, "ld.uble"),
28325 +    NORMAL_MNEMONIC(LD_UBHI, LD_UBHI, "ld.ubhi"),
28326 +    NORMAL_MNEMONIC(LD_UBVS, LD_UBVS, "ld.ubvs"),
28327 +    NORMAL_MNEMONIC(LD_UBVC, LD_UBVC, "ld.ubvc"),
28328 +    NORMAL_MNEMONIC(LD_UBQS, LD_UBQS, "ld.ubqs"),
28329 +    NORMAL_MNEMONIC(LD_UBAL, LD_UBAL, "ld.ubal"),
28330 +    NORMAL_MNEMONIC(LD_UBHS, LD_UBHS, "ld.ubhs"),
28331 +    NORMAL_MNEMONIC(LD_UBLO, LD_UBLO, "ld.ublo"),
28332 +    NORMAL_MNEMONIC(ST_WEQ, ST_WEQ, "st.weq"),
28333 +    NORMAL_MNEMONIC(ST_WNE, ST_WNE, "st.wne"),
28334 +    NORMAL_MNEMONIC(ST_WCC, ST_WCC, "st.wcc"),
28335 +    NORMAL_MNEMONIC(ST_WCS, ST_WCS, "st.wcs"),
28336 +    NORMAL_MNEMONIC(ST_WGE, ST_WGE, "st.wge"),
28337 +    NORMAL_MNEMONIC(ST_WLT, ST_WLT, "st.wlt"),
28338 +    NORMAL_MNEMONIC(ST_WMI, ST_WMI, "st.wmi"),
28339 +    NORMAL_MNEMONIC(ST_WPL, ST_WPL, "st.wpl"),
28340 +    NORMAL_MNEMONIC(ST_WLS, ST_WLS, "st.wls"),
28341 +    NORMAL_MNEMONIC(ST_WGT, ST_WGT, "st.wgt"),
28342 +    NORMAL_MNEMONIC(ST_WLE, ST_WLE, "st.wle"),
28343 +    NORMAL_MNEMONIC(ST_WHI, ST_WHI, "st.whi"),
28344 +    NORMAL_MNEMONIC(ST_WVS, ST_WVS, "st.wvs"),
28345 +    NORMAL_MNEMONIC(ST_WVC, ST_WVC, "st.wvc"),
28346 +    NORMAL_MNEMONIC(ST_WQS, ST_WQS, "st.wqs"),
28347 +    NORMAL_MNEMONIC(ST_WAL, ST_WAL, "st.wal"),
28348 +    NORMAL_MNEMONIC(ST_WHS, ST_WHS, "st.whs"),
28349 +    NORMAL_MNEMONIC(ST_WLO, ST_WLO, "st.wlo"),
28350 +    NORMAL_MNEMONIC(ST_HEQ, ST_HEQ, "st.heq"),
28351 +    NORMAL_MNEMONIC(ST_HNE, ST_HNE, "st.hne"),
28352 +    NORMAL_MNEMONIC(ST_HCC, ST_HCC, "st.hcc"),
28353 +    NORMAL_MNEMONIC(ST_HCS, ST_HCS, "st.hcs"),
28354 +    NORMAL_MNEMONIC(ST_HGE, ST_HGE, "st.hge"),
28355 +    NORMAL_MNEMONIC(ST_HLT, ST_HLT, "st.hlt"),
28356 +    NORMAL_MNEMONIC(ST_HMI, ST_HMI, "st.hmi"),
28357 +    NORMAL_MNEMONIC(ST_HPL, ST_HPL, "st.hpl"),
28358 +    NORMAL_MNEMONIC(ST_HLS, ST_HLS, "st.hls"),
28359 +    NORMAL_MNEMONIC(ST_HGT, ST_HGT, "st.hgt"),
28360 +    NORMAL_MNEMONIC(ST_HLE, ST_HLE, "st.hle"),
28361 +    NORMAL_MNEMONIC(ST_HHI, ST_HHI, "st.hhi"),
28362 +    NORMAL_MNEMONIC(ST_HVS, ST_HVS, "st.hvs"),
28363 +    NORMAL_MNEMONIC(ST_HVC, ST_HVC, "st.hvc"),
28364 +    NORMAL_MNEMONIC(ST_HQS, ST_HQS, "st.hqs"),
28365 +    NORMAL_MNEMONIC(ST_HAL, ST_HAL, "st.hal"),
28366 +    NORMAL_MNEMONIC(ST_HHS, ST_HHS, "st.hhs"),
28367 +    NORMAL_MNEMONIC(ST_HLO, ST_HLO, "st.hlo"),
28368 +    NORMAL_MNEMONIC(ST_BEQ, ST_BEQ, "st.beq"),
28369 +    NORMAL_MNEMONIC(ST_BNE, ST_BNE, "st.bne"),
28370 +    NORMAL_MNEMONIC(ST_BCC, ST_BCC, "st.bcc"),
28371 +    NORMAL_MNEMONIC(ST_BCS, ST_BCS, "st.bcs"),
28372 +    NORMAL_MNEMONIC(ST_BGE, ST_BGE, "st.bge"),
28373 +    NORMAL_MNEMONIC(ST_BLT, ST_BLT, "st.blt"),
28374 +    NORMAL_MNEMONIC(ST_BMI, ST_BMI, "st.bmi"),
28375 +    NORMAL_MNEMONIC(ST_BPL, ST_BPL, "st.bpl"),
28376 +    NORMAL_MNEMONIC(ST_BLS, ST_BLS, "st.bls"),
28377 +    NORMAL_MNEMONIC(ST_BGT, ST_BGT, "st.bgt"),
28378 +    NORMAL_MNEMONIC(ST_BLE, ST_BLE, "st.ble"),
28379 +    NORMAL_MNEMONIC(ST_BHI, ST_BHI, "st.bhi"),
28380 +    NORMAL_MNEMONIC(ST_BVS, ST_BVS, "st.bvs"),
28381 +    NORMAL_MNEMONIC(ST_BVC, ST_BVC, "st.bvc"),
28382 +    NORMAL_MNEMONIC(ST_BQS, ST_BQS, "st.bqs"),
28383 +    NORMAL_MNEMONIC(ST_BAL, ST_BAL, "st.bal"),
28384 +    NORMAL_MNEMONIC(ST_BHS, ST_BHS, "st.bhs"),
28385 +    NORMAL_MNEMONIC(ST_BLO, ST_BLO, "st.blo"),
28386 +    NORMAL_MNEMONIC(MOVH, MOVH, "movh"),
28387 +
28388 +  };
28389 +#undef NORMAL_MNEMONIC
28390 +#undef ALIAS_MNEMONIC
28391 +#undef FP_MNEMONIC
28392 --- /dev/null
28393 +++ b/opcodes/avr32-opc.h
28394 @@ -0,0 +1,2341 @@
28395 +/* Opcode tables for AVR32.
28396 +   Copyright 2005,2006,2007,2008,2009 Atmel Corporation.
28397 +
28398 +   Written by Haavard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
28399 +
28400 +   This file is part of libopcodes.
28401 +
28402 +   This program is free software; you can redistribute it and/or
28403 +   modify it under the terms of the GNU General Public License as
28404 +   published by the Free Software Foundation; either version 2 of the
28405 +   License, or (at your option) any later version.
28406 +
28407 +   This program is distributed in the hope that it will be useful, but
28408 +   WITHOUT ANY WARRANTY; without even the implied warranty of
28409 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
28410 +   General Public License for more details.
28411 +
28412 +   You should have received a copy of the GNU General Public License
28413 +   along with this program; if not, write to the Free Software
28414 +   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
28415 +   02111-1307, USA.  */
28416 +
28417 +#include "bfd.h"
28418 +
28419 +#define AVR32_MAX_OPERANDS     8
28420 +#define AVR32_MAX_FIELDS       8
28421 +
28422 +#define AVR32_V1               (1 << 1)
28423 +#define AVR32_SIMD             (1 << 2)
28424 +#define AVR32_DSP              (1 << 3)
28425 +#define AVR32_RMW              (1 << 4)
28426 +#define AVR32_V2               (1 << 5)
28427 +#define AVR32_V3               (1 << 6)
28428 +#define AVR32_V3FP             (1 << 7)
28429 +#define AVR32_PICO             (1 << 17)
28430 +
28431 +/* Registers we commonly refer to */
28432 +#define AVR32_REG_R12          12
28433 +#define AVR32_REG_SP           13
28434 +#define AVR32_REG_LR           14
28435 +#define AVR32_REG_PC           15
28436 +
28437 +struct avr32_ifield
28438 +{
28439 +  int id;
28440 +  unsigned short bitsize;
28441 +  unsigned short shift;
28442 +  unsigned long mask;
28443 +
28444 +  /* If the value doesn't fit, it will be truncated with no warning */
28445 +  void (*insert)(const struct avr32_ifield *, void *, unsigned long);
28446 +  void (*extract)(const struct avr32_ifield *, void *, unsigned long *);
28447 +};
28448 +
28449 +struct avr32_opcode
28450 +{
28451 +  int id;
28452 +  int size;
28453 +  unsigned long value;
28454 +  unsigned long mask;
28455 +  const struct avr32_syntax *syntax;
28456 +  bfd_reloc_code_real_type reloc_type;
28457 +  unsigned int nr_fields;
28458 +  /* if relaxable, which field is variable, otherwise -1 */
28459 +  int var_field;
28460 +  const struct avr32_ifield *fields[AVR32_MAX_FIELDS];
28461 +};
28462 +
28463 +struct avr32_alias
28464 +{
28465 +  int id;
28466 +  const struct avr32_opcode *opc;
28467 +  struct {
28468 +    int is_opindex;
28469 +    unsigned long value;
28470 +  } operand_map[AVR32_MAX_OPERANDS];
28471 +};
28472 +
28473 +struct avr32_syntax
28474 +{
28475 +  int id;
28476 +  unsigned long isa_flags;
28477 +  const struct avr32_mnemonic *mnemonic;
28478 +  int type;
28479 +  union {
28480 +    const struct avr32_opcode *opc;
28481 +    const struct avr32_alias *alias;
28482 +  } u;
28483 +  const struct avr32_syntax *next;
28484 +  /* negative means "vararg" */
28485 +  int nr_operands;
28486 +  int operand[AVR32_MAX_OPERANDS];
28487 +};
28488 +
28489 +#if 0
28490 +#define AVR32_ALIAS_MAKE_CONST(val) ((val) | 0x80000000UL)
28491 +#define AVR32_ALIAS_IS_CONST(mapval) (((mapval) & 0x80000000UL) != 0)
28492 +#define AVR32_ALIAS_GET_CONST(mapval) ((mapval) & ~0x80000000UL)
28493 +#endif
28494 +
28495 +struct avr32_mnemonic
28496 +{
28497 +  int id;
28498 +  const char *name;
28499 +  const struct avr32_syntax *syntax;
28500 +};
28501 +
28502 +extern const struct avr32_ifield avr32_ifield_table[];
28503 +extern struct avr32_opcode avr32_opc_table[];
28504 +extern const struct avr32_syntax avr32_syntax_table[];
28505 +extern const struct avr32_alias avr32_alias_table[];
28506 +extern const struct avr32_mnemonic avr32_mnemonic_table[];
28507 +
28508 +extern void avr32_insert_simple(const struct avr32_ifield *field,
28509 +                               void *buf, unsigned long value);
28510 +extern void avr32_insert_bit5c(const struct avr32_ifield *field,
28511 +                              void *buf, unsigned long value);
28512 +extern void avr32_insert_k10(const struct avr32_ifield *field,
28513 +                            void *buf, unsigned long value);
28514 +extern void avr32_insert_k21(const struct avr32_ifield *field,
28515 +                            void *buf, unsigned long value);
28516 +extern void avr32_insert_cpop(const struct avr32_ifield *field,
28517 +                             void *buf, unsigned long value);
28518 +extern void avr32_insert_k12cp(const struct avr32_ifield *field,
28519 +                              void *buf, unsigned long value);
28520 +
28521 +extern void avr32_extract_simple(const struct avr32_ifield *field,
28522 +                                void *buf, unsigned long *value);
28523 +extern void avr32_extract_bit5c(const struct avr32_ifield *field,
28524 +                               void *buf, unsigned long *value);
28525 +extern void avr32_extract_k10(const struct avr32_ifield *field,
28526 +                             void *buf, unsigned long *value);
28527 +extern void avr32_extract_k21(const struct avr32_ifield *field,
28528 +                             void *buf, unsigned long *value);
28529 +extern void avr32_extract_cpop(const struct avr32_ifield *field,
28530 +                              void *buf, unsigned long *value);
28531 +extern void avr32_extract_k12cp(const struct avr32_ifield *field,
28532 +                               void *buf, unsigned long *value);
28533 +
28534 +enum avr32_operand_type
28535 +{
28536 +  AVR32_OPERAND_INTREG,                /* just a register */
28537 +  AVR32_OPERAND_INTREG_PREDEC, /* register with pre-decrement */
28538 +  AVR32_OPERAND_INTREG_POSTINC,        /* register with post-increment */
28539 +  AVR32_OPERAND_INTREG_LSL,    /* register with left shift */
28540 +  AVR32_OPERAND_INTREG_LSR,    /* register with right shift */
28541 +  AVR32_OPERAND_INTREG_BSEL,   /* register with byte selector */
28542 +  AVR32_OPERAND_INTREG_HSEL,   /* register with halfword selector */
28543 +  AVR32_OPERAND_INTREG_SDISP,  /* Rp[signed disp] */
28544 +  AVR32_OPERAND_INTREG_SDISP_H,        /* Rp[signed hword-aligned disp] */
28545 +  AVR32_OPERAND_INTREG_SDISP_W,        /* Rp[signed word-aligned disp] */
28546 +  AVR32_OPERAND_INTREG_UDISP,  /* Rp[unsigned disp] */
28547 +  AVR32_OPERAND_INTREG_UDISP_H,        /* Rp[unsigned hword-aligned disp] */
28548 +  AVR32_OPERAND_INTREG_UDISP_W, /* Rp[unsigned word-aligned disp] */
28549 +  AVR32_OPERAND_INTREG_INDEX,  /* Rp[Ri << sa] */
28550 +  AVR32_OPERAND_INTREG_XINDEX, /* Rp[Ri:bytesel << 2] */
28551 +  AVR32_OPERAND_DWREG,         /* Even-numbered register */
28552 +  AVR32_OPERAND_PC_UDISP_W,    /* PC[unsigned word-aligned disp] or label */
28553 +  AVR32_OPERAND_SP,            /* Just SP */
28554 +  AVR32_OPERAND_SP_UDISP_W,    /* SP[unsigned word-aligned disp] */
28555 +  AVR32_OPERAND_CPNO,
28556 +  AVR32_OPERAND_CPREG,
28557 +  AVR32_OPERAND_CPREG_D,
28558 +  AVR32_OPERAND_UNSIGNED_CONST,
28559 +  AVR32_OPERAND_UNSIGNED_CONST_W,
28560 +  AVR32_OPERAND_SIGNED_CONST,
28561 +  AVR32_OPERAND_SIGNED_CONST_W,
28562 +  AVR32_OPERAND_JMPLABEL,
28563 +  AVR32_OPERAND_UNSIGNED_NUMBER,
28564 +  AVR32_OPERAND_UNSIGNED_NUMBER_W,
28565 +  AVR32_OPERAND_REGLIST8,
28566 +  AVR32_OPERAND_REGLIST9,
28567 +  AVR32_OPERAND_REGLIST16,
28568 +  AVR32_OPERAND_REGLIST_LDM,
28569 +  AVR32_OPERAND_REGLIST_CP8,
28570 +  AVR32_OPERAND_REGLIST_CPD8,
28571 +  AVR32_OPERAND_RETVAL,
28572 +  AVR32_OPERAND_MCALL,
28573 +  AVR32_OPERAND_JOSPINC,
28574 +  AVR32_OPERAND_COH,
28575 +  AVR32_OPERAND_PICO_REG_W,
28576 +  AVR32_OPERAND_PICO_REG_D,
28577 +  AVR32_OPERAND_PICO_REGLIST_W,
28578 +  AVR32_OPERAND_PICO_REGLIST_D,
28579 +  AVR32_OPERAND_PICO_IN,
28580 +  AVR32_OPERAND_PICO_OUT0,
28581 +  AVR32_OPERAND_PICO_OUT1,
28582 +  AVR32_OPERAND_PICO_OUT2,
28583 +  AVR32_OPERAND_PICO_OUT3,
28584 +  AVR32_OPERAND__END_
28585 +};
28586 +#define AVR32_OPERAND_UNKNOWN AVR32_OPERAND__END_
28587 +#define AVR32_NR_OPERANDS AVR32_OPERAND__END_
28588 +
28589 +enum avr32_ifield_type
28590 +{
28591 +  AVR32_IFIELD_RX,
28592 +  AVR32_IFIELD_RY,
28593 +  AVR32_IFIELD_COND4C,
28594 +  AVR32_IFIELD_K8C,
28595 +  AVR32_IFIELD_K7C,
28596 +  AVR32_IFIELD_K5C,
28597 +  AVR32_IFIELD_K3,
28598 +  AVR32_IFIELD_RY_DW,
28599 +  AVR32_IFIELD_COND4E,
28600 +  AVR32_IFIELD_K8E,
28601 +  AVR32_IFIELD_BIT5C,
28602 +  AVR32_IFIELD_COND3,
28603 +  AVR32_IFIELD_K10,
28604 +  AVR32_IFIELD_POPM,
28605 +  AVR32_IFIELD_K2,
28606 +  AVR32_IFIELD_RD_E,
28607 +  AVR32_IFIELD_RD_DW,
28608 +  AVR32_IFIELD_X,
28609 +  AVR32_IFIELD_Y,
28610 +  AVR32_IFIELD_X2,
28611 +  AVR32_IFIELD_Y2,
28612 +  AVR32_IFIELD_K5E,
28613 +  AVR32_IFIELD_PART2,
28614 +  AVR32_IFIELD_PART1,
28615 +  AVR32_IFIELD_K16,
28616 +  AVR32_IFIELD_CACHEOP,
28617 +  AVR32_IFIELD_K11,
28618 +  AVR32_IFIELD_K21,
28619 +  AVR32_IFIELD_CPOP,
28620 +  AVR32_IFIELD_CPNO,
28621 +  AVR32_IFIELD_CRD_RI,
28622 +  AVR32_IFIELD_CRX,
28623 +  AVR32_IFIELD_CRY,
28624 +  AVR32_IFIELD_K7E,
28625 +  AVR32_IFIELD_CRD_DW,
28626 +  AVR32_IFIELD_PART1_K12,
28627 +  AVR32_IFIELD_PART2_K12,
28628 +  AVR32_IFIELD_K12,
28629 +  AVR32_IFIELD_S5,
28630 +  AVR32_IFIELD_K5E2,
28631 +  AVR32_IFIELD_K4,
28632 +  AVR32_IFIELD_COND4E2,
28633 +  AVR32_IFIELD_K8E2,
28634 +  AVR32_IFIELD_K6,
28635 +  AVR32_IFIELD_MEM15,
28636 +  AVR32_IFIELD_MEMB5,
28637 +  AVR32_IFIELD_W,
28638 +  AVR32_IFIELD_CM_HL,
28639 +  AVR32_IFIELD_K12CP,
28640 +  AVR32_IFIELD_K9E,
28641 +  AVR32_IFIELD_FP_RX,
28642 +  AVR32_IFIELD_FP_RY,
28643 +  AVR32_IFIELD_FP_RD,
28644 +  AVR32_IFIELD_FP_RA,
28645 +  AVR32_IFIELD__END_,
28646 +};
28647 +#define AVR32_NR_IFIELDS AVR32_IFIELD__END_
28648 +
28649 +enum avr32_opc_type
28650 +{
28651 +  AVR32_OPC_ABS,
28652 +  AVR32_OPC_ACALL,
28653 +  AVR32_OPC_ACR,
28654 +  AVR32_OPC_ADC,
28655 +  AVR32_OPC_ADD1,
28656 +  AVR32_OPC_ADD2,
28657 +  AVR32_OPC_ADDABS,
28658 +  AVR32_OPC_ADDHH_W,
28659 +  AVR32_OPC_AND1,
28660 +  AVR32_OPC_AND2,
28661 +  AVR32_OPC_AND3,
28662 +  AVR32_OPC_ANDH,
28663 +  AVR32_OPC_ANDH_COH,
28664 +  AVR32_OPC_ANDL,
28665 +  AVR32_OPC_ANDL_COH,
28666 +  AVR32_OPC_ANDN,
28667 +  AVR32_OPC_ASR1,
28668 +  AVR32_OPC_ASR3,
28669 +  AVR32_OPC_ASR2,
28670 +  AVR32_OPC_BLD,
28671 +  AVR32_OPC_BREQ1,
28672 +  AVR32_OPC_BRNE1,
28673 +  AVR32_OPC_BRCC1,
28674 +  AVR32_OPC_BRCS1,
28675 +  AVR32_OPC_BRGE1,
28676 +  AVR32_OPC_BRLT1,
28677 +  AVR32_OPC_BRMI1,
28678 +  AVR32_OPC_BRPL1,
28679 +  AVR32_OPC_BREQ2,
28680 +  AVR32_OPC_BRNE2,
28681 +  AVR32_OPC_BRCC2,
28682 +  AVR32_OPC_BRCS2,
28683 +  AVR32_OPC_BRGE2,
28684 +  AVR32_OPC_BRLT2,
28685 +  AVR32_OPC_BRMI2,
28686 +  AVR32_OPC_BRPL2,
28687 +  AVR32_OPC_BRLS,
28688 +  AVR32_OPC_BRGT,
28689 +  AVR32_OPC_BRLE,
28690 +  AVR32_OPC_BRHI,
28691 +  AVR32_OPC_BRVS,
28692 +  AVR32_OPC_BRVC,
28693 +  AVR32_OPC_BRQS,
28694 +  AVR32_OPC_BRAL,
28695 +  AVR32_OPC_BREAKPOINT,
28696 +  AVR32_OPC_BREV,
28697 +  AVR32_OPC_BST,
28698 +  AVR32_OPC_CACHE,
28699 +  AVR32_OPC_CASTS_B,
28700 +  AVR32_OPC_CASTS_H,
28701 +  AVR32_OPC_CASTU_B,
28702 +  AVR32_OPC_CASTU_H,
28703 +  AVR32_OPC_CBR,
28704 +  AVR32_OPC_CLZ,
28705 +  AVR32_OPC_COM,
28706 +  AVR32_OPC_COP,
28707 +  AVR32_OPC_CP_B,
28708 +  AVR32_OPC_CP_H,
28709 +  AVR32_OPC_CP_W1,
28710 +  AVR32_OPC_CP_W2,
28711 +  AVR32_OPC_CP_W3,
28712 +  AVR32_OPC_CPC1,
28713 +  AVR32_OPC_CPC2,
28714 +  AVR32_OPC_CSRF,
28715 +  AVR32_OPC_CSRFCZ,
28716 +  AVR32_OPC_DIVS,
28717 +  AVR32_OPC_DIVU,
28718 +  AVR32_OPC_EOR1,
28719 +  AVR32_OPC_EOR2,
28720 +  AVR32_OPC_EOR3,
28721 +  AVR32_OPC_EORL,
28722 +  AVR32_OPC_EORH,
28723 +  AVR32_OPC_FRS,
28724 +  AVR32_OPC_ICALL,
28725 +  AVR32_OPC_INCJOSP,
28726 +  AVR32_OPC_LD_D1,
28727 +  AVR32_OPC_LD_D2,
28728 +  AVR32_OPC_LD_D3,
28729 +  AVR32_OPC_LD_D5,
28730 +  AVR32_OPC_LD_D4,
28731 +  AVR32_OPC_LD_SB2,
28732 +  AVR32_OPC_LD_SB1,
28733 +  AVR32_OPC_LD_UB1,
28734 +  AVR32_OPC_LD_UB2,
28735 +  AVR32_OPC_LD_UB5,
28736 +  AVR32_OPC_LD_UB3,
28737 +  AVR32_OPC_LD_UB4,
28738 +  AVR32_OPC_LD_SH1,
28739 +  AVR32_OPC_LD_SH2,
28740 +  AVR32_OPC_LD_SH5,
28741 +  AVR32_OPC_LD_SH3,
28742 +  AVR32_OPC_LD_SH4,
28743 +  AVR32_OPC_LD_UH1,
28744 +  AVR32_OPC_LD_UH2,
28745 +  AVR32_OPC_LD_UH5,
28746 +  AVR32_OPC_LD_UH3,
28747 +  AVR32_OPC_LD_UH4,
28748 +  AVR32_OPC_LD_W1,
28749 +  AVR32_OPC_LD_W2,
28750 +  AVR32_OPC_LD_W5,
28751 +  AVR32_OPC_LD_W6,
28752 +  AVR32_OPC_LD_W3,
28753 +  AVR32_OPC_LD_W4,
28754 +  AVR32_OPC_LDC_D1,
28755 +  AVR32_OPC_LDC_D2,
28756 +  AVR32_OPC_LDC_D3,
28757 +  AVR32_OPC_LDC_W1,
28758 +  AVR32_OPC_LDC_W2,
28759 +  AVR32_OPC_LDC_W3,
28760 +  AVR32_OPC_LDC0_D,
28761 +  AVR32_OPC_LDC0_W,
28762 +  AVR32_OPC_LDCM_D,
28763 +  AVR32_OPC_LDCM_D_PU,
28764 +  AVR32_OPC_LDCM_W,
28765 +  AVR32_OPC_LDCM_W_PU,
28766 +  AVR32_OPC_LDDPC,
28767 +  AVR32_OPC_LDDPC_EXT,
28768 +  AVR32_OPC_LDDSP,
28769 +  AVR32_OPC_LDINS_B,
28770 +  AVR32_OPC_LDINS_H,
28771 +  AVR32_OPC_LDM,
28772 +  AVR32_OPC_LDMTS,
28773 +  AVR32_OPC_LDMTS_PU,
28774 +  AVR32_OPC_LDSWP_SH,
28775 +  AVR32_OPC_LDSWP_UH,
28776 +  AVR32_OPC_LDSWP_W,
28777 +  AVR32_OPC_LSL1,
28778 +  AVR32_OPC_LSL3,
28779 +  AVR32_OPC_LSL2,
28780 +  AVR32_OPC_LSR1,
28781 +  AVR32_OPC_LSR3,
28782 +  AVR32_OPC_LSR2,
28783 +  AVR32_OPC_MAC,
28784 +  AVR32_OPC_MACHH_D,
28785 +  AVR32_OPC_MACHH_W,
28786 +  AVR32_OPC_MACS_D,
28787 +  AVR32_OPC_MACSATHH_W,
28788 +  AVR32_OPC_MACUD,
28789 +  AVR32_OPC_MACWH_D,
28790 +  AVR32_OPC_MAX,
28791 +  AVR32_OPC_MCALL,
28792 +  AVR32_OPC_MFDR,
28793 +  AVR32_OPC_MFSR,
28794 +  AVR32_OPC_MIN,
28795 +  AVR32_OPC_MOV3,
28796 +  AVR32_OPC_MOV1,
28797 +  AVR32_OPC_MOV2,
28798 +  AVR32_OPC_MOVEQ1,
28799 +  AVR32_OPC_MOVNE1,
28800 +  AVR32_OPC_MOVCC1,
28801 +  AVR32_OPC_MOVCS1,
28802 +  AVR32_OPC_MOVGE1,
28803 +  AVR32_OPC_MOVLT1,
28804 +  AVR32_OPC_MOVMI1,
28805 +  AVR32_OPC_MOVPL1,
28806 +  AVR32_OPC_MOVLS1,
28807 +  AVR32_OPC_MOVGT1,
28808 +  AVR32_OPC_MOVLE1,
28809 +  AVR32_OPC_MOVHI1,
28810 +  AVR32_OPC_MOVVS1,
28811 +  AVR32_OPC_MOVVC1,
28812 +  AVR32_OPC_MOVQS1,
28813 +  AVR32_OPC_MOVAL1,
28814 +  AVR32_OPC_MOVEQ2,
28815 +  AVR32_OPC_MOVNE2,
28816 +  AVR32_OPC_MOVCC2,
28817 +  AVR32_OPC_MOVCS2,
28818 +  AVR32_OPC_MOVGE2,
28819 +  AVR32_OPC_MOVLT2,
28820 +  AVR32_OPC_MOVMI2,
28821 +  AVR32_OPC_MOVPL2,
28822 +  AVR32_OPC_MOVLS2,
28823 +  AVR32_OPC_MOVGT2,
28824 +  AVR32_OPC_MOVLE2,
28825 +  AVR32_OPC_MOVHI2,
28826 +  AVR32_OPC_MOVVS2,
28827 +  AVR32_OPC_MOVVC2,
28828 +  AVR32_OPC_MOVQS2,
28829 +  AVR32_OPC_MOVAL2,
28830 +  AVR32_OPC_MTDR,
28831 +  AVR32_OPC_MTSR,
28832 +  AVR32_OPC_MUL1,
28833 +  AVR32_OPC_MUL2,
28834 +  AVR32_OPC_MUL3,
28835 +  AVR32_OPC_MULHH_W,
28836 +  AVR32_OPC_MULNHH_W,
28837 +  AVR32_OPC_MULNWH_D,
28838 +  AVR32_OPC_MULSD,
28839 +  AVR32_OPC_MULSATHH_H,
28840 +  AVR32_OPC_MULSATHH_W,
28841 +  AVR32_OPC_MULSATRNDHH_H,
28842 +  AVR32_OPC_MULSATRNDWH_W,
28843 +  AVR32_OPC_MULSATWH_W,
28844 +  AVR32_OPC_MULU_D,
28845 +  AVR32_OPC_MULWH_D,
28846 +  AVR32_OPC_MUSFR,
28847 +  AVR32_OPC_MUSTR,
28848 +  AVR32_OPC_MVCR_D,
28849 +  AVR32_OPC_MVCR_W,
28850 +  AVR32_OPC_MVRC_D,
28851 +  AVR32_OPC_MVRC_W,
28852 +  AVR32_OPC_NEG,
28853 +  AVR32_OPC_NOP,
28854 +  AVR32_OPC_OR1,
28855 +  AVR32_OPC_OR2,
28856 +  AVR32_OPC_OR3,
28857 +  AVR32_OPC_ORH,
28858 +  AVR32_OPC_ORL,
28859 +  AVR32_OPC_PABS_SB,
28860 +  AVR32_OPC_PABS_SH,
28861 +  AVR32_OPC_PACKSH_SB,
28862 +  AVR32_OPC_PACKSH_UB,
28863 +  AVR32_OPC_PACKW_SH,
28864 +  AVR32_OPC_PADD_B,
28865 +  AVR32_OPC_PADD_H,
28866 +  AVR32_OPC_PADDH_SH,
28867 +  AVR32_OPC_PADDH_UB,
28868 +  AVR32_OPC_PADDS_SB,
28869 +  AVR32_OPC_PADDS_SH,
28870 +  AVR32_OPC_PADDS_UB,
28871 +  AVR32_OPC_PADDS_UH,
28872 +  AVR32_OPC_PADDSUB_H,
28873 +  AVR32_OPC_PADDSUBH_SH,
28874 +  AVR32_OPC_PADDSUBS_SH,
28875 +  AVR32_OPC_PADDSUBS_UH,
28876 +  AVR32_OPC_PADDX_H,
28877 +  AVR32_OPC_PADDXH_SH,
28878 +  AVR32_OPC_PADDXS_SH,
28879 +  AVR32_OPC_PADDXS_UH,
28880 +  AVR32_OPC_PASR_B,
28881 +  AVR32_OPC_PASR_H,
28882 +  AVR32_OPC_PAVG_SH,
28883 +  AVR32_OPC_PAVG_UB,
28884 +  AVR32_OPC_PLSL_B,
28885 +  AVR32_OPC_PLSL_H,
28886 +  AVR32_OPC_PLSR_B,
28887 +  AVR32_OPC_PLSR_H,
28888 +  AVR32_OPC_PMAX_SH,
28889 +  AVR32_OPC_PMAX_UB,
28890 +  AVR32_OPC_PMIN_SH,
28891 +  AVR32_OPC_PMIN_UB,
28892 +  AVR32_OPC_POPJC,
28893 +  AVR32_OPC_POPM,
28894 +  AVR32_OPC_POPM_E,
28895 +  AVR32_OPC_PREF,
28896 +  AVR32_OPC_PSAD,
28897 +  AVR32_OPC_PSUB_B,
28898 +  AVR32_OPC_PSUB_H,
28899 +  AVR32_OPC_PSUBADD_H,
28900 +  AVR32_OPC_PSUBADDH_SH,
28901 +  AVR32_OPC_PSUBADDS_SH,
28902 +  AVR32_OPC_PSUBADDS_UH,
28903 +  AVR32_OPC_PSUBH_SH,
28904 +  AVR32_OPC_PSUBH_UB,
28905 +  AVR32_OPC_PSUBS_SB,
28906 +  AVR32_OPC_PSUBS_SH,
28907 +  AVR32_OPC_PSUBS_UB,
28908 +  AVR32_OPC_PSUBS_UH,
28909 +  AVR32_OPC_PSUBX_H,
28910 +  AVR32_OPC_PSUBXH_SH,
28911 +  AVR32_OPC_PSUBXS_SH,
28912 +  AVR32_OPC_PSUBXS_UH,
28913 +  AVR32_OPC_PUNPCKSB_H,
28914 +  AVR32_OPC_PUNPCKUB_H,
28915 +  AVR32_OPC_PUSHJC,
28916 +  AVR32_OPC_PUSHM,
28917 +  AVR32_OPC_PUSHM_E,
28918 +  AVR32_OPC_RCALL1,
28919 +  AVR32_OPC_RCALL2,
28920 +  AVR32_OPC_RETEQ,
28921 +  AVR32_OPC_RETNE,
28922 +  AVR32_OPC_RETCC,
28923 +  AVR32_OPC_RETCS,
28924 +  AVR32_OPC_RETGE,
28925 +  AVR32_OPC_RETLT,
28926 +  AVR32_OPC_RETMI,
28927 +  AVR32_OPC_RETPL,
28928 +  AVR32_OPC_RETLS,
28929 +  AVR32_OPC_RETGT,
28930 +  AVR32_OPC_RETLE,
28931 +  AVR32_OPC_RETHI,
28932 +  AVR32_OPC_RETVS,
28933 +  AVR32_OPC_RETVC,
28934 +  AVR32_OPC_RETQS,
28935 +  AVR32_OPC_RETAL,
28936 +  AVR32_OPC_RETD,
28937 +  AVR32_OPC_RETE,
28938 +  AVR32_OPC_RETJ,
28939 +  AVR32_OPC_RETS,
28940 +  AVR32_OPC_RJMP,
28941 +  AVR32_OPC_ROL,
28942 +  AVR32_OPC_ROR,
28943 +  AVR32_OPC_RSUB1,
28944 +  AVR32_OPC_RSUB2,
28945 +  AVR32_OPC_SATADD_H,
28946 +  AVR32_OPC_SATADD_W,
28947 +  AVR32_OPC_SATRNDS,
28948 +  AVR32_OPC_SATRNDU,
28949 +  AVR32_OPC_SATS,
28950 +  AVR32_OPC_SATSUB_H,
28951 +  AVR32_OPC_SATSUB_W1,
28952 +  AVR32_OPC_SATSUB_W2,
28953 +  AVR32_OPC_SATU,
28954 +  AVR32_OPC_SBC,
28955 +  AVR32_OPC_SBR,
28956 +  AVR32_OPC_SCALL,
28957 +  AVR32_OPC_SCR,
28958 +  AVR32_OPC_SLEEP,
28959 +  AVR32_OPC_SREQ,
28960 +  AVR32_OPC_SRNE,
28961 +  AVR32_OPC_SRCC,
28962 +  AVR32_OPC_SRCS,
28963 +  AVR32_OPC_SRGE,
28964 +  AVR32_OPC_SRLT,
28965 +  AVR32_OPC_SRMI,
28966 +  AVR32_OPC_SRPL,
28967 +  AVR32_OPC_SRLS,
28968 +  AVR32_OPC_SRGT,
28969 +  AVR32_OPC_SRLE,
28970 +  AVR32_OPC_SRHI,
28971 +  AVR32_OPC_SRVS,
28972 +  AVR32_OPC_SRVC,
28973 +  AVR32_OPC_SRQS,
28974 +  AVR32_OPC_SRAL,
28975 +  AVR32_OPC_SSRF,
28976 +  AVR32_OPC_ST_B1,
28977 +  AVR32_OPC_ST_B2,
28978 +  AVR32_OPC_ST_B5,
28979 +  AVR32_OPC_ST_B3,
28980 +  AVR32_OPC_ST_B4,
28981 +  AVR32_OPC_ST_D1,
28982 +  AVR32_OPC_ST_D2,
28983 +  AVR32_OPC_ST_D3,
28984 +  AVR32_OPC_ST_D5,
28985 +  AVR32_OPC_ST_D4,
28986 +  AVR32_OPC_ST_H1,
28987 +  AVR32_OPC_ST_H2,
28988 +  AVR32_OPC_ST_H5,
28989 +  AVR32_OPC_ST_H3,
28990 +  AVR32_OPC_ST_H4,
28991 +  AVR32_OPC_ST_W1,
28992 +  AVR32_OPC_ST_W2,
28993 +  AVR32_OPC_ST_W5,
28994 +  AVR32_OPC_ST_W3,
28995 +  AVR32_OPC_ST_W4,
28996 +  AVR32_OPC_STC_D1,
28997 +  AVR32_OPC_STC_D2,
28998 +  AVR32_OPC_STC_D3,
28999 +  AVR32_OPC_STC_W1,
29000 +  AVR32_OPC_STC_W2,
29001 +  AVR32_OPC_STC_W3,
29002 +  AVR32_OPC_STC0_D,
29003 +  AVR32_OPC_STC0_W,
29004 +  AVR32_OPC_STCM_D,
29005 +  AVR32_OPC_STCM_D_PU,
29006 +  AVR32_OPC_STCM_W,
29007 +  AVR32_OPC_STCM_W_PU,
29008 +  AVR32_OPC_STCOND,
29009 +  AVR32_OPC_STDSP,
29010 +  AVR32_OPC_STHH_W2,
29011 +  AVR32_OPC_STHH_W1,
29012 +  AVR32_OPC_STM,
29013 +  AVR32_OPC_STM_PU,
29014 +  AVR32_OPC_STMTS,
29015 +  AVR32_OPC_STMTS_PU,
29016 +  AVR32_OPC_STSWP_H,
29017 +  AVR32_OPC_STSWP_W,
29018 +  AVR32_OPC_SUB1,
29019 +  AVR32_OPC_SUB2,
29020 +  AVR32_OPC_SUB5,
29021 +  AVR32_OPC_SUB3_SP,
29022 +  AVR32_OPC_SUB3,
29023 +  AVR32_OPC_SUB4,
29024 +  AVR32_OPC_SUBEQ,
29025 +  AVR32_OPC_SUBNE,
29026 +  AVR32_OPC_SUBCC,
29027 +  AVR32_OPC_SUBCS,
29028 +  AVR32_OPC_SUBGE,
29029 +  AVR32_OPC_SUBLT,
29030 +  AVR32_OPC_SUBMI,
29031 +  AVR32_OPC_SUBPL,
29032 +  AVR32_OPC_SUBLS,
29033 +  AVR32_OPC_SUBGT,
29034 +  AVR32_OPC_SUBLE,
29035 +  AVR32_OPC_SUBHI,
29036 +  AVR32_OPC_SUBVS,
29037 +  AVR32_OPC_SUBVC,
29038 +  AVR32_OPC_SUBQS,
29039 +  AVR32_OPC_SUBAL,
29040 +  AVR32_OPC_SUBFEQ,
29041 +  AVR32_OPC_SUBFNE,
29042 +  AVR32_OPC_SUBFCC,
29043 +  AVR32_OPC_SUBFCS,
29044 +  AVR32_OPC_SUBFGE,
29045 +  AVR32_OPC_SUBFLT,
29046 +  AVR32_OPC_SUBFMI,
29047 +  AVR32_OPC_SUBFPL,
29048 +  AVR32_OPC_SUBFLS,
29049 +  AVR32_OPC_SUBFGT,
29050 +  AVR32_OPC_SUBFLE,
29051 +  AVR32_OPC_SUBFHI,
29052 +  AVR32_OPC_SUBFVS,
29053 +  AVR32_OPC_SUBFVC,
29054 +  AVR32_OPC_SUBFQS,
29055 +  AVR32_OPC_SUBFAL,
29056 +  AVR32_OPC_SUBHH_W,
29057 +  AVR32_OPC_SWAP_B,
29058 +  AVR32_OPC_SWAP_BH,
29059 +  AVR32_OPC_SWAP_H,
29060 +  AVR32_OPC_SYNC,
29061 +  AVR32_OPC_TLBR,
29062 +  AVR32_OPC_TLBS,
29063 +  AVR32_OPC_TLBW,
29064 +  AVR32_OPC_TNBZ,
29065 +  AVR32_OPC_TST,
29066 +  AVR32_OPC_XCHG,
29067 +  AVR32_OPC_MEMC,
29068 +  AVR32_OPC_MEMS,
29069 +  AVR32_OPC_MEMT,
29070 +  AVR32_OPC_BFEXTS,
29071 +  AVR32_OPC_BFEXTU,
29072 +  AVR32_OPC_BFINS,
29073 +  AVR32_OPC_RSUBEQ,
29074 +  AVR32_OPC_RSUBNE,
29075 +  AVR32_OPC_RSUBCC,
29076 +  AVR32_OPC_RSUBCS,
29077 +  AVR32_OPC_RSUBGE,
29078 +  AVR32_OPC_RSUBLT,
29079 +  AVR32_OPC_RSUBMI,
29080 +  AVR32_OPC_RSUBPL,
29081 +  AVR32_OPC_RSUBLS,
29082 +  AVR32_OPC_RSUBGT,
29083 +  AVR32_OPC_RSUBLE,
29084 +  AVR32_OPC_RSUBHI,
29085 +  AVR32_OPC_RSUBVS,
29086 +  AVR32_OPC_RSUBVC,
29087 +  AVR32_OPC_RSUBQS,
29088 +  AVR32_OPC_RSUBAL,
29089 +  AVR32_OPC_ADDEQ,
29090 +  AVR32_OPC_ADDNE,
29091 +  AVR32_OPC_ADDCC,
29092 +  AVR32_OPC_ADDCS,
29093 +  AVR32_OPC_ADDGE,
29094 +  AVR32_OPC_ADDLT,
29095 +  AVR32_OPC_ADDMI,
29096 +  AVR32_OPC_ADDPL,
29097 +  AVR32_OPC_ADDLS,
29098 +  AVR32_OPC_ADDGT,
29099 +  AVR32_OPC_ADDLE,
29100 +  AVR32_OPC_ADDHI,
29101 +  AVR32_OPC_ADDVS,
29102 +  AVR32_OPC_ADDVC,
29103 +  AVR32_OPC_ADDQS,
29104 +  AVR32_OPC_ADDAL,
29105 +  AVR32_OPC_SUB2EQ,
29106 +  AVR32_OPC_SUB2NE,
29107 +  AVR32_OPC_SUB2CC,
29108 +  AVR32_OPC_SUB2CS,
29109 +  AVR32_OPC_SUB2GE,
29110 +  AVR32_OPC_SUB2LT,
29111 +  AVR32_OPC_SUB2MI,
29112 +  AVR32_OPC_SUB2PL,
29113 +  AVR32_OPC_SUB2LS,
29114 +  AVR32_OPC_SUB2GT,
29115 +  AVR32_OPC_SUB2LE,
29116 +  AVR32_OPC_SUB2HI,
29117 +  AVR32_OPC_SUB2VS,
29118 +  AVR32_OPC_SUB2VC,
29119 +  AVR32_OPC_SUB2QS,
29120 +  AVR32_OPC_SUB2AL,
29121 +  AVR32_OPC_ANDEQ,
29122 +  AVR32_OPC_ANDNE,
29123 +  AVR32_OPC_ANDCC,
29124 +  AVR32_OPC_ANDCS,
29125 +  AVR32_OPC_ANDGE,
29126 +  AVR32_OPC_ANDLT,
29127 +  AVR32_OPC_ANDMI,
29128 +  AVR32_OPC_ANDPL,
29129 +  AVR32_OPC_ANDLS,
29130 +  AVR32_OPC_ANDGT,
29131 +  AVR32_OPC_ANDLE,
29132 +  AVR32_OPC_ANDHI,
29133 +  AVR32_OPC_ANDVS,
29134 +  AVR32_OPC_ANDVC,
29135 +  AVR32_OPC_ANDQS,
29136 +  AVR32_OPC_ANDAL,
29137 +  AVR32_OPC_OREQ,
29138 +  AVR32_OPC_ORNE,
29139 +  AVR32_OPC_ORCC,
29140 +  AVR32_OPC_ORCS,
29141 +  AVR32_OPC_ORGE,
29142 +  AVR32_OPC_ORLT,
29143 +  AVR32_OPC_ORMI,
29144 +  AVR32_OPC_ORPL,
29145 +  AVR32_OPC_ORLS,
29146 +  AVR32_OPC_ORGT,
29147 +  AVR32_OPC_ORLE,
29148 +  AVR32_OPC_ORHI,
29149 +  AVR32_OPC_ORVS,
29150 +  AVR32_OPC_ORVC,
29151 +  AVR32_OPC_ORQS,
29152 +  AVR32_OPC_ORAL,
29153 +  AVR32_OPC_EOREQ,
29154 +  AVR32_OPC_EORNE,
29155 +  AVR32_OPC_EORCC,
29156 +  AVR32_OPC_EORCS,
29157 +  AVR32_OPC_EORGE,
29158 +  AVR32_OPC_EORLT,
29159 +  AVR32_OPC_EORMI,
29160 +  AVR32_OPC_EORPL,
29161 +  AVR32_OPC_EORLS,
29162 +  AVR32_OPC_EORGT,
29163 +  AVR32_OPC_EORLE,
29164 +  AVR32_OPC_EORHI,
29165 +  AVR32_OPC_EORVS,
29166 +  AVR32_OPC_EORVC,
29167 +  AVR32_OPC_EORQS,
29168 +  AVR32_OPC_EORAL,
29169 +  AVR32_OPC_LD_WEQ,
29170 +  AVR32_OPC_LD_WNE,
29171 +  AVR32_OPC_LD_WCC,
29172 +  AVR32_OPC_LD_WCS,
29173 +  AVR32_OPC_LD_WGE,
29174 +  AVR32_OPC_LD_WLT,
29175 +  AVR32_OPC_LD_WMI,
29176 +  AVR32_OPC_LD_WPL,
29177 +  AVR32_OPC_LD_WLS,
29178 +  AVR32_OPC_LD_WGT,
29179 +  AVR32_OPC_LD_WLE,
29180 +  AVR32_OPC_LD_WHI,
29181 +  AVR32_OPC_LD_WVS,
29182 +  AVR32_OPC_LD_WVC,
29183 +  AVR32_OPC_LD_WQS,
29184 +  AVR32_OPC_LD_WAL,
29185 +  AVR32_OPC_LD_SHEQ,
29186 +  AVR32_OPC_LD_SHNE,
29187 +  AVR32_OPC_LD_SHCC,
29188 +  AVR32_OPC_LD_SHCS,
29189 +  AVR32_OPC_LD_SHGE,
29190 +  AVR32_OPC_LD_SHLT,
29191 +  AVR32_OPC_LD_SHMI,
29192 +  AVR32_OPC_LD_SHPL,
29193 +  AVR32_OPC_LD_SHLS,
29194 +  AVR32_OPC_LD_SHGT,
29195 +  AVR32_OPC_LD_SHLE,
29196 +  AVR32_OPC_LD_SHHI,
29197 +  AVR32_OPC_LD_SHVS,
29198 +  AVR32_OPC_LD_SHVC,
29199 +  AVR32_OPC_LD_SHQS,
29200 +  AVR32_OPC_LD_SHAL,
29201 +  AVR32_OPC_LD_UHEQ,
29202 +  AVR32_OPC_LD_UHNE,
29203 +  AVR32_OPC_LD_UHCC,
29204 +  AVR32_OPC_LD_UHCS,
29205 +  AVR32_OPC_LD_UHGE,
29206 +  AVR32_OPC_LD_UHLT,
29207 +  AVR32_OPC_LD_UHMI,
29208 +  AVR32_OPC_LD_UHPL,
29209 +  AVR32_OPC_LD_UHLS,
29210 +  AVR32_OPC_LD_UHGT,
29211 +  AVR32_OPC_LD_UHLE,
29212 +  AVR32_OPC_LD_UHHI,
29213 +  AVR32_OPC_LD_UHVS,
29214 +  AVR32_OPC_LD_UHVC,
29215 +  AVR32_OPC_LD_UHQS,
29216 +  AVR32_OPC_LD_UHAL,
29217 +  AVR32_OPC_LD_SBEQ,
29218 +  AVR32_OPC_LD_SBNE,
29219 +  AVR32_OPC_LD_SBCC,
29220 +  AVR32_OPC_LD_SBCS,
29221 +  AVR32_OPC_LD_SBGE,
29222 +  AVR32_OPC_LD_SBLT,
29223 +  AVR32_OPC_LD_SBMI,
29224 +  AVR32_OPC_LD_SBPL,
29225 +  AVR32_OPC_LD_SBLS,
29226 +  AVR32_OPC_LD_SBGT,
29227 +  AVR32_OPC_LD_SBLE,
29228 +  AVR32_OPC_LD_SBHI,
29229 +  AVR32_OPC_LD_SBVS,
29230 +  AVR32_OPC_LD_SBVC,
29231 +  AVR32_OPC_LD_SBQS,
29232 +  AVR32_OPC_LD_SBAL,
29233 +  AVR32_OPC_LD_UBEQ,
29234 +  AVR32_OPC_LD_UBNE,
29235 +  AVR32_OPC_LD_UBCC,
29236 +  AVR32_OPC_LD_UBCS,
29237 +  AVR32_OPC_LD_UBGE,
29238 +  AVR32_OPC_LD_UBLT,
29239 +  AVR32_OPC_LD_UBMI,
29240 +  AVR32_OPC_LD_UBPL,
29241 +  AVR32_OPC_LD_UBLS,
29242 +  AVR32_OPC_LD_UBGT,
29243 +  AVR32_OPC_LD_UBLE,
29244 +  AVR32_OPC_LD_UBHI,
29245 +  AVR32_OPC_LD_UBVS,
29246 +  AVR32_OPC_LD_UBVC,
29247 +  AVR32_OPC_LD_UBQS,
29248 +  AVR32_OPC_LD_UBAL,
29249 +  AVR32_OPC_ST_WEQ,
29250 +  AVR32_OPC_ST_WNE,
29251 +  AVR32_OPC_ST_WCC,
29252 +  AVR32_OPC_ST_WCS,
29253 +  AVR32_OPC_ST_WGE,
29254 +  AVR32_OPC_ST_WLT,
29255 +  AVR32_OPC_ST_WMI,
29256 +  AVR32_OPC_ST_WPL,
29257 +  AVR32_OPC_ST_WLS,
29258 +  AVR32_OPC_ST_WGT,
29259 +  AVR32_OPC_ST_WLE,
29260 +  AVR32_OPC_ST_WHI,
29261 +  AVR32_OPC_ST_WVS,
29262 +  AVR32_OPC_ST_WVC,
29263 +  AVR32_OPC_ST_WQS,
29264 +  AVR32_OPC_ST_WAL,
29265 +  AVR32_OPC_ST_HEQ,
29266 +  AVR32_OPC_ST_HNE,
29267 +  AVR32_OPC_ST_HCC,
29268 +  AVR32_OPC_ST_HCS,
29269 +  AVR32_OPC_ST_HGE,
29270 +  AVR32_OPC_ST_HLT,
29271 +  AVR32_OPC_ST_HMI,
29272 +  AVR32_OPC_ST_HPL,
29273 +  AVR32_OPC_ST_HLS,
29274 +  AVR32_OPC_ST_HGT,
29275 +  AVR32_OPC_ST_HLE,
29276 +  AVR32_OPC_ST_HHI,
29277 +  AVR32_OPC_ST_HVS,
29278 +  AVR32_OPC_ST_HVC,
29279 +  AVR32_OPC_ST_HQS,
29280 +  AVR32_OPC_ST_HAL,
29281 +  AVR32_OPC_ST_BEQ,
29282 +  AVR32_OPC_ST_BNE,
29283 +  AVR32_OPC_ST_BCC,
29284 +  AVR32_OPC_ST_BCS,
29285 +  AVR32_OPC_ST_BGE,
29286 +  AVR32_OPC_ST_BLT,
29287 +  AVR32_OPC_ST_BMI,
29288 +  AVR32_OPC_ST_BPL,
29289 +  AVR32_OPC_ST_BLS,
29290 +  AVR32_OPC_ST_BGT,
29291 +  AVR32_OPC_ST_BLE,
29292 +  AVR32_OPC_ST_BHI,
29293 +  AVR32_OPC_ST_BVS,
29294 +  AVR32_OPC_ST_BVC,
29295 +  AVR32_OPC_ST_BQS,
29296 +  AVR32_OPC_ST_BAL,
29297 +  AVR32_OPC_MOVH,
29298 +  AVR32_OPC_SSCALL,
29299 +  AVR32_OPC_RETSS,
29300 +  AVR32_OPC_FMAC_S,
29301 +  AVR32_OPC_FNMAC_S,
29302 +  AVR32_OPC_FMSC_S,
29303 +  AVR32_OPC_FNMSC_S,
29304 +  AVR32_OPC_FMUL_S,
29305 +  AVR32_OPC_FNMUL_S,
29306 +  AVR32_OPC_FADD_S,
29307 +  AVR32_OPC_FSUB_S,
29308 +  AVR32_OPC_FCASTRS_SW,
29309 +  AVR32_OPC_FCASTRS_UW,
29310 +  AVR32_OPC_FCASTSW_S,
29311 +  AVR32_OPC_FCASTUW_S,
29312 +  AVR32_OPC_FCMP_S,
29313 +  AVR32_OPC_FCHK_S,
29314 +  AVR32_OPC_FRCPA_S,
29315 +  AVR32_OPC_FRSQRTA_S,
29316 +  AVR32_OPC__END_
29317 +};
29318 +#define AVR32_NR_OPCODES AVR32_OPC__END_
29319 +
29320 +enum avr32_syntax_type
29321 +{
29322 +  AVR32_SYNTAX_ABS,
29323 +  AVR32_SYNTAX_ACALL,
29324 +  AVR32_SYNTAX_ACR,
29325 +  AVR32_SYNTAX_ADC,
29326 +  AVR32_SYNTAX_ADD1,
29327 +  AVR32_SYNTAX_ADD2,
29328 +  AVR32_SYNTAX_ADDABS,
29329 +  AVR32_SYNTAX_ADDHH_W,
29330 +  AVR32_SYNTAX_AND1,
29331 +  AVR32_SYNTAX_AND2,
29332 +  AVR32_SYNTAX_AND3,
29333 +  AVR32_SYNTAX_ANDH,
29334 +  AVR32_SYNTAX_ANDH_COH,
29335 +  AVR32_SYNTAX_ANDL,
29336 +  AVR32_SYNTAX_ANDL_COH,
29337 +  AVR32_SYNTAX_ANDN,
29338 +  AVR32_SYNTAX_ASR1,
29339 +  AVR32_SYNTAX_ASR3,
29340 +  AVR32_SYNTAX_ASR2,
29341 +  AVR32_SYNTAX_BFEXTS,
29342 +  AVR32_SYNTAX_BFEXTU,
29343 +  AVR32_SYNTAX_BFINS,
29344 +  AVR32_SYNTAX_BLD,
29345 +  AVR32_SYNTAX_BREQ1,
29346 +  AVR32_SYNTAX_BRNE1,
29347 +  AVR32_SYNTAX_BRCC1,
29348 +  AVR32_SYNTAX_BRCS1,
29349 +  AVR32_SYNTAX_BRGE1,
29350 +  AVR32_SYNTAX_BRLT1,
29351 +  AVR32_SYNTAX_BRMI1,
29352 +  AVR32_SYNTAX_BRPL1,
29353 +  AVR32_SYNTAX_BRHS1,
29354 +  AVR32_SYNTAX_BRLO1,
29355 +  AVR32_SYNTAX_BREQ2,
29356 +  AVR32_SYNTAX_BRNE2,
29357 +  AVR32_SYNTAX_BRCC2,
29358 +  AVR32_SYNTAX_BRCS2,
29359 +  AVR32_SYNTAX_BRGE2,
29360 +  AVR32_SYNTAX_BRLT2,
29361 +  AVR32_SYNTAX_BRMI2,
29362 +  AVR32_SYNTAX_BRPL2,
29363 +  AVR32_SYNTAX_BRLS,
29364 +  AVR32_SYNTAX_BRGT,
29365 +  AVR32_SYNTAX_BRLE,
29366 +  AVR32_SYNTAX_BRHI,
29367 +  AVR32_SYNTAX_BRVS,
29368 +  AVR32_SYNTAX_BRVC,
29369 +  AVR32_SYNTAX_BRQS,
29370 +  AVR32_SYNTAX_BRAL,
29371 +  AVR32_SYNTAX_BRHS2,
29372 +  AVR32_SYNTAX_BRLO2,
29373 +  AVR32_SYNTAX_BREAKPOINT,
29374 +  AVR32_SYNTAX_BREV,
29375 +  AVR32_SYNTAX_BST,
29376 +  AVR32_SYNTAX_CACHE,
29377 +  AVR32_SYNTAX_CASTS_B,
29378 +  AVR32_SYNTAX_CASTS_H,
29379 +  AVR32_SYNTAX_CASTU_B,
29380 +  AVR32_SYNTAX_CASTU_H,
29381 +  AVR32_SYNTAX_CBR,
29382 +  AVR32_SYNTAX_CLZ,
29383 +  AVR32_SYNTAX_COM,
29384 +  AVR32_SYNTAX_COP,
29385 +  AVR32_SYNTAX_CP_B,
29386 +  AVR32_SYNTAX_CP_H,
29387 +  AVR32_SYNTAX_CP_W1,
29388 +  AVR32_SYNTAX_CP_W2,
29389 +  AVR32_SYNTAX_CP_W3,
29390 +  AVR32_SYNTAX_CPC1,
29391 +  AVR32_SYNTAX_CPC2,
29392 +  AVR32_SYNTAX_CSRF,
29393 +  AVR32_SYNTAX_CSRFCZ,
29394 +  AVR32_SYNTAX_DIVS,
29395 +  AVR32_SYNTAX_DIVU,
29396 +  AVR32_SYNTAX_EOR1,
29397 +  AVR32_SYNTAX_EOR2,
29398 +  AVR32_SYNTAX_EOR3,
29399 +  AVR32_SYNTAX_EORL,
29400 +  AVR32_SYNTAX_EORH,
29401 +  AVR32_SYNTAX_FRS,
29402 +  AVR32_SYNTAX_SSCALL,
29403 +  AVR32_SYNTAX_RETSS,
29404 +  AVR32_SYNTAX_ICALL,
29405 +  AVR32_SYNTAX_INCJOSP,
29406 +  AVR32_SYNTAX_LD_D1,
29407 +  AVR32_SYNTAX_LD_D2,
29408 +  AVR32_SYNTAX_LD_D3,
29409 +  AVR32_SYNTAX_LD_D5,
29410 +  AVR32_SYNTAX_LD_D4,
29411 +  AVR32_SYNTAX_LD_SB2,
29412 +  AVR32_SYNTAX_LD_SB1,
29413 +  AVR32_SYNTAX_LD_UB1,
29414 +  AVR32_SYNTAX_LD_UB2,
29415 +  AVR32_SYNTAX_LD_UB5,
29416 +  AVR32_SYNTAX_LD_UB3,
29417 +  AVR32_SYNTAX_LD_UB4,
29418 +  AVR32_SYNTAX_LD_SH1,
29419 +  AVR32_SYNTAX_LD_SH2,
29420 +  AVR32_SYNTAX_LD_SH5,
29421 +  AVR32_SYNTAX_LD_SH3,
29422 +  AVR32_SYNTAX_LD_SH4,
29423 +  AVR32_SYNTAX_LD_UH1,
29424 +  AVR32_SYNTAX_LD_UH2,
29425 +  AVR32_SYNTAX_LD_UH5,
29426 +  AVR32_SYNTAX_LD_UH3,
29427 +  AVR32_SYNTAX_LD_UH4,
29428 +  AVR32_SYNTAX_LD_W1,
29429 +  AVR32_SYNTAX_LD_W2,
29430 +  AVR32_SYNTAX_LD_W5,
29431 +  AVR32_SYNTAX_LD_W6,
29432 +  AVR32_SYNTAX_LD_W3,
29433 +  AVR32_SYNTAX_LD_W4,
29434 +  AVR32_SYNTAX_LDC_D1,
29435 +  AVR32_SYNTAX_LDC_D2,
29436 +  AVR32_SYNTAX_LDC_D3,
29437 +  AVR32_SYNTAX_LDC_W1,
29438 +  AVR32_SYNTAX_LDC_W2,
29439 +  AVR32_SYNTAX_LDC_W3,
29440 +  AVR32_SYNTAX_LDC0_D,
29441 +  AVR32_SYNTAX_LDC0_W,
29442 +  AVR32_SYNTAX_LDCM_D,
29443 +  AVR32_SYNTAX_LDCM_D_PU,
29444 +  AVR32_SYNTAX_LDCM_W,
29445 +  AVR32_SYNTAX_LDCM_W_PU,
29446 +  AVR32_SYNTAX_LDDPC,
29447 +  AVR32_SYNTAX_LDDPC_EXT,
29448 +  AVR32_SYNTAX_LDDSP,
29449 +  AVR32_SYNTAX_LDINS_B,
29450 +  AVR32_SYNTAX_LDINS_H,
29451 +  AVR32_SYNTAX_LDM,
29452 +  AVR32_SYNTAX_LDMTS,
29453 +  AVR32_SYNTAX_LDMTS_PU,
29454 +  AVR32_SYNTAX_LDSWP_SH,
29455 +  AVR32_SYNTAX_LDSWP_UH,
29456 +  AVR32_SYNTAX_LDSWP_W,
29457 +  AVR32_SYNTAX_LSL1,
29458 +  AVR32_SYNTAX_LSL3,
29459 +  AVR32_SYNTAX_LSL2,
29460 +  AVR32_SYNTAX_LSR1,
29461 +  AVR32_SYNTAX_LSR3,
29462 +  AVR32_SYNTAX_LSR2,
29463 +  AVR32_SYNTAX_MAC,
29464 +  AVR32_SYNTAX_MACHH_D,
29465 +  AVR32_SYNTAX_MACHH_W,
29466 +  AVR32_SYNTAX_MACS_D,
29467 +  AVR32_SYNTAX_MACSATHH_W,
29468 +  AVR32_SYNTAX_MACUD,
29469 +  AVR32_SYNTAX_MACWH_D,
29470 +  AVR32_SYNTAX_MAX,
29471 +  AVR32_SYNTAX_MCALL,
29472 +  AVR32_SYNTAX_MFDR,
29473 +  AVR32_SYNTAX_MFSR,
29474 +  AVR32_SYNTAX_MIN,
29475 +  AVR32_SYNTAX_MOV3,
29476 +  AVR32_SYNTAX_MOV1,
29477 +  AVR32_SYNTAX_MOV2,
29478 +  AVR32_SYNTAX_MOVEQ1,
29479 +  AVR32_SYNTAX_MOVNE1,
29480 +  AVR32_SYNTAX_MOVCC1,
29481 +  AVR32_SYNTAX_MOVCS1,
29482 +  AVR32_SYNTAX_MOVGE1,
29483 +  AVR32_SYNTAX_MOVLT1,
29484 +  AVR32_SYNTAX_MOVMI1,
29485 +  AVR32_SYNTAX_MOVPL1,
29486 +  AVR32_SYNTAX_MOVLS1,
29487 +  AVR32_SYNTAX_MOVGT1,
29488 +  AVR32_SYNTAX_MOVLE1,
29489 +  AVR32_SYNTAX_MOVHI1,
29490 +  AVR32_SYNTAX_MOVVS1,
29491 +  AVR32_SYNTAX_MOVVC1,
29492 +  AVR32_SYNTAX_MOVQS1,
29493 +  AVR32_SYNTAX_MOVAL1,
29494 +  AVR32_SYNTAX_MOVHS1,
29495 +  AVR32_SYNTAX_MOVLO1,
29496 +  AVR32_SYNTAX_MOVEQ2,
29497 +  AVR32_SYNTAX_MOVNE2,
29498 +  AVR32_SYNTAX_MOVCC2,
29499 +  AVR32_SYNTAX_MOVCS2,
29500 +  AVR32_SYNTAX_MOVGE2,
29501 +  AVR32_SYNTAX_MOVLT2,
29502 +  AVR32_SYNTAX_MOVMI2,
29503 +  AVR32_SYNTAX_MOVPL2,
29504 +  AVR32_SYNTAX_MOVLS2,
29505 +  AVR32_SYNTAX_MOVGT2,
29506 +  AVR32_SYNTAX_MOVLE2,
29507 +  AVR32_SYNTAX_MOVHI2,
29508 +  AVR32_SYNTAX_MOVVS2,
29509 +  AVR32_SYNTAX_MOVVC2,
29510 +  AVR32_SYNTAX_MOVQS2,
29511 +  AVR32_SYNTAX_MOVAL2,
29512 +  AVR32_SYNTAX_MOVHS2,
29513 +  AVR32_SYNTAX_MOVLO2,
29514 +  AVR32_SYNTAX_MTDR,
29515 +  AVR32_SYNTAX_MTSR,
29516 +  AVR32_SYNTAX_MUL1,
29517 +  AVR32_SYNTAX_MUL2,
29518 +  AVR32_SYNTAX_MUL3,
29519 +  AVR32_SYNTAX_MULHH_W,
29520 +  AVR32_SYNTAX_MULNHH_W,
29521 +  AVR32_SYNTAX_MULNWH_D,
29522 +  AVR32_SYNTAX_MULSD,
29523 +  AVR32_SYNTAX_MULSATHH_H,
29524 +  AVR32_SYNTAX_MULSATHH_W,
29525 +  AVR32_SYNTAX_MULSATRNDHH_H,
29526 +  AVR32_SYNTAX_MULSATRNDWH_W,
29527 +  AVR32_SYNTAX_MULSATWH_W,
29528 +  AVR32_SYNTAX_MULU_D,
29529 +  AVR32_SYNTAX_MULWH_D,
29530 +  AVR32_SYNTAX_MUSFR,
29531 +  AVR32_SYNTAX_MUSTR,
29532 +  AVR32_SYNTAX_MVCR_D,
29533 +  AVR32_SYNTAX_MVCR_W,
29534 +  AVR32_SYNTAX_MVRC_D,
29535 +  AVR32_SYNTAX_MVRC_W,
29536 +  AVR32_SYNTAX_NEG,
29537 +  AVR32_SYNTAX_NOP,
29538 +  AVR32_SYNTAX_OR1,
29539 +  AVR32_SYNTAX_OR2,
29540 +  AVR32_SYNTAX_OR3,
29541 +  AVR32_SYNTAX_ORH,
29542 +  AVR32_SYNTAX_ORL,
29543 +  AVR32_SYNTAX_PABS_SB,
29544 +  AVR32_SYNTAX_PABS_SH,
29545 +  AVR32_SYNTAX_PACKSH_SB,
29546 +  AVR32_SYNTAX_PACKSH_UB,
29547 +  AVR32_SYNTAX_PACKW_SH,
29548 +  AVR32_SYNTAX_PADD_B,
29549 +  AVR32_SYNTAX_PADD_H,
29550 +  AVR32_SYNTAX_PADDH_SH,
29551 +  AVR32_SYNTAX_PADDH_UB,
29552 +  AVR32_SYNTAX_PADDS_SB,
29553 +  AVR32_SYNTAX_PADDS_SH,
29554 +  AVR32_SYNTAX_PADDS_UB,
29555 +  AVR32_SYNTAX_PADDS_UH,
29556 +  AVR32_SYNTAX_PADDSUB_H,
29557 +  AVR32_SYNTAX_PADDSUBH_SH,
29558 +  AVR32_SYNTAX_PADDSUBS_SH,
29559 +  AVR32_SYNTAX_PADDSUBS_UH,
29560 +  AVR32_SYNTAX_PADDX_H,
29561 +  AVR32_SYNTAX_PADDXH_SH,
29562 +  AVR32_SYNTAX_PADDXS_SH,
29563 +  AVR32_SYNTAX_PADDXS_UH,
29564 +  AVR32_SYNTAX_PASR_B,
29565 +  AVR32_SYNTAX_PASR_H,
29566 +  AVR32_SYNTAX_PAVG_SH,
29567 +  AVR32_SYNTAX_PAVG_UB,
29568 +  AVR32_SYNTAX_PLSL_B,
29569 +  AVR32_SYNTAX_PLSL_H,
29570 +  AVR32_SYNTAX_PLSR_B,
29571 +  AVR32_SYNTAX_PLSR_H,
29572 +  AVR32_SYNTAX_PMAX_SH,
29573 +  AVR32_SYNTAX_PMAX_UB,
29574 +  AVR32_SYNTAX_PMIN_SH,
29575 +  AVR32_SYNTAX_PMIN_UB,
29576 +  AVR32_SYNTAX_POPJC,
29577 +  AVR32_SYNTAX_POPM,
29578 +  AVR32_SYNTAX_POPM_E,
29579 +  AVR32_SYNTAX_PREF,
29580 +  AVR32_SYNTAX_PSAD,
29581 +  AVR32_SYNTAX_PSUB_B,
29582 +  AVR32_SYNTAX_PSUB_H,
29583 +  AVR32_SYNTAX_PSUBADD_H,
29584 +  AVR32_SYNTAX_PSUBADDH_SH,
29585 +  AVR32_SYNTAX_PSUBADDS_SH,
29586 +  AVR32_SYNTAX_PSUBADDS_UH,
29587 +  AVR32_SYNTAX_PSUBH_SH,
29588 +  AVR32_SYNTAX_PSUBH_UB,
29589 +  AVR32_SYNTAX_PSUBS_SB,
29590 +  AVR32_SYNTAX_PSUBS_SH,
29591 +  AVR32_SYNTAX_PSUBS_UB,
29592 +  AVR32_SYNTAX_PSUBS_UH,
29593 +  AVR32_SYNTAX_PSUBX_H,
29594 +  AVR32_SYNTAX_PSUBXH_SH,
29595 +  AVR32_SYNTAX_PSUBXS_SH,
29596 +  AVR32_SYNTAX_PSUBXS_UH,
29597 +  AVR32_SYNTAX_PUNPCKSB_H,
29598 +  AVR32_SYNTAX_PUNPCKUB_H,
29599 +  AVR32_SYNTAX_PUSHJC,
29600 +  AVR32_SYNTAX_PUSHM,
29601 +  AVR32_SYNTAX_PUSHM_E,
29602 +  AVR32_SYNTAX_RCALL1,
29603 +  AVR32_SYNTAX_RCALL2,
29604 +  AVR32_SYNTAX_RETEQ,
29605 +  AVR32_SYNTAX_RETNE,
29606 +  AVR32_SYNTAX_RETCC,
29607 +  AVR32_SYNTAX_RETCS,
29608 +  AVR32_SYNTAX_RETGE,
29609 +  AVR32_SYNTAX_RETLT,
29610 +  AVR32_SYNTAX_RETMI,
29611 +  AVR32_SYNTAX_RETPL,
29612 +  AVR32_SYNTAX_RETLS,
29613 +  AVR32_SYNTAX_RETGT,
29614 +  AVR32_SYNTAX_RETLE,
29615 +  AVR32_SYNTAX_RETHI,
29616 +  AVR32_SYNTAX_RETVS,
29617 +  AVR32_SYNTAX_RETVC,
29618 +  AVR32_SYNTAX_RETQS,
29619 +  AVR32_SYNTAX_RETAL,
29620 +  AVR32_SYNTAX_RETHS,
29621 +  AVR32_SYNTAX_RETLO,
29622 +  AVR32_SYNTAX_RETD,
29623 +  AVR32_SYNTAX_RETE,
29624 +  AVR32_SYNTAX_RETJ,
29625 +  AVR32_SYNTAX_RETS,
29626 +  AVR32_SYNTAX_RJMP,
29627 +  AVR32_SYNTAX_ROL,
29628 +  AVR32_SYNTAX_ROR,
29629 +  AVR32_SYNTAX_RSUB1,
29630 +  AVR32_SYNTAX_RSUB2,
29631 +  AVR32_SYNTAX_SATADD_H,
29632 +  AVR32_SYNTAX_SATADD_W,
29633 +  AVR32_SYNTAX_SATRNDS,
29634 +  AVR32_SYNTAX_SATRNDU,
29635 +  AVR32_SYNTAX_SATS,
29636 +  AVR32_SYNTAX_SATSUB_H,
29637 +  AVR32_SYNTAX_SATSUB_W1,
29638 +  AVR32_SYNTAX_SATSUB_W2,
29639 +  AVR32_SYNTAX_SATU,
29640 +  AVR32_SYNTAX_SBC,
29641 +  AVR32_SYNTAX_SBR,
29642 +  AVR32_SYNTAX_SCALL,
29643 +  AVR32_SYNTAX_SCR,
29644 +  AVR32_SYNTAX_SLEEP,
29645 +  AVR32_SYNTAX_SREQ,
29646 +  AVR32_SYNTAX_SRNE,
29647 +  AVR32_SYNTAX_SRCC,
29648 +  AVR32_SYNTAX_SRCS,
29649 +  AVR32_SYNTAX_SRGE,
29650 +  AVR32_SYNTAX_SRLT,
29651 +  AVR32_SYNTAX_SRMI,
29652 +  AVR32_SYNTAX_SRPL,
29653 +  AVR32_SYNTAX_SRLS,
29654 +  AVR32_SYNTAX_SRGT,
29655 +  AVR32_SYNTAX_SRLE,
29656 +  AVR32_SYNTAX_SRHI,
29657 +  AVR32_SYNTAX_SRVS,
29658 +  AVR32_SYNTAX_SRVC,
29659 +  AVR32_SYNTAX_SRQS,
29660 +  AVR32_SYNTAX_SRAL,
29661 +  AVR32_SYNTAX_SRHS,
29662 +  AVR32_SYNTAX_SRLO,
29663 +  AVR32_SYNTAX_SSRF,
29664 +  AVR32_SYNTAX_ST_B1,
29665 +  AVR32_SYNTAX_ST_B2,
29666 +  AVR32_SYNTAX_ST_B5,
29667 +  AVR32_SYNTAX_ST_B3,
29668 +  AVR32_SYNTAX_ST_B4,
29669 +  AVR32_SYNTAX_ST_D1,
29670 +  AVR32_SYNTAX_ST_D2,
29671 +  AVR32_SYNTAX_ST_D3,
29672 +  AVR32_SYNTAX_ST_D5,
29673 +  AVR32_SYNTAX_ST_D4,
29674 +  AVR32_SYNTAX_ST_H1,
29675 +  AVR32_SYNTAX_ST_H2,
29676 +  AVR32_SYNTAX_ST_H5,
29677 +  AVR32_SYNTAX_ST_H3,
29678 +  AVR32_SYNTAX_ST_H4,
29679 +  AVR32_SYNTAX_ST_W1,
29680 +  AVR32_SYNTAX_ST_W2,
29681 +  AVR32_SYNTAX_ST_W5,
29682 +  AVR32_SYNTAX_ST_W3,
29683 +  AVR32_SYNTAX_ST_W4,
29684 +  AVR32_SYNTAX_STC_D1,
29685 +  AVR32_SYNTAX_STC_D2,
29686 +  AVR32_SYNTAX_STC_D3,
29687 +  AVR32_SYNTAX_STC_W1,
29688 +  AVR32_SYNTAX_STC_W2,
29689 +  AVR32_SYNTAX_STC_W3,
29690 +  AVR32_SYNTAX_STC0_D,
29691 +  AVR32_SYNTAX_STC0_W,
29692 +  AVR32_SYNTAX_STCM_D,
29693 +  AVR32_SYNTAX_STCM_D_PU,
29694 +  AVR32_SYNTAX_STCM_W,
29695 +  AVR32_SYNTAX_STCM_W_PU,
29696 +  AVR32_SYNTAX_STCOND,
29697 +  AVR32_SYNTAX_STDSP,
29698 +  AVR32_SYNTAX_STHH_W2,
29699 +  AVR32_SYNTAX_STHH_W1,
29700 +  AVR32_SYNTAX_STM,
29701 +  AVR32_SYNTAX_STM_PU,
29702 +  AVR32_SYNTAX_STMTS,
29703 +  AVR32_SYNTAX_STMTS_PU,
29704 +  AVR32_SYNTAX_STSWP_H,
29705 +  AVR32_SYNTAX_STSWP_W,
29706 +  AVR32_SYNTAX_SUB1,
29707 +  AVR32_SYNTAX_SUB2,
29708 +  AVR32_SYNTAX_SUB5,
29709 +  AVR32_SYNTAX_SUB3_SP,
29710 +  AVR32_SYNTAX_SUB3,
29711 +  AVR32_SYNTAX_SUB4,
29712 +  AVR32_SYNTAX_SUBEQ,
29713 +  AVR32_SYNTAX_SUBNE,
29714 +  AVR32_SYNTAX_SUBCC,
29715 +  AVR32_SYNTAX_SUBCS,
29716 +  AVR32_SYNTAX_SUBGE,
29717 +  AVR32_SYNTAX_SUBLT,
29718 +  AVR32_SYNTAX_SUBMI,
29719 +  AVR32_SYNTAX_SUBPL,
29720 +  AVR32_SYNTAX_SUBLS,
29721 +  AVR32_SYNTAX_SUBGT,
29722 +  AVR32_SYNTAX_SUBLE,
29723 +  AVR32_SYNTAX_SUBHI,
29724 +  AVR32_SYNTAX_SUBVS,
29725 +  AVR32_SYNTAX_SUBVC,
29726 +  AVR32_SYNTAX_SUBQS,
29727 +  AVR32_SYNTAX_SUBAL,
29728 +  AVR32_SYNTAX_SUBHS,
29729 +  AVR32_SYNTAX_SUBLO,
29730 +  AVR32_SYNTAX_SUBFEQ,
29731 +  AVR32_SYNTAX_SUBFNE,
29732 +  AVR32_SYNTAX_SUBFCC,
29733 +  AVR32_SYNTAX_SUBFCS,
29734 +  AVR32_SYNTAX_SUBFGE,
29735 +  AVR32_SYNTAX_SUBFLT,
29736 +  AVR32_SYNTAX_SUBFMI,
29737 +  AVR32_SYNTAX_SUBFPL,
29738 +  AVR32_SYNTAX_SUBFLS,
29739 +  AVR32_SYNTAX_SUBFGT,
29740 +  AVR32_SYNTAX_SUBFLE,
29741 +  AVR32_SYNTAX_SUBFHI,
29742 +  AVR32_SYNTAX_SUBFVS,
29743 +  AVR32_SYNTAX_SUBFVC,
29744 +  AVR32_SYNTAX_SUBFQS,
29745 +  AVR32_SYNTAX_SUBFAL,
29746 +  AVR32_SYNTAX_SUBFHS,
29747 +  AVR32_SYNTAX_SUBFLO,
29748 +  AVR32_SYNTAX_SUBHH_W,
29749 +  AVR32_SYNTAX_SWAP_B,
29750 +  AVR32_SYNTAX_SWAP_BH,
29751 +  AVR32_SYNTAX_SWAP_H,
29752 +  AVR32_SYNTAX_SYNC,
29753 +  AVR32_SYNTAX_TLBR,
29754 +  AVR32_SYNTAX_TLBS,
29755 +  AVR32_SYNTAX_TLBW,
29756 +  AVR32_SYNTAX_TNBZ,
29757 +  AVR32_SYNTAX_TST,
29758 +  AVR32_SYNTAX_XCHG,
29759 +  AVR32_SYNTAX_MEMC,
29760 +  AVR32_SYNTAX_MEMS,
29761 +  AVR32_SYNTAX_MEMT,
29762 +  AVR32_SYNTAX_FMAC_S,
29763 +  AVR32_SYNTAX_FNMAC_S,
29764 +  AVR32_SYNTAX_FMSC_S,
29765 +  AVR32_SYNTAX_FNMSC_S,
29766 +  AVR32_SYNTAX_FMUL_S,
29767 +  AVR32_SYNTAX_FNMUL_S,
29768 +  AVR32_SYNTAX_FADD_S,
29769 +  AVR32_SYNTAX_FSUB_S,
29770 +  AVR32_SYNTAX_FCASTRS_SW,
29771 +  AVR32_SYNTAX_FCASTRS_UW,
29772 +  AVR32_SYNTAX_FCASTSW_S,
29773 +  AVR32_SYNTAX_FCASTUW_S,
29774 +  AVR32_SYNTAX_FCMP_S,
29775 +  AVR32_SYNTAX_FCHK_S,
29776 +  AVR32_SYNTAX_FRCPA_S,
29777 +  AVR32_SYNTAX_FRSQRTA_S,
29778 +  AVR32_SYNTAX_LDA_W,
29779 +  AVR32_SYNTAX_CALL,
29780 +  AVR32_SYNTAX_PICOSVMAC0,
29781 +  AVR32_SYNTAX_PICOSVMAC1,
29782 +  AVR32_SYNTAX_PICOSVMAC2,
29783 +  AVR32_SYNTAX_PICOSVMAC3,
29784 +  AVR32_SYNTAX_PICOSVMUL0,
29785 +  AVR32_SYNTAX_PICOSVMUL1,
29786 +  AVR32_SYNTAX_PICOSVMUL2,
29787 +  AVR32_SYNTAX_PICOSVMUL3,
29788 +  AVR32_SYNTAX_PICOVMAC0,
29789 +  AVR32_SYNTAX_PICOVMAC1,
29790 +  AVR32_SYNTAX_PICOVMAC2,
29791 +  AVR32_SYNTAX_PICOVMAC3,
29792 +  AVR32_SYNTAX_PICOVMUL0,
29793 +  AVR32_SYNTAX_PICOVMUL1,
29794 +  AVR32_SYNTAX_PICOVMUL2,
29795 +  AVR32_SYNTAX_PICOVMUL3,
29796 +  AVR32_SYNTAX_PICOLD_D2,
29797 +  AVR32_SYNTAX_PICOLD_D3,
29798 +  AVR32_SYNTAX_PICOLD_D1,
29799 +  AVR32_SYNTAX_PICOLD_W2,
29800 +  AVR32_SYNTAX_PICOLD_W3,
29801 +  AVR32_SYNTAX_PICOLD_W1,
29802 +  AVR32_SYNTAX_PICOLDM_D,
29803 +  AVR32_SYNTAX_PICOLDM_D_PU,
29804 +  AVR32_SYNTAX_PICOLDM_W,
29805 +  AVR32_SYNTAX_PICOLDM_W_PU,
29806 +  AVR32_SYNTAX_PICOMV_D1,
29807 +  AVR32_SYNTAX_PICOMV_D2,
29808 +  AVR32_SYNTAX_PICOMV_W1,
29809 +  AVR32_SYNTAX_PICOMV_W2,
29810 +  AVR32_SYNTAX_PICOST_D2,
29811 +  AVR32_SYNTAX_PICOST_D3,
29812 +  AVR32_SYNTAX_PICOST_D1,
29813 +  AVR32_SYNTAX_PICOST_W2,
29814 +  AVR32_SYNTAX_PICOST_W3,
29815 +  AVR32_SYNTAX_PICOST_W1,
29816 +  AVR32_SYNTAX_PICOSTM_D,
29817 +  AVR32_SYNTAX_PICOSTM_D_PU,
29818 +  AVR32_SYNTAX_PICOSTM_W,
29819 +  AVR32_SYNTAX_PICOSTM_W_PU,
29820 +  AVR32_SYNTAX_RSUBEQ,
29821 +  AVR32_SYNTAX_RSUBNE,
29822 +  AVR32_SYNTAX_RSUBCC,
29823 +  AVR32_SYNTAX_RSUBCS,
29824 +  AVR32_SYNTAX_RSUBGE,
29825 +  AVR32_SYNTAX_RSUBLT,
29826 +  AVR32_SYNTAX_RSUBMI,
29827 +  AVR32_SYNTAX_RSUBPL,
29828 +  AVR32_SYNTAX_RSUBLS,
29829 +  AVR32_SYNTAX_RSUBGT,
29830 +  AVR32_SYNTAX_RSUBLE,
29831 +  AVR32_SYNTAX_RSUBHI,
29832 +  AVR32_SYNTAX_RSUBVS,
29833 +  AVR32_SYNTAX_RSUBVC,
29834 +  AVR32_SYNTAX_RSUBQS,
29835 +  AVR32_SYNTAX_RSUBAL,
29836 +  AVR32_SYNTAX_RSUBHS,
29837 +  AVR32_SYNTAX_RSUBLO,
29838 +  AVR32_SYNTAX_ADDEQ,
29839 +  AVR32_SYNTAX_ADDNE,
29840 +  AVR32_SYNTAX_ADDCC,
29841 +  AVR32_SYNTAX_ADDCS,
29842 +  AVR32_SYNTAX_ADDGE,
29843 +  AVR32_SYNTAX_ADDLT,
29844 +  AVR32_SYNTAX_ADDMI,
29845 +  AVR32_SYNTAX_ADDPL,
29846 +  AVR32_SYNTAX_ADDLS,
29847 +  AVR32_SYNTAX_ADDGT,
29848 +  AVR32_SYNTAX_ADDLE,
29849 +  AVR32_SYNTAX_ADDHI,
29850 +  AVR32_SYNTAX_ADDVS,
29851 +  AVR32_SYNTAX_ADDVC,
29852 +  AVR32_SYNTAX_ADDQS,
29853 +  AVR32_SYNTAX_ADDAL,
29854 +  AVR32_SYNTAX_ADDHS,
29855 +  AVR32_SYNTAX_ADDLO,
29856 +  AVR32_SYNTAX_SUB2EQ,
29857 +  AVR32_SYNTAX_SUB2NE,
29858 +  AVR32_SYNTAX_SUB2CC,
29859 +  AVR32_SYNTAX_SUB2CS,
29860 +  AVR32_SYNTAX_SUB2GE,
29861 +  AVR32_SYNTAX_SUB2LT,
29862 +  AVR32_SYNTAX_SUB2MI,
29863 +  AVR32_SYNTAX_SUB2PL,
29864 +  AVR32_SYNTAX_SUB2LS,
29865 +  AVR32_SYNTAX_SUB2GT,
29866 +  AVR32_SYNTAX_SUB2LE,
29867 +  AVR32_SYNTAX_SUB2HI,
29868 +  AVR32_SYNTAX_SUB2VS,
29869 +  AVR32_SYNTAX_SUB2VC,
29870 +  AVR32_SYNTAX_SUB2QS,
29871 +  AVR32_SYNTAX_SUB2AL,
29872 +  AVR32_SYNTAX_SUB2HS,
29873 +  AVR32_SYNTAX_SUB2LO,
29874 +  AVR32_SYNTAX_ANDEQ,
29875 +  AVR32_SYNTAX_ANDNE,
29876 +  AVR32_SYNTAX_ANDCC,
29877 +  AVR32_SYNTAX_ANDCS,
29878 +  AVR32_SYNTAX_ANDGE,
29879 +  AVR32_SYNTAX_ANDLT,
29880 +  AVR32_SYNTAX_ANDMI,
29881 +  AVR32_SYNTAX_ANDPL,
29882 +  AVR32_SYNTAX_ANDLS,
29883 +  AVR32_SYNTAX_ANDGT,
29884 +  AVR32_SYNTAX_ANDLE,
29885 +  AVR32_SYNTAX_ANDHI,
29886 +  AVR32_SYNTAX_ANDVS,
29887 +  AVR32_SYNTAX_ANDVC,
29888 +  AVR32_SYNTAX_ANDQS,
29889 +  AVR32_SYNTAX_ANDAL,
29890 +  AVR32_SYNTAX_ANDHS,
29891 +  AVR32_SYNTAX_ANDLO,
29892 +  AVR32_SYNTAX_OREQ,
29893 +  AVR32_SYNTAX_ORNE,
29894 +  AVR32_SYNTAX_ORCC,
29895 +  AVR32_SYNTAX_ORCS,
29896 +  AVR32_SYNTAX_ORGE,
29897 +  AVR32_SYNTAX_ORLT,
29898 +  AVR32_SYNTAX_ORMI,
29899 +  AVR32_SYNTAX_ORPL,
29900 +  AVR32_SYNTAX_ORLS,
29901 +  AVR32_SYNTAX_ORGT,
29902 +  AVR32_SYNTAX_ORLE,
29903 +  AVR32_SYNTAX_ORHI,
29904 +  AVR32_SYNTAX_ORVS,
29905 +  AVR32_SYNTAX_ORVC,
29906 +  AVR32_SYNTAX_ORQS,
29907 +  AVR32_SYNTAX_ORAL,
29908 +  AVR32_SYNTAX_ORHS,
29909 +  AVR32_SYNTAX_ORLO,
29910 +  AVR32_SYNTAX_EOREQ,
29911 +  AVR32_SYNTAX_EORNE,
29912 +  AVR32_SYNTAX_EORCC,
29913 +  AVR32_SYNTAX_EORCS,
29914 +  AVR32_SYNTAX_EORGE,
29915 +  AVR32_SYNTAX_EORLT,
29916 +  AVR32_SYNTAX_EORMI,
29917 +  AVR32_SYNTAX_EORPL,
29918 +  AVR32_SYNTAX_EORLS,
29919 +  AVR32_SYNTAX_EORGT,
29920 +  AVR32_SYNTAX_EORLE,
29921 +  AVR32_SYNTAX_EORHI,
29922 +  AVR32_SYNTAX_EORVS,
29923 +  AVR32_SYNTAX_EORVC,
29924 +  AVR32_SYNTAX_EORQS,
29925 +  AVR32_SYNTAX_EORAL,
29926 +  AVR32_SYNTAX_EORHS,
29927 +  AVR32_SYNTAX_EORLO,
29928 +  AVR32_SYNTAX_LD_WEQ,
29929 +  AVR32_SYNTAX_LD_WNE,
29930 +  AVR32_SYNTAX_LD_WCC,
29931 +  AVR32_SYNTAX_LD_WCS,
29932 +  AVR32_SYNTAX_LD_WGE,
29933 +  AVR32_SYNTAX_LD_WLT,
29934 +  AVR32_SYNTAX_LD_WMI,
29935 +  AVR32_SYNTAX_LD_WPL,
29936 +  AVR32_SYNTAX_LD_WLS,
29937 +  AVR32_SYNTAX_LD_WGT,
29938 +  AVR32_SYNTAX_LD_WLE,
29939 +  AVR32_SYNTAX_LD_WHI,
29940 +  AVR32_SYNTAX_LD_WVS,
29941 +  AVR32_SYNTAX_LD_WVC,
29942 +  AVR32_SYNTAX_LD_WQS,
29943 +  AVR32_SYNTAX_LD_WAL,
29944 +  AVR32_SYNTAX_LD_WHS,
29945 +  AVR32_SYNTAX_LD_WLO,
29946 +  AVR32_SYNTAX_LD_SHEQ,
29947 +  AVR32_SYNTAX_LD_SHNE,
29948 +  AVR32_SYNTAX_LD_SHCC,
29949 +  AVR32_SYNTAX_LD_SHCS,
29950 +  AVR32_SYNTAX_LD_SHGE,
29951 +  AVR32_SYNTAX_LD_SHLT,
29952 +  AVR32_SYNTAX_LD_SHMI,
29953 +  AVR32_SYNTAX_LD_SHPL,
29954 +  AVR32_SYNTAX_LD_SHLS,
29955 +  AVR32_SYNTAX_LD_SHGT,
29956 +  AVR32_SYNTAX_LD_SHLE,
29957 +  AVR32_SYNTAX_LD_SHHI,
29958 +  AVR32_SYNTAX_LD_SHVS,
29959 +  AVR32_SYNTAX_LD_SHVC,
29960 +  AVR32_SYNTAX_LD_SHQS,
29961 +  AVR32_SYNTAX_LD_SHAL,
29962 +  AVR32_SYNTAX_LD_SHHS,
29963 +  AVR32_SYNTAX_LD_SHLO,
29964 +  AVR32_SYNTAX_LD_UHEQ,
29965 +  AVR32_SYNTAX_LD_UHNE,
29966 +  AVR32_SYNTAX_LD_UHCC,
29967 +  AVR32_SYNTAX_LD_UHCS,
29968 +  AVR32_SYNTAX_LD_UHGE,
29969 +  AVR32_SYNTAX_LD_UHLT,
29970 +  AVR32_SYNTAX_LD_UHMI,
29971 +  AVR32_SYNTAX_LD_UHPL,
29972 +  AVR32_SYNTAX_LD_UHLS,
29973 +  AVR32_SYNTAX_LD_UHGT,
29974 +  AVR32_SYNTAX_LD_UHLE,
29975 +  AVR32_SYNTAX_LD_UHHI,
29976 +  AVR32_SYNTAX_LD_UHVS,
29977 +  AVR32_SYNTAX_LD_UHVC,
29978 +  AVR32_SYNTAX_LD_UHQS,
29979 +  AVR32_SYNTAX_LD_UHAL,
29980 +  AVR32_SYNTAX_LD_UHHS,
29981 +  AVR32_SYNTAX_LD_UHLO,
29982 +  AVR32_SYNTAX_LD_SBEQ,
29983 +  AVR32_SYNTAX_LD_SBNE,
29984 +  AVR32_SYNTAX_LD_SBCC,
29985 +  AVR32_SYNTAX_LD_SBCS,
29986 +  AVR32_SYNTAX_LD_SBGE,
29987 +  AVR32_SYNTAX_LD_SBLT,
29988 +  AVR32_SYNTAX_LD_SBMI,
29989 +  AVR32_SYNTAX_LD_SBPL,
29990 +  AVR32_SYNTAX_LD_SBLS,
29991 +  AVR32_SYNTAX_LD_SBGT,
29992 +  AVR32_SYNTAX_LD_SBLE,
29993 +  AVR32_SYNTAX_LD_SBHI,
29994 +  AVR32_SYNTAX_LD_SBVS,
29995 +  AVR32_SYNTAX_LD_SBVC,
29996 +  AVR32_SYNTAX_LD_SBQS,
29997 +  AVR32_SYNTAX_LD_SBAL,
29998 +  AVR32_SYNTAX_LD_SBHS,
29999 +  AVR32_SYNTAX_LD_SBLO,
30000 +  AVR32_SYNTAX_LD_UBEQ,
30001 +  AVR32_SYNTAX_LD_UBNE,
30002 +  AVR32_SYNTAX_LD_UBCC,
30003 +  AVR32_SYNTAX_LD_UBCS,
30004 +  AVR32_SYNTAX_LD_UBGE,
30005 +  AVR32_SYNTAX_LD_UBLT,
30006 +  AVR32_SYNTAX_LD_UBMI,
30007 +  AVR32_SYNTAX_LD_UBPL,
30008 +  AVR32_SYNTAX_LD_UBLS,
30009 +  AVR32_SYNTAX_LD_UBGT,
30010 +  AVR32_SYNTAX_LD_UBLE,
30011 +  AVR32_SYNTAX_LD_UBHI,
30012 +  AVR32_SYNTAX_LD_UBVS,
30013 +  AVR32_SYNTAX_LD_UBVC,
30014 +  AVR32_SYNTAX_LD_UBQS,
30015 +  AVR32_SYNTAX_LD_UBAL,
30016 +  AVR32_SYNTAX_LD_UBHS,
30017 +  AVR32_SYNTAX_LD_UBLO,
30018 +  AVR32_SYNTAX_ST_WEQ,
30019 +  AVR32_SYNTAX_ST_WNE,
30020 +  AVR32_SYNTAX_ST_WCC,
30021 +  AVR32_SYNTAX_ST_WCS,
30022 +  AVR32_SYNTAX_ST_WGE,
30023 +  AVR32_SYNTAX_ST_WLT,
30024 +  AVR32_SYNTAX_ST_WMI,
30025 +  AVR32_SYNTAX_ST_WPL,
30026 +  AVR32_SYNTAX_ST_WLS,
30027 +  AVR32_SYNTAX_ST_WGT,
30028 +  AVR32_SYNTAX_ST_WLE,
30029 +  AVR32_SYNTAX_ST_WHI,
30030 +  AVR32_SYNTAX_ST_WVS,
30031 +  AVR32_SYNTAX_ST_WVC,
30032 +  AVR32_SYNTAX_ST_WQS,
30033 +  AVR32_SYNTAX_ST_WAL,
30034 +  AVR32_SYNTAX_ST_WHS,
30035 +  AVR32_SYNTAX_ST_WLO,
30036 +  AVR32_SYNTAX_ST_HEQ,
30037 +  AVR32_SYNTAX_ST_HNE,
30038 +  AVR32_SYNTAX_ST_HCC,
30039 +  AVR32_SYNTAX_ST_HCS,
30040 +  AVR32_SYNTAX_ST_HGE,
30041 +  AVR32_SYNTAX_ST_HLT,
30042 +  AVR32_SYNTAX_ST_HMI,
30043 +  AVR32_SYNTAX_ST_HPL,
30044 +  AVR32_SYNTAX_ST_HLS,
30045 +  AVR32_SYNTAX_ST_HGT,
30046 +  AVR32_SYNTAX_ST_HLE,
30047 +  AVR32_SYNTAX_ST_HHI,
30048 +  AVR32_SYNTAX_ST_HVS,
30049 +  AVR32_SYNTAX_ST_HVC,
30050 +  AVR32_SYNTAX_ST_HQS,
30051 +  AVR32_SYNTAX_ST_HAL,
30052 +  AVR32_SYNTAX_ST_HHS,
30053 +  AVR32_SYNTAX_ST_HLO,
30054 +  AVR32_SYNTAX_ST_BEQ,
30055 +  AVR32_SYNTAX_ST_BNE,
30056 +  AVR32_SYNTAX_ST_BCC,
30057 +  AVR32_SYNTAX_ST_BCS,
30058 +  AVR32_SYNTAX_ST_BGE,
30059 +  AVR32_SYNTAX_ST_BLT,
30060 +  AVR32_SYNTAX_ST_BMI,
30061 +  AVR32_SYNTAX_ST_BPL,
30062 +  AVR32_SYNTAX_ST_BLS,
30063 +  AVR32_SYNTAX_ST_BGT,
30064 +  AVR32_SYNTAX_ST_BLE,
30065 +  AVR32_SYNTAX_ST_BHI,
30066 +  AVR32_SYNTAX_ST_BVS,
30067 +  AVR32_SYNTAX_ST_BVC,
30068 +  AVR32_SYNTAX_ST_BQS,
30069 +  AVR32_SYNTAX_ST_BAL,
30070 +  AVR32_SYNTAX_ST_BHS,
30071 +  AVR32_SYNTAX_ST_BLO,
30072 +  AVR32_SYNTAX_MOVH,
30073 +  AVR32_SYNTAX__END_
30074 +};
30075 +#define AVR32_NR_SYNTAX AVR32_SYNTAX__END_
30076 +
30077 +enum avr32_alias_type
30078 +  {
30079 +    AVR32_ALIAS_PICOSVMAC0,
30080 +    AVR32_ALIAS_PICOSVMAC1,
30081 +    AVR32_ALIAS_PICOSVMAC2,
30082 +    AVR32_ALIAS_PICOSVMAC3,
30083 +    AVR32_ALIAS_PICOSVMUL0,
30084 +    AVR32_ALIAS_PICOSVMUL1,
30085 +    AVR32_ALIAS_PICOSVMUL2,
30086 +    AVR32_ALIAS_PICOSVMUL3,
30087 +    AVR32_ALIAS_PICOVMAC0,
30088 +    AVR32_ALIAS_PICOVMAC1,
30089 +    AVR32_ALIAS_PICOVMAC2,
30090 +    AVR32_ALIAS_PICOVMAC3,
30091 +    AVR32_ALIAS_PICOVMUL0,
30092 +    AVR32_ALIAS_PICOVMUL1,
30093 +    AVR32_ALIAS_PICOVMUL2,
30094 +    AVR32_ALIAS_PICOVMUL3,
30095 +    AVR32_ALIAS_PICOLD_D1,
30096 +    AVR32_ALIAS_PICOLD_D2,
30097 +    AVR32_ALIAS_PICOLD_D3,
30098 +    AVR32_ALIAS_PICOLD_W1,
30099 +    AVR32_ALIAS_PICOLD_W2,
30100 +    AVR32_ALIAS_PICOLD_W3,
30101 +    AVR32_ALIAS_PICOLDM_D,
30102 +    AVR32_ALIAS_PICOLDM_D_PU,
30103 +    AVR32_ALIAS_PICOLDM_W,
30104 +    AVR32_ALIAS_PICOLDM_W_PU,
30105 +    AVR32_ALIAS_PICOMV_D1,
30106 +    AVR32_ALIAS_PICOMV_D2,
30107 +    AVR32_ALIAS_PICOMV_W1,
30108 +    AVR32_ALIAS_PICOMV_W2,
30109 +    AVR32_ALIAS_PICOST_D1,
30110 +    AVR32_ALIAS_PICOST_D2,
30111 +    AVR32_ALIAS_PICOST_D3,
30112 +    AVR32_ALIAS_PICOST_W1,
30113 +    AVR32_ALIAS_PICOST_W2,
30114 +    AVR32_ALIAS_PICOST_W3,
30115 +    AVR32_ALIAS_PICOSTM_D,
30116 +    AVR32_ALIAS_PICOSTM_D_PU,
30117 +    AVR32_ALIAS_PICOSTM_W,
30118 +    AVR32_ALIAS_PICOSTM_W_PU,
30119 +    AVR32_ALIAS__END_
30120 +  };
30121 +#define AVR32_NR_ALIAS AVR32_ALIAS__END_
30122 +
30123 +enum avr32_mnemonic_type
30124 +{
30125 +  AVR32_MNEMONIC_ABS,
30126 +  AVR32_MNEMONIC_ACALL,
30127 +  AVR32_MNEMONIC_ACR,
30128 +  AVR32_MNEMONIC_ADC,
30129 +  AVR32_MNEMONIC_ADD,
30130 +  AVR32_MNEMONIC_ADDABS,
30131 +  AVR32_MNEMONIC_ADDHH_W,
30132 +  AVR32_MNEMONIC_AND,
30133 +  AVR32_MNEMONIC_ANDH,
30134 +  AVR32_MNEMONIC_ANDL,
30135 +  AVR32_MNEMONIC_ANDN,
30136 +  AVR32_MNEMONIC_ASR,
30137 +  AVR32_MNEMONIC_BFEXTS,
30138 +  AVR32_MNEMONIC_BFEXTU,
30139 +  AVR32_MNEMONIC_BFINS,
30140 +  AVR32_MNEMONIC_BLD,
30141 +  AVR32_MNEMONIC_BREQ,
30142 +  AVR32_MNEMONIC_BRNE,
30143 +  AVR32_MNEMONIC_BRCC,
30144 +  AVR32_MNEMONIC_BRCS,
30145 +  AVR32_MNEMONIC_BRGE,
30146 +  AVR32_MNEMONIC_BRLT,
30147 +  AVR32_MNEMONIC_BRMI,
30148 +  AVR32_MNEMONIC_BRPL,
30149 +  AVR32_MNEMONIC_BRHS,
30150 +  AVR32_MNEMONIC_BRLO,
30151 +  AVR32_MNEMONIC_BRLS,
30152 +  AVR32_MNEMONIC_BRGT,
30153 +  AVR32_MNEMONIC_BRLE,
30154 +  AVR32_MNEMONIC_BRHI,
30155 +  AVR32_MNEMONIC_BRVS,
30156 +  AVR32_MNEMONIC_BRVC,
30157 +  AVR32_MNEMONIC_BRQS,
30158 +  AVR32_MNEMONIC_BRAL,
30159 +  AVR32_MNEMONIC_BREAKPOINT,
30160 +  AVR32_MNEMONIC_BREV,
30161 +  AVR32_MNEMONIC_BST,
30162 +  AVR32_MNEMONIC_CACHE,
30163 +  AVR32_MNEMONIC_CASTS_B,
30164 +  AVR32_MNEMONIC_CASTS_H,
30165 +  AVR32_MNEMONIC_CASTU_B,
30166 +  AVR32_MNEMONIC_CASTU_H,
30167 +  AVR32_MNEMONIC_CBR,
30168 +  AVR32_MNEMONIC_CLZ,
30169 +  AVR32_MNEMONIC_COM,
30170 +  AVR32_MNEMONIC_COP,
30171 +  AVR32_MNEMONIC_CP_B,
30172 +  AVR32_MNEMONIC_CP_H,
30173 +  AVR32_MNEMONIC_CP_W,
30174 +  AVR32_MNEMONIC_CP,
30175 +  AVR32_MNEMONIC_CPC,
30176 +  AVR32_MNEMONIC_CSRF,
30177 +  AVR32_MNEMONIC_CSRFCZ,
30178 +  AVR32_MNEMONIC_DIVS,
30179 +  AVR32_MNEMONIC_DIVU,
30180 +  AVR32_MNEMONIC_EOR,
30181 +  AVR32_MNEMONIC_EORL,
30182 +  AVR32_MNEMONIC_EORH,
30183 +  AVR32_MNEMONIC_FRS,
30184 +  AVR32_MNEMONIC_SSCALL,
30185 +  AVR32_MNEMONIC_RETSS,
30186 +  AVR32_MNEMONIC_ICALL,
30187 +  AVR32_MNEMONIC_INCJOSP,
30188 +  AVR32_MNEMONIC_LD_D,
30189 +  AVR32_MNEMONIC_LD_SB,
30190 +  AVR32_MNEMONIC_LD_UB,
30191 +  AVR32_MNEMONIC_LD_SH,
30192 +  AVR32_MNEMONIC_LD_UH,
30193 +  AVR32_MNEMONIC_LD_W,
30194 +  AVR32_MNEMONIC_LDC_D,
30195 +  AVR32_MNEMONIC_LDC_W,
30196 +  AVR32_MNEMONIC_LDC0_D,
30197 +  AVR32_MNEMONIC_LDC0_W,
30198 +  AVR32_MNEMONIC_LDCM_D,
30199 +  AVR32_MNEMONIC_LDCM_W,
30200 +  AVR32_MNEMONIC_LDDPC,
30201 +  AVR32_MNEMONIC_LDDSP,
30202 +  AVR32_MNEMONIC_LDINS_B,
30203 +  AVR32_MNEMONIC_LDINS_H,
30204 +  AVR32_MNEMONIC_LDM,
30205 +  AVR32_MNEMONIC_LDMTS,
30206 +  AVR32_MNEMONIC_LDSWP_SH,
30207 +  AVR32_MNEMONIC_LDSWP_UH,
30208 +  AVR32_MNEMONIC_LDSWP_W,
30209 +  AVR32_MNEMONIC_LSL,
30210 +  AVR32_MNEMONIC_LSR,
30211 +  AVR32_MNEMONIC_MAC,
30212 +  AVR32_MNEMONIC_MACHH_D,
30213 +  AVR32_MNEMONIC_MACHH_W,
30214 +  AVR32_MNEMONIC_MACS_D,
30215 +  AVR32_MNEMONIC_MACSATHH_W,
30216 +  AVR32_MNEMONIC_MACU_D,
30217 +  AVR32_MNEMONIC_MACWH_D,
30218 +  AVR32_MNEMONIC_MAX,
30219 +  AVR32_MNEMONIC_MCALL,
30220 +  AVR32_MNEMONIC_MFDR,
30221 +  AVR32_MNEMONIC_MFSR,
30222 +  AVR32_MNEMONIC_MIN,
30223 +  AVR32_MNEMONIC_MOV,
30224 +  AVR32_MNEMONIC_MOVEQ,
30225 +  AVR32_MNEMONIC_MOVNE,
30226 +  AVR32_MNEMONIC_MOVCC,
30227 +  AVR32_MNEMONIC_MOVCS,
30228 +  AVR32_MNEMONIC_MOVGE,
30229 +  AVR32_MNEMONIC_MOVLT,
30230 +  AVR32_MNEMONIC_MOVMI,
30231 +  AVR32_MNEMONIC_MOVPL,
30232 +  AVR32_MNEMONIC_MOVLS,
30233 +  AVR32_MNEMONIC_MOVGT,
30234 +  AVR32_MNEMONIC_MOVLE,
30235 +  AVR32_MNEMONIC_MOVHI,
30236 +  AVR32_MNEMONIC_MOVVS,
30237 +  AVR32_MNEMONIC_MOVVC,
30238 +  AVR32_MNEMONIC_MOVQS,
30239 +  AVR32_MNEMONIC_MOVAL,
30240 +  AVR32_MNEMONIC_MOVHS,
30241 +  AVR32_MNEMONIC_MOVLO,
30242 +  AVR32_MNEMONIC_MTDR,
30243 +  AVR32_MNEMONIC_MTSR,
30244 +  AVR32_MNEMONIC_MUL,
30245 +  AVR32_MNEMONIC_MULHH_W,
30246 +  AVR32_MNEMONIC_MULNHH_W,
30247 +  AVR32_MNEMONIC_MULNWH_D,
30248 +  AVR32_MNEMONIC_MULS_D,
30249 +  AVR32_MNEMONIC_MULSATHH_H,
30250 +  AVR32_MNEMONIC_MULSATHH_W,
30251 +  AVR32_MNEMONIC_MULSATRNDHH_H,
30252 +  AVR32_MNEMONIC_MULSATRNDWH_W,
30253 +  AVR32_MNEMONIC_MULSATWH_W,
30254 +  AVR32_MNEMONIC_MULU_D,
30255 +  AVR32_MNEMONIC_MULWH_D,
30256 +  AVR32_MNEMONIC_MUSFR,
30257 +  AVR32_MNEMONIC_MUSTR,
30258 +  AVR32_MNEMONIC_MVCR_D,
30259 +  AVR32_MNEMONIC_MVCR_W,
30260 +  AVR32_MNEMONIC_MVRC_D,
30261 +  AVR32_MNEMONIC_MVRC_W,
30262 +  AVR32_MNEMONIC_NEG,
30263 +  AVR32_MNEMONIC_NOP,
30264 +  AVR32_MNEMONIC_OR,
30265 +  AVR32_MNEMONIC_ORH,
30266 +  AVR32_MNEMONIC_ORL,
30267 +  AVR32_MNEMONIC_PABS_SB,
30268 +  AVR32_MNEMONIC_PABS_SH,
30269 +  AVR32_MNEMONIC_PACKSH_SB,
30270 +  AVR32_MNEMONIC_PACKSH_UB,
30271 +  AVR32_MNEMONIC_PACKW_SH,
30272 +  AVR32_MNEMONIC_PADD_B,
30273 +  AVR32_MNEMONIC_PADD_H,
30274 +  AVR32_MNEMONIC_PADDH_SH,
30275 +  AVR32_MNEMONIC_PADDH_UB,
30276 +  AVR32_MNEMONIC_PADDS_SB,
30277 +  AVR32_MNEMONIC_PADDS_SH,
30278 +  AVR32_MNEMONIC_PADDS_UB,
30279 +  AVR32_MNEMONIC_PADDS_UH,
30280 +  AVR32_MNEMONIC_PADDSUB_H,
30281 +  AVR32_MNEMONIC_PADDSUBH_SH,
30282 +  AVR32_MNEMONIC_PADDSUBS_SH,
30283 +  AVR32_MNEMONIC_PADDSUBS_UH,
30284 +  AVR32_MNEMONIC_PADDX_H,
30285 +  AVR32_MNEMONIC_PADDXH_SH,
30286 +  AVR32_MNEMONIC_PADDXS_SH,
30287 +  AVR32_MNEMONIC_PADDXS_UH,
30288 +  AVR32_MNEMONIC_PASR_B,
30289 +  AVR32_MNEMONIC_PASR_H,
30290 +  AVR32_MNEMONIC_PAVG_SH,
30291 +  AVR32_MNEMONIC_PAVG_UB,
30292 +  AVR32_MNEMONIC_PLSL_B,
30293 +  AVR32_MNEMONIC_PLSL_H,
30294 +  AVR32_MNEMONIC_PLSR_B,
30295 +  AVR32_MNEMONIC_PLSR_H,
30296 +  AVR32_MNEMONIC_PMAX_SH,
30297 +  AVR32_MNEMONIC_PMAX_UB,
30298 +  AVR32_MNEMONIC_PMIN_SH,
30299 +  AVR32_MNEMONIC_PMIN_UB,
30300 +  AVR32_MNEMONIC_POPJC,
30301 +  AVR32_MNEMONIC_POPM,
30302 +  AVR32_MNEMONIC_PREF,
30303 +  AVR32_MNEMONIC_PSAD,
30304 +  AVR32_MNEMONIC_PSUB_B,
30305 +  AVR32_MNEMONIC_PSUB_H,
30306 +  AVR32_MNEMONIC_PSUBADD_H,
30307 +  AVR32_MNEMONIC_PSUBADDH_SH,
30308 +  AVR32_MNEMONIC_PSUBADDS_SH,
30309 +  AVR32_MNEMONIC_PSUBADDS_UH,
30310 +  AVR32_MNEMONIC_PSUBH_SH,
30311 +  AVR32_MNEMONIC_PSUBH_UB,
30312 +  AVR32_MNEMONIC_PSUBS_SB,
30313 +  AVR32_MNEMONIC_PSUBS_SH,
30314 +  AVR32_MNEMONIC_PSUBS_UB,
30315 +  AVR32_MNEMONIC_PSUBS_UH,
30316 +  AVR32_MNEMONIC_PSUBX_H,
30317 +  AVR32_MNEMONIC_PSUBXH_SH,
30318 +  AVR32_MNEMONIC_PSUBXS_SH,
30319 +  AVR32_MNEMONIC_PSUBXS_UH,
30320 +  AVR32_MNEMONIC_PUNPCKSB_H,
30321 +  AVR32_MNEMONIC_PUNPCKUB_H,
30322 +  AVR32_MNEMONIC_PUSHJC,
30323 +  AVR32_MNEMONIC_PUSHM,
30324 +  AVR32_MNEMONIC_RCALL,
30325 +  AVR32_MNEMONIC_RETEQ,
30326 +  AVR32_MNEMONIC_RETNE,
30327 +  AVR32_MNEMONIC_RETCC,
30328 +  AVR32_MNEMONIC_RETCS,
30329 +  AVR32_MNEMONIC_RETGE,
30330 +  AVR32_MNEMONIC_RETLT,
30331 +  AVR32_MNEMONIC_RETMI,
30332 +  AVR32_MNEMONIC_RETPL,
30333 +  AVR32_MNEMONIC_RETLS,
30334 +  AVR32_MNEMONIC_RETGT,
30335 +  AVR32_MNEMONIC_RETLE,
30336 +  AVR32_MNEMONIC_RETHI,
30337 +  AVR32_MNEMONIC_RETVS,
30338 +  AVR32_MNEMONIC_RETVC,
30339 +  AVR32_MNEMONIC_RETQS,
30340 +  AVR32_MNEMONIC_RETAL,
30341 +  AVR32_MNEMONIC_RETHS,
30342 +  AVR32_MNEMONIC_RETLO,
30343 +  AVR32_MNEMONIC_RET,
30344 +  AVR32_MNEMONIC_RETD,
30345 +  AVR32_MNEMONIC_RETE,
30346 +  AVR32_MNEMONIC_RETJ,
30347 +  AVR32_MNEMONIC_RETS,
30348 +  AVR32_MNEMONIC_RJMP,
30349 +  AVR32_MNEMONIC_ROL,
30350 +  AVR32_MNEMONIC_ROR,
30351 +  AVR32_MNEMONIC_RSUB,
30352 +  AVR32_MNEMONIC_SATADD_H,
30353 +  AVR32_MNEMONIC_SATADD_W,
30354 +  AVR32_MNEMONIC_SATRNDS,
30355 +  AVR32_MNEMONIC_SATRNDU,
30356 +  AVR32_MNEMONIC_SATS,
30357 +  AVR32_MNEMONIC_SATSUB_H,
30358 +  AVR32_MNEMONIC_SATSUB_W,
30359 +  AVR32_MNEMONIC_SATU,
30360 +  AVR32_MNEMONIC_SBC,
30361 +  AVR32_MNEMONIC_SBR,
30362 +  AVR32_MNEMONIC_SCALL,
30363 +  AVR32_MNEMONIC_SCR,
30364 +  AVR32_MNEMONIC_SLEEP,
30365 +  AVR32_MNEMONIC_SREQ,
30366 +  AVR32_MNEMONIC_SRNE,
30367 +  AVR32_MNEMONIC_SRCC,
30368 +  AVR32_MNEMONIC_SRCS,
30369 +  AVR32_MNEMONIC_SRGE,
30370 +  AVR32_MNEMONIC_SRLT,
30371 +  AVR32_MNEMONIC_SRMI,
30372 +  AVR32_MNEMONIC_SRPL,
30373 +  AVR32_MNEMONIC_SRLS,
30374 +  AVR32_MNEMONIC_SRGT,
30375 +  AVR32_MNEMONIC_SRLE,
30376 +  AVR32_MNEMONIC_SRHI,
30377 +  AVR32_MNEMONIC_SRVS,
30378 +  AVR32_MNEMONIC_SRVC,
30379 +  AVR32_MNEMONIC_SRQS,
30380 +  AVR32_MNEMONIC_SRAL,
30381 +  AVR32_MNEMONIC_SRHS,
30382 +  AVR32_MNEMONIC_SRLO,
30383 +  AVR32_MNEMONIC_SSRF,
30384 +  AVR32_MNEMONIC_ST_B,
30385 +  AVR32_MNEMONIC_ST_D,
30386 +  AVR32_MNEMONIC_ST_H,
30387 +  AVR32_MNEMONIC_ST_W,
30388 +  AVR32_MNEMONIC_STC_D,
30389 +  AVR32_MNEMONIC_STC_W,
30390 +  AVR32_MNEMONIC_STC0_D,
30391 +  AVR32_MNEMONIC_STC0_W,
30392 +  AVR32_MNEMONIC_STCM_D,
30393 +  AVR32_MNEMONIC_STCM_W,
30394 +  AVR32_MNEMONIC_STCOND,
30395 +  AVR32_MNEMONIC_STDSP,
30396 +  AVR32_MNEMONIC_STHH_W,
30397 +  AVR32_MNEMONIC_STM,
30398 +  AVR32_MNEMONIC_STMTS,
30399 +  AVR32_MNEMONIC_STSWP_H,
30400 +  AVR32_MNEMONIC_STSWP_W,
30401 +  AVR32_MNEMONIC_SUB,
30402 +  AVR32_MNEMONIC_SUBEQ,
30403 +  AVR32_MNEMONIC_SUBNE,
30404 +  AVR32_MNEMONIC_SUBCC,
30405 +  AVR32_MNEMONIC_SUBCS,
30406 +  AVR32_MNEMONIC_SUBGE,
30407 +  AVR32_MNEMONIC_SUBLT,
30408 +  AVR32_MNEMONIC_SUBMI,
30409 +  AVR32_MNEMONIC_SUBPL,
30410 +  AVR32_MNEMONIC_SUBLS,
30411 +  AVR32_MNEMONIC_SUBGT,
30412 +  AVR32_MNEMONIC_SUBLE,
30413 +  AVR32_MNEMONIC_SUBHI,
30414 +  AVR32_MNEMONIC_SUBVS,
30415 +  AVR32_MNEMONIC_SUBVC,
30416 +  AVR32_MNEMONIC_SUBQS,
30417 +  AVR32_MNEMONIC_SUBAL,
30418 +  AVR32_MNEMONIC_SUBHS,
30419 +  AVR32_MNEMONIC_SUBLO,
30420 +  AVR32_MNEMONIC_SUBFEQ,
30421 +  AVR32_MNEMONIC_SUBFNE,
30422 +  AVR32_MNEMONIC_SUBFCC,
30423 +  AVR32_MNEMONIC_SUBFCS,
30424 +  AVR32_MNEMONIC_SUBFGE,
30425 +  AVR32_MNEMONIC_SUBFLT,
30426 +  AVR32_MNEMONIC_SUBFMI,
30427 +  AVR32_MNEMONIC_SUBFPL,
30428 +  AVR32_MNEMONIC_SUBFLS,
30429 +  AVR32_MNEMONIC_SUBFGT,
30430 +  AVR32_MNEMONIC_SUBFLE,
30431 +  AVR32_MNEMONIC_SUBFHI,
30432 +  AVR32_MNEMONIC_SUBFVS,
30433 +  AVR32_MNEMONIC_SUBFVC,
30434 +  AVR32_MNEMONIC_SUBFQS,
30435 +  AVR32_MNEMONIC_SUBFAL,
30436 +  AVR32_MNEMONIC_SUBFHS,
30437 +  AVR32_MNEMONIC_SUBFLO,
30438 +  AVR32_MNEMONIC_SUBHH_W,
30439 +  AVR32_MNEMONIC_SWAP_B,
30440 +  AVR32_MNEMONIC_SWAP_BH,
30441 +  AVR32_MNEMONIC_SWAP_H,
30442 +  AVR32_MNEMONIC_SYNC,
30443 +  AVR32_MNEMONIC_TLBR,
30444 +  AVR32_MNEMONIC_TLBS,
30445 +  AVR32_MNEMONIC_TLBW,
30446 +  AVR32_MNEMONIC_TNBZ,
30447 +  AVR32_MNEMONIC_TST,
30448 +  AVR32_MNEMONIC_XCHG,
30449 +  AVR32_MNEMONIC_MEMC,
30450 +  AVR32_MNEMONIC_MEMS,
30451 +  AVR32_MNEMONIC_MEMT,
30452 +  AVR32_MNEMONIC_FMAC_S,
30453 +  AVR32_MNEMONIC_FNMAC_S,
30454 +  AVR32_MNEMONIC_FMSC_S,
30455 +  AVR32_MNEMONIC_FNMSC_S,
30456 +  AVR32_MNEMONIC_FMUL_S,
30457 +  AVR32_MNEMONIC_FNMUL_S,
30458 +  AVR32_MNEMONIC_FADD_S,
30459 +  AVR32_MNEMONIC_FSUB_S,
30460 +  AVR32_MNEMONIC_FCASTRS_SW,
30461 +  AVR32_MNEMONIC_FCASTRS_UW,
30462 +  AVR32_MNEMONIC_FCASTSW_S,
30463 +  AVR32_MNEMONIC_FCASTUW_S,
30464 +  AVR32_MNEMONIC_FCMP_S,
30465 +  AVR32_MNEMONIC_FCHK_S,
30466 +  AVR32_MNEMONIC_FRCPA_S,
30467 +  AVR32_MNEMONIC_FRSQRTA_S,
30468 +  /* AVR32_MNEMONIC_FLD_S,
30469 +     AVR32_MNEMONIC_FLD_D,
30470 +     AVR32_MNEMONIC_FST_S,
30471 +     AVR32_MNEMONIC_FST_D, */
30472 +  AVR32_MNEMONIC_LDA_W,
30473 +  AVR32_MNEMONIC_CALL,
30474 +  AVR32_MNEMONIC_PICOSVMAC,
30475 +  AVR32_MNEMONIC_PICOSVMUL,
30476 +  AVR32_MNEMONIC_PICOVMAC,
30477 +  AVR32_MNEMONIC_PICOVMUL,
30478 +  AVR32_MNEMONIC_PICOLD_D,
30479 +  AVR32_MNEMONIC_PICOLD_W,
30480 +  AVR32_MNEMONIC_PICOLDM_D,
30481 +  AVR32_MNEMONIC_PICOLDM_W,
30482 +  AVR32_MNEMONIC_PICOMV_D,
30483 +  AVR32_MNEMONIC_PICOMV_W,
30484 +  AVR32_MNEMONIC_PICOST_D,
30485 +  AVR32_MNEMONIC_PICOST_W,
30486 +  AVR32_MNEMONIC_PICOSTM_D,
30487 +  AVR32_MNEMONIC_PICOSTM_W,
30488 +  AVR32_MNEMONIC_RSUBEQ,
30489 +  AVR32_MNEMONIC_RSUBNE,
30490 +  AVR32_MNEMONIC_RSUBCC,
30491 +  AVR32_MNEMONIC_RSUBCS,
30492 +  AVR32_MNEMONIC_RSUBGE,
30493 +  AVR32_MNEMONIC_RSUBLT,
30494 +  AVR32_MNEMONIC_RSUBMI,
30495 +  AVR32_MNEMONIC_RSUBPL,
30496 +  AVR32_MNEMONIC_RSUBLS,
30497 +  AVR32_MNEMONIC_RSUBGT,
30498 +  AVR32_MNEMONIC_RSUBLE,
30499 +  AVR32_MNEMONIC_RSUBHI,
30500 +  AVR32_MNEMONIC_RSUBVS,
30501 +  AVR32_MNEMONIC_RSUBVC,
30502 +  AVR32_MNEMONIC_RSUBQS,
30503 +  AVR32_MNEMONIC_RSUBAL,
30504 +  AVR32_MNEMONIC_RSUBHS,
30505 +  AVR32_MNEMONIC_RSUBLO,
30506 +  AVR32_MNEMONIC_ADDEQ,
30507 +  AVR32_MNEMONIC_ADDNE,
30508 +  AVR32_MNEMONIC_ADDCC,
30509 +  AVR32_MNEMONIC_ADDCS,
30510 +  AVR32_MNEMONIC_ADDGE,
30511 +  AVR32_MNEMONIC_ADDLT,
30512 +  AVR32_MNEMONIC_ADDMI,
30513 +  AVR32_MNEMONIC_ADDPL,
30514 +  AVR32_MNEMONIC_ADDLS,
30515 +  AVR32_MNEMONIC_ADDGT,
30516 +  AVR32_MNEMONIC_ADDLE,
30517 +  AVR32_MNEMONIC_ADDHI,
30518 +  AVR32_MNEMONIC_ADDVS,
30519 +  AVR32_MNEMONIC_ADDVC,
30520 +  AVR32_MNEMONIC_ADDQS,
30521 +  AVR32_MNEMONIC_ADDAL,
30522 +  AVR32_MNEMONIC_ADDHS,
30523 +  AVR32_MNEMONIC_ADDLO,
30524 +  AVR32_MNEMONIC_ANDEQ,
30525 +  AVR32_MNEMONIC_ANDNE,
30526 +  AVR32_MNEMONIC_ANDCC,
30527 +  AVR32_MNEMONIC_ANDCS,
30528 +  AVR32_MNEMONIC_ANDGE,
30529 +  AVR32_MNEMONIC_ANDLT,
30530 +  AVR32_MNEMONIC_ANDMI,
30531 +  AVR32_MNEMONIC_ANDPL,
30532 +  AVR32_MNEMONIC_ANDLS,
30533 +  AVR32_MNEMONIC_ANDGT,
30534 +  AVR32_MNEMONIC_ANDLE,
30535 +  AVR32_MNEMONIC_ANDHI,
30536 +  AVR32_MNEMONIC_ANDVS,
30537 +  AVR32_MNEMONIC_ANDVC,
30538 +  AVR32_MNEMONIC_ANDQS,
30539 +  AVR32_MNEMONIC_ANDAL,
30540 +  AVR32_MNEMONIC_ANDHS,
30541 +  AVR32_MNEMONIC_ANDLO,
30542 +  AVR32_MNEMONIC_OREQ,
30543 +  AVR32_MNEMONIC_ORNE,
30544 +  AVR32_MNEMONIC_ORCC,
30545 +  AVR32_MNEMONIC_ORCS,
30546 +  AVR32_MNEMONIC_ORGE,
30547 +  AVR32_MNEMONIC_ORLT,
30548 +  AVR32_MNEMONIC_ORMI,
30549 +  AVR32_MNEMONIC_ORPL,
30550 +  AVR32_MNEMONIC_ORLS,
30551 +  AVR32_MNEMONIC_ORGT,
30552 +  AVR32_MNEMONIC_ORLE,
30553 +  AVR32_MNEMONIC_ORHI,
30554 +  AVR32_MNEMONIC_ORVS,
30555 +  AVR32_MNEMONIC_ORVC,
30556 +  AVR32_MNEMONIC_ORQS,
30557 +  AVR32_MNEMONIC_ORAL,
30558 +  AVR32_MNEMONIC_ORHS,
30559 +  AVR32_MNEMONIC_ORLO,
30560 +  AVR32_MNEMONIC_EOREQ,
30561 +  AVR32_MNEMONIC_EORNE,
30562 +  AVR32_MNEMONIC_EORCC,
30563 +  AVR32_MNEMONIC_EORCS,
30564 +  AVR32_MNEMONIC_EORGE,
30565 +  AVR32_MNEMONIC_EORLT,
30566 +  AVR32_MNEMONIC_EORMI,
30567 +  AVR32_MNEMONIC_EORPL,
30568 +  AVR32_MNEMONIC_EORLS,
30569 +  AVR32_MNEMONIC_EORGT,
30570 +  AVR32_MNEMONIC_EORLE,
30571 +  AVR32_MNEMONIC_EORHI,
30572 +  AVR32_MNEMONIC_EORVS,
30573 +  AVR32_MNEMONIC_EORVC,
30574 +  AVR32_MNEMONIC_EORQS,
30575 +  AVR32_MNEMONIC_EORAL,
30576 +  AVR32_MNEMONIC_EORHS,
30577 +  AVR32_MNEMONIC_EORLO,
30578 +  AVR32_MNEMONIC_LD_WEQ,
30579 +  AVR32_MNEMONIC_LD_WNE,
30580 +  AVR32_MNEMONIC_LD_WCC,
30581 +  AVR32_MNEMONIC_LD_WCS,
30582 +  AVR32_MNEMONIC_LD_WGE,
30583 +  AVR32_MNEMONIC_LD_WLT,
30584 +  AVR32_MNEMONIC_LD_WMI,
30585 +  AVR32_MNEMONIC_LD_WPL,
30586 +  AVR32_MNEMONIC_LD_WLS,
30587 +  AVR32_MNEMONIC_LD_WGT,
30588 +  AVR32_MNEMONIC_LD_WLE,
30589 +  AVR32_MNEMONIC_LD_WHI,
30590 +  AVR32_MNEMONIC_LD_WVS,
30591 +  AVR32_MNEMONIC_LD_WVC,
30592 +  AVR32_MNEMONIC_LD_WQS,
30593 +  AVR32_MNEMONIC_LD_WAL,
30594 +  AVR32_MNEMONIC_LD_WHS,
30595 +  AVR32_MNEMONIC_LD_WLO,
30596 +  AVR32_MNEMONIC_LD_SHEQ,
30597 +  AVR32_MNEMONIC_LD_SHNE,
30598 +  AVR32_MNEMONIC_LD_SHCC,
30599 +  AVR32_MNEMONIC_LD_SHCS,
30600 +  AVR32_MNEMONIC_LD_SHGE,
30601 +  AVR32_MNEMONIC_LD_SHLT,
30602 +  AVR32_MNEMONIC_LD_SHMI,
30603 +  AVR32_MNEMONIC_LD_SHPL,
30604 +  AVR32_MNEMONIC_LD_SHLS,
30605 +  AVR32_MNEMONIC_LD_SHGT,
30606 +  AVR32_MNEMONIC_LD_SHLE,
30607 +  AVR32_MNEMONIC_LD_SHHI,
30608 +  AVR32_MNEMONIC_LD_SHVS,
30609 +  AVR32_MNEMONIC_LD_SHVC,
30610 +  AVR32_MNEMONIC_LD_SHQS,
30611 +  AVR32_MNEMONIC_LD_SHAL,
30612 +  AVR32_MNEMONIC_LD_SHHS,
30613 +  AVR32_MNEMONIC_LD_SHLO,
30614 +  AVR32_MNEMONIC_LD_UHEQ,
30615 +  AVR32_MNEMONIC_LD_UHNE,
30616 +  AVR32_MNEMONIC_LD_UHCC,
30617 +  AVR32_MNEMONIC_LD_UHCS,
30618 +  AVR32_MNEMONIC_LD_UHGE,
30619 +  AVR32_MNEMONIC_LD_UHLT,
30620 +  AVR32_MNEMONIC_LD_UHMI,
30621 +  AVR32_MNEMONIC_LD_UHPL,
30622 +  AVR32_MNEMONIC_LD_UHLS,
30623 +  AVR32_MNEMONIC_LD_UHGT,
30624 +  AVR32_MNEMONIC_LD_UHLE,
30625 +  AVR32_MNEMONIC_LD_UHHI,
30626 +  AVR32_MNEMONIC_LD_UHVS,
30627 +  AVR32_MNEMONIC_LD_UHVC,
30628 +  AVR32_MNEMONIC_LD_UHQS,
30629 +  AVR32_MNEMONIC_LD_UHAL,
30630 +  AVR32_MNEMONIC_LD_UHHS,
30631 +  AVR32_MNEMONIC_LD_UHLO,
30632 +  AVR32_MNEMONIC_LD_SBEQ,
30633 +  AVR32_MNEMONIC_LD_SBNE,
30634 +  AVR32_MNEMONIC_LD_SBCC,
30635 +  AVR32_MNEMONIC_LD_SBCS,
30636 +  AVR32_MNEMONIC_LD_SBGE,
30637 +  AVR32_MNEMONIC_LD_SBLT,
30638 +  AVR32_MNEMONIC_LD_SBMI,
30639 +  AVR32_MNEMONIC_LD_SBPL,
30640 +  AVR32_MNEMONIC_LD_SBLS,
30641 +  AVR32_MNEMONIC_LD_SBGT,
30642 +  AVR32_MNEMONIC_LD_SBLE,
30643 +  AVR32_MNEMONIC_LD_SBHI,
30644 +  AVR32_MNEMONIC_LD_SBVS,
30645 +  AVR32_MNEMONIC_LD_SBVC,
30646 +  AVR32_MNEMONIC_LD_SBQS,
30647 +  AVR32_MNEMONIC_LD_SBAL,
30648 +  AVR32_MNEMONIC_LD_SBHS,
30649 +  AVR32_MNEMONIC_LD_SBLO,
30650 +  AVR32_MNEMONIC_LD_UBEQ,
30651 +  AVR32_MNEMONIC_LD_UBNE,
30652 +  AVR32_MNEMONIC_LD_UBCC,
30653 +  AVR32_MNEMONIC_LD_UBCS,
30654 +  AVR32_MNEMONIC_LD_UBGE,
30655 +  AVR32_MNEMONIC_LD_UBLT,
30656 +  AVR32_MNEMONIC_LD_UBMI,
30657 +  AVR32_MNEMONIC_LD_UBPL,
30658 +  AVR32_MNEMONIC_LD_UBLS,
30659 +  AVR32_MNEMONIC_LD_UBGT,
30660 +  AVR32_MNEMONIC_LD_UBLE,
30661 +  AVR32_MNEMONIC_LD_UBHI,
30662 +  AVR32_MNEMONIC_LD_UBVS,
30663 +  AVR32_MNEMONIC_LD_UBVC,
30664 +  AVR32_MNEMONIC_LD_UBQS,
30665 +  AVR32_MNEMONIC_LD_UBAL,
30666 +  AVR32_MNEMONIC_LD_UBHS,
30667 +  AVR32_MNEMONIC_LD_UBLO,
30668 +  AVR32_MNEMONIC_ST_WEQ,
30669 +  AVR32_MNEMONIC_ST_WNE,
30670 +  AVR32_MNEMONIC_ST_WCC,
30671 +  AVR32_MNEMONIC_ST_WCS,
30672 +  AVR32_MNEMONIC_ST_WGE,
30673 +  AVR32_MNEMONIC_ST_WLT,
30674 +  AVR32_MNEMONIC_ST_WMI,
30675 +  AVR32_MNEMONIC_ST_WPL,
30676 +  AVR32_MNEMONIC_ST_WLS,
30677 +  AVR32_MNEMONIC_ST_WGT,
30678 +  AVR32_MNEMONIC_ST_WLE,
30679 +  AVR32_MNEMONIC_ST_WHI,
30680 +  AVR32_MNEMONIC_ST_WVS,
30681 +  AVR32_MNEMONIC_ST_WVC,
30682 +  AVR32_MNEMONIC_ST_WQS,
30683 +  AVR32_MNEMONIC_ST_WAL,
30684 +  AVR32_MNEMONIC_ST_WHS,
30685 +  AVR32_MNEMONIC_ST_WLO,
30686 +  AVR32_MNEMONIC_ST_HEQ,
30687 +  AVR32_MNEMONIC_ST_HNE,
30688 +  AVR32_MNEMONIC_ST_HCC,
30689 +  AVR32_MNEMONIC_ST_HCS,
30690 +  AVR32_MNEMONIC_ST_HGE,
30691 +  AVR32_MNEMONIC_ST_HLT,
30692 +  AVR32_MNEMONIC_ST_HMI,
30693 +  AVR32_MNEMONIC_ST_HPL,
30694 +  AVR32_MNEMONIC_ST_HLS,
30695 +  AVR32_MNEMONIC_ST_HGT,
30696 +  AVR32_MNEMONIC_ST_HLE,
30697 +  AVR32_MNEMONIC_ST_HHI,
30698 +  AVR32_MNEMONIC_ST_HVS,
30699 +  AVR32_MNEMONIC_ST_HVC,
30700 +  AVR32_MNEMONIC_ST_HQS,
30701 +  AVR32_MNEMONIC_ST_HAL,
30702 +  AVR32_MNEMONIC_ST_HHS,
30703 +  AVR32_MNEMONIC_ST_HLO,
30704 +  AVR32_MNEMONIC_ST_BEQ,
30705 +  AVR32_MNEMONIC_ST_BNE,
30706 +  AVR32_MNEMONIC_ST_BCC,
30707 +  AVR32_MNEMONIC_ST_BCS,
30708 +  AVR32_MNEMONIC_ST_BGE,
30709 +  AVR32_MNEMONIC_ST_BLT,
30710 +  AVR32_MNEMONIC_ST_BMI,
30711 +  AVR32_MNEMONIC_ST_BPL,
30712 +  AVR32_MNEMONIC_ST_BLS,
30713 +  AVR32_MNEMONIC_ST_BGT,
30714 +  AVR32_MNEMONIC_ST_BLE,
30715 +  AVR32_MNEMONIC_ST_BHI,
30716 +  AVR32_MNEMONIC_ST_BVS,
30717 +  AVR32_MNEMONIC_ST_BVC,
30718 +  AVR32_MNEMONIC_ST_BQS,
30719 +  AVR32_MNEMONIC_ST_BAL,
30720 +  AVR32_MNEMONIC_ST_BHS,
30721 +  AVR32_MNEMONIC_ST_BLO,
30722 +  AVR32_MNEMONIC_MOVH,
30723 +  AVR32_MNEMONIC__END_
30724 +};
30725 +#define AVR32_NR_MNEMONICS AVR32_MNEMONIC__END_
30726 +
30727 +enum avr32_syntax_parser
30728 +  {
30729 +    AVR32_PARSER_NORMAL,
30730 +    AVR32_PARSER_ALIAS,
30731 +    AVR32_PARSER_LDA,
30732 +    AVR32_PARSER_CALL,
30733 +    AVR32_PARSER__END_
30734 +  };
30735 +#define AVR32_NR_PARSERS AVR32_PARSER__END_
30736 --- a/opcodes/configure
30737 +++ b/opcodes/configure
30738 @@ -12417,6 +12417,7 @@ if test x${all_targets} = xfalse ; then
30739         bfd_arc_arch)           ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
30740         bfd_arm_arch)           ta="$ta arm-dis.lo" ;;
30741         bfd_avr_arch)           ta="$ta avr-dis.lo" ;;
30742 +       bfd_avr32_arch)         ta="$ta avr32-asm.lo avr32-dis.lo avr32-opc.lo" ;;
30743         bfd_bfin_arch)          ta="$ta bfin-dis.lo" ;;
30744         bfd_cr16_arch)          ta="$ta cr16-dis.lo cr16-opc.lo" ;;
30745         bfd_cris_arch)          ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
30746 --- a/opcodes/configure.in
30747 +++ b/opcodes/configure.in
30748 @@ -223,6 +223,7 @@ if test x${all_targets} = xfalse ; then
30749         bfd_arc_arch)           ta="$ta arc-dis.lo arc-opc.lo arc-ext.lo" ;;
30750         bfd_arm_arch)           ta="$ta arm-dis.lo" ;;
30751         bfd_avr_arch)           ta="$ta avr-dis.lo" ;;
30752 +       bfd_avr32_arch)         ta="$ta avr32-asm.lo avr32-dis.lo avr32-opc.lo" ;;
30753         bfd_bfin_arch)          ta="$ta bfin-dis.lo" ;;
30754         bfd_cr16_arch)          ta="$ta cr16-dis.lo cr16-opc.lo" ;;
30755         bfd_cris_arch)          ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
30756 @@ -285,7 +286,7 @@ if test x${all_targets} = xfalse ; then
30757                                 ta="$ta sh64-dis.lo sh64-opc.lo"
30758                                 archdefs="$archdefs -DINCLUDE_SHMEDIA"
30759                                 break;;
30760 -           esac;
30761 +           esac
30762           done
30763                                 ta="$ta sh-dis.lo cgen-bitset.lo" ;;
30764         bfd_sparc_arch)         ta="$ta sparc-dis.lo sparc-opc.lo" ;;
30765 --- a/opcodes/disassemble.c
30766 +++ b/opcodes/disassemble.c
30767 @@ -27,6 +27,7 @@
30768  #define ARCH_arc
30769  #define ARCH_arm
30770  #define ARCH_avr
30771 +#define ARCH_avr32
30772  #define ARCH_bfin
30773  #define ARCH_cr16
30774  #define ARCH_cris
30775 @@ -130,6 +131,11 @@ disassembler (abfd)
30776        disassemble = print_insn_avr;
30777        break;
30778  #endif
30779 +#ifdef ARCH_avr32
30780 +    case bfd_arch_avr32:
30781 +      disassemble = print_insn_avr32;
30782 +      break;
30783 +#endif
30784  #ifdef ARCH_bfin
30785      case bfd_arch_bfin:
30786        disassemble = print_insn_bfin;
30787 @@ -489,6 +495,9 @@ disassembler_usage (stream)
30788  #ifdef ARCH_i386
30789    print_i386_disassembler_options (stream);
30790  #endif
30791 +#ifdef ARCH_avr32
30792 +  print_avr32_disassembler_options (stream);
30793 +#endif
30794  #ifdef ARCH_s390
30795    print_s390_disassembler_options (stream);
30796  #endif