target/linux/xburst/patches-3.10/008-Add-jz4740-udc-driver.patch

   1 From b3e08e29f6f32dfb400374dc96d0a2f61e6adceb Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 24 Apr 2010 12:18:46 +0200
   4 Subject: [PATCH 08/16] Add jz4740 udc driver
   5
   6 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
   7 ---
   8  drivers/usb/gadget/Kconfig        |    8 +
   9  drivers/usb/gadget/Makefile       |    1 +
  10  drivers/usb/gadget/gadget_chips.h |    1 +
  11  drivers/usb/gadget/jz4740_udc.c   | 2155 +++++++++++++++++++++++++++++++++++++
  12  drivers/usb/gadget/jz4740_udc.h   |  101 ++
  13  5 files changed, 2266 insertions(+)
  14  create mode 100644 drivers/usb/gadget/jz4740_udc.c
  15  create mode 100644 drivers/usb/gadget/jz4740_udc.h
  16
  17 --- a/drivers/usb/gadget/Kconfig
  18 +++ b/drivers/usb/gadget/Kconfig
  19 @@ -192,6 +192,14 @@ config USB_FUSB300
  20         help
  21            Faraday usb device controller FUSB300 driver
  22
  23 +config USB_JZ4740
  24 +       tristate "JZ4740 UDC"
  25 +       depends on MACH_JZ4740
  26 +       select USB_GADGET_DUALSPEED
  27 +       help
  28 +          Select this to support the Ingenic JZ4740 processor
  29 +          high speed USB device controller.
  30 +
  31  config USB_OMAP
  32         tristate "OMAP USB Device Controller"
  33         depends on ARCH_OMAP1
  34 --- a/drivers/usb/gadget/Makefile
  35 +++ b/drivers/usb/gadget/Makefile
  36 @@ -34,6 +34,7 @@ obj-$(CONFIG_USB_MV_UDC)      += mv_udc.o
  37  mv_udc-y                       := mv_udc_core.o
  38  obj-$(CONFIG_USB_FUSB300)      += fusb300_udc.o
  39  obj-$(CONFIG_USB_MV_U3D)       += mv_u3d_core.o
  40 +obj-$(CONFIG_USB_JZ4740)       += jz4740_udc.o
  41
  42  # USB Functions
  43  usb_f_acm-y                    := f_acm.o
  44 --- a/drivers/usb/gadget/gadget_chips.h
  45 +++ b/drivers/usb/gadget/gadget_chips.h
  46 @@ -29,6 +29,7 @@
  47   */
  48  #define gadget_is_at91(g)              (!strcmp("at91_udc", (g)->name))
  49  #define gadget_is_goku(g)              (!strcmp("goku_udc", (g)->name))
  50 +#define gadget_is_jz4740(g)            (!strcmp("ingenic_hsusb", (g)->name))
  51  #define gadget_is_musbhdrc(g)          (!strcmp("musb-hdrc", (g)->name))
  52  #define gadget_is_net2280(g)           (!strcmp("net2280", (g)->name))
  53  #define gadget_is_pxa(g)               (!strcmp("pxa25x_udc", (g)->name))
  54 --- /dev/null
  55 +++ b/drivers/usb/gadget/jz4740_udc.c
  56 @@ -0,0 +1,2155 @@
  57 +/*
  58 + * linux/drivers/usb/gadget/jz4740_udc.c
  59 + *
  60 + * Ingenic JZ4740 on-chip high speed USB device controller
  61 + *
  62 + * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
  63 + * Author: <jlwei@ingenic.cn>
  64 + *
  65 + * This program is free software; you can redistribute it and/or modify
  66 + * it under the terms of the GNU General Public License as published by
  67 + * the Free Software Foundation; either version 2 of the License, or
  68 + * (at your option) any later version.
  69 + */
  70 +
  71 +/*
  72 + * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
  73 + *
  74 + *  - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
  75 + *  - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
  76 + */
  77 +
  78 +#include <linux/kernel.h>
  79 +#include <linux/module.h>
  80 +#include <linux/platform_device.h>
  81 +#include <linux/delay.h>
  82 +#include <linux/ioport.h>
  83 +#include <linux/slab.h>
  84 +#include <linux/errno.h>
  85 +#include <linux/init.h>
  86 +#include <linux/list.h>
  87 +#include <linux/interrupt.h>
  88 +#include <linux/proc_fs.h>
  89 +#include <linux/usb.h>
  90 +#include <linux/usb/gadget.h>
  91 +#include <linux/clk.h>
  92 +
  93 +#include <asm/byteorder.h>
  94 +#include <asm/io.h>
  95 +#include <asm/irq.h>
  96 +#include <asm/mach-jz4740/clock.h>
  97 +
  98 +#include "jz4740_udc.h"
  99 +
 100 +#define JZ_REG_UDC_FADDR       0x00 /* Function Address 8-bit */
 101 +#define JZ_REG_UDC_POWER       0x01 /* Power Management 8-bit */
 102 +#define JZ_REG_UDC_INTRIN      0x02 /* Interrupt IN 16-bit */
 103 +#define JZ_REG_UDC_INTROUT     0x04 /* Interrupt OUT 16-bit */
 104 +#define JZ_REG_UDC_INTRINE     0x06 /* Intr IN enable 16-bit */
 105 +#define JZ_REG_UDC_INTROUTE    0x08 /* Intr OUT enable 16-bit */
 106 +#define JZ_REG_UDC_INTRUSB     0x0a /* Interrupt USB 8-bit */
 107 +#define JZ_REG_UDC_INTRUSBE    0x0b /* Interrupt USB Enable 8-bit */
 108 +#define JZ_REG_UDC_FRAME       0x0c /* Frame number 16-bit */
 109 +#define JZ_REG_UDC_INDEX       0x0e /* Index register 8-bit */
 110 +#define JZ_REG_UDC_TESTMODE    0x0f /* USB test mode 8-bit */
 111 +
 112 +#define JZ_REG_UDC_CSR0                0x12 /* EP0 CSR 8-bit */
 113 +#define JZ_REG_UDC_INMAXP      0x10 /* EP1-2 IN Max Pkt Size 16-bit */
 114 +#define JZ_REG_UDC_INCSR       0x12 /* EP1-2 IN CSR LSB 8/16bit */
 115 +#define JZ_REG_UDC_INCSRH      0x13 /* EP1-2 IN CSR MSB 8-bit */
 116 +
 117 +#define JZ_REG_UDC_OUTMAXP     0x14 /* EP1 OUT Max Pkt Size 16-bit */
 118 +#define JZ_REG_UDC_OUTCSR      0x16 /* EP1 OUT CSR LSB 8/16bit */
 119 +#define JZ_REG_UDC_OUTCSRH     0x17 /* EP1 OUT CSR MSB 8-bit */
 120 +#define JZ_REG_UDC_OUTCOUNT    0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
 121 +
 122 +#define JZ_REG_UDC_EP_FIFO(x)  (4 * (x) + 0x20)
 123 +
 124 +#define JZ_REG_UDC_EPINFO      0x78 /* Endpoint information */
 125 +#define JZ_REG_UDC_RAMINFO     0x79 /* RAM information */
 126 +
 127 +#define JZ_REG_UDC_INTR                0x200 /* DMA pending interrupts */
 128 +#define JZ_REG_UDC_CNTL1       0x204 /* DMA channel 1 control */
 129 +#define JZ_REG_UDC_ADDR1       0x208 /* DMA channel 1 AHB memory addr */
 130 +#define JZ_REG_UDC_COUNT1      0x20c /* DMA channel 1 byte count */
 131 +#define JZ_REG_UDC_CNTL2       0x214 /* DMA channel 2 control */
 132 +#define JZ_REG_UDC_ADDR2       0x218 /* DMA channel 2 AHB memory addr */
 133 +#define JZ_REG_UDC_COUNT2      0x21c /* DMA channel 2 byte count */
 134 +
 135 +/* Power register bit masks */
 136 +#define USB_POWER_SUSPENDM     0x01
 137 +#define USB_POWER_RESUME       0x04
 138 +#define USB_POWER_HSMODE       0x10
 139 +#define USB_POWER_HSENAB       0x20
 140 +#define USB_POWER_SOFTCONN     0x40
 141 +
 142 +/* Interrupt register bit masks */
 143 +#define USB_INTR_SUSPEND       0x01
 144 +#define USB_INTR_RESUME                0x02
 145 +#define USB_INTR_RESET         0x04
 146 +
 147 +#define USB_INTR_EP0           0x0001
 148 +#define USB_INTR_INEP1         0x0002
 149 +#define USB_INTR_INEP2         0x0004
 150 +#define USB_INTR_OUTEP1                0x0002
 151 +
 152 +/* CSR0 bit masks */
 153 +#define USB_CSR0_OUTPKTRDY     0x01
 154 +#define USB_CSR0_INPKTRDY      0x02
 155 +#define USB_CSR0_SENTSTALL     0x04
 156 +#define USB_CSR0_DATAEND       0x08
 157 +#define USB_CSR0_SETUPEND      0x10
 158 +#define USB_CSR0_SENDSTALL     0x20
 159 +#define USB_CSR0_SVDOUTPKTRDY  0x40
 160 +#define USB_CSR0_SVDSETUPEND   0x80
 161 +
 162 +/* Endpoint CSR register bits */
 163 +#define USB_INCSRH_AUTOSET     0x80
 164 +#define USB_INCSRH_ISO         0x40
 165 +#define USB_INCSRH_MODE                0x20
 166 +#define USB_INCSRH_DMAREQENAB  0x10
 167 +#define USB_INCSRH_DMAREQMODE  0x04
 168 +#define USB_INCSR_CDT          0x40
 169 +#define USB_INCSR_SENTSTALL    0x20
 170 +#define USB_INCSR_SENDSTALL    0x10
 171 +#define USB_INCSR_FF           0x08
 172 +#define USB_INCSR_UNDERRUN     0x04
 173 +#define USB_INCSR_FFNOTEMPT    0x02
 174 +#define USB_INCSR_INPKTRDY     0x01
 175 +
 176 +#define USB_OUTCSRH_AUTOCLR    0x80
 177 +#define USB_OUTCSRH_ISO                0x40
 178 +#define USB_OUTCSRH_DMAREQENAB 0x20
 179 +#define USB_OUTCSRH_DNYT       0x10
 180 +#define USB_OUTCSRH_DMAREQMODE 0x08
 181 +#define USB_OUTCSR_CDT         0x80
 182 +#define USB_OUTCSR_SENTSTALL   0x40
 183 +#define USB_OUTCSR_SENDSTALL   0x20
 184 +#define USB_OUTCSR_FF          0x10
 185 +#define USB_OUTCSR_DATAERR     0x08
 186 +#define USB_OUTCSR_OVERRUN     0x04
 187 +#define USB_OUTCSR_FFFULL      0x02
 188 +#define USB_OUTCSR_OUTPKTRDY   0x01
 189 +
 190 +/* DMA control bits */
 191 +#define USB_CNTL_ENA           0x01
 192 +#define USB_CNTL_DIR_IN                0x02
 193 +#define USB_CNTL_MODE_1                0x04
 194 +#define USB_CNTL_INTR_EN       0x08
 195 +#define USB_CNTL_EP(n)         ((n) << 4)
 196 +#define USB_CNTL_BURST_0       (0 << 9)
 197 +#define USB_CNTL_BURST_4       (1 << 9)
 198 +#define USB_CNTL_BURST_8       (2 << 9)
 199 +#define USB_CNTL_BURST_16      (3 << 9)
 200 +
 201 +
 202 +#ifndef DEBUG
 203 +# define DEBUG(fmt,args...) do {} while(0)
 204 +#endif
 205 +#ifndef DEBUG_EP0
 206 +# define NO_STATES
 207 +# define DEBUG_EP0(fmt,args...) do {} while(0)
 208 +#endif
 209 +#ifndef DEBUG_SETUP
 210 +# define DEBUG_SETUP(fmt,args...) do {} while(0)
 211 +#endif
 212 +
 213 +/*
 214 + * Local declarations.
 215 + */
 216 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
 217 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
 218 +
 219 +static void done(struct jz4740_ep *ep, struct jz4740_request *req,
 220 +                int status);
 221 +static void pio_irq_enable(struct jz4740_ep *ep);
 222 +static void pio_irq_disable(struct jz4740_ep *ep);
 223 +static void stop_activity(struct jz4740_udc *dev,
 224 +                         struct usb_gadget_driver *driver);
 225 +static void nuke(struct jz4740_ep *ep, int status);
 226 +static void flush(struct jz4740_ep *ep);
 227 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
 228 +
 229 +/*-------------------------------------------------------------------------*/
 230 +
 231 +/* inline functions of register read/write/set/clear  */
 232 +
 233 +static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
 234 +{
 235 +       return readb(udc->base + reg);
 236 +}
 237 +
 238 +static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
 239 +{
 240 +       return readw(udc->base + reg);
 241 +}
 242 +
 243 +static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
 244 +{
 245 +       return readl(udc->base + reg);
 246 +}
 247 +
 248 +static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
 249 +{
 250 +       writeb(val, udc->base + reg);
 251 +}
 252 +
 253 +static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
 254 +{
 255 +       writew(val, udc->base + reg);
 256 +}
 257 +
 258 +static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
 259 +{
 260 +       writel(val, udc->base + reg);
 261 +}
 262 +
 263 +static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
 264 +{
 265 +       usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
 266 +}
 267 +
 268 +static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
 269 +{
 270 +       usb_writew(udc, reg, usb_readw(udc, reg) | mask);
 271 +}
 272 +
 273 +static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
 274 +{
 275 +       usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
 276 +}
 277 +
 278 +static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
 279 +{
 280 +       usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
 281 +}
 282 +
 283 +/*-------------------------------------------------------------------------*/
 284 +
 285 +static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
 286 +{
 287 +       usb_writeb(udc, JZ_REG_UDC_INDEX, index);
 288 +}
 289 +
 290 +static inline void jz_udc_select_ep(struct jz4740_ep *ep)
 291 +{
 292 +       jz_udc_set_index(ep->dev, ep_index(ep));
 293 +}
 294 +
 295 +static inline int write_packet(struct jz4740_ep *ep,
 296 +                                  struct jz4740_request *req, unsigned int count)
 297 +{
 298 +       uint8_t *buf;
 299 +       unsigned int length;
 300 +       void __iomem *fifo = ep->dev->base + ep->fifo;
 301 +
 302 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 303 +
 304 +       buf = req->req.buf + req->req.actual;
 305 +
 306 +       length = req->req.length - req->req.actual;
 307 +       if (length > count)
 308 +               length = count;
 309 +       req->req.actual += length;
 310 +
 311 +       DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo);
 312 +
 313 +       writesl(fifo, buf, length >> 2);
 314 +       writesb(fifo, &buf[length - (length & 3)], length & 3);
 315 +
 316 +       return length;
 317 +}
 318 +
 319 +static int read_packet(struct jz4740_ep *ep,
 320 +                                 struct jz4740_request *req, unsigned int count)
 321 +{
 322 +       uint8_t *buf;
 323 +       unsigned int length;
 324 +       void __iomem *fifo = ep->dev->base + ep->fifo;
 325 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 326 +
 327 +       buf = req->req.buf + req->req.actual;
 328 +
 329 +       length = req->req.length - req->req.actual;
 330 +       if (length > count)
 331 +               length = count;
 332 +       req->req.actual += length;
 333 +
 334 +       DEBUG("Read %d, fifo %x\n", length, ep->fifo);
 335 +
 336 +       readsl(fifo, buf, length >> 2);
 337 +       readsb(fifo, &buf[length - (length & 3)], length & 3);
 338 +
 339 +       return length;
 340 +}
 341 +
 342 +/*-------------------------------------------------------------------------*/
 343 +
 344 +/*
 345 + *     udc_disable - disable USB device controller
 346 + */
 347 +static void udc_disable(struct jz4740_udc *dev)
 348 +{
 349 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 350 +
 351 +       udc_set_address(dev, 0);
 352 +
 353 +       /* Disable interrupts */
 354 +       usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
 355 +       usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
 356 +       usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
 357 +
 358 +       /* Disable DMA */
 359 +       usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
 360 +       usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
 361 +
 362 +       /* Disconnect from usb */
 363 +       usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
 364 +
 365 +       /* Disable the USB PHY */
 366 +       clk_disable_unprepare(dev->clk);
 367 +
 368 +       dev->ep0state = WAIT_FOR_SETUP;
 369 +       dev->gadget.speed = USB_SPEED_UNKNOWN;
 370 +
 371 +       return;
 372 +}
 373 +
 374 +/*
 375 + *     udc_reinit - initialize software state
 376 + */
 377 +static void udc_reinit(struct jz4740_udc *dev)
 378 +{
 379 +       int i;
 380 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 381 +
 382 +       /* device/ep0 records init */
 383 +       INIT_LIST_HEAD(&dev->gadget.ep_list);
 384 +       INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
 385 +       dev->ep0state = WAIT_FOR_SETUP;
 386 +
 387 +       for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
 388 +               struct jz4740_ep *ep = &dev->ep[i];
 389 +
 390 +               if (i != 0)
 391 +                       list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
 392 +
 393 +               INIT_LIST_HEAD(&ep->queue);
 394 +               ep->desc = 0;
 395 +               ep->stopped = 0;
 396 +       }
 397 +}
 398 +
 399 +/* until it's enabled, this UDC should be completely invisible
 400 + * to any USB host.
 401 + */
 402 +static void udc_enable(struct jz4740_udc *dev)
 403 +{
 404 +       int i;
 405 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 406 +
 407 +       /* UDC state is incorrect - Added by River */
 408 +       if (dev->state != UDC_STATE_ENABLE) {
 409 +               return;
 410 +       }
 411 +
 412 +       dev->gadget.speed = USB_SPEED_UNKNOWN;
 413 +
 414 +       /* Flush FIFO for each */
 415 +       for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
 416 +               struct jz4740_ep *ep = &dev->ep[i];
 417 +
 418 +               jz_udc_select_ep(ep);
 419 +               flush(ep);
 420 +       }
 421 +
 422 +       /* Set this bit to allow the UDC entering low-power mode when
 423 +        * there are no actions on the USB bus.
 424 +        * UDC still works during this bit was set.
 425 +        */
 426 +       jz4740_clock_udc_enable_auto_suspend();
 427 +
 428 +       /* Enable the USB PHY */
 429 +       clk_prepare_enable(dev->clk);
 430 +
 431 +       /* Disable interrupts */
 432 +/*     usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
 433 +       usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
 434 +       usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
 435 +
 436 +       /* Enable interrupts */
 437 +       usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
 438 +       usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
 439 +       /* Don't enable rest of the interrupts */
 440 +       /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
 441 +          usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
 442 +
 443 +       /* Enable SUSPEND */
 444 +       /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
 445 +
 446 +       /* Enable HS Mode */
 447 +       usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
 448 +
 449 +       /* Let host detect UDC:
 450 +        * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
 451 +        * transistor on and pull the USBDP pin HIGH.
 452 +        */
 453 +       usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
 454 +
 455 +       return;
 456 +}
 457 +
 458 +/*-------------------------------------------------------------------------*/
 459 +
 460 +/* keeping it simple:
 461 + * - one bus driver, initted first;
 462 + * - one function driver, initted second
 463 + */
 464 +
 465 +/*
 466 + * Register entry point for the peripheral controller driver.
 467 + */
 468 +
 469 +static int jz4740_udc_start(struct usb_gadget *gadget,
 470 +       struct usb_gadget_driver *driver)
 471 +{
 472 +       struct jz4740_udc *udc = container_of(gadget, struct jz4740_udc, gadget);
 473 +
 474 +       /* hook up the driver */
 475 +       udc->driver = driver;
 476 +
 477 +
 478 +       /* then enable host detection and ep0; and we're ready
 479 +        * for set_configuration as well as eventual disconnect.
 480 +        */
 481 +       udc_enable(udc);
 482 +
 483 +       DEBUG("%s: registered gadget driver '%s'\n", gadget->name,
 484 +             driver->driver.name);
 485 +
 486 +       return 0;
 487 +}
 488 +
 489 +static void stop_activity(struct jz4740_udc *dev,
 490 +                         struct usb_gadget_driver *driver)
 491 +{
 492 +       int i;
 493 +
 494 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 495 +
 496 +       /* don't disconnect drivers more than once */
 497 +       if (dev->gadget.speed == USB_SPEED_UNKNOWN)
 498 +               driver = 0;
 499 +       dev->gadget.speed = USB_SPEED_UNKNOWN;
 500 +
 501 +       /* prevent new request submissions, kill any outstanding requests  */
 502 +       for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
 503 +               struct jz4740_ep *ep = &dev->ep[i];
 504 +
 505 +               ep->stopped = 1;
 506 +
 507 +               jz_udc_select_ep(ep);
 508 +               nuke(ep, -ESHUTDOWN);
 509 +       }
 510 +
 511 +       /* report disconnect; the driver is already quiesced */
 512 +       if (driver) {
 513 +               spin_unlock(&dev->lock);
 514 +               driver->disconnect(&dev->gadget);
 515 +               spin_lock(&dev->lock);
 516 +       }
 517 +
 518 +       /* re-init driver-visible data structures */
 519 +       udc_reinit(dev);
 520 +}
 521 +
 522 +
 523 +/*
 524 + * Unregister entry point for the peripheral controller driver.
 525 + */
 526 +static int jz4740_udc_stop(struct usb_gadget *gadget,
 527 +       struct usb_gadget_driver *driver)
 528 +{
 529 +       struct jz4740_udc *udc = container_of(gadget, struct jz4740_udc, gadget);
 530 +       unsigned long flags;
 531 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 532 +
 533 +       spin_lock_irqsave(&udc->lock, flags);
 534 +       udc->driver = NULL;
 535 +       stop_activity(udc, driver);
 536 +       spin_unlock_irqrestore(&udc->lock, flags);
 537 +
 538 +       udc_disable(udc);
 539 +
 540 +       DEBUG("unregistered driver '%s'\n", driver->driver.name);
 541 +
 542 +       return 0;
 543 +}
 544 +
 545 +/*-------------------------------------------------------------------------*/
 546 +
 547 +/** Write request to FIFO (max write == maxp size)
 548 + *  Return:  0 = still running, 1 = completed, negative = errno
 549 + *  NOTE: INDEX register must be set for EP
 550 + */
 551 +static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
 552 +{
 553 +       struct jz4740_udc *dev = ep->dev;
 554 +       uint32_t max, csr;
 555 +
 556 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 557 +       max = le16_to_cpu(ep->desc->wMaxPacketSize);
 558 +
 559 +       csr = usb_readb(dev, ep->csr);
 560 +
 561 +       if (!(csr & USB_INCSR_FFNOTEMPT)) {
 562 +               unsigned count;
 563 +               int is_last, is_short;
 564 +
 565 +               count = write_packet(ep, req, max);
 566 +               usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
 567 +
 568 +               /* last packet is usually short (or a zlp) */
 569 +               if (unlikely(count != max))
 570 +                       is_last = is_short = 1;
 571 +               else {
 572 +                       if (likely(req->req.length != req->req.actual)
 573 +                           || req->req.zero)
 574 +                               is_last = 0;
 575 +                       else
 576 +                               is_last = 1;
 577 +                       /* interrupt/iso maxpacket may not fill the fifo */
 578 +                       is_short = unlikely(max < ep_maxpacket(ep));
 579 +               }
 580 +
 581 +               DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
 582 +                     ep->ep.name, count,
 583 +                     is_last ? "/L" : "", is_short ? "/S" : "",
 584 +                     req->req.length - req->req.actual, req);
 585 +
 586 +               /* requests complete when all IN data is in the FIFO */
 587 +               if (is_last) {
 588 +                       done(ep, req, 0);
 589 +                       if (list_empty(&ep->queue)) {
 590 +                               pio_irq_disable(ep);
 591 +                       }
 592 +                       return 1;
 593 +               }
 594 +       } else {
 595 +               DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
 596 +       }
 597 +
 598 +       return 0;
 599 +}
 600 +
 601 +/** Read to request from FIFO (max read == bytes in fifo)
 602 + *  Return:  0 = still running, 1 = completed, negative = errno
 603 + *  NOTE: INDEX register must be set for EP
 604 + */
 605 +static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
 606 +{
 607 +       struct jz4740_udc *dev = ep->dev;
 608 +       uint32_t csr;
 609 +       unsigned count, is_short;
 610 +
 611 +       /* make sure there's a packet in the FIFO. */
 612 +       csr = usb_readb(dev, ep->csr);
 613 +       if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
 614 +               DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
 615 +               return -EINVAL;
 616 +       }
 617 +
 618 +       /* read all bytes from this packet */
 619 +       count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
 620 +
 621 +       is_short = (count < ep->ep.maxpacket);
 622 +
 623 +       count = read_packet(ep, req, count);
 624 +
 625 +       DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
 626 +             ep->ep.name, csr, count,
 627 +             is_short ? "/S" : "", req, req->req.actual, req->req.length);
 628 +
 629 +       /* Clear OutPktRdy */
 630 +       usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
 631 +
 632 +       /* completion */
 633 +       if (is_short || req->req.actual == req->req.length) {
 634 +               done(ep, req, 0);
 635 +
 636 +               if (list_empty(&ep->queue))
 637 +                       pio_irq_disable(ep);
 638 +               return 1;
 639 +       }
 640 +
 641 +       /* finished that packet.  the next one may be waiting... */
 642 +       return 0;
 643 +}
 644 +
 645 +/*
 646 + *     done - retire a request; caller blocked irqs
 647 + *  INDEX register is preserved to keep same
 648 + */
 649 +static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
 650 +{
 651 +       unsigned int stopped = ep->stopped;
 652 +       uint32_t index;
 653 +
 654 +       DEBUG("%s, %p\n", __FUNCTION__, ep);
 655 +       list_del_init(&req->queue);
 656 +
 657 +       if (likely(req->req.status == -EINPROGRESS))
 658 +               req->req.status = status;
 659 +       else
 660 +               status = req->req.status;
 661 +
 662 +       if (status && status != -ESHUTDOWN)
 663 +               DEBUG("complete %s req %p stat %d len %u/%u\n",
 664 +                     ep->ep.name, &req->req, status,
 665 +                     req->req.actual, req->req.length);
 666 +
 667 +       /* don't modify queue heads during completion callback */
 668 +       ep->stopped = 1;
 669 +       /* Read current index (completion may modify it) */
 670 +       index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
 671 +       spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
 672 +
 673 +       req->req.complete(&ep->ep, &req->req);
 674 +
 675 +       spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
 676 +       /* Restore index */
 677 +       jz_udc_set_index(ep->dev, index);
 678 +       ep->stopped = stopped;
 679 +}
 680 +
 681 +static inline unsigned int jz4740_udc_ep_irq_enable_reg(struct jz4740_ep *ep)
 682 +{
 683 +       if (ep_is_in(ep))
 684 +               return JZ_REG_UDC_INTRINE;
 685 +       else
 686 +               return JZ_REG_UDC_INTROUTE;
 687 +}
 688 +
 689 +/** Enable EP interrupt */
 690 +static void pio_irq_enable(struct jz4740_ep *ep)
 691 +{
 692 +       DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
 693 +
 694 +       usb_setw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
 695 +}
 696 +
 697 +/** Disable EP interrupt */
 698 +static void pio_irq_disable(struct jz4740_ep *ep)
 699 +{
 700 +       DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
 701 +
 702 +       usb_clearw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
 703 +}
 704 +
 705 +/*
 706 + *     nuke - dequeue ALL requests
 707 + */
 708 +static void nuke(struct jz4740_ep *ep, int status)
 709 +{
 710 +       struct jz4740_request *req;
 711 +
 712 +       DEBUG("%s, %p\n", __FUNCTION__, ep);
 713 +
 714 +       /* Flush FIFO */
 715 +       flush(ep);
 716 +
 717 +       /* called with irqs blocked */
 718 +       while (!list_empty(&ep->queue)) {
 719 +               req = list_entry(ep->queue.next, struct jz4740_request, queue);
 720 +               done(ep, req, status);
 721 +       }
 722 +
 723 +       /* Disable IRQ if EP is enabled (has descriptor) */
 724 +       if (ep->desc)
 725 +               pio_irq_disable(ep);
 726 +}
 727 +
 728 +/** Flush EP FIFO
 729 + * NOTE: INDEX register must be set before this call
 730 + */
 731 +static void flush(struct jz4740_ep *ep)
 732 +{
 733 +       DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
 734 +
 735 +       switch (ep->type) {
 736 +       case ep_bulk_in:
 737 +       case ep_interrupt:
 738 +               usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
 739 +               break;
 740 +       case ep_bulk_out:
 741 +               usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
 742 +               break;
 743 +       case ep_control:
 744 +               break;
 745 +       }
 746 +}
 747 +
 748 +/**
 749 + * jz4740_in_epn - handle IN interrupt
 750 + */
 751 +static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
 752 +{
 753 +       uint32_t csr;
 754 +       struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
 755 +       struct jz4740_request *req;
 756 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 757 +
 758 +       jz_udc_select_ep(ep);
 759 +
 760 +       csr = usb_readb(dev, ep->csr);
 761 +       DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
 762 +
 763 +       if (csr & USB_INCSR_SENTSTALL) {
 764 +               DEBUG("USB_INCSR_SENTSTALL\n");
 765 +               usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
 766 +               return;
 767 +       }
 768 +
 769 +       if (!ep->desc) {
 770 +               DEBUG("%s: NO EP DESC\n", __FUNCTION__);
 771 +               return;
 772 +       }
 773 +
 774 +       if (!list_empty(&ep->queue)) {
 775 +               req = list_first_entry(&ep->queue, struct jz4740_request, queue);
 776 +               write_fifo(ep, req);
 777 +       }
 778 +}
 779 +
 780 +/*
 781 + * Bulk OUT (recv)
 782 + */
 783 +static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
 784 +{
 785 +       struct jz4740_ep *ep = &dev->ep[ep_idx];
 786 +       struct jz4740_request *req;
 787 +
 788 +       DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
 789 +
 790 +       jz_udc_select_ep(ep);
 791 +       if (ep->desc) {
 792 +               uint32_t csr;
 793 +
 794 +               while ((csr = usb_readb(dev, ep->csr)) &
 795 +                      (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
 796 +                       DEBUG("%s: %x\n", __FUNCTION__, csr);
 797 +
 798 +                       if (csr & USB_OUTCSR_SENTSTALL) {
 799 +                               DEBUG("%s: stall sent, flush fifo\n",
 800 +                                     __FUNCTION__);
 801 +                               /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
 802 +                               flush(ep);
 803 +                       } else if (csr & USB_OUTCSR_OUTPKTRDY) {
 804 +                               if (list_empty(&ep->queue))
 805 +                                       req = 0;
 806 +                               else
 807 +                                       req =
 808 +                                               list_entry(ep->queue.next,
 809 +                                                          struct jz4740_request,
 810 +                                                          queue);
 811 +
 812 +                               if (!req) {
 813 +                                       DEBUG("%s: NULL REQ %d\n",
 814 +                                             __FUNCTION__, ep_idx);
 815 +                                       break;
 816 +                               } else {
 817 +                                       read_fifo(ep, req);
 818 +                               }
 819 +                       }
 820 +               }
 821 +       } else {
 822 +               /* Throw packet away.. */
 823 +               DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
 824 +               flush(ep);
 825 +       }
 826 +}
 827 +
 828 +/** Halt specific EP
 829 + *  Return 0 if success
 830 + *  NOTE: Sets INDEX register to EP !
 831 + */
 832 +static int jz4740_set_halt(struct usb_ep *_ep, int value)
 833 +{
 834 +       struct jz4740_udc *dev;
 835 +       struct jz4740_ep *ep;
 836 +       unsigned long flags;
 837 +
 838 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
 839 +
 840 +       ep = container_of(_ep, struct jz4740_ep, ep);
 841 +       if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
 842 +               DEBUG("%s, bad ep\n", __FUNCTION__);
 843 +               return -EINVAL;
 844 +       }
 845 +
 846 +       dev = ep->dev;
 847 +
 848 +       spin_lock_irqsave(&dev->lock, flags);
 849 +
 850 +       jz_udc_select_ep(ep);
 851 +
 852 +       DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
 853 +
 854 +       if (ep_index(ep) == 0) {
 855 +               /* EP0 */
 856 +               usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
 857 +       } else if (ep_is_in(ep)) {
 858 +               uint32_t csr = usb_readb(dev, ep->csr);
 859 +               if (value && ((csr & USB_INCSR_FFNOTEMPT)
 860 +                             || !list_empty(&ep->queue))) {
 861 +                       /*
 862 +                        * Attempts to halt IN endpoints will fail (returning -EAGAIN)
 863 +                        * if any transfer requests are still queued, or if the controller
 864 +                        * FIFO still holds bytes that the host hasn\92t collected.
 865 +                        */
 866 +                       spin_unlock_irqrestore(&dev->lock, flags);
 867 +                       DEBUG
 868 +                           ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
 869 +                            (csr & USB_INCSR_FFNOTEMPT),
 870 +                            !list_empty(&ep->queue));
 871 +                       return -EAGAIN;
 872 +               }
 873 +               flush(ep);
 874 +               if (value) {
 875 +                       usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
 876 +               } else {
 877 +                       usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
 878 +                       usb_setb(dev, ep->csr, USB_INCSR_CDT);
 879 +               }
 880 +       } else {
 881 +
 882 +               flush(ep);
 883 +               if (value) {
 884 +                       usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
 885 +               } else {
 886 +                       usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
 887 +                       usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
 888 +               }
 889 +       }
 890 +
 891 +       ep->stopped = value;
 892 +
 893 +       spin_unlock_irqrestore(&dev->lock, flags);
 894 +
 895 +       DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
 896 +
 897 +       return 0;
 898 +}
 899 +
 900 +
 901 +static int jz4740_ep_enable(struct usb_ep *_ep,
 902 +                           const struct usb_endpoint_descriptor *desc)
 903 +{
 904 +       struct jz4740_ep *ep;
 905 +       struct jz4740_udc *dev;
 906 +       unsigned long flags;
 907 +       uint32_t max, csrh = 0;
 908 +
 909 +       DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
 910 +
 911 +       if (!_ep || !desc)
 912 +               return -EINVAL;
 913 +
 914 +       ep = container_of(_ep, struct jz4740_ep, ep);
 915 +       if (ep->desc || ep->type == ep_control
 916 +           || desc->bDescriptorType != USB_DT_ENDPOINT
 917 +           || ep->bEndpointAddress != desc->bEndpointAddress) {
 918 +               DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
 919 +               return -EINVAL;
 920 +       }
 921 +
 922 +       /* xfer types must match, except that interrupt ~= bulk */
 923 +       if (ep->bmAttributes != desc->bmAttributes
 924 +           && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 925 +           && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 926 +               DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 927 +               return -EINVAL;
 928 +       }
 929 +
 930 +       dev = ep->dev;
 931 +       if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 932 +               DEBUG("%s, bogus device state\n", __FUNCTION__);
 933 +               return -ESHUTDOWN;
 934 +       }
 935 +
 936 +       max = le16_to_cpu(desc->wMaxPacketSize);
 937 +
 938 +       spin_lock_irqsave(&ep->dev->lock, flags);
 939 +
 940 +       /* Configure the endpoint */
 941 +       jz_udc_select_ep(ep);
 942 +       if (ep_is_in(ep)) {
 943 +               usb_writew(dev, JZ_REG_UDC_INMAXP, max);
 944 +               switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
 945 +               case USB_ENDPOINT_XFER_BULK:
 946 +               case USB_ENDPOINT_XFER_INT:
 947 +                       csrh &= ~USB_INCSRH_ISO;
 948 +                       break;
 949 +               case USB_ENDPOINT_XFER_ISOC:
 950 +                       csrh |= USB_INCSRH_ISO;
 951 +                       break;
 952 +               }
 953 +               usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
 954 +       }
 955 +       else {
 956 +               usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
 957 +               switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
 958 +               case USB_ENDPOINT_XFER_BULK:
 959 +                        csrh &= ~USB_OUTCSRH_ISO;
 960 +                       break;
 961 +               case USB_ENDPOINT_XFER_INT:
 962 +                       csrh &= ~USB_OUTCSRH_ISO;
 963 +                       csrh |= USB_OUTCSRH_DNYT;
 964 +                       break;
 965 +               case USB_ENDPOINT_XFER_ISOC:
 966 +                       csrh |= USB_OUTCSRH_ISO;
 967 +                       break;
 968 +               }
 969 +               usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
 970 +       }
 971 +
 972 +
 973 +       ep->stopped = 0;
 974 +       ep->desc = desc;
 975 +       ep->ep.maxpacket = max;
 976 +
 977 +       spin_unlock_irqrestore(&ep->dev->lock, flags);
 978 +
 979 +       /* Reset halt state (does flush) */
 980 +       jz4740_set_halt(_ep, 0);
 981 +
 982 +       DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
 983 +
 984 +       return 0;
 985 +}
 986 +
 987 +/** Disable EP
 988 + *  NOTE: Sets INDEX register
 989 + */
 990 +static int jz4740_ep_disable(struct usb_ep *_ep)
 991 +{
 992 +       struct jz4740_ep *ep;
 993 +       unsigned long flags;
 994 +
 995 +       DEBUG("%s, %p\n", __FUNCTION__, _ep);
 996 +
 997 +       ep = container_of(_ep, struct jz4740_ep, ep);
 998 +       if (!_ep || !ep->desc) {
 999 +               DEBUG("%s, %s not enabled\n", __FUNCTION__,
1000 +                     _ep ? ep->ep.name : NULL);
1001 +               return -EINVAL;
1002 +       }
1003 +
1004 +       spin_lock_irqsave(&ep->dev->lock, flags);
1005 +
1006 +       jz_udc_select_ep(ep);
1007 +
1008 +       /* Nuke all pending requests (does flush) */
1009 +       nuke(ep, -ESHUTDOWN);
1010 +
1011 +       /* Disable ep IRQ */
1012 +       pio_irq_disable(ep);
1013 +
1014 +       ep->desc = 0;
1015 +       ep->stopped = 1;
1016 +
1017 +       spin_unlock_irqrestore(&ep->dev->lock, flags);
1018 +
1019 +       DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1020 +       return 0;
1021 +}
1022 +
1023 +static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1024 +{
1025 +       struct jz4740_request *req;
1026 +
1027 +       req = kzalloc(sizeof(*req), gfp_flags);
1028 +       if (!req)
1029 +               return NULL;
1030 +
1031 +       INIT_LIST_HEAD(&req->queue);
1032 +
1033 +       return &req->req;
1034 +}
1035 +
1036 +static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1037 +{
1038 +       struct jz4740_request *req;
1039 +
1040 +       req = container_of(_req, struct jz4740_request, req);
1041 +       WARN_ON(!list_empty(&req->queue));
1042 +
1043 +       kfree(req);
1044 +}
1045 +
1046 +/*--------------------------------------------------------------------*/
1047 +
1048 +/** Queue one request
1049 + *  Kickstart transfer if needed
1050 + *  NOTE: Sets INDEX register
1051 + */
1052 +static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1053 +                       gfp_t gfp_flags)
1054 +{
1055 +       struct jz4740_request *req;
1056 +       struct jz4740_ep *ep;
1057 +       struct jz4740_udc *dev;
1058 +
1059 +       DEBUG("%s, %p\n", __FUNCTION__, _ep);
1060 +
1061 +       req = container_of(_req, struct jz4740_request, req);
1062 +       if (unlikely
1063 +           (!_req || !_req->complete || !_req->buf
1064 +            || !list_empty(&req->queue))) {
1065 +               DEBUG("%s, bad params\n", __FUNCTION__);
1066 +               return -EINVAL;
1067 +       }
1068 +
1069 +       ep = container_of(_ep, struct jz4740_ep, ep);
1070 +       if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1071 +               DEBUG("%s, bad ep\n", __FUNCTION__);
1072 +               return -EINVAL;
1073 +       }
1074 +
1075 +       dev = ep->dev;
1076 +       if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1077 +               DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1078 +               return -ESHUTDOWN;
1079 +       }
1080 +
1081 +       DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1082 +             _req->buf);
1083 +
1084 +       spin_lock_irqsave(&dev->lock, dev->lock_flags);
1085 +
1086 +       _req->status = -EINPROGRESS;
1087 +       _req->actual = 0;
1088 +
1089 +       /* kickstart this i/o queue? */
1090 +       DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1091 +             ep->stopped);
1092 +       if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1093 +               uint32_t csr;
1094 +
1095 +               if (unlikely(ep_index(ep) == 0)) {
1096 +                       /* EP0 */
1097 +                       list_add_tail(&req->queue, &ep->queue);
1098 +                       jz4740_ep0_kick(dev, ep);
1099 +                       req = 0;
1100 +               }
1101 +               else if (ep_is_in(ep)) {
1102 +                       /* EP1 & EP2 */
1103 +                       jz_udc_select_ep(ep);
1104 +                       csr = usb_readb(dev, ep->csr);
1105 +                       pio_irq_enable(ep);
1106 +                       if (!(csr & USB_INCSR_FFNOTEMPT)) {
1107 +                               if (write_fifo(ep, req) == 1)
1108 +                                       req = 0;
1109 +                       }
1110 +               } else {
1111 +                       /* EP1 */
1112 +                       jz_udc_select_ep(ep);
1113 +                       csr = usb_readb(dev, ep->csr);
1114 +                       pio_irq_enable(ep);
1115 +                       if (csr & USB_OUTCSR_OUTPKTRDY) {
1116 +                               if (read_fifo(ep, req) == 1)
1117 +                                       req = 0;
1118 +                       }
1119 +               }
1120 +       }
1121 +
1122 +       /* pio or dma irq handler advances the queue. */
1123 +       if (likely(req != 0))
1124 +               list_add_tail(&req->queue, &ep->queue);
1125 +
1126 +       spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1127 +
1128 +       return 0;
1129 +}
1130 +
1131 +/* dequeue JUST ONE request */
1132 +static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1133 +{
1134 +       struct jz4740_ep *ep;
1135 +       struct jz4740_request *req;
1136 +       unsigned long flags;
1137 +
1138 +       DEBUG("%s, %p\n", __FUNCTION__, _ep);
1139 +
1140 +       ep = container_of(_ep, struct jz4740_ep, ep);
1141 +       if (!_ep || ep->type == ep_control)
1142 +               return -EINVAL;
1143 +
1144 +       spin_lock_irqsave(&ep->dev->lock, flags);
1145 +
1146 +       /* make sure it's actually queued on this endpoint */
1147 +       list_for_each_entry(req, &ep->queue, queue) {
1148 +               if (&req->req == _req)
1149 +                       break;
1150 +       }
1151 +       if (&req->req != _req) {
1152 +               spin_unlock_irqrestore(&ep->dev->lock, flags);
1153 +               return -EINVAL;
1154 +       }
1155 +       done(ep, req, -ECONNRESET);
1156 +
1157 +       spin_unlock_irqrestore(&ep->dev->lock, flags);
1158 +       return 0;
1159 +}
1160 +
1161 +/** Return bytes in EP FIFO
1162 + *  NOTE: Sets INDEX register to EP
1163 + */
1164 +static int jz4740_fifo_status(struct usb_ep *_ep)
1165 +{
1166 +       uint32_t csr;
1167 +       int count = 0;
1168 +       struct jz4740_ep *ep;
1169 +       unsigned long flags;
1170 +
1171 +       ep = container_of(_ep, struct jz4740_ep, ep);
1172 +       if (!_ep) {
1173 +               DEBUG("%s, bad ep\n", __FUNCTION__);
1174 +               return -ENODEV;
1175 +       }
1176 +
1177 +       DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1178 +
1179 +       /* LPD can't report unclaimed bytes from IN fifos */
1180 +       if (ep_is_in(ep))
1181 +               return -EOPNOTSUPP;
1182 +
1183 +       spin_lock_irqsave(&ep->dev->lock, flags);
1184 +       jz_udc_select_ep(ep);
1185 +
1186 +       csr = usb_readb(ep->dev, ep->csr);
1187 +       if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1188 +           csr & 0x1) {
1189 +               count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1190 +       }
1191 +
1192 +       spin_unlock_irqrestore(&ep->dev->lock, flags);
1193 +
1194 +       return count;
1195 +}
1196 +
1197 +/** Flush EP FIFO
1198 + *  NOTE: Sets INDEX register to EP
1199 + */
1200 +static void jz4740_fifo_flush(struct usb_ep *_ep)
1201 +{
1202 +       struct jz4740_ep *ep;
1203 +       unsigned long flags;
1204 +
1205 +       DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1206 +
1207 +       ep = container_of(_ep, struct jz4740_ep, ep);
1208 +       if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1209 +               DEBUG("%s, bad ep\n", __FUNCTION__);
1210 +               return;
1211 +       }
1212 +
1213 +       spin_lock_irqsave(&ep->dev->lock, flags);
1214 +
1215 +       jz_udc_select_ep(ep);
1216 +       flush(ep);
1217 +
1218 +       spin_unlock_irqrestore(&ep->dev->lock, flags);
1219 +}
1220 +
1221 +/****************************************************************/
1222 +/* End Point 0 related functions                                */
1223 +/****************************************************************/
1224 +
1225 +/* return:  0 = still running, 1 = completed, negative = errno */
1226 +static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1227 +{
1228 +       uint32_t max;
1229 +       unsigned count;
1230 +       int is_last;
1231 +
1232 +    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1233 +       max = ep_maxpacket(ep);
1234 +
1235 +       count = write_packet(ep, req, max);
1236 +
1237 +       /* last packet is usually short (or a zlp) */
1238 +       if (unlikely(count != max))
1239 +               is_last = 1;
1240 +       else {
1241 +               if (likely(req->req.length != req->req.actual) || req->req.zero)
1242 +                       is_last = 0;
1243 +               else
1244 +                       is_last = 1;
1245 +       }
1246 +
1247 +       DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1248 +                 ep->ep.name, count,
1249 +                 is_last ? "/L" : "", req->req.length - req->req.actual, req);
1250 +
1251 +       /* requests complete when all IN data is in the FIFO */
1252 +       if (is_last) {
1253 +               done(ep, req, 0);
1254 +               return 1;
1255 +       }
1256 +
1257 +       return 0;
1258 +}
1259 +
1260 +static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1261 +                                      unsigned char *cp, int max)
1262 +{
1263 +       int bytes;
1264 +       int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1265 +
1266 +       if (count > max)
1267 +               count = max;
1268 +       bytes = count;
1269 +       while (count--)
1270 +               *cp++ = usb_readb(ep->dev, ep->fifo);
1271 +
1272 +       return bytes;
1273 +}
1274 +
1275 +static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1276 +                                        unsigned char *cp, int count)
1277 +{
1278 +       DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1279 +       while (count--)
1280 +               usb_writeb(ep->dev, ep->fifo, *cp++);
1281 +}
1282 +
1283 +static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1284 +{
1285 +       struct jz4740_udc *dev = ep->dev;
1286 +       uint32_t csr;
1287 +       uint8_t *buf;
1288 +       unsigned bufferspace, count, is_short;
1289 +
1290 +       DEBUG_EP0("%s\n", __FUNCTION__);
1291 +
1292 +       csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1293 +       if (!(csr & USB_CSR0_OUTPKTRDY))
1294 +               return 0;
1295 +
1296 +       buf = req->req.buf + req->req.actual;
1297 +       prefetchw(buf);
1298 +       bufferspace = req->req.length - req->req.actual;
1299 +
1300 +       /* read all bytes from this packet */
1301 +       if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1302 +               count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1303 +               req->req.actual += min(count, bufferspace);
1304 +       } else                  /* zlp */
1305 +               count = 0;
1306 +
1307 +       is_short = (count < ep->ep.maxpacket);
1308 +       DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1309 +                 ep->ep.name, csr, count,
1310 +                 is_short ? "/S" : "", req, req->req.actual, req->req.length);
1311 +
1312 +       while (likely(count-- != 0)) {
1313 +               uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1314 +
1315 +               if (unlikely(bufferspace == 0)) {
1316 +                       /* this happens when the driver's buffer
1317 +                        * is smaller than what the host sent.
1318 +                        * discard the extra data.
1319 +                        */
1320 +                       if (req->req.status != -EOVERFLOW)
1321 +                               DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1322 +                                         count);
1323 +                       req->req.status = -EOVERFLOW;
1324 +               } else {
1325 +                       *buf++ = byte;
1326 +                       bufferspace--;
1327 +               }
1328 +       }
1329 +
1330 +       /* completion */
1331 +       if (is_short || req->req.actual == req->req.length) {
1332 +               done(ep, req, 0);
1333 +               return 1;
1334 +       }
1335 +
1336 +       /* finished that packet.  the next one may be waiting... */
1337 +       return 0;
1338 +}
1339 +
1340 +/**
1341 + * udc_set_address - set the USB address for this device
1342 + * @address:
1343 + *
1344 + * Called from control endpoint function after it decodes a set address setup packet.
1345 + */
1346 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1347 +{
1348 +       DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1349 +
1350 +       usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1351 +}
1352 +
1353 +/*
1354 + * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1355 + *      - if error
1356 + *              set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1357 + *      - else
1358 + *              set USB_CSR0_SVDOUTPKTRDY bit
1359 +                               if last set USB_CSR0_DATAEND bit
1360 + */
1361 +static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1362 +{
1363 +       struct jz4740_request *req;
1364 +       struct jz4740_ep *ep = &dev->ep[0];
1365 +       int ret;
1366 +
1367 +       DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1368 +
1369 +       if (list_empty(&ep->queue))
1370 +               req = 0;
1371 +       else
1372 +               req = list_entry(ep->queue.next, struct jz4740_request, queue);
1373 +
1374 +       if (req) {
1375 +               if (req->req.length == 0) {
1376 +                       DEBUG_EP0("ZERO LENGTH OUT!\n");
1377 +                       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1378 +                       dev->ep0state = WAIT_FOR_SETUP;
1379 +                       return;
1380 +               } else if (kickstart) {
1381 +                       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1382 +                       return;
1383 +               }
1384 +               ret = read_fifo_ep0(ep, req);
1385 +               if (ret) {
1386 +                       /* Done! */
1387 +                       DEBUG_EP0("%s: finished, waiting for status\n",
1388 +                                 __FUNCTION__);
1389 +                       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1390 +                       dev->ep0state = WAIT_FOR_SETUP;
1391 +               } else {
1392 +                       /* Not done yet.. */
1393 +                       DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1394 +                       usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1395 +               }
1396 +       } else {
1397 +               DEBUG_EP0("NO REQ??!\n");
1398 +       }
1399 +}
1400 +
1401 +/*
1402 + * DATA_STATE_XMIT
1403 + */
1404 +static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1405 +{
1406 +       struct jz4740_request *req;
1407 +       struct jz4740_ep *ep = &dev->ep[0];
1408 +       int ret, need_zlp = 0;
1409 +
1410 +       DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1411 +
1412 +       if (list_empty(&ep->queue))
1413 +               req = 0;
1414 +       else
1415 +               req = list_entry(ep->queue.next, struct jz4740_request, queue);
1416 +
1417 +       if (!req) {
1418 +               DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1419 +               return 0;
1420 +       }
1421 +
1422 +       if (req->req.length == 0) {
1423 +               usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1424 +               dev->ep0state = WAIT_FOR_SETUP;
1425 +               return 1;
1426 +       }
1427 +
1428 +       if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1429 +               /* Next write will end with the packet size, */
1430 +               /* so we need zero-length-packet */
1431 +               need_zlp = 1;
1432 +       }
1433 +
1434 +       ret = write_fifo_ep0(ep, req);
1435 +
1436 +       if (ret == 1 && !need_zlp) {
1437 +               /* Last packet */
1438 +               DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1439 +
1440 +               usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1441 +               dev->ep0state = WAIT_FOR_SETUP;
1442 +       } else {
1443 +               DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1444 +               usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1445 +       }
1446 +
1447 +       if (need_zlp) {
1448 +               DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1449 +               usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1450 +               dev->ep0state = DATA_STATE_NEED_ZLP;
1451 +       }
1452 +
1453 +       return 1;
1454 +}
1455 +
1456 +static int jz4740_handle_get_status(struct jz4740_udc *dev,
1457 +                                   struct usb_ctrlrequest *ctrl)
1458 +{
1459 +       struct jz4740_ep *ep0 = &dev->ep[0];
1460 +       struct jz4740_ep *qep;
1461 +       int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1462 +       uint16_t val = 0;
1463 +
1464 +    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1465 +
1466 +       if (reqtype == USB_RECIP_INTERFACE) {
1467 +               /* This is not supported.
1468 +                * And according to the USB spec, this one does nothing..
1469 +                * Just return 0
1470 +                */
1471 +               DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1472 +       } else if (reqtype == USB_RECIP_DEVICE) {
1473 +               DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1474 +               val |= (1 << 0);        /* Self powered */
1475 +               /*val |= (1<<1); *//* Remote wakeup */
1476 +       } else if (reqtype == USB_RECIP_ENDPOINT) {
1477 +               int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1478 +
1479 +               DEBUG_SETUP
1480 +                       ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1481 +                        ep_num, ctrl->wLength);
1482 +
1483 +               if (ctrl->wLength > 2 || ep_num > 3)
1484 +                       return -EOPNOTSUPP;
1485 +
1486 +               qep = &dev->ep[ep_num];
1487 +               if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1488 +                   && ep_index(qep) != 0) {
1489 +                       return -EOPNOTSUPP;
1490 +               }
1491 +
1492 +               jz_udc_select_ep(qep);
1493 +
1494 +               /* Return status on next IN token */
1495 +               switch (qep->type) {
1496 +               case ep_control:
1497 +                       val =
1498 +                           (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1499 +                           USB_CSR0_SENDSTALL;
1500 +                       break;
1501 +               case ep_bulk_in:
1502 +               case ep_interrupt:
1503 +                       val =
1504 +                           (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1505 +                           USB_INCSR_SENDSTALL;
1506 +                       break;
1507 +               case ep_bulk_out:
1508 +                       val =
1509 +                           (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1510 +                           USB_OUTCSR_SENDSTALL;
1511 +                       break;
1512 +               }
1513 +
1514 +               /* Back to EP0 index */
1515 +               jz_udc_set_index(dev, 0);
1516 +
1517 +               DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1518 +                           ctrl->wIndex, val);
1519 +       } else {
1520 +               DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1521 +               return -EOPNOTSUPP;
1522 +       }
1523 +
1524 +       /* Clear "out packet ready" */
1525 +       usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1526 +       /* Put status to FIFO */
1527 +       jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1528 +       /* Issue "In packet ready" */
1529 +       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1530 +
1531 +       return 0;
1532 +}
1533 +
1534 +/*
1535 + * WAIT_FOR_SETUP (OUTPKTRDY)
1536 + *      - read data packet from EP0 FIFO
1537 + *      - decode command
1538 + *      - if error
1539 + *              set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1540 + *      - else
1541 + *              set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1542 + */
1543 +static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1544 +{
1545 +       struct jz4740_ep *ep = &dev->ep[0];
1546 +       struct usb_ctrlrequest ctrl;
1547 +       int i;
1548 +
1549 +       DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1550 +
1551 +       /* Nuke all previous transfers */
1552 +       nuke(ep, -EPROTO);
1553 +
1554 +       /* read control req from fifo (8 bytes) */
1555 +       jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1556 +
1557 +       DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1558 +                   ctrl.bRequestType, ctrl.bRequest,
1559 +                   ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1560 +
1561 +       /* Set direction of EP0 */
1562 +       if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1563 +               ep->bEndpointAddress |= USB_DIR_IN;
1564 +       } else {
1565 +               ep->bEndpointAddress &= ~USB_DIR_IN;
1566 +       }
1567 +
1568 +       /* Handle some SETUP packets ourselves */
1569 +       switch (ctrl.bRequest) {
1570 +       case USB_REQ_SET_ADDRESS:
1571 +               if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1572 +                       break;
1573 +
1574 +               DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1575 +               udc_set_address(dev, ctrl.wValue);
1576 +               usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1577 +               return;
1578 +
1579 +       case USB_REQ_SET_CONFIGURATION:
1580 +               if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1581 +                       break;
1582 +
1583 +               DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1584 +/*             usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1585 +
1586 +               /* Enable RESUME and SUSPEND interrupts */
1587 +               usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1588 +               break;
1589 +
1590 +       case USB_REQ_SET_INTERFACE:
1591 +               if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1592 +                       break;
1593 +
1594 +               DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1595 +/*             usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1596 +               break;
1597 +
1598 +       case USB_REQ_GET_STATUS:
1599 +               if (jz4740_handle_get_status(dev, &ctrl) == 0)
1600 +                       return;
1601 +
1602 +       case USB_REQ_CLEAR_FEATURE:
1603 +       case USB_REQ_SET_FEATURE:
1604 +               if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1605 +                       struct jz4740_ep *qep;
1606 +                       int ep_num = (ctrl.wIndex & 0x0f);
1607 +
1608 +                       /* Support only HALT feature */
1609 +                       if (ctrl.wValue != 0 || ctrl.wLength != 0
1610 +                           || ep_num > 3 || ep_num < 1)
1611 +                               break;
1612 +
1613 +                       qep = &dev->ep[ep_num];
1614 +                       spin_unlock(&dev->lock);
1615 +                       if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1616 +                               DEBUG_SETUP("SET_FEATURE (%d)\n",
1617 +                                           ep_num);
1618 +                               jz4740_set_halt(&qep->ep, 1);
1619 +                       } else {
1620 +                               DEBUG_SETUP("CLR_FEATURE (%d)\n",
1621 +                                           ep_num);
1622 +                               jz4740_set_halt(&qep->ep, 0);
1623 +                       }
1624 +                       spin_lock(&dev->lock);
1625 +
1626 +                       jz_udc_set_index(dev, 0);
1627 +
1628 +                       /* Reply with a ZLP on next IN token */
1629 +                       usb_setb(dev, JZ_REG_UDC_CSR0,
1630 +                                (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1631 +                       return;
1632 +               }
1633 +               break;
1634 +
1635 +       default:
1636 +               break;
1637 +       }
1638 +
1639 +       /* gadget drivers see class/vendor specific requests,
1640 +        * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1641 +        * and more.
1642 +        */
1643 +       if (dev->driver) {
1644 +               /* device-2-host (IN) or no data setup command, process immediately */
1645 +               spin_unlock(&dev->lock);
1646 +
1647 +               i = dev->driver->setup(&dev->gadget, &ctrl);
1648 +               spin_lock(&dev->lock);
1649 +
1650 +               if (unlikely(i < 0)) {
1651 +                       /* setup processing failed, force stall */
1652 +                       DEBUG_SETUP
1653 +                           ("  --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1654 +                            i);
1655 +                       jz_udc_set_index(dev, 0);
1656 +                       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1657 +
1658 +                       /* ep->stopped = 1; */
1659 +                       dev->ep0state = WAIT_FOR_SETUP;
1660 +               }
1661 +               else {
1662 +                       DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1663 +/*                     if (!ctrl.wLength) {
1664 +                               usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1665 +                       }*/
1666 +               }
1667 +       }
1668 +}
1669 +
1670 +/*
1671 + * DATA_STATE_NEED_ZLP
1672 + */
1673 +static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1674 +{
1675 +       DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1676 +
1677 +       usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1678 +       dev->ep0state = WAIT_FOR_SETUP;
1679 +}
1680 +
1681 +/*
1682 + * handle ep0 interrupt
1683 + */
1684 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1685 +{
1686 +       struct jz4740_ep *ep = &dev->ep[0];
1687 +       uint32_t csr;
1688 +
1689 +    DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1690 +       /* Set index 0 */
1691 +       jz_udc_set_index(dev, 0);
1692 +       csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1693 +
1694 +       DEBUG_EP0("%s: csr = %x  state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1695 +
1696 +       /*
1697 +        * if SENT_STALL is set
1698 +        *      - clear the SENT_STALL bit
1699 +        */
1700 +       if (csr & USB_CSR0_SENTSTALL) {
1701 +               DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1702 +               usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1703 +               nuke(ep, -ECONNABORTED);
1704 +               dev->ep0state = WAIT_FOR_SETUP;
1705 +               return;
1706 +       }
1707 +
1708 +       /*
1709 +        * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1710 +        *      - fill EP0 FIFO
1711 +        *      - if last packet
1712 +        *      -       set IN_PKT_RDY | DATA_END
1713 +        *      - else
1714 +        *              set IN_PKT_RDY
1715 +        */
1716 +       if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1717 +               DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1718 +                         __FUNCTION__);
1719 +
1720 +               switch (dev->ep0state) {
1721 +               case DATA_STATE_XMIT:
1722 +                       DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1723 +                       jz4740_ep0_in(dev, csr);
1724 +                       return;
1725 +               case DATA_STATE_NEED_ZLP:
1726 +                       DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1727 +                       jz4740_ep0_in_zlp(dev, csr);
1728 +                       return;
1729 +               default:
1730 +                       /* Stall? */
1731 +//                     DEBUG_EP0("Odd state!! state = %s\n",
1732 +//                               state_names[dev->ep0state]);
1733 +                       dev->ep0state = WAIT_FOR_SETUP;
1734 +                       /* nuke(ep, 0); */
1735 +                       /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1736 +//                     break;
1737 +                       return;
1738 +               }
1739 +       }
1740 +
1741 +       /*
1742 +        * if SETUPEND is set
1743 +        *      - abort the last transfer
1744 +        *      - set SERVICED_SETUP_END_BIT
1745 +        */
1746 +       if (csr & USB_CSR0_SETUPEND) {
1747 +               DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1748 +
1749 +               usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1750 +               nuke(ep, 0);
1751 +               dev->ep0state = WAIT_FOR_SETUP;
1752 +       }
1753 +
1754 +       /*
1755 +        * if USB_CSR0_OUTPKTRDY is set
1756 +        *      - read data packet from EP0 FIFO
1757 +        *      - decode command
1758 +        *      - if error
1759 +        *              set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1760 +        *      - else
1761 +        *              set SVDOUTPKTRDY | DATAEND bits
1762 +        */
1763 +       if (csr & USB_CSR0_OUTPKTRDY) {
1764 +
1765 +               DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1766 +                         csr);
1767 +
1768 +               switch (dev->ep0state) {
1769 +               case WAIT_FOR_SETUP:
1770 +                       DEBUG_EP0("WAIT_FOR_SETUP\n");
1771 +                       jz4740_ep0_setup(dev, csr);
1772 +                       break;
1773 +
1774 +               case DATA_STATE_RECV:
1775 +                       DEBUG_EP0("DATA_STATE_RECV\n");
1776 +                       jz4740_ep0_out(dev, csr, 0);
1777 +                       break;
1778 +
1779 +               default:
1780 +                       /* send stall? */
1781 +                       DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
1782 +                                 dev->ep0state);
1783 +                       break;
1784 +               }
1785 +       }
1786 +}
1787 +
1788 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
1789 +{
1790 +       uint32_t csr;
1791 +
1792 +       jz_udc_set_index(dev, 0);
1793 +
1794 +       DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1795 +
1796 +       /* Clear "out packet ready" */
1797 +
1798 +       if (ep_is_in(ep)) {
1799 +               usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1800 +               csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1801 +               dev->ep0state = DATA_STATE_XMIT;
1802 +               jz4740_ep0_in(dev, csr);
1803 +       } else {
1804 +               csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1805 +               dev->ep0state = DATA_STATE_RECV;
1806 +               jz4740_ep0_out(dev, csr, 1);
1807 +       }
1808 +}
1809 +
1810 +/** Handle USB RESET interrupt
1811 + */
1812 +static void jz4740_reset_irq(struct jz4740_udc *dev)
1813 +{
1814 +       dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
1815 +               USB_SPEED_HIGH : USB_SPEED_FULL;
1816 +
1817 +       DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0,
1818 +                   (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
1819 +}
1820 +
1821 +/*
1822 + *     jz4740 usb device interrupt handler.
1823 + */
1824 +static irqreturn_t jz4740_udc_irq(int irq, void *devid)
1825 +{
1826 +       struct jz4740_udc *jz4740_udc = devid;
1827 +       uint8_t index;
1828 +
1829 +       uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
1830 +       uint32_t intr_in  = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN);
1831 +       uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT);
1832 +       uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR);
1833 +
1834 +       if (!intr_usb && !intr_in && !intr_out && !intr_dma)
1835 +               return IRQ_HANDLED;
1836 +
1837 +
1838 +       DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
1839 +             intr_out, intr_in, intr_usb);
1840 +
1841 +       spin_lock(&jz4740_udc->lock);
1842 +       index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX);
1843 +
1844 +       /* Check for resume from suspend mode */
1845 +       if ((intr_usb & USB_INTR_RESUME) &&
1846 +           (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
1847 +               DEBUG("USB resume\n");
1848 +               jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */
1849 +       }
1850 +
1851 +       /* Check for system interrupts */
1852 +       if (intr_usb & USB_INTR_RESET) {
1853 +               DEBUG("USB reset\n");
1854 +               jz4740_reset_irq(jz4740_udc);
1855 +       }
1856 +
1857 +       /* Check for endpoint 0 interrupt */
1858 +       if (intr_in & USB_INTR_EP0) {
1859 +               DEBUG("USB_INTR_EP0 (control)\n");
1860 +               jz4740_handle_ep0(jz4740_udc, intr_in);
1861 +       }
1862 +
1863 +       /* Check for Bulk-IN DMA interrupt */
1864 +       if (intr_dma & 0x1) {
1865 +               int ep_num;
1866 +               struct jz4740_ep *ep;
1867 +               ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
1868 +               ep = &jz4740_udc->ep[ep_num + 1];
1869 +               jz_udc_select_ep(ep);
1870 +               usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY);
1871 +/*             jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/
1872 +       }
1873 +
1874 +       /* Check for Bulk-OUT DMA interrupt */
1875 +       if (intr_dma & 0x2) {
1876 +               int ep_num;
1877 +               ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
1878 +               jz4740_out_epn(jz4740_udc, ep_num, intr_out);
1879 +       }
1880 +
1881 +       /* Check for each configured endpoint interrupt */
1882 +       if (intr_in & USB_INTR_INEP1) {
1883 +               DEBUG("USB_INTR_INEP1\n");
1884 +               jz4740_in_epn(jz4740_udc, 1, intr_in);
1885 +       }
1886 +
1887 +       if (intr_in & USB_INTR_INEP2) {
1888 +               DEBUG("USB_INTR_INEP2\n");
1889 +               jz4740_in_epn(jz4740_udc, 2, intr_in);
1890 +       }
1891 +
1892 +       if (intr_out & USB_INTR_OUTEP1) {
1893 +               DEBUG("USB_INTR_OUTEP1\n");
1894 +               jz4740_out_epn(jz4740_udc, 1, intr_out);
1895 +       }
1896 +
1897 +       /* Check for suspend mode */
1898 +       if ((intr_usb & USB_INTR_SUSPEND) &&
1899 +           (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
1900 +               DEBUG("USB suspend\n");
1901 +               jz4740_udc->driver->suspend(&jz4740_udc->gadget);
1902 +               /* Host unloaded from us, can do something, such as flushing
1903 +                the NAND block cache etc. */
1904 +       }
1905 +
1906 +    jz_udc_set_index(jz4740_udc, index);
1907 +
1908 +       spin_unlock(&jz4740_udc->lock);
1909 +
1910 +       return IRQ_HANDLED;
1911 +}
1912 +
1913 +
1914 +
1915 +/*-------------------------------------------------------------------------*/
1916 +
1917 +
1918 +static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
1919 +{
1920 +       return container_of(gadget, struct jz4740_udc, gadget);
1921 +}
1922 +
1923 +static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
1924 +{
1925 +       DEBUG("%s, %p\n", __FUNCTION__, _gadget);
1926 +       return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
1927 +}
1928 +
1929 +static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
1930 +{
1931 +       /* host may not have enabled remote wakeup */
1932 +       /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
1933 +          return -EHOSTUNREACH;
1934 +          udc_set_mask_UDCCR(UDCCR_RSM); */
1935 +       return -ENOTSUPP;
1936 +}
1937 +
1938 +static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
1939 +{
1940 +       struct jz4740_udc *udc = gadget_to_udc(_gadget);
1941 +       unsigned long flags;
1942 +
1943 +       local_irq_save(flags);
1944 +
1945 +       if (on) {
1946 +               udc->state = UDC_STATE_ENABLE;
1947 +               udc_enable(udc);
1948 +       } else {
1949 +               udc->state = UDC_STATE_DISABLE;
1950 +               udc_disable(udc);
1951 +       }
1952 +
1953 +       local_irq_restore(flags);
1954 +
1955 +       return 0;
1956 +}
1957 +
1958 +static const struct usb_gadget_ops jz4740_udc_ops = {
1959 +       .get_frame = jz4740_udc_get_frame,
1960 +       .wakeup = jz4740_udc_wakeup,
1961 +       .pullup = jz4740_udc_pullup,
1962 +       .udc_start = jz4740_udc_start,
1963 +       .udc_stop = jz4740_udc_stop,
1964 +};
1965 +
1966 +static struct usb_ep_ops jz4740_ep_ops = {
1967 +       .enable         = jz4740_ep_enable,
1968 +       .disable        = jz4740_ep_disable,
1969 +
1970 +       .alloc_request  = jz4740_alloc_request,
1971 +       .free_request   = jz4740_free_request,
1972 +
1973 +       .queue          = jz4740_queue,
1974 +       .dequeue        = jz4740_dequeue,
1975 +
1976 +       .set_halt       = jz4740_set_halt,
1977 +       .fifo_status    = jz4740_fifo_status,
1978 +       .fifo_flush     = jz4740_fifo_flush,
1979 +};
1980 +
1981 +
1982 +/*-------------------------------------------------------------------------*/
1983 +
1984 +static struct jz4740_udc jz4740_udc_controller = {
1985 +       .gadget = {
1986 +               .ops = &jz4740_udc_ops,
1987 +               .ep0 = &jz4740_udc_controller.ep[0].ep,
1988 +               .max_speed = USB_SPEED_HIGH,
1989 +               .name = "jz4740-udc",
1990 +               .dev = {
1991 +                       .init_name = "gadget",
1992 +               },
1993 +       },
1994 +
1995 +       /* control endpoint */
1996 +       .ep[0] = {
1997 +               .ep = {
1998 +                       .name = "ep0",
1999 +                       .ops = &jz4740_ep_ops,
2000 +                       .maxpacket = EP0_MAXPACKETSIZE,
2001 +               },
2002 +               .dev = &jz4740_udc_controller,
2003 +
2004 +               .bEndpointAddress = 0,
2005 +               .bmAttributes = 0,
2006 +
2007 +               .type = ep_control,
2008 +               .fifo = JZ_REG_UDC_EP_FIFO(0),
2009 +               .csr = JZ_REG_UDC_CSR0,
2010 +       },
2011 +
2012 +       /* bulk out endpoint */
2013 +       .ep[1] = {
2014 +               .ep = {
2015 +                       .name = "ep1out-bulk",
2016 +                       .ops = &jz4740_ep_ops,
2017 +                       .maxpacket = EPBULK_MAXPACKETSIZE,
2018 +               },
2019 +               .dev = &jz4740_udc_controller,
2020 +
2021 +               .bEndpointAddress = 1,
2022 +               .bmAttributes = USB_ENDPOINT_XFER_BULK,
2023 +
2024 +               .type = ep_bulk_out,
2025 +               .fifo = JZ_REG_UDC_EP_FIFO(1),
2026 +               .csr = JZ_REG_UDC_OUTCSR,
2027 +       },
2028 +
2029 +       /* bulk in endpoint */
2030 +       .ep[2] = {
2031 +               .ep = {
2032 +                       .name = "ep1in-bulk",
2033 +                       .ops = &jz4740_ep_ops,
2034 +                       .maxpacket = EPBULK_MAXPACKETSIZE,
2035 +               },
2036 +               .dev = &jz4740_udc_controller,
2037 +
2038 +               .bEndpointAddress = 1 | USB_DIR_IN,
2039 +               .bmAttributes = USB_ENDPOINT_XFER_BULK,
2040 +
2041 +               .type = ep_bulk_in,
2042 +               .fifo = JZ_REG_UDC_EP_FIFO(1),
2043 +               .csr = JZ_REG_UDC_INCSR,
2044 +       },
2045 +
2046 +       /* interrupt in endpoint */
2047 +       .ep[3] = {
2048 +               .ep = {
2049 +                       .name = "ep2in-int",
2050 +                       .ops = &jz4740_ep_ops,
2051 +                       .maxpacket = EPINTR_MAXPACKETSIZE,
2052 +               },
2053 +               .dev = &jz4740_udc_controller,
2054 +
2055 +               .bEndpointAddress = 2 | USB_DIR_IN,
2056 +               .bmAttributes = USB_ENDPOINT_XFER_INT,
2057 +
2058 +               .type = ep_interrupt,
2059 +               .fifo = JZ_REG_UDC_EP_FIFO(2),
2060 +               .csr = JZ_REG_UDC_INCSR,
2061 +       },
2062 +};
2063 +
2064 +static int jz4740_udc_probe(struct platform_device *pdev)
2065 +{
2066 +       struct jz4740_udc *jz4740_udc = &jz4740_udc_controller;
2067 +       int ret;
2068 +
2069 +       spin_lock_init(&jz4740_udc->lock);
2070 +
2071 +       jz4740_udc->dev = &pdev->dev;
2072 +
2073 +       jz4740_udc->clk = clk_get(&pdev->dev, "udc");
2074 +       if (IS_ERR(jz4740_udc->clk)) {
2075 +               ret = PTR_ERR(jz4740_udc->clk);
2076 +               dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2077 +               return ret;
2078 +       }
2079 +
2080 +       platform_set_drvdata(pdev, jz4740_udc);
2081 +
2082 +       jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2083 +
2084 +       if (!jz4740_udc->mem) {
2085 +               ret = -ENOENT;
2086 +               dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2087 +               goto err_clk_put;
2088 +       }
2089 +
2090 +       jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start,
2091 +       resource_size(jz4740_udc->mem), pdev->name);
2092 +
2093 +       if (!jz4740_udc->mem) {
2094 +               ret = -EBUSY;
2095 +               dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2096 +               goto err_clk_put;
2097 +       }
2098 +
2099 +       jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2100 +
2101 +       if (!jz4740_udc->base) {
2102 +               ret = -EBUSY;
2103 +               dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2104 +               goto err_release_mem_region;
2105 +       }
2106 +
2107 +       jz4740_udc->irq = platform_get_irq(pdev, 0);
2108 +       ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name,
2109 +       jz4740_udc);
2110 +       if (ret) {
2111 +               dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2112 +               goto err_iounmap;
2113 +       }
2114 +
2115 +       ret = usb_add_gadget_udc(&pdev->dev, &jz4740_udc->gadget);
2116 +       if (ret) {
2117 +               dev_err(&pdev->dev, "Failed to add gadget: %d\n", ret);
2118 +               goto err_free_irq;
2119 +       }
2120 +
2121 +/*     udc_disable(jz4740_udc);*/
2122 +       udc_reinit(jz4740_udc);
2123 +
2124 +       return 0;
2125 +
2126 +err_free_irq:
2127 +       free_irq(jz4740_udc->irq, pdev);
2128 +err_iounmap:
2129 +       iounmap(jz4740_udc->base);
2130 +err_release_mem_region:
2131 +       release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2132 +err_clk_put:
2133 +       clk_put(jz4740_udc->clk);
2134 +
2135 +       return ret;
2136 +}
2137 +
2138 +static int jz4740_udc_remove(struct platform_device *pdev)
2139 +{
2140 +       struct jz4740_udc *dev = platform_get_drvdata(pdev);
2141 +
2142 +       usb_del_gadget_udc(&dev->gadget);
2143 +       if (dev->driver)
2144 +               return -EBUSY;
2145 +
2146 +       udc_disable(dev);
2147 +
2148 +       free_irq(dev->irq, dev);
2149 +       iounmap(dev->base);
2150 +       release_mem_region(dev->mem->start, resource_size(dev->mem));
2151 +       clk_put(dev->clk);
2152 +
2153 +       return 0;
2154 +}
2155 +
2156 +#ifdef CONFIG_PM
2157 +
2158 +static int jz4740_udc_suspend(struct device *dev)
2159 +{
2160 +       struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2161 +
2162 +       if (jz4740_udc->state == UDC_STATE_ENABLE)
2163 +               udc_disable(jz4740_udc);
2164 +
2165 +       return 0;
2166 +}
2167 +
2168 +static int jz4740_udc_resume(struct device *dev)
2169 +{
2170 +       struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2171 +
2172 +       if (jz4740_udc->state == UDC_STATE_ENABLE)
2173 +               udc_enable(jz4740_udc);
2174 +
2175 +       return 0;
2176 +}
2177 +
2178 +static SIMPLE_DEV_PM_OPS(jz4740_udc_pm_ops, jz4740_udc_suspend, jz4740_udc_resume);
2179 +#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2180 +
2181 +#else
2182 +#define JZ4740_UDC_PM_OPS NULL
2183 +#endif
2184 +
2185 +static struct platform_driver udc_driver = {
2186 +       .probe          = jz4740_udc_probe,
2187 +       .remove         = jz4740_udc_remove,
2188 +       .driver         = {
2189 +               .name   = "jz-udc",
2190 +               .owner  = THIS_MODULE,
2191 +               .pm             = JZ4740_UDC_PM_OPS,
2192 +       },
2193 +};
2194 +
2195 +/*-------------------------------------------------------------------------*/
2196 +
2197 +static int __init udc_init (void)
2198 +{
2199 +       return platform_driver_register(&udc_driver);
2200 +}
2201 +module_init(udc_init);
2202 +
2203 +static void __exit udc_exit (void)
2204 +{
2205 +       platform_driver_unregister(&udc_driver);
2206 +}
2207 +module_exit(udc_exit);
2208 +
2209 +MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2210 +MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2211 +MODULE_LICENSE("GPL");
2212 --- /dev/null
2213 +++ b/drivers/usb/gadget/jz4740_udc.h
2214 @@ -0,0 +1,101 @@
2215 +/*
2216 + * linux/drivers/usb/gadget/jz4740_udc.h
2217 + *
2218 + * Ingenic JZ4740 on-chip high speed USB device controller
2219 + *
2220 + * Copyright (C) 2006 Ingenic Semiconductor Inc.
2221 + * Author: <jlwei@ingenic.cn>
2222 + *
2223 + * This program is free software; you can redistribute it and/or modify
2224 + * it under the terms of the GNU General Public License as published by
2225 + * the Free Software Foundation; either version 2 of the License, or
2226 + * (at your option) any later version.
2227 + */
2228 +
2229 +#ifndef __USB_GADGET_JZ4740_H__
2230 +#define __USB_GADGET_JZ4740_H__
2231 +
2232 +/*-------------------------------------------------------------------------*/
2233 +
2234 +// Max packet size
2235 +#define EP0_MAXPACKETSIZE      64
2236 +#define EPBULK_MAXPACKETSIZE   512
2237 +#define EPINTR_MAXPACKETSIZE   64
2238 +
2239 +#define UDC_MAX_ENDPOINTS       4
2240 +
2241 +/*-------------------------------------------------------------------------*/
2242 +
2243 +enum ep_type {
2244 +       ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
2245 +};
2246 +
2247 +struct jz4740_ep {
2248 +       struct usb_ep ep;
2249 +       struct jz4740_udc *dev;
2250 +
2251 +       const struct usb_endpoint_descriptor *desc;
2252 +
2253 +       uint8_t stopped;
2254 +       uint8_t bEndpointAddress;
2255 +       uint8_t bmAttributes;
2256 +
2257 +       enum ep_type type;
2258 +       size_t fifo;
2259 +       uint32_t csr;
2260 +
2261 +       uint32_t reg_addr;
2262 +       struct list_head queue;
2263 +};
2264 +
2265 +struct jz4740_request {
2266 +       struct usb_request req;
2267 +       struct list_head queue;
2268 +};
2269 +
2270 +enum ep0state {
2271 +       WAIT_FOR_SETUP,         /* between STATUS ack and SETUP report */
2272 +       DATA_STATE_XMIT,        /* data tx stage */
2273 +       DATA_STATE_NEED_ZLP,    /* data tx zlp stage */
2274 +       WAIT_FOR_OUT_STATUS,    /* status stages */
2275 +       DATA_STATE_RECV,        /* data rx stage */
2276 +};
2277 +
2278 +/* For function binding with UDC Disable - Added by River */
2279 +typedef enum {
2280 +       UDC_STATE_ENABLE = 0,
2281 +       UDC_STATE_DISABLE,
2282 +}udc_state_t;
2283 +
2284 +struct jz4740_udc {
2285 +       struct usb_gadget gadget;
2286 +       struct usb_gadget_driver *driver;
2287 +       struct device *dev;
2288 +       spinlock_t lock;
2289 +       unsigned long lock_flags;
2290 +
2291 +       enum ep0state ep0state;
2292 +       struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
2293 +
2294 +       udc_state_t state;
2295 +
2296 +       struct resource *mem;
2297 +       void __iomem *base;
2298 +       int irq;
2299 +
2300 +       struct clk *clk;
2301 +};
2302 +
2303 +#define ep_maxpacket(EP)       ((EP)->ep.maxpacket)
2304 +
2305 +static inline bool ep_is_in(const struct jz4740_ep *ep)
2306 +{
2307 +       return (ep->bEndpointAddress & USB_DIR_IN) == USB_DIR_IN;
2308 +}
2309 +
2310 +static inline uint8_t ep_index(const struct jz4740_ep *ep)
2311 +{
2312 +       return ep->bEndpointAddress & 0xf;
2313 +}
2314 +
2315 +#endif /* __USB_GADGET_JZ4740_H__ */