target/linux/xburst/patches-2.6.35/061-asoc.patch

   1 From def17bc36684a36ca60211759c84bcc43f4f385a Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 19 Jun 2010 16:50:37 +0200
   4 Subject: [PATCH] ASoC: Add JZ4740 ASoC support
   5
   6 This patch adds ASoC support for JZ4740 SoCs I2S module.
   7
   8 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
   9 Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
  10 Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
  11 ---
  12  sound/soc/Kconfig             |    1 +
  13  sound/soc/Makefile            |    1 +
  14  sound/soc/jz4740/Kconfig      |   14 +
  15  sound/soc/jz4740/Makefile     |    9 +
  16  sound/soc/jz4740/jz4740-i2s.c |  540 +++++++++++++++++++++++++++++++++++++++++
  17  sound/soc/jz4740/jz4740-i2s.h |   18 ++
  18  sound/soc/jz4740/jz4740-pcm.c |  373 ++++++++++++++++++++++++++++
  19  sound/soc/jz4740/jz4740-pcm.h |   22 ++
  20  8 files changed, 978 insertions(+), 0 deletions(-)
  21  create mode 100644 sound/soc/jz4740/Kconfig
  22  create mode 100644 sound/soc/jz4740/Makefile
  23  create mode 100644 sound/soc/jz4740/jz4740-i2s.c
  24  create mode 100644 sound/soc/jz4740/jz4740-i2s.h
  25  create mode 100644 sound/soc/jz4740/jz4740-pcm.c
  26  create mode 100644 sound/soc/jz4740/jz4740-pcm.h
  27
  28 --- a/sound/soc/Kconfig
  29 +++ b/sound/soc/Kconfig
  30 @@ -36,6 +36,7 @@ source "sound/soc/s3c24xx/Kconfig"
  31  source "sound/soc/s6000/Kconfig"
  32  source "sound/soc/sh/Kconfig"
  33  source "sound/soc/txx9/Kconfig"
  34 +source "sound/soc/jz4740/Kconfig"
  35
  36  # Supported codecs
  37  source "sound/soc/codecs/Kconfig"
  38 --- a/sound/soc/Makefile
  39 +++ b/sound/soc/Makefile
  40 @@ -14,3 +14,4 @@ obj-$(CONFIG_SND_SOC) += s3c24xx/
  41  obj-$(CONFIG_SND_SOC)  += s6000/
  42  obj-$(CONFIG_SND_SOC)  += sh/
  43  obj-$(CONFIG_SND_SOC)  += txx9/
  44 +obj-$(CONFIG_SND_SOC)  += jz4740/
  45 --- /dev/null
  46 +++ b/sound/soc/jz4740/Kconfig
  47 @@ -0,0 +1,14 @@
  48 +config SND_JZ4740_SOC
  49 +       tristate "SoC Audio for Ingenic JZ4740 SoC"
  50 +       depends on MACH_JZ4740 && SND_SOC
  51 +       help
  52 +         Say Y or M if you want to add support for codecs attached to
  53 +         the JZ4740 I2S interface. You will also need to select the audio
  54 +         interfaces to support below.
  55 +
  56 +config SND_JZ4740_SOC_I2S
  57 +       depends on SND_JZ4740_SOC
  58 +       tristate "SoC Audio (I2S protocol) for Ingenic JZ4740 SoC"
  59 +       help
  60 +         Say Y if you want to use I2S protocol and I2S codec on Ingenic JZ4740
  61 +         based boards.
  62 --- /dev/null
  63 +++ b/sound/soc/jz4740/Makefile
  64 @@ -0,0 +1,9 @@
  65 +#
  66 +# Jz4740 Platform Support
  67 +#
  68 +snd-soc-jz4740-objs := jz4740-pcm.o
  69 +snd-soc-jz4740-i2s-objs := jz4740-i2s.o
  70 +
  71 +obj-$(CONFIG_SND_JZ4740_SOC) += snd-soc-jz4740.o
  72 +obj-$(CONFIG_SND_JZ4740_SOC_I2S) += snd-soc-jz4740-i2s.o
  73 +
  74 --- /dev/null
  75 +++ b/sound/soc/jz4740/jz4740-i2s.c
  76 @@ -0,0 +1,540 @@
  77 +/*
  78 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  79 + *
  80 + *  This program is free software; you can redistribute it and/or modify it
  81 + *  under  the terms of the GNU General  Public License as published by the
  82 + *  Free Software Foundation;  either version 2 of the License, or (at your
  83 + *  option) any later version.
  84 + *
  85 + *  You should have received a copy of the GNU General Public License along
  86 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  87 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  88 + *
  89 + */
  90 +
  91 +#include <linux/init.h>
  92 +#include <linux/io.h>
  93 +#include <linux/kernel.h>
  94 +#include <linux/module.h>
  95 +#include <linux/platform_device.h>
  96 +#include <linux/slab.h>
  97 +
  98 +#include <linux/clk.h>
  99 +#include <linux/delay.h>
 100 +
 101 +#include <linux/dma-mapping.h>
 102 +
 103 +#include <sound/core.h>
 104 +#include <sound/pcm.h>
 105 +#include <sound/pcm_params.h>
 106 +#include <sound/soc.h>
 107 +#include <sound/soc-dapm.h>
 108 +#include <sound/initval.h>
 109 +
 110 +#include "jz4740-i2s.h"
 111 +#include "jz4740-pcm.h"
 112 +
 113 +#define JZ_REG_AIC_CONF                0x00
 114 +#define JZ_REG_AIC_CTRL                0x04
 115 +#define JZ_REG_AIC_I2S_FMT     0x10
 116 +#define JZ_REG_AIC_FIFO_STATUS 0x14
 117 +#define JZ_REG_AIC_I2S_STATUS  0x1c
 118 +#define JZ_REG_AIC_CLK_DIV     0x30
 119 +#define JZ_REG_AIC_FIFO                0x34
 120 +
 121 +#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
 122 +#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf <<  8)
 123 +#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
 124 +#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
 125 +#define JZ_AIC_CONF_I2S BIT(4)
 126 +#define JZ_AIC_CONF_RESET BIT(3)
 127 +#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
 128 +#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
 129 +#define JZ_AIC_CONF_ENABLE BIT(0)
 130 +
 131 +#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
 132 +#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
 133 +
 134 +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
 135 +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
 136 +#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
 137 +#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
 138 +#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
 139 +#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
 140 +#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
 141 +#define JZ_AIC_CTRL_FLUSH              BIT(8)
 142 +#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
 143 +#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
 144 +#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
 145 +#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
 146 +#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
 147 +#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
 148 +#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
 149 +
 150 +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
 151 +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET  16
 152 +
 153 +#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
 154 +#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
 155 +#define JZ_AIC_I2S_FMT_MSB BIT(0)
 156 +
 157 +#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
 158 +
 159 +#define JZ_AIC_CLK_DIV_MASK 0xf
 160 +
 161 +struct jz4740_i2s {
 162 +       struct resource *mem;
 163 +       void __iomem *base;
 164 +       dma_addr_t phys_base;
 165 +
 166 +       struct clk *clk_aic;
 167 +       struct clk *clk_i2s;
 168 +
 169 +       struct jz4740_pcm_config pcm_config_playback;
 170 +       struct jz4740_pcm_config pcm_config_capture;
 171 +};
 172 +
 173 +static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
 174 +       unsigned int reg)
 175 +{
 176 +       return readl(i2s->base + reg);
 177 +}
 178 +
 179 +static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
 180 +       unsigned int reg, uint32_t value)
 181 +{
 182 +       writel(value, i2s->base + reg);
 183 +}
 184 +
 185 +static inline struct jz4740_i2s *jz4740_dai_to_i2s(struct snd_soc_dai *dai)
 186 +{
 187 +       return dai->private_data;
 188 +}
 189 +
 190 +static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
 191 +       struct snd_soc_dai *dai)
 192 +{
 193 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 194 +       uint32_t conf, ctrl;
 195 +
 196 +       if (dai->active)
 197 +               return 0;
 198 +
 199 +       ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
 200 +       ctrl |= JZ_AIC_CTRL_FLUSH;
 201 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
 202 +
 203 +       clk_enable(i2s->clk_i2s);
 204 +
 205 +       conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 206 +       conf |= JZ_AIC_CONF_ENABLE;
 207 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 208 +
 209 +       return 0;
 210 +}
 211 +
 212 +static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
 213 +       struct snd_soc_dai *dai)
 214 +{
 215 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 216 +       uint32_t conf;
 217 +
 218 +       if (!dai->active)
 219 +               return;
 220 +
 221 +       conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 222 +       conf &= ~JZ_AIC_CONF_ENABLE;
 223 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 224 +
 225 +       clk_disable(i2s->clk_i2s);
 226 +}
 227 +
 228 +static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 229 +       struct snd_soc_dai *dai)
 230 +{
 231 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 232 +
 233 +       uint32_t ctrl;
 234 +       uint32_t mask;
 235 +
 236 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 237 +               mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
 238 +       else
 239 +               mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
 240 +
 241 +       ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
 242 +
 243 +       switch (cmd) {
 244 +       case SNDRV_PCM_TRIGGER_START:
 245 +       case SNDRV_PCM_TRIGGER_RESUME:
 246 +       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 247 +               ctrl |= mask;
 248 +               break;
 249 +       case SNDRV_PCM_TRIGGER_STOP:
 250 +       case SNDRV_PCM_TRIGGER_SUSPEND:
 251 +       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 252 +               ctrl &= ~mask;
 253 +               break;
 254 +       default:
 255 +               return -EINVAL;
 256 +       }
 257 +
 258 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
 259 +
 260 +       return 0;
 261 +}
 262 +
 263 +static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 264 +{
 265 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 266 +
 267 +       uint32_t format = 0;
 268 +       uint32_t conf;
 269 +
 270 +       conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 271 +
 272 +       conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
 273 +
 274 +       switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 275 +       case SND_SOC_DAIFMT_CBS_CFS:
 276 +               conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
 277 +               format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
 278 +               break;
 279 +       case SND_SOC_DAIFMT_CBM_CFS:
 280 +               conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
 281 +               break;
 282 +       case SND_SOC_DAIFMT_CBS_CFM:
 283 +               conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
 284 +               break;
 285 +       case SND_SOC_DAIFMT_CBM_CFM:
 286 +               break;
 287 +       default:
 288 +               return -EINVAL;
 289 +       }
 290 +
 291 +       switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 292 +       case SND_SOC_DAIFMT_MSB:
 293 +               format |= JZ_AIC_I2S_FMT_MSB;
 294 +               break;
 295 +       case SND_SOC_DAIFMT_I2S:
 296 +               break;
 297 +       default:
 298 +               return -EINVAL;
 299 +       }
 300 +
 301 +       switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 302 +       case SND_SOC_DAIFMT_NB_NF:
 303 +               break;
 304 +       default:
 305 +               return -EINVAL;
 306 +       }
 307 +
 308 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 309 +       jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
 310 +
 311 +       return 0;
 312 +}
 313 +
 314 +static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
 315 +       struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 316 +{
 317 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 318 +       enum jz4740_dma_width dma_width;
 319 +       struct jz4740_pcm_config *pcm_config;
 320 +       unsigned int sample_size;
 321 +       uint32_t ctrl;
 322 +
 323 +       ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
 324 +
 325 +       switch (params_format(params)) {
 326 +       case SNDRV_PCM_FORMAT_S8:
 327 +               sample_size = 0;
 328 +               dma_width = JZ4740_DMA_WIDTH_8BIT;
 329 +               break;
 330 +       case SNDRV_PCM_FORMAT_S16:
 331 +               sample_size = 1;
 332 +               dma_width = JZ4740_DMA_WIDTH_16BIT;
 333 +               break;
 334 +       default:
 335 +               return -EINVAL;
 336 +       }
 337 +
 338 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 339 +               ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
 340 +               ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
 341 +               if (params_channels(params) == 1)
 342 +                       ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
 343 +               else
 344 +                       ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
 345 +
 346 +               pcm_config = &i2s->pcm_config_playback;
 347 +               pcm_config->dma_config.dst_width = dma_width;
 348 +
 349 +       } else {
 350 +               ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
 351 +               ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
 352 +
 353 +               pcm_config = &i2s->pcm_config_capture;
 354 +               pcm_config->dma_config.src_width = dma_width;
 355 +       }
 356 +
 357 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
 358 +
 359 +       snd_soc_dai_set_dma_data(dai, substream, pcm_config);
 360 +
 361 +       return 0;
 362 +}
 363 +
 364 +static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 365 +       unsigned int freq, int dir)
 366 +{
 367 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 368 +       struct clk *parent;
 369 +       int ret = 0;
 370 +
 371 +       switch (clk_id) {
 372 +       case JZ4740_I2S_CLKSRC_EXT:
 373 +               parent = clk_get(NULL, "ext");
 374 +               clk_set_parent(i2s->clk_i2s, parent);
 375 +               break;
 376 +       case JZ4740_I2S_CLKSRC_PLL:
 377 +               parent = clk_get(NULL, "pll half");
 378 +               clk_set_parent(i2s->clk_i2s, parent);
 379 +               ret = clk_set_rate(i2s->clk_i2s, freq);
 380 +               break;
 381 +       default:
 382 +               return -EINVAL;
 383 +       }
 384 +       clk_put(parent);
 385 +
 386 +       return ret;
 387 +}
 388 +
 389 +static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
 390 +{
 391 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 392 +       uint32_t conf;
 393 +
 394 +       if (dai->active) {
 395 +               conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 396 +               conf &= ~JZ_AIC_CONF_ENABLE;
 397 +               jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 398 +
 399 +               clk_disable(i2s->clk_i2s);
 400 +       }
 401 +
 402 +       clk_disable(i2s->clk_aic);
 403 +
 404 +       return 0;
 405 +}
 406 +
 407 +static int jz4740_i2s_resume(struct snd_soc_dai *dai)
 408 +{
 409 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 410 +       uint32_t conf;
 411 +
 412 +       clk_enable(i2s->clk_aic);
 413 +
 414 +       if (dai->active) {
 415 +               clk_enable(i2s->clk_i2s);
 416 +
 417 +               conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 418 +               conf |= JZ_AIC_CONF_ENABLE;
 419 +               jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 420 +       }
 421 +
 422 +       return 0;
 423 +}
 424 +
 425 +static int jz4740_i2s_probe(struct platform_device *pdev, struct snd_soc_dai *dai)
 426 +{
 427 +       struct jz4740_i2s *i2s = jz4740_dai_to_i2s(dai);
 428 +       uint32_t conf;
 429 +
 430 +       conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
 431 +               (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
 432 +               JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
 433 +               JZ_AIC_CONF_I2S |
 434 +               JZ_AIC_CONF_INTERNAL_CODEC;
 435 +
 436 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
 437 +       jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 438 +
 439 +       return 0;
 440 +}
 441 +
 442 +static struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
 443 +       .startup = jz4740_i2s_startup,
 444 +       .shutdown = jz4740_i2s_shutdown,
 445 +       .trigger = jz4740_i2s_trigger,
 446 +       .hw_params = jz4740_i2s_hw_params,
 447 +       .set_fmt = jz4740_i2s_set_fmt,
 448 +       .set_sysclk = jz4740_i2s_set_sysclk,
 449 +};
 450 +
 451 +#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
 452 +               SNDRV_PCM_FMTBIT_S16_LE)
 453 +
 454 +struct snd_soc_dai jz4740_i2s_dai = {
 455 +       .name = "jz4740-i2s",
 456 +       .probe = jz4740_i2s_probe,
 457 +       .playback = {
 458 +               .channels_min = 1,
 459 +               .channels_max = 2,
 460 +               .rates = SNDRV_PCM_RATE_8000_48000,
 461 +               .formats = JZ4740_I2S_FMTS,
 462 +       },
 463 +       .capture = {
 464 +               .channels_min = 2,
 465 +               .channels_max = 2,
 466 +               .rates = SNDRV_PCM_RATE_8000_48000,
 467 +               .formats = JZ4740_I2S_FMTS,
 468 +       },
 469 +       .symmetric_rates = 1,
 470 +       .ops = &jz4740_i2s_dai_ops,
 471 +       .suspend = jz4740_i2s_suspend,
 472 +       .resume = jz4740_i2s_resume,
 473 +};
 474 +EXPORT_SYMBOL_GPL(jz4740_i2s_dai);
 475 +
 476 +static void __devinit jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
 477 +{
 478 +       struct jz4740_dma_config *dma_config;
 479 +
 480 +       /* Playback */
 481 +       dma_config = &i2s->pcm_config_playback.dma_config;
 482 +       dma_config->src_width = JZ4740_DMA_WIDTH_32BIT,
 483 +       dma_config->transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE;
 484 +       dma_config->request_type = JZ4740_DMA_TYPE_AIC_TRANSMIT;
 485 +       dma_config->flags = JZ4740_DMA_SRC_AUTOINC;
 486 +       dma_config->mode = JZ4740_DMA_MODE_SINGLE;
 487 +       i2s->pcm_config_playback.fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;
 488 +
 489 +       /* Capture */
 490 +       dma_config = &i2s->pcm_config_capture.dma_config;
 491 +       dma_config->dst_width = JZ4740_DMA_WIDTH_32BIT,
 492 +       dma_config->transfer_size = JZ4740_DMA_TRANSFER_SIZE_16BYTE;
 493 +       dma_config->request_type = JZ4740_DMA_TYPE_AIC_RECEIVE;
 494 +       dma_config->flags = JZ4740_DMA_DST_AUTOINC;
 495 +       dma_config->mode = JZ4740_DMA_MODE_SINGLE;
 496 +       i2s->pcm_config_capture.fifo_addr = i2s->phys_base + JZ_REG_AIC_FIFO;
 497 +}
 498 +
 499 +static int __devinit jz4740_i2s_dev_probe(struct platform_device *pdev)
 500 +{
 501 +       struct jz4740_i2s *i2s;
 502 +       int ret;
 503 +
 504 +       i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
 505 +
 506 +       if (!i2s)
 507 +               return -ENOMEM;
 508 +
 509 +       i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 510 +       if (!i2s->mem) {
 511 +               ret = -ENOENT;
 512 +               goto err_free;
 513 +       }
 514 +
 515 +       i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
 516 +                               pdev->name);
 517 +       if (!i2s->mem) {
 518 +               ret = -EBUSY;
 519 +               goto err_free;
 520 +       }
 521 +
 522 +       i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
 523 +       if (!i2s->base) {
 524 +               ret = -EBUSY;
 525 +               goto err_release_mem_region;
 526 +       }
 527 +
 528 +       i2s->phys_base = i2s->mem->start;
 529 +
 530 +       i2s->clk_aic = clk_get(&pdev->dev, "aic");
 531 +       if (IS_ERR(i2s->clk_aic)) {
 532 +               ret = PTR_ERR(i2s->clk_aic);
 533 +               goto err_iounmap;
 534 +       }
 535 +
 536 +       i2s->clk_i2s = clk_get(&pdev->dev, "i2s");
 537 +       if (IS_ERR(i2s->clk_i2s)) {
 538 +               ret = PTR_ERR(i2s->clk_i2s);
 539 +               goto err_clk_put_aic;
 540 +       }
 541 +
 542 +       clk_enable(i2s->clk_aic);
 543 +
 544 +       jz4740_i2c_init_pcm_config(i2s);
 545 +
 546 +       jz4740_i2s_dai.private_data = i2s;
 547 +       ret = snd_soc_register_dai(&jz4740_i2s_dai);
 548 +
 549 +       if (ret) {
 550 +               dev_err(&pdev->dev, "Failed to register DAI\n");
 551 +               goto err_clk_put_i2s;
 552 +       }
 553 +
 554 +       platform_set_drvdata(pdev, i2s);
 555 +
 556 +       return 0;
 557 +
 558 +err_clk_put_i2s:
 559 +       clk_disable(i2s->clk_aic);
 560 +       clk_put(i2s->clk_i2s);
 561 +err_clk_put_aic:
 562 +       clk_put(i2s->clk_aic);
 563 +err_iounmap:
 564 +       iounmap(i2s->base);
 565 +err_release_mem_region:
 566 +       release_mem_region(i2s->mem->start, resource_size(i2s->mem));
 567 +err_free:
 568 +       kfree(i2s);
 569 +
 570 +       return ret;
 571 +}
 572 +
 573 +static int __devexit jz4740_i2s_dev_remove(struct platform_device *pdev)
 574 +{
 575 +       struct jz4740_i2s *i2s = platform_get_drvdata(pdev);
 576 +
 577 +       snd_soc_unregister_dai(&jz4740_i2s_dai);
 578 +
 579 +       clk_disable(i2s->clk_aic);
 580 +       clk_put(i2s->clk_i2s);
 581 +       clk_put(i2s->clk_aic);
 582 +
 583 +       iounmap(i2s->base);
 584 +       release_mem_region(i2s->mem->start, resource_size(i2s->mem));
 585 +
 586 +       platform_set_drvdata(pdev, NULL);
 587 +       kfree(i2s);
 588 +
 589 +       return 0;
 590 +}
 591 +
 592 +static struct platform_driver jz4740_i2s_driver = {
 593 +       .probe = jz4740_i2s_dev_probe,
 594 +       .remove = __devexit_p(jz4740_i2s_dev_remove),
 595 +       .driver = {
 596 +               .name = "jz4740-i2s",
 597 +               .owner = THIS_MODULE,
 598 +       },
 599 +};
 600 +
 601 +static int __init jz4740_i2s_init(void)
 602 +{
 603 +       return platform_driver_register(&jz4740_i2s_driver);
 604 +}
 605 +module_init(jz4740_i2s_init);
 606 +
 607 +static void __exit jz4740_i2s_exit(void)
 608 +{
 609 +       platform_driver_unregister(&jz4740_i2s_driver);
 610 +}
 611 +module_exit(jz4740_i2s_exit);
 612 +
 613 +MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
 614 +MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
 615 +MODULE_LICENSE("GPL");
 616 +MODULE_ALIAS("platform:jz4740-i2s");
 617 --- /dev/null
 618 +++ b/sound/soc/jz4740/jz4740-i2s.h
 619 @@ -0,0 +1,18 @@
 620 +/*
 621 + * This program is free software; you can redistribute it and/or modify
 622 + * it under the terms of the GNU General Public License version 2 as
 623 + * published by the Free Software Foundation.
 624 + */
 625 +
 626 +#ifndef _JZ4740_I2S_H
 627 +#define _JZ4740_I2S_H
 628 +
 629 +/* I2S clock source */
 630 +#define JZ4740_I2S_CLKSRC_EXT 0
 631 +#define JZ4740_I2S_CLKSRC_PLL 1
 632 +
 633 +#define JZ4740_I2S_BIT_CLK             0
 634 +
 635 +extern struct snd_soc_dai jz4740_i2s_dai;
 636 +
 637 +#endif
 638 --- /dev/null
 639 +++ b/sound/soc/jz4740/jz4740-pcm.c
 640 @@ -0,0 +1,373 @@
 641 +/*
 642 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 643 + *
 644 + *  This program is free software; you can redistribute         it and/or modify it
 645 + *  under  the terms of         the GNU General  Public License as published by the
 646 + *  Free Software Foundation;  either version 2 of the License, or (at your
 647 + *  option) any later version.
 648 + *
 649 + *  You should have received a copy of the  GNU General Public License along
 650 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 651 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 652 + *
 653 + */
 654 +
 655 +#include <linux/init.h>
 656 +#include <linux/interrupt.h>
 657 +#include <linux/kernel.h>
 658 +#include <linux/module.h>
 659 +#include <linux/platform_device.h>
 660 +#include <linux/slab.h>
 661 +
 662 +#include <linux/dma-mapping.h>
 663 +
 664 +#include <sound/core.h>
 665 +#include <sound/pcm.h>
 666 +#include <sound/pcm_params.h>
 667 +#include <sound/soc.h>
 668 +
 669 +#include <asm/mach-jz4740/dma.h>
 670 +#include "jz4740-pcm.h"
 671 +
 672 +struct jz4740_runtime_data {
 673 +       unsigned long dma_period;
 674 +       dma_addr_t dma_start;
 675 +       dma_addr_t dma_pos;
 676 +       dma_addr_t dma_end;
 677 +
 678 +       struct jz4740_dma_chan *dma;
 679 +
 680 +       dma_addr_t fifo_addr;
 681 +};
 682 +
 683 +/* identify hardware playback capabilities */
 684 +static const struct snd_pcm_hardware jz4740_pcm_hardware = {
 685 +       .info = SNDRV_PCM_INFO_MMAP |
 686 +               SNDRV_PCM_INFO_MMAP_VALID |
 687 +               SNDRV_PCM_INFO_INTERLEAVED |
 688 +               SNDRV_PCM_INFO_BLOCK_TRANSFER,
 689 +       .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
 690 +
 691 +       .rates                  = SNDRV_PCM_RATE_8000_48000,
 692 +       .channels_min           = 1,
 693 +       .channels_max           = 2,
 694 +       .period_bytes_min       = 16,
 695 +       .period_bytes_max       = 2 * PAGE_SIZE,
 696 +       .periods_min            = 2,
 697 +       .periods_max            = 128,
 698 +       .buffer_bytes_max       = 128 * 2 * PAGE_SIZE,
 699 +       .fifo_size              = 32,
 700 +};
 701 +
 702 +static void jz4740_pcm_start_transfer(struct jz4740_runtime_data *prtd,
 703 +       struct snd_pcm_substream *substream)
 704 +{
 705 +       unsigned long count;
 706 +
 707 +       if (prtd->dma_pos == prtd->dma_end)
 708 +               prtd->dma_pos = prtd->dma_start;
 709 +
 710 +       if (prtd->dma_pos + prtd->dma_period > prtd->dma_end)
 711 +               count = prtd->dma_end - prtd->dma_pos;
 712 +       else
 713 +               count = prtd->dma_period;
 714 +
 715 +       jz4740_dma_disable(prtd->dma);
 716 +
 717 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 718 +               jz4740_dma_set_src_addr(prtd->dma, prtd->dma_pos);
 719 +               jz4740_dma_set_dst_addr(prtd->dma, prtd->fifo_addr);
 720 +       } else {
 721 +               jz4740_dma_set_src_addr(prtd->dma, prtd->fifo_addr);
 722 +               jz4740_dma_set_dst_addr(prtd->dma, prtd->dma_pos);
 723 +       }
 724 +
 725 +       jz4740_dma_set_transfer_count(prtd->dma, count);
 726 +
 727 +       prtd->dma_pos += count;
 728 +
 729 +       jz4740_dma_enable(prtd->dma);
 730 +}
 731 +
 732 +static void jz4740_pcm_dma_transfer_done(struct jz4740_dma_chan *dma, int err,
 733 +       void *dev_id)
 734 +{
 735 +       struct snd_pcm_substream *substream = dev_id;
 736 +       struct snd_pcm_runtime *runtime = substream->runtime;
 737 +       struct jz4740_runtime_data *prtd = runtime->private_data;
 738 +
 739 +       snd_pcm_period_elapsed(substream);
 740 +
 741 +       jz4740_pcm_start_transfer(prtd, substream);
 742 +}
 743 +
 744 +static int jz4740_pcm_hw_params(struct snd_pcm_substream *substream,
 745 +       struct snd_pcm_hw_params *params)
 746 +{
 747 +       struct snd_pcm_runtime *runtime = substream->runtime;
 748 +       struct jz4740_runtime_data *prtd = runtime->private_data;
 749 +       struct snd_soc_pcm_runtime *rtd = substream->private_data;
 750 +       struct jz4740_pcm_config *config;
 751 +
 752 +       config = snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream);
 753 +
 754 +       if (!config)
 755 +               return 0;
 756 +
 757 +       if (!prtd->dma) {
 758 +               if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 759 +                       prtd->dma = jz4740_dma_request(substream, "PCM Capture");
 760 +               else
 761 +                       prtd->dma = jz4740_dma_request(substream, "PCM Playback");
 762 +       }
 763 +
 764 +       if (!prtd->dma)
 765 +               return -EBUSY;
 766 +
 767 +       jz4740_dma_configure(prtd->dma, &config->dma_config);
 768 +       prtd->fifo_addr = config->fifo_addr;
 769 +
 770 +       jz4740_dma_set_complete_cb(prtd->dma, jz4740_pcm_dma_transfer_done);
 771 +
 772 +       snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
 773 +       runtime->dma_bytes = params_buffer_bytes(params);
 774 +
 775 +       prtd->dma_period = params_period_bytes(params);
 776 +       prtd->dma_start = runtime->dma_addr;
 777 +       prtd->dma_pos = prtd->dma_start;
 778 +       prtd->dma_end = prtd->dma_start + runtime->dma_bytes;
 779 +
 780 +       return 0;
 781 +}
 782 +
 783 +static int jz4740_pcm_hw_free(struct snd_pcm_substream *substream)
 784 +{
 785 +       struct jz4740_runtime_data *prtd = substream->runtime->private_data;
 786 +
 787 +       snd_pcm_set_runtime_buffer(substream, NULL);
 788 +       if (prtd->dma) {
 789 +               jz4740_dma_free(prtd->dma);
 790 +               prtd->dma = NULL;
 791 +       }
 792 +
 793 +       return 0;
 794 +}
 795 +
 796 +static int jz4740_pcm_prepare(struct snd_pcm_substream *substream)
 797 +{
 798 +       struct jz4740_runtime_data *prtd = substream->runtime->private_data;
 799 +
 800 +       if (!prtd->dma)
 801 +               return -EBUSY;
 802 +
 803 +       prtd->dma_pos = prtd->dma_start;
 804 +
 805 +       return 0;
 806 +}
 807 +
 808 +static int jz4740_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
 809 +{
 810 +       struct snd_pcm_runtime *runtime = substream->runtime;
 811 +       struct jz4740_runtime_data *prtd = runtime->private_data;
 812 +
 813 +       switch (cmd) {
 814 +       case SNDRV_PCM_TRIGGER_START:
 815 +       case SNDRV_PCM_TRIGGER_RESUME:
 816 +       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 817 +               jz4740_pcm_start_transfer(prtd, substream);
 818 +               break;
 819 +       case SNDRV_PCM_TRIGGER_STOP:
 820 +       case SNDRV_PCM_TRIGGER_SUSPEND:
 821 +       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 822 +               jz4740_dma_disable(prtd->dma);
 823 +               break;
 824 +       default:
 825 +               break;
 826 +       }
 827 +
 828 +       return 0;
 829 +}
 830 +
 831 +static snd_pcm_uframes_t jz4740_pcm_pointer(struct snd_pcm_substream *substream)
 832 +{
 833 +       struct snd_pcm_runtime *runtime = substream->runtime;
 834 +       struct jz4740_runtime_data *prtd = runtime->private_data;
 835 +       unsigned long byte_offset;
 836 +       snd_pcm_uframes_t offset;
 837 +       struct jz4740_dma_chan *dma = prtd->dma;
 838 +
 839 +       /* prtd->dma_pos points to the end of the current transfer. So by
 840 +        * subtracting prdt->dma_start we get the offset to the end of the
 841 +        * current period in bytes. By subtracting the residue of the transfer
 842 +        * we get the current offset in bytes. */
 843 +       byte_offset = prtd->dma_pos - prtd->dma_start;
 844 +       byte_offset -= jz4740_dma_get_residue(dma);
 845 +
 846 +       offset = bytes_to_frames(runtime, byte_offset);
 847 +       if (offset >= runtime->buffer_size)
 848 +               offset = 0;
 849 +
 850 +       return offset;
 851 +}
 852 +
 853 +static int jz4740_pcm_open(struct snd_pcm_substream *substream)
 854 +{
 855 +       struct snd_pcm_runtime *runtime = substream->runtime;
 856 +       struct jz4740_runtime_data *prtd;
 857 +
 858 +       prtd = kzalloc(sizeof(*prtd), GFP_KERNEL);
 859 +       if (prtd == NULL)
 860 +               return -ENOMEM;
 861 +
 862 +       snd_soc_set_runtime_hwparams(substream, &jz4740_pcm_hardware);
 863 +
 864 +       runtime->private_data = prtd;
 865 +
 866 +       return 0;
 867 +}
 868 +
 869 +static int jz4740_pcm_close(struct snd_pcm_substream *substream)
 870 +{
 871 +       struct snd_pcm_runtime *runtime = substream->runtime;
 872 +       struct jz4740_runtime_data *prtd = runtime->private_data;
 873 +
 874 +       kfree(prtd);
 875 +
 876 +       return 0;
 877 +}
 878 +
 879 +static int jz4740_pcm_mmap(struct snd_pcm_substream *substream,
 880 +       struct vm_area_struct *vma)
 881 +{
 882 +       return remap_pfn_range(vma, vma->vm_start,
 883 +                       substream->dma_buffer.addr >> PAGE_SHIFT,
 884 +                       vma->vm_end - vma->vm_start, vma->vm_page_prot);
 885 +}
 886 +
 887 +static struct snd_pcm_ops jz4740_pcm_ops = {
 888 +       .open           = jz4740_pcm_open,
 889 +       .close          = jz4740_pcm_close,
 890 +       .ioctl          = snd_pcm_lib_ioctl,
 891 +       .hw_params      = jz4740_pcm_hw_params,
 892 +       .hw_free        = jz4740_pcm_hw_free,
 893 +       .prepare        = jz4740_pcm_prepare,
 894 +       .trigger        = jz4740_pcm_trigger,
 895 +       .pointer        = jz4740_pcm_pointer,
 896 +       .mmap           = jz4740_pcm_mmap,
 897 +};
 898 +
 899 +static int jz4740_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
 900 +{
 901 +       struct snd_pcm_substream *substream = pcm->streams[stream].substream;
 902 +       struct snd_dma_buffer *buf = &substream->dma_buffer;
 903 +       size_t size = jz4740_pcm_hardware.buffer_bytes_max;
 904 +
 905 +       buf->dev.type = SNDRV_DMA_TYPE_DEV;
 906 +       buf->dev.dev = pcm->card->dev;
 907 +       buf->private_data = NULL;
 908 +
 909 +       buf->area = dma_alloc_noncoherent(pcm->card->dev, size,
 910 +                                         &buf->addr, GFP_KERNEL);
 911 +       if (!buf->area)
 912 +               return -ENOMEM;
 913 +
 914 +       buf->bytes = size;
 915 +
 916 +       return 0;
 917 +}
 918 +
 919 +static void jz4740_pcm_free(struct snd_pcm *pcm)
 920 +{
 921 +       struct snd_pcm_substream *substream;
 922 +       struct snd_dma_buffer *buf;
 923 +       int stream;
 924 +
 925 +       for (stream = 0; stream < SNDRV_PCM_STREAM_LAST; ++stream) {
 926 +               substream = pcm->streams[stream].substream;
 927 +               if (!substream)
 928 +                       continue;
 929 +
 930 +               buf = &substream->dma_buffer;
 931 +               if (!buf->area)
 932 +                       continue;
 933 +
 934 +               dma_free_noncoherent(pcm->card->dev, buf->bytes, buf->area,
 935 +                               buf->addr);
 936 +               buf->area = NULL;
 937 +       }
 938 +}
 939 +
 940 +static u64 jz4740_pcm_dmamask = DMA_BIT_MASK(32);
 941 +
 942 +int jz4740_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
 943 +       struct snd_pcm *pcm)
 944 +{
 945 +       int ret = 0;
 946 +
 947 +       if (!card->dev->dma_mask)
 948 +               card->dev->dma_mask = &jz4740_pcm_dmamask;
 949 +
 950 +       if (!card->dev->coherent_dma_mask)
 951 +               card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
 952 +
 953 +       if (dai->playback.channels_min) {
 954 +               ret = jz4740_pcm_preallocate_dma_buffer(pcm,
 955 +                       SNDRV_PCM_STREAM_PLAYBACK);
 956 +               if (ret)
 957 +                       goto err;
 958 +       }
 959 +
 960 +       if (dai->capture.channels_min) {
 961 +               ret = jz4740_pcm_preallocate_dma_buffer(pcm,
 962 +                       SNDRV_PCM_STREAM_CAPTURE);
 963 +               if (ret)
 964 +                       goto err;
 965 +       }
 966 +
 967 +err:
 968 +       return ret;
 969 +}
 970 +
 971 +struct snd_soc_platform jz4740_soc_platform = {
 972 +               .name           = "jz4740-pcm",
 973 +               .pcm_ops        = &jz4740_pcm_ops,
 974 +               .pcm_new        = jz4740_pcm_new,
 975 +               .pcm_free       = jz4740_pcm_free,
 976 +};
 977 +EXPORT_SYMBOL_GPL(jz4740_soc_platform);
 978 +
 979 +static int __devinit jz4740_pcm_probe(struct platform_device *pdev)
 980 +{
 981 +       return snd_soc_register_platform(&jz4740_soc_platform);
 982 +}
 983 +
 984 +static int __devexit jz4740_pcm_remove(struct platform_device *pdev)
 985 +{
 986 +       snd_soc_unregister_platform(&jz4740_soc_platform);
 987 +       return 0;
 988 +}
 989 +
 990 +static struct platform_driver jz4740_pcm_driver = {
 991 +       .probe = jz4740_pcm_probe,
 992 +       .remove = __devexit_p(jz4740_pcm_remove),
 993 +       .driver = {
 994 +               .name = "jz4740-pcm",
 995 +               .owner = THIS_MODULE,
 996 +       },
 997 +};
 998 +
 999 +static int __init jz4740_soc_platform_init(void)
1000 +{
1001 +       return platform_driver_register(&jz4740_pcm_driver);
1002 +}
1003 +module_init(jz4740_soc_platform_init);
1004 +
1005 +static void __exit jz4740_soc_platform_exit(void)
1006 +{
1007 +       return platform_driver_unregister(&jz4740_pcm_driver);
1008 +}
1009 +module_exit(jz4740_soc_platform_exit);
1010 +
1011 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1012 +MODULE_DESCRIPTION("Ingenic SoC JZ4740 PCM driver");
1013 +MODULE_LICENSE("GPL");
1014 --- /dev/null
1015 +++ b/sound/soc/jz4740/jz4740-pcm.h
1016 @@ -0,0 +1,22 @@
1017 +/*
1018 + *
1019 + * This program is free software; you can redistribute it and/or modify
1020 + * it under the terms of the GNU General Public License version 2 as
1021 + * published by the Free Software Foundation.
1022 + */
1023 +
1024 +#ifndef _JZ4740_PCM_H
1025 +#define _JZ4740_PCM_H
1026 +
1027 +#include <linux/dma-mapping.h>
1028 +#include <asm/mach-jz4740/dma.h>
1029 +
1030 +/* platform data */
1031 +extern struct snd_soc_platform jz4740_soc_platform;
1032 +
1033 +struct jz4740_pcm_config {
1034 +       struct jz4740_dma_config dma_config;
1035 +       phys_addr_t fifo_addr;
1036 +};
1037 +
1038 +#endif