target/linux/xburst/patches-2.6.35/010-dma.patch

   1 From ced95a5a9d7a3ba168e8518d9b5004c9a0cad1fe Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 19 Jun 2010 04:08:14 +0000
   4 Subject: [PATCH] MIPS: JZ4740: Add DMA support.
   5
   6 Add support for DMA transfers on JZ4740 SoCs.
   7
   8 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
   9 Cc: linux-mips@linux-mips.org
  10 Cc: linux-kernel@vger.kernel.org
  11 Patchwork: https://patchwork.linux-mips.org/patch/1401/
  12 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  13 ---
  14  arch/mips/include/asm/mach-jz4740/dma.h |   90 ++++++++++
  15  arch/mips/jz4740/dma.c                  |  289 +++++++++++++++++++++++++++++++
  16  2 files changed, 379 insertions(+), 0 deletions(-)
  17  create mode 100644 arch/mips/include/asm/mach-jz4740/dma.h
  18  create mode 100644 arch/mips/jz4740/dma.c
  19
  20 --- /dev/null
  21 +++ b/arch/mips/include/asm/mach-jz4740/dma.h
  22 @@ -0,0 +1,90 @@
  23 +/*
  24 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  25 + *  JZ7420/JZ4740 DMA definitions
  26 + *
  27 + *  This program is free software; you can redistribute it and/or modify it
  28 + *  under  the terms of the GNU General  Public License as published by the
  29 + *  Free Software Foundation;  either version 2 of the License, or (at your
  30 + *  option) any later version.
  31 + *
  32 + *  You should have received a copy of the GNU General Public License along
  33 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  34 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  35 + *
  36 + */
  37 +
  38 +#ifndef __ASM_MACH_JZ4740_DMA_H__
  39 +#define __ASM_MACH_JZ4740_DMA_H__
  40 +
  41 +struct jz4740_dma_chan;
  42 +
  43 +enum jz4740_dma_request_type {
  44 +       JZ4740_DMA_TYPE_AUTO_REQUEST    = 8,
  45 +       JZ4740_DMA_TYPE_UART_TRANSMIT   = 20,
  46 +       JZ4740_DMA_TYPE_UART_RECEIVE    = 21,
  47 +       JZ4740_DMA_TYPE_SPI_TRANSMIT    = 22,
  48 +       JZ4740_DMA_TYPE_SPI_RECEIVE     = 23,
  49 +       JZ4740_DMA_TYPE_AIC_TRANSMIT    = 24,
  50 +       JZ4740_DMA_TYPE_AIC_RECEIVE     = 25,
  51 +       JZ4740_DMA_TYPE_MMC_TRANSMIT    = 26,
  52 +       JZ4740_DMA_TYPE_MMC_RECEIVE     = 27,
  53 +       JZ4740_DMA_TYPE_TCU             = 28,
  54 +       JZ4740_DMA_TYPE_SADC            = 29,
  55 +       JZ4740_DMA_TYPE_SLCD            = 30,
  56 +};
  57 +
  58 +enum jz4740_dma_width {
  59 +       JZ4740_DMA_WIDTH_32BIT  = 0,
  60 +       JZ4740_DMA_WIDTH_8BIT   = 1,
  61 +       JZ4740_DMA_WIDTH_16BIT  = 2,
  62 +};
  63 +
  64 +enum jz4740_dma_transfer_size {
  65 +       JZ4740_DMA_TRANSFER_SIZE_4BYTE  = 0,
  66 +       JZ4740_DMA_TRANSFER_SIZE_1BYTE  = 1,
  67 +       JZ4740_DMA_TRANSFER_SIZE_2BYTE  = 2,
  68 +       JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
  69 +       JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
  70 +};
  71 +
  72 +enum jz4740_dma_flags {
  73 +       JZ4740_DMA_SRC_AUTOINC = 0x2,
  74 +       JZ4740_DMA_DST_AUTOINC = 0x1,
  75 +};
  76 +
  77 +enum jz4740_dma_mode {
  78 +       JZ4740_DMA_MODE_SINGLE  = 0,
  79 +       JZ4740_DMA_MODE_BLOCK   = 1,
  80 +};
  81 +
  82 +struct jz4740_dma_config {
  83 +       enum jz4740_dma_width src_width;
  84 +       enum jz4740_dma_width dst_width;
  85 +       enum jz4740_dma_transfer_size transfer_size;
  86 +       enum jz4740_dma_request_type request_type;
  87 +       enum jz4740_dma_flags flags;
  88 +       enum jz4740_dma_mode mode;
  89 +};
  90 +
  91 +typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
  92 +
  93 +struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
  94 +void jz4740_dma_free(struct jz4740_dma_chan *dma);
  95 +
  96 +void jz4740_dma_configure(struct jz4740_dma_chan *dma,
  97 +       const struct jz4740_dma_config *config);
  98 +
  99 +
 100 +void jz4740_dma_enable(struct jz4740_dma_chan *dma);
 101 +void jz4740_dma_disable(struct jz4740_dma_chan *dma);
 102 +
 103 +void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
 104 +void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
 105 +void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
 106 +
 107 +uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
 108 +
 109 +void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
 110 +       jz4740_dma_complete_callback_t cb);
 111 +
 112 +#endif  /* __ASM_JZ4740_DMA_H__ */
 113 --- /dev/null
 114 +++ b/arch/mips/jz4740/dma.c
 115 @@ -0,0 +1,289 @@
 116 +/*
 117 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 118 + *  JZ4740 SoC DMA support
 119 + *
 120 + *  This program is free software; you can redistribute it and/or modify it
 121 + *  under  the terms of the GNU General  Public License as published by the
 122 + *  Free Software Foundation;  either version 2 of the License, or (at your
 123 + *  option) any later version.
 124 + *
 125 + *  You should have received a copy of the GNU General Public License along
 126 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 127 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 128 + *
 129 + */
 130 +
 131 +#include <linux/kernel.h>
 132 +#include <linux/module.h>
 133 +#include <linux/spinlock.h>
 134 +#include <linux/interrupt.h>
 135 +
 136 +#include <linux/dma-mapping.h>
 137 +#include <asm/mach-jz4740/dma.h>
 138 +#include <asm/mach-jz4740/base.h>
 139 +
 140 +#define JZ_REG_DMA_SRC_ADDR(x)         (0x00 + (x) * 0x20)
 141 +#define JZ_REG_DMA_DST_ADDR(x)         (0x04 + (x) * 0x20)
 142 +#define JZ_REG_DMA_TRANSFER_COUNT(x)   (0x08 + (x) * 0x20)
 143 +#define JZ_REG_DMA_REQ_TYPE(x)         (0x0C + (x) * 0x20)
 144 +#define JZ_REG_DMA_STATUS_CTRL(x)      (0x10 + (x) * 0x20)
 145 +#define JZ_REG_DMA_CMD(x)              (0x14 + (x) * 0x20)
 146 +#define JZ_REG_DMA_DESC_ADDR(x)                (0x18 + (x) * 0x20)
 147 +
 148 +#define JZ_REG_DMA_CTRL                        0x300
 149 +#define JZ_REG_DMA_IRQ                 0x304
 150 +#define JZ_REG_DMA_DOORBELL            0x308
 151 +#define JZ_REG_DMA_DOORBELL_SET                0x30C
 152 +
 153 +#define JZ_DMA_STATUS_CTRL_NO_DESC             BIT(31)
 154 +#define JZ_DMA_STATUS_CTRL_DESC_INV            BIT(6)
 155 +#define JZ_DMA_STATUS_CTRL_ADDR_ERR            BIT(4)
 156 +#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE       BIT(3)
 157 +#define JZ_DMA_STATUS_CTRL_HALT                        BIT(2)
 158 +#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE     BIT(1)
 159 +#define JZ_DMA_STATUS_CTRL_ENABLE              BIT(0)
 160 +
 161 +#define JZ_DMA_CMD_SRC_INC                     BIT(23)
 162 +#define JZ_DMA_CMD_DST_INC                     BIT(22)
 163 +#define JZ_DMA_CMD_RDIL_MASK                   (0xf << 16)
 164 +#define JZ_DMA_CMD_SRC_WIDTH_MASK              (0x3 << 14)
 165 +#define JZ_DMA_CMD_DST_WIDTH_MASK              (0x3 << 12)
 166 +#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK                (0x7 << 8)
 167 +#define JZ_DMA_CMD_BLOCK_MODE                  BIT(7)
 168 +#define JZ_DMA_CMD_DESC_VALID                  BIT(4)
 169 +#define JZ_DMA_CMD_DESC_VALID_MODE             BIT(3)
 170 +#define JZ_DMA_CMD_VALID_IRQ_ENABLE            BIT(2)
 171 +#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE         BIT(1)
 172 +#define JZ_DMA_CMD_LINK_ENABLE                 BIT(0)
 173 +
 174 +#define JZ_DMA_CMD_FLAGS_OFFSET 22
 175 +#define JZ_DMA_CMD_RDIL_OFFSET 16
 176 +#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
 177 +#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
 178 +#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
 179 +#define JZ_DMA_CMD_MODE_OFFSET 7
 180 +
 181 +#define JZ_DMA_CTRL_PRIORITY_MASK      (0x3 << 8)
 182 +#define JZ_DMA_CTRL_HALT               BIT(3)
 183 +#define JZ_DMA_CTRL_ADDRESS_ERROR      BIT(2)
 184 +#define JZ_DMA_CTRL_ENABLE             BIT(0)
 185 +
 186 +
 187 +static void __iomem *jz4740_dma_base;
 188 +static spinlock_t jz4740_dma_lock;
 189 +
 190 +static inline uint32_t jz4740_dma_read(size_t reg)
 191 +{
 192 +       return readl(jz4740_dma_base + reg);
 193 +}
 194 +
 195 +static inline void jz4740_dma_write(size_t reg, uint32_t val)
 196 +{
 197 +       writel(val, jz4740_dma_base + reg);
 198 +}
 199 +
 200 +static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask)
 201 +{
 202 +       uint32_t val2;
 203 +       val2 = jz4740_dma_read(reg);
 204 +       val2 &= ~mask;
 205 +       val2 |= val;
 206 +       jz4740_dma_write(reg, val2);
 207 +}
 208 +
 209 +struct jz4740_dma_chan {
 210 +       unsigned int id;
 211 +       void *dev;
 212 +       const char *name;
 213 +
 214 +       enum jz4740_dma_flags flags;
 215 +       uint32_t transfer_shift;
 216 +
 217 +       jz4740_dma_complete_callback_t complete_cb;
 218 +
 219 +       unsigned used:1;
 220 +};
 221 +
 222 +#define JZ4740_DMA_CHANNEL(_id) { .id = _id }
 223 +
 224 +struct jz4740_dma_chan jz4740_dma_channels[] = {
 225 +       JZ4740_DMA_CHANNEL(0),
 226 +       JZ4740_DMA_CHANNEL(1),
 227 +       JZ4740_DMA_CHANNEL(2),
 228 +       JZ4740_DMA_CHANNEL(3),
 229 +       JZ4740_DMA_CHANNEL(4),
 230 +       JZ4740_DMA_CHANNEL(5),
 231 +};
 232 +
 233 +struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name)
 234 +{
 235 +       unsigned int i;
 236 +       struct jz4740_dma_chan *dma = NULL;
 237 +
 238 +       spin_lock(&jz4740_dma_lock);
 239 +
 240 +       for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) {
 241 +               if (!jz4740_dma_channels[i].used) {
 242 +                       dma = &jz4740_dma_channels[i];
 243 +                       dma->used = 1;
 244 +                       break;
 245 +               }
 246 +       }
 247 +
 248 +       spin_unlock(&jz4740_dma_lock);
 249 +
 250 +       if (!dma)
 251 +               return NULL;
 252 +
 253 +       dma->dev = dev;
 254 +       dma->name = name;
 255 +
 256 +       return dma;
 257 +}
 258 +EXPORT_SYMBOL_GPL(jz4740_dma_request);
 259 +
 260 +void jz4740_dma_configure(struct jz4740_dma_chan *dma,
 261 +       const struct jz4740_dma_config *config)
 262 +{
 263 +       uint32_t cmd;
 264 +
 265 +       switch (config->transfer_size) {
 266 +       case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
 267 +               dma->transfer_shift = 1;
 268 +               break;
 269 +       case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
 270 +               dma->transfer_shift = 2;
 271 +               break;
 272 +       case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
 273 +               dma->transfer_shift = 4;
 274 +               break;
 275 +       case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
 276 +               dma->transfer_shift = 5;
 277 +               break;
 278 +       default:
 279 +               dma->transfer_shift = 0;
 280 +               break;
 281 +       }
 282 +
 283 +       cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET;
 284 +       cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
 285 +       cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
 286 +       cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
 287 +       cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET;
 288 +       cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
 289 +
 290 +       jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd);
 291 +       jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0);
 292 +       jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type);
 293 +}
 294 +EXPORT_SYMBOL_GPL(jz4740_dma_configure);
 295 +
 296 +void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src)
 297 +{
 298 +       jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src);
 299 +}
 300 +EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr);
 301 +
 302 +void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst)
 303 +{
 304 +       jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst);
 305 +}
 306 +EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr);
 307 +
 308 +void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count)
 309 +{
 310 +       count >>= dma->transfer_shift;
 311 +       jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count);
 312 +}
 313 +EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count);
 314 +
 315 +void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
 316 +       jz4740_dma_complete_callback_t cb)
 317 +{
 318 +       dma->complete_cb = cb;
 319 +}
 320 +EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb);
 321 +
 322 +void jz4740_dma_free(struct jz4740_dma_chan *dma)
 323 +{
 324 +       dma->dev = NULL;
 325 +       dma->complete_cb = NULL;
 326 +       dma->used = 0;
 327 +}
 328 +EXPORT_SYMBOL_GPL(jz4740_dma_free);
 329 +
 330 +void jz4740_dma_enable(struct jz4740_dma_chan *dma)
 331 +{
 332 +       jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id),
 333 +                       JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
 334 +                       JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
 335 +                       JZ_DMA_STATUS_CTRL_ENABLE);
 336 +
 337 +       jz4740_dma_write_mask(JZ_REG_DMA_CTRL,
 338 +                       JZ_DMA_CTRL_ENABLE,
 339 +                       JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
 340 +}
 341 +EXPORT_SYMBOL_GPL(jz4740_dma_enable);
 342 +
 343 +void jz4740_dma_disable(struct jz4740_dma_chan *dma)
 344 +{
 345 +       jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
 346 +                       JZ_DMA_STATUS_CTRL_ENABLE);
 347 +}
 348 +EXPORT_SYMBOL_GPL(jz4740_dma_disable);
 349 +
 350 +uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma)
 351 +{
 352 +       uint32_t residue;
 353 +       residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id));
 354 +       return residue << dma->transfer_shift;
 355 +}
 356 +EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
 357 +
 358 +static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
 359 +{
 360 +       uint32_t status;
 361 +
 362 +       status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
 363 +
 364 +       jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
 365 +               JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
 366 +
 367 +       if (dma->complete_cb)
 368 +               dma->complete_cb(dma, 0, dma->dev);
 369 +}
 370 +
 371 +static irqreturn_t jz4740_dma_irq(int irq, void *dev_id)
 372 +{
 373 +       uint32_t irq_status;
 374 +       unsigned int i;
 375 +
 376 +       irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ);
 377 +
 378 +       for (i = 0; i < 6; ++i) {
 379 +               if (irq_status & (1 << i))
 380 +                       jz4740_dma_chan_irq(&jz4740_dma_channels[i]);
 381 +       }
 382 +
 383 +       return IRQ_HANDLED;
 384 +}
 385 +
 386 +static int jz4740_dma_init(void)
 387 +{
 388 +       unsigned int ret;
 389 +
 390 +       jz4740_dma_base = ioremap(JZ4740_DMAC_BASE_ADDR, 0x400);
 391 +
 392 +       if (!jz4740_dma_base)
 393 +               return -EBUSY;
 394 +
 395 +       spin_lock_init(&jz4740_dma_lock);
 396 +
 397 +       ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL);
 398 +
 399 +       if (ret)
 400 +               printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret);
 401 +
 402 +       return ret;
 403 +}
 404 +arch_initcall(jz4740_dma_init);