2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform timer support
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
16 #include <linux/kernel.h>
17 #include <linux/interrupt.h>
18 #include <linux/time.h>
19 #include <linux/clockchips.h>
20 #include <linux/clk.h>
22 #include <asm/mach-jz4740/irq.h>
23 #include <asm/mach-jz4740/jz4740.h>
26 #define JZ_REG_TIMER_STOP 0x1C
27 #define JZ_REG_TIMER_STOP_SET 0x2C
28 #define JZ_REG_TIMER_STOP_CLEAR 0x3C
29 #define JZ_REG_TIMER_ENABLE 0x10
30 #define JZ_REG_TIMER_ENABLE_SET 0x14
31 #define JZ_REG_TIMER_ENABLE_CLEAR 0x18
32 #define JZ_REG_TIMER_FLAG 0x20
33 #define JZ_REG_TIMER_FLAG_SET 0x24
34 #define JZ_REG_TIMER_FLAG_CLEAR 0x28
35 #define JZ_REG_TIMER_MASK 0x30
36 #define JZ_REG_TIMER_MASK_SET 0x34
37 #define JZ_REG_TIMER_MASK_CLEAR 0x38
39 #define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x40)
40 #define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x44)
41 #define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x48)
42 #define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x4C)
44 #define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
45 #define JZ_TIMER_IRQ_FULL(x) BIT(x)
47 #define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
48 #define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
49 #define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
50 #define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
51 #define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
52 #define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
53 #define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
54 #define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
55 #define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
56 #define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
58 #define JZ_TIMER_CTRL_SRC_EXT BIT(2)
59 #define JZ_TIMER_CTRL_SRC_RTC BIT(1)
60 #define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
62 static void __iomem *jz4740_timer_base;
63 static uint16_t jz4740_jiffies_per_tick;
65 void jz4740_timer_enable_watchdog(void)
67 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
70 void jz4740_timer_disable_watchdog(void)
72 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
75 static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
77 writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
80 static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
82 writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
85 static void jz4740_init_timer(void)
88 val |= JZ_TIMER_CTRL_PRESCALE_16;
89 val |= JZ_TIMER_CTRL_SRC_EXT;
91 writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(0));
92 writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
93 writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(1));
94 writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(1));
97 static void jz4740_timer_enable(unsigned int timer)
99 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
100 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
103 static void jz4740_timer_disable(unsigned int timer)
105 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
106 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
109 static void jz4740_timer_irq_full_enable(unsigned int timer)
111 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
112 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
115 static int jz4740_timer_irq_full_is_enabled(unsigned int timer)
117 return !(readl(jz4740_timer_base + JZ_REG_TIMER_MASK) &
118 JZ_TIMER_IRQ_FULL(timer));
121 static void jz4740_timer_irq_full_disable(unsigned int timer)
123 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
126 static void jz4740_timer_irq_half_enable(unsigned int timer)
128 writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
129 writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
132 static void jz4740_timer_irq_half_disable(unsigned int timer)
134 writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
137 static cycle_t jz4740_clocksource_read(struct clocksource *cs)
140 val = readw(jz4740_timer_base + JZ_REG_TIMER_CNT(1));
144 static struct clocksource jz4740_clocksource = {
145 .name = "jz4740-timer",
147 .read = jz4740_clocksource_read,
148 .mask = CLOCKSOURCE_MASK(16),
149 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
152 static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
154 struct clock_event_device *cd = devid;
156 writel(JZ_TIMER_IRQ_FULL(0), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
158 if (cd->mode != CLOCK_EVT_MODE_PERIODIC) {
159 jz4740_timer_disable(0);
160 cd->event_handler(cd);
162 cd->event_handler(cd);
168 static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
169 struct clock_event_device *cd)
172 case CLOCK_EVT_MODE_PERIODIC:
173 writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
174 writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
175 case CLOCK_EVT_MODE_RESUME:
176 jz4740_timer_irq_full_enable(0);
177 jz4740_timer_enable(0);
179 case CLOCK_EVT_MODE_ONESHOT:
180 case CLOCK_EVT_MODE_SHUTDOWN:
181 jz4740_timer_disable(0);
188 static int jz4740_clockevent_set_next(unsigned long evt, struct
189 clock_event_device *cd)
191 writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
192 writew(evt, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
193 jz4740_timer_enable(0);
198 static struct clock_event_device jz4740_clockevent = {
199 .name = "jz4740-timer",
200 .features = CLOCK_EVT_FEAT_PERIODIC,
201 .set_next_event = jz4740_clockevent_set_next,
202 .set_mode = jz4740_clockevent_set_mode,
207 static struct irqaction jz_irqaction = {
208 .handler = jz4740_clockevent_irq,
209 .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_DISABLED,
210 .name = "jz4740-timerirq",
211 .dev_id = &jz4740_clockevent,
215 void __init plat_time_init(void)
221 jz4740_timer_base = ioremap(CPHYSADDR(TCU_BASE), 0x100);
223 if (!jz4740_timer_base) {
224 printk(KERN_ERR "Failed to ioremap timer registers");
228 /*ext_clk = clk_get(NULL, "ext");
229 clk_rate = clk_get_rate(ext_clk) >> 4;
233 clk_rate = JZ_EXTAL >> 4;
235 jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
237 clockevent_set_clock(&jz4740_clockevent, clk_rate);
238 jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
239 jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
240 jz4740_clockevent.cpumask = cpumask_of(0);
242 clockevents_register_device(&jz4740_clockevent);
244 clocksource_set_clock(&jz4740_clocksource, clk_rate);
245 ret = clocksource_register(&jz4740_clocksource);
248 printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
250 setup_irq(JZ_IRQ_TCU0, &jz_irqaction);
253 writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
254 jz4740_timer_irq_half_disable(0);
255 jz4740_timer_irq_full_enable(0);
256 jz4740_timer_enable(0);
258 jz4740_timer_irq_half_disable(1);
259 jz4740_timer_irq_full_disable(1);
261 jz4740_timer_enable(1);