target/linux/sunxi/patches-3.13/210-clk-sunxi-add-a20-output-clk.patch

   1 From 5ca9eadcb5f5cd9af6f1650029ad64052a1a0b10 Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Tue, 24 Dec 2013 21:26:17 +0800
   4 Subject: [PATCH] clk: sunxi: Allwinner A20 output clock support
   5
   6 This patch adds support for the external clock outputs on the
   7 Allwinner A20 SoC. The clock outputs are similar to "module 0"
   8 type clocks, with different offsets and widths for clock factors.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 ---
  12  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
  13  drivers/clk/sunxi/clk-sunxi.c                     | 57 +++++++++++++++++++++++
  14  2 files changed, 58 insertions(+)
  15
  16 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
  17 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
  18 @@ -37,6 +37,7 @@ Required properties:
  19         "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
  20         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
  21         "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
  22 +       "allwinner,sun7i-a20-out-clk" - for the external output clocks
  23
  24  Required properties for all clocks:
  25  - reg : shall be the control register address for the clock.
  26 --- a/drivers/clk/sunxi/clk-sunxi.c
  27 +++ b/drivers/clk/sunxi/clk-sunxi.c
  28 @@ -396,6 +396,47 @@ void clk_sunxi_mmc_phase_control(struct
  29
  30
  31  /**
  32 + * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
  33 + * CLK_OUT rate is calculated as follows
  34 + * rate = (parent_rate >> p) / (m + 1);
  35 + */
  36 +
  37 +static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
  38 +                                     u8 *n, u8 *k, u8 *m, u8 *p)
  39 +{
  40 +       u8 div, calcm, calcp;
  41 +
  42 +       /* These clocks can only divide, so we will never be able to achieve
  43 +        * frequencies higher than the parent frequency */
  44 +       if (*freq > parent_rate)
  45 +               *freq = parent_rate;
  46 +
  47 +       div = parent_rate / *freq;
  48 +
  49 +       if (div < 32)
  50 +               calcp = 0;
  51 +       else if (div / 2 < 32)
  52 +               calcp = 1;
  53 +       else if (div / 4 < 32)
  54 +               calcp = 2;
  55 +       else
  56 +               calcp = 3;
  57 +
  58 +       calcm = DIV_ROUND_UP(div, 1 << calcp);
  59 +
  60 +       *freq = (parent_rate >> calcp) / calcm;
  61 +
  62 +       /* we were called to round the frequency, we can now return */
  63 +       if (n == NULL)
  64 +               return;
  65 +
  66 +       *m = calcm - 1;
  67 +       *p = calcp;
  68 +}
  69 +
  70 +
  71 +
  72 +/**
  73   * sunxi_factors_clk_setup() - Setup function for factor clocks
  74   */
  75
  76 @@ -455,6 +496,14 @@ static struct clk_factors_config sun4i_m
  77         .pwidth = 2,
  78  };
  79
  80 +/* user manual says "n" but it's really "p" */
  81 +static struct clk_factors_config sun7i_a20_out_config = {
  82 +       .mshift = 8,
  83 +       .mwidth = 5,
  84 +       .pshift = 20,
  85 +       .pwidth = 2,
  86 +};
  87 +
  88  static const struct factors_data sun4i_pll1_data __initconst = {
  89         .enable = 31,
  90         .table = &sun4i_pll1_config,
  91 @@ -491,6 +540,13 @@ static const struct factors_data sun4i_m
  92         .getter = sun4i_get_mod0_factors,
  93  };
  94
  95 +static const struct factors_data sun7i_a20_out_data __initconst = {
  96 +       .enable = 31,
  97 +       .mux = 24,
  98 +       .table = &sun7i_a20_out_config,
  99 +       .getter = sun7i_a20_get_out_factors,
 100 +};
 101 +
 102  static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
 103                                                 const struct factors_data *data)
 104  {
 105 @@ -998,6 +1054,7 @@ static const struct of_device_id clk_fac
 106         {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
 107         {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
 108         {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
 109 +       {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
 110         {}
 111  };
 112