target/linux/sunxi/patches-3.13/210-clk-sunxi-add-a20-output-clk.patch

   1 From 5ca9eadcb5f5cd9af6f1650029ad64052a1a0b10 Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Tue, 24 Dec 2013 21:26:17 +0800
   4 Subject: [PATCH] clk: sunxi: Allwinner A20 output clock support
   5
   6 This patch adds support for the external clock outputs on the
   7 Allwinner A20 SoC. The clock outputs are similar to "module 0"
   8 type clocks, with different offsets and widths for clock factors.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 ---
  12  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
  13  drivers/clk/sunxi/clk-sunxi.c                     | 57 +++++++++++++++++++++++
  14  2 files changed, 58 insertions(+)
  15
  16 diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
  17 index 941bd93..79c7197 100644
  18 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
  19 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
  20 @@ -36,6 +36,7 @@ Required properties:
  21         "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
  22         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
  23         "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
  24 +       "allwinner,sun7i-a20-out-clk" - for the external output clocks
  25
  26  Required properties for all clocks:
  27  - reg : shall be the control register address for the clock.
  28 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
  29 index 8a07a68..df1f385 100644
  30 --- a/drivers/clk/sunxi/clk-sunxi.c
  31 +++ b/drivers/clk/sunxi/clk-sunxi.c
  32 @@ -396,6 +396,47 @@ void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
  33
  34
  35  /**
  36 + * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
  37 + * CLK_OUT rate is calculated as follows
  38 + * rate = (parent_rate >> p) / (m + 1);
  39 + */
  40 +
  41 +static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
  42 +                                     u8 *n, u8 *k, u8 *m, u8 *p)
  43 +{
  44 +       u8 div, calcm, calcp;
  45 +
  46 +       /* These clocks can only divide, so we will never be able to achieve
  47 +        * frequencies higher than the parent frequency */
  48 +       if (*freq > parent_rate)
  49 +               *freq = parent_rate;
  50 +
  51 +       div = parent_rate / *freq;
  52 +
  53 +       if (div < 32)
  54 +               calcp = 0;
  55 +       else if (div / 2 < 32)
  56 +               calcp = 1;
  57 +       else if (div / 4 < 32)
  58 +               calcp = 2;
  59 +       else
  60 +               calcp = 3;
  61 +
  62 +       calcm = DIV_ROUND_UP(div, 1 << calcp);
  63 +
  64 +       *freq = (parent_rate >> calcp) / calcm;
  65 +
  66 +       /* we were called to round the frequency, we can now return */
  67 +       if (n == NULL)
  68 +               return;
  69 +
  70 +       *m = calcm - 1;
  71 +       *p = calcp;
  72 +}
  73 +
  74 +
  75 +
  76 +/**
  77   * sunxi_factors_clk_setup() - Setup function for factor clocks
  78   */
  79
  80 @@ -455,6 +496,14 @@ struct factors_data {
  81         .pwidth = 2,
  82  };
  83
  84 +/* user manual says "n" but it's really "p" */
  85 +static struct clk_factors_config sun7i_a20_out_config = {
  86 +       .mshift = 8,
  87 +       .mwidth = 5,
  88 +       .pshift = 20,
  89 +       .pwidth = 2,
  90 +};
  91 +
  92  static const struct factors_data sun4i_pll1_data __initconst = {
  93         .enable = 31,
  94         .table = &sun4i_pll1_config,
  95 @@ -492,6 +541,13 @@ struct factors_data {
  96         .getter = sun4i_get_mod0_factors,
  97  };
  98
  99 +static const struct factors_data sun7i_a20_out_data __initconst = {
 100 +       .enable = 31,
 101 +       .mux = 24,
 102 +       .table = &sun7i_a20_out_config,
 103 +       .getter = sun7i_a20_get_out_factors,
 104 +};
 105 +
 106  static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
 107                                                 const struct factors_data *data)
 108  {
 109 @@ -995,6 +1051,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 110         {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
 111         {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
 112         {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
 113 +       {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
 114         {}
 115  };
 116
 117 --
 118 1.8.5.1
 119