target/linux/sunxi/patches-3.13/200-sun5i-timer-add-support-for-reset-ctrler.patch

   1 From 99489f45debd07f6e1cfa36f5c9890409714518d Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Fri, 20 Dec 2013 22:41:08 +0100
   4 Subject: [PATCH] clocksource: sun5i: Add support for reset controller
   5
   6 The Allwinner A31 that uses this timer has the timer IP asserted in reset.
   7 Add an optional reset property to the DT, and deassert the timer from reset if
   8 it's there.
   9
  10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 ---
  12  .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt       | 4 ++++
  13  drivers/clocksource/timer-sun5i.c                                   | 6 ++++++
  14  2 files changed, 10 insertions(+)
  15
  16 diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
  17 index 7c26154..27cfc7d 100644
  18 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
  19 +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
  20 @@ -9,6 +9,9 @@ Required properties:
  21                 one)
  22  - clocks: phandle to the source clock (usually the AHB clock)
  23
  24 +Optionnal properties:
  25 +- resets: phandle to a reset controller asserting the timer
  26 +
  27  Example:
  28
  29  timer@01c60000 {
  30 @@ -19,4 +22,5 @@ timer@01c60000 {
  31                      <0 53 1>,
  32                      <0 54 1>;
  33         clocks = <&ahb1_gates 19>;
  34 +       resets = <&ahb1rst 19>;
  35  };
  36 diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
  37 index bddc522..f74d75e 100644
  38 --- a/drivers/clocksource/timer-sun5i.c
  39 +++ b/drivers/clocksource/timer-sun5i.c
  40 @@ -16,6 +16,7 @@
  41  #include <linux/interrupt.h>
  42  #include <linux/irq.h>
  43  #include <linux/irqreturn.h>
  44 +#include <linux/reset.h>
  45  #include <linux/sched_clock.h>
  46  #include <linux/of.h>
  47  #include <linux/of_address.h>
  48 @@ -143,6 +144,7 @@ static u32 sun5i_timer_sched_read(void)
  49
  50  static void __init sun5i_timer_init(struct device_node *node)
  51  {
  52 +       struct reset_control *rstc;
  53         unsigned long rate;
  54         struct clk *clk;
  55         int ret, irq;
  56 @@ -162,6 +164,10 @@ static void __init sun5i_timer_init(struct device_node *node)
  57         clk_prepare_enable(clk);
  58         rate = clk_get_rate(clk);
  59
  60 +       rstc = of_reset_control_get(node, NULL);
  61 +       if (!IS_ERR(rstc))
  62 +               reset_control_deassert(rstc);
  63 +
  64         writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
  65         writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
  66                timer_base + TIMER_CTL_REG(1));
  67 --
  68 1.8.5.1
  69