sunxi: initial 3.13 support
[openwrt.git] / target / linux / sunxi / patches-3.13 / 161-sunxi-ahci-add-driver.patch
1 From 22345cc059de4a6ea1dc7657dd6ad86ca16a8814 Mon Sep 17 00:00:00 2001
2 From: Oliver Schinagl <oliver@schinagl.nl>
3 Date: Tue, 3 Dec 2013 12:07:01 +0100
4 Subject: [PATCH] ARM: sunxi: Add ahci-sunxi driver for the Allwinner SUNXi
5  SoCs sata
6
7 This patch adds support for the ahci sata controler found on Allwinner A10
8 and A20 SoCs.
9
10 Orignally written by Olliver Schinagl using the approach of having a platform
11 device which probe method creates a new child platform device which gets
12 driven by ahci_platform.c, as done by ahci_imx.c .
13
14 Given that almost all functionality already is shared through libahci /
15 ata-core, and that ahci_platform.c cannot cleanly handle somewhat more complex
16 platform specific ahci cases, such as the sunxi case, it was refactored into
17 a stand-alone platform driver by Hans de Goede.
18
19 Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
20 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
21 ---
22  .../devicetree/bindings/ata/ahci-sunxi.txt         |  24 ++
23  drivers/ata/Kconfig                                |   9 +
24  drivers/ata/Makefile                               |   1 +
25  drivers/ata/ahci_sunxi.c                           | 349 +++++++++++++++++++++
26  4 files changed, 383 insertions(+)
27  create mode 100644 Documentation/devicetree/bindings/ata/ahci-sunxi.txt
28  create mode 100644 drivers/ata/ahci_sunxi.c
29
30 diff --git a/Documentation/devicetree/bindings/ata/ahci-sunxi.txt b/Documentation/devicetree/bindings/ata/ahci-sunxi.txt
31 new file mode 100644
32 index 0000000..0792fa5
33 --- /dev/null
34 +++ b/Documentation/devicetree/bindings/ata/ahci-sunxi.txt
35 @@ -0,0 +1,24 @@
36 +Allwinner SUNXI AHCI SATA Controller
37 +
38 +SATA nodes are defined to describe on-chip Serial ATA controllers.
39 +Each SATA controller should have its own node.
40 +
41 +Required properties:
42 +- compatible   : compatible list, contains "allwinner,sun4i-a10-ahci"
43 +- reg          : <registers mapping>
44 +- interrupts   : <interrupt mapping for AHCI IRQ>
45 +- clocks       : clocks for ACHI
46 +- clock-names  : clock names for AHCI
47 +
48 +Optional properties:
49 +- pwr-supply   : regulator to control the power supply GPIO
50 +
51 +Example:
52 +       ahci@01c18000 {
53 +               compatible = "allwinner,sun4i-a10-ahci";
54 +               reg = <0x01c18000 0x1000>;
55 +               interrupts = <0 56 1>;
56 +               clocks = <&ahb_gates 25>, <&pll6 0>;
57 +               clock-names = "ahb_sata", "pll6_sata";
58 +               pwr-supply = <&reg_ahci_5v>;
59 +       };
60 diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
61 index 4e73772..3c80bbe 100644
62 --- a/drivers/ata/Kconfig
63 +++ b/drivers/ata/Kconfig
64 @@ -106,6 +106,15 @@ config AHCI_IMX
65  
66           If unsure, say N.
67  
68 +config AHCI_SUNXI
69 +       tristate "Allwinner sunxi AHCI SATA support"
70 +       depends on ARCH_SUNXI
71 +       help
72 +         This option enables support for the Allwinner sunxi SoC's
73 +         onboard AHCI SATA.
74 +
75 +         If unsure, say N.
76 +
77  config SATA_FSL
78         tristate "Freescale 3.0Gbps SATA support"
79         depends on FSL_SOC
80 diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
81 index 46518c6..956abc3 100644
82 --- a/drivers/ata/Makefile
83 +++ b/drivers/ata/Makefile
84 @@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24)      += sata_sil24.o
85  obj-$(CONFIG_SATA_DWC)         += sata_dwc_460ex.o
86  obj-$(CONFIG_SATA_HIGHBANK)    += sata_highbank.o libahci.o
87  obj-$(CONFIG_AHCI_IMX)         += ahci_imx.o
88 +obj-$(CONFIG_AHCI_SUNXI)       += ahci_sunxi.o libahci.o
89  
90  # SFF w/ custom DMA
91  obj-$(CONFIG_PDC_ADMA)         += pdc_adma.o
92 diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
93 new file mode 100644
94 index 0000000..22d3972
95 --- /dev/null
96 +++ b/drivers/ata/ahci_sunxi.c
97 @@ -0,0 +1,349 @@
98 +/*
99 + * Allwinner sunxi AHCI SATA platform driver
100 + * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
101 + * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
102 + *
103 + * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
104 + * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
105 + * Daniel Wang <danielwang@allwinnertech.com>
106 + *
107 + * This program is free software; you can redistribute it and/or modify it
108 + * under the terms and conditions of the GNU General Public License,
109 + * version 2, as published by the Free Software Foundation.
110 + *
111 + * This program is distributed in the hope it will be useful, but WITHOUT
112 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
113 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
114 + * more details.
115 + */
116 +
117 +#include <linux/clk.h>
118 +#include <linux/errno.h>
119 +#include <linux/kernel.h>
120 +#include <linux/module.h>
121 +#include <linux/of_device.h>
122 +#include <linux/platform_device.h>
123 +#include <linux/regulator/consumer.h>
124 +#include "ahci.h"
125 +
126 +#define AHCI_BISTAFR 0x00a0
127 +#define AHCI_BISTCR 0x00a4
128 +#define AHCI_BISTFCTR 0x00a8
129 +#define AHCI_BISTSR 0x00ac
130 +#define AHCI_BISTDECR 0x00b0
131 +#define AHCI_DIAGNR0 0x00b4
132 +#define AHCI_DIAGNR1 0x00b8
133 +#define AHCI_OOBR 0x00bc
134 +#define AHCI_PHYCS0R 0x00c0
135 +#define AHCI_PHYCS1R 0x00c4
136 +#define AHCI_PHYCS2R 0x00c8
137 +#define AHCI_TIMER1MS 0x00e0
138 +#define AHCI_GPARAM1R 0x00e8
139 +#define AHCI_GPARAM2R 0x00ec
140 +#define AHCI_PPARAMR 0x00f0
141 +#define AHCI_TESTR 0x00f4
142 +#define AHCI_VERSIONR 0x00f8
143 +#define AHCI_IDR 0x00fc
144 +#define AHCI_RWCR 0x00fc
145 +#define AHCI_P0DMACR 0x0170
146 +#define AHCI_P0PHYCR 0x0178
147 +#define AHCI_P0PHYSR 0x017c
148 +
149 +struct sunxi_ahci {
150 +       struct ahci_host_priv hpriv;
151 +       struct regulator *pwr;
152 +       struct clk *sata_clk;
153 +       struct clk *ahb_clk;
154 +};
155 +
156 +static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
157 +{
158 +       u32 reg_val;
159 +
160 +       reg_val = readl(reg);
161 +       reg_val &= ~(clr_val);
162 +       writel(reg_val, reg);
163 +}
164 +
165 +static void sunxi_setbits(void __iomem *reg, u32 set_val)
166 +{
167 +       u32 reg_val;
168 +
169 +       reg_val = readl(reg);
170 +       reg_val |= set_val;
171 +       writel(reg_val, reg);
172 +}
173 +
174 +static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
175 +{
176 +       u32 reg_val;
177 +
178 +       reg_val = readl(reg);
179 +       reg_val &= ~(clr_val);
180 +       reg_val |= set_val;
181 +       writel(reg_val, reg);
182 +}
183 +
184 +static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
185 +{
186 +       return (readl(reg) >> shift) & mask;
187 +}
188 +
189 +static int sunxi_ahci_phy_init(struct device *dev, void __iomem *reg_base)
190 +{
191 +       u32 reg_val;
192 +       int timeout;
193 +
194 +       /* This magic is from the original code */
195 +       writel(0, reg_base + AHCI_RWCR);
196 +       mdelay(5);
197 +
198 +       sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
199 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
200 +                        (0x7 << 24),
201 +                        (0x5 << 24) | BIT(23) | BIT(18));
202 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
203 +                        (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
204 +                        (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
205 +       sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
206 +       sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
207 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
208 +                        (0x7 << 20), (0x3 << 20));
209 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
210 +                        (0x1f << 5), (0x19 << 5));
211 +       mdelay(5);
212 +
213 +       sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
214 +
215 +       timeout = 0x100000;
216 +       do {
217 +               reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
218 +       } while (--timeout && (reg_val != 0x2));
219 +       if (!timeout) {
220 +               dev_err(dev, "PHY power up failed.\n");
221 +               return -EIO;
222 +       }
223 +
224 +       sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
225 +
226 +       timeout = 0x100000;
227 +       do {
228 +               reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
229 +       } while (--timeout && reg_val);
230 +       if (!timeout) {
231 +               dev_err(dev, "PHY calibration failed.\n");
232 +               return -EIO;
233 +       }
234 +       mdelay(15);
235 +
236 +       writel(0x7, reg_base + AHCI_RWCR);
237 +
238 +       return 0;
239 +}
240 +
241 +void sunxi_ahci_pre_start_engine(struct ata_port *ap)
242 +{
243 +       struct ahci_host_priv *hpriv = ap->host->private_data;
244 +
245 +       /* Setup DMA before DMA start */
246 +       sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
247 +}
248 +
249 +static int sunxi_ahci_enable_clks(struct sunxi_ahci *ahci)
250 +{
251 +       int ret;
252 +
253 +       ret = clk_prepare_enable(ahci->sata_clk);
254 +       if (ret)
255 +               return ret;
256 +
257 +       ret = clk_prepare_enable(ahci->ahb_clk);
258 +       if (ret)
259 +               clk_disable_unprepare(ahci->sata_clk);
260 +
261 +       return ret;
262 +}
263 +
264 +static void sunxi_ahci_disable_clks(struct sunxi_ahci *ahci)
265 +{
266 +       clk_disable_unprepare(ahci->ahb_clk);
267 +       clk_disable_unprepare(ahci->sata_clk);
268 +}
269 +
270 +static void sunxi_ahci_host_stop(struct ata_host *host)
271 +{
272 +       struct ahci_host_priv *hpriv = host->private_data;
273 +       struct sunxi_ahci *ahci = hpriv->plat_data;
274 +
275 +       if (!IS_ERR(ahci->pwr))
276 +               regulator_disable(ahci->pwr);
277 +
278 +       sunxi_ahci_disable_clks(ahci);
279 +}
280 +
281 +static struct ata_port_operations sunxi_ahci_platform_ops = {
282 +       .inherits       = &ahci_ops,
283 +       .host_stop      = sunxi_ahci_host_stop,
284 +};
285 +
286 +static const struct ata_port_info sunxiahci_port_info = {
287 +       AHCI_HFLAGS(AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
288 +                         AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ),
289 +       .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
290 +       .pio_mask       = ATA_PIO4,
291 +       .udma_mask      = ATA_UDMA6,
292 +       .port_ops       = &sunxi_ahci_platform_ops,
293 +};
294 +
295 +static struct scsi_host_template sunxi_ahci_platform_sht = {
296 +       AHCI_SHT("sunxi_ahci"),
297 +};
298 +
299 +static int sunxi_ahci_probe(struct platform_device *pdev)
300 +{
301 +       struct device *dev = &pdev->dev;
302 +       const struct ata_port_info *ppi[] = { &sunxiahci_port_info, NULL };
303 +       struct sunxi_ahci *ahci;
304 +       struct ata_host *host;
305 +       int ret;
306 +
307 +       ahci = devm_kzalloc(&pdev->dev, sizeof(*ahci), GFP_KERNEL);
308 +       if (!ahci)
309 +               return -ENOMEM;
310 +
311 +       ahci->pwr = devm_regulator_get_optional(dev, "pwr");
312 +       if (IS_ERR(ahci->pwr) && PTR_ERR(ahci->pwr) == -EPROBE_DEFER)
313 +               return -EPROBE_DEFER;
314 +
315 +       host = ata_host_alloc_pinfo(dev, ppi, 1);
316 +       if (!host)
317 +               return -ENOMEM;
318 +
319 +       host->private_data = &ahci->hpriv;
320 +       host->flags |= ATA_HOST_PARALLEL_SCAN;
321 +
322 +       ahci->hpriv.flags = (unsigned long)ppi[0]->private_data;
323 +       ahci->hpriv.plat_data = ahci;
324 +       ahci->hpriv.pre_start_engine = sunxi_ahci_pre_start_engine;
325 +       ahci->hpriv.mmio = devm_ioremap_resource(dev,
326 +                             platform_get_resource(pdev, IORESOURCE_MEM, 0));
327 +       if (IS_ERR(ahci->hpriv.mmio))
328 +               return PTR_ERR(ahci->hpriv.mmio);
329 +
330 +       ahci->ahb_clk = devm_clk_get(&pdev->dev, "ahb_sata");
331 +       if (IS_ERR(ahci->ahb_clk))
332 +               return PTR_ERR(ahci->ahb_clk);
333 +
334 +       ahci->sata_clk = devm_clk_get(&pdev->dev, "pll6_sata");
335 +       if (IS_ERR(ahci->sata_clk))
336 +               return PTR_ERR(ahci->sata_clk);
337 +
338 +       ret = sunxi_ahci_enable_clks(ahci);
339 +       if (ret)
340 +               return ret;
341 +
342 +       if (!IS_ERR(ahci->pwr)) {
343 +               ret = regulator_enable(ahci->pwr);
344 +               if (ret) {
345 +                       sunxi_ahci_disable_clks(ahci);
346 +                       return ret;
347 +               }
348 +       }
349 +
350 +       ret = sunxi_ahci_phy_init(dev, ahci->hpriv.mmio);
351 +       if (ret) {
352 +               sunxi_ahci_host_stop(host);
353 +               return ret;
354 +       }
355 +
356 +       ahci_save_initial_config(dev, &ahci->hpriv, 0, 0);
357 +
358 +       ret = ahci_reset_controller(host);
359 +       if (ret) {
360 +               sunxi_ahci_host_stop(host);
361 +               return ret;
362 +       }
363 +
364 +       ahci_init_controller(host);
365 +       ahci_print_info(host, "sunxi");
366 +
367 +       ret = ata_host_activate(host, platform_get_irq(pdev, 0),
368 +                               ahci_interrupt, 0, &sunxi_ahci_platform_sht);
369 +       if (ret)
370 +               sunxi_ahci_host_stop(host);
371 +
372 +       return ret;
373 +}
374 +
375 +#ifdef CONFIG_PM_SLEEP
376 +static int sunxi_ahci_susp(struct device *dev)
377 +{
378 +       struct ata_host *host = dev_get_drvdata(dev);
379 +       struct ahci_host_priv *hpriv = host->private_data;
380 +       struct sunxi_ahci *ahci = hpriv->plat_data;
381 +       int ret;
382 +
383 +       /*
384 +        * AHCI spec rev1.1 section 8.3.3:
385 +        * Software must disable interrupts prior to requesting a
386 +        * transition of the HBA to D3 state.
387 +        */
388 +       sunxi_clrbits(hpriv->mmio + HOST_CTL, HOST_IRQ_EN);
389 +
390 +       ret = ata_host_suspend(host, PMSG_SUSPEND);
391 +       if (ret)
392 +               return ret;
393 +
394 +       sunxi_ahci_disable_clks(ahci);
395 +
396 +       return 0;
397 +}
398 +
399 +static int sunxi_ahci_resume(struct device *dev)
400 +{
401 +       struct ata_host *host = dev_get_drvdata(dev);
402 +       struct ahci_host_priv *hpriv = host->private_data;
403 +       struct sunxi_ahci *ahci = hpriv->plat_data;
404 +       int ret;
405 +
406 +       ret = sunxi_ahci_enable_clks(ahci);
407 +       if (ret)
408 +               return ret;
409 +
410 +       if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
411 +               ret = ahci_reset_controller(host);
412 +               if (ret)
413 +                       return ret;
414 +
415 +               ahci_init_controller(host);
416 +       }
417 +
418 +       ata_host_resume(host);
419 +
420 +       return 0;
421 +}
422 +#endif
423 +
424 +static SIMPLE_DEV_PM_OPS(sunxi_ahci_pmo, sunxi_ahci_susp, sunxi_ahci_resume);
425 +
426 +static const struct of_device_id sunxi_ahci_of_match[] = {
427 +       { .compatible = "allwinner,sun4i-a10-ahci" },
428 +       { /* sentinel */ },
429 +};
430 +MODULE_DEVICE_TABLE(of, sunxi_ahci_of_match);
431 +
432 +static struct platform_driver sunxi_ahci_driver = {
433 +       .probe = sunxi_ahci_probe,
434 +       .remove = ata_platform_remove_one,
435 +       .driver = {
436 +               .name = "sunxi-ahci",
437 +               .owner = THIS_MODULE,
438 +               .of_match_table = sunxi_ahci_of_match,
439 +               .pm = &sunxi_ahci_pmo,
440 +       },
441 +};
442 +module_platform_driver(sunxi_ahci_driver);
443 +
444 +MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA platform driver");
445 +MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
446 +MODULE_LICENSE("GPL");
447 -- 
448 1.8.5.1
449