target/linux/sunxi/patches-3.13/145-clksrc-add-hstimer.patch

   1 From 3bf30f6381f9287eb99ce096bf2fa327a69c8a71 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Thu, 7 Nov 2013 12:01:48 +0100
   4 Subject: [PATCH] clocksource: Add Allwinner SoCs HS timers driver
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Most of the Allwinner SoCs (at this time, all but the A10) also have a
  10 High Speed timers that are not using the 24MHz oscillator as a source
  11 but rather the AHB clock running much faster.
  12
  13 The IP is slightly different between the A10s/A13 and the one used in
  14 the A20/A31, since the latter have 4 timers available, while the former
  15 have only 2 of them.
  16
  17 [dlezcano] : Fixed conflict with b788beda "Order Kconfig options
  18                 alphabetically"
  19
  20 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  21 Tested-by: Emilio López <emilio@elopez.com.ar>
  22 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
  23 ---
  24  .../bindings/timer/allwinner,sun5i-a13-hstimer.txt |  22 +++
  25  arch/arm/mach-sunxi/Kconfig                        |   1 +
  26  drivers/clocksource/Kconfig                        |   4 +
  27  drivers/clocksource/Makefile                       |   1 +
  28  drivers/clocksource/timer-sun5i.c                  | 192 +++++++++++++++++++++
  29  5 files changed, 220 insertions(+)
  30  create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
  31  create mode 100644 drivers/clocksource/timer-sun5i.c
  32
  33 --- /dev/null
  34 +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
  35 @@ -0,0 +1,22 @@
  36 +Allwinner SoCs High Speed Timer Controller
  37 +
  38 +Required properties:
  39 +
  40 +- compatible : should be "allwinner,sun5i-a13-hstimer" or
  41 +               "allwinner,sun7i-a20-hstimer"
  42 +- reg : Specifies base physical address and size of the registers.
  43 +- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
  44 +               one)
  45 +- clocks: phandle to the source clock (usually the AHB clock)
  46 +
  47 +Example:
  48 +
  49 +timer@01c60000 {
  50 +       compatible = "allwinner,sun7i-a20-hstimer";
  51 +       reg = <0x01c60000 0x1000>;
  52 +       interrupts = <0 51 1>,
  53 +                    <0 52 1>,
  54 +                    <0 53 1>,
  55 +                    <0 54 1>;
  56 +       clocks = <&ahb1_gates 19>;
  57 +};
  58 --- a/arch/arm/mach-sunxi/Kconfig
  59 +++ b/arch/arm/mach-sunxi/Kconfig
  60 @@ -13,3 +13,4 @@ config ARCH_SUNXI
  61         select PINCTRL_SUNXI
  62         select SPARSE_IRQ
  63         select SUN4I_TIMER
  64 +       select SUN5I_HSTIMER
  65 --- a/drivers/clocksource/Kconfig
  66 +++ b/drivers/clocksource/Kconfig
  67 @@ -37,6 +37,10 @@ config SUN4I_TIMER
  68         select CLKSRC_MMIO
  69         bool
  70
  71 +config SUN5I_HSTIMER
  72 +       select CLKSRC_MMIO
  73 +       bool
  74 +
  75  config VT8500_TIMER
  76         bool
  77
  78 --- a/drivers/clocksource/Makefile
  79 +++ b/drivers/clocksource/Makefile
  80 @@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_MOXART)     += moxart_time
  81  obj-$(CONFIG_ARCH_MXS)         += mxs_timer.o
  82  obj-$(CONFIG_ARCH_PRIMA2)      += timer-prima2.o
  83  obj-$(CONFIG_SUN4I_TIMER)      += sun4i_timer.o
  84 +obj-$(CONFIG_SUN5I_HSTIMER)    += timer-sun5i.o
  85  obj-$(CONFIG_ARCH_TEGRA)       += tegra20_timer.o
  86  obj-$(CONFIG_VT8500_TIMER)     += vt8500_timer.o
  87  obj-$(CONFIG_ARCH_NSPIRE)      += zevio-timer.o
  88 --- /dev/null
  89 +++ b/drivers/clocksource/timer-sun5i.c
  90 @@ -0,0 +1,192 @@
  91 +/*
  92 + * Allwinner SoCs hstimer driver.
  93 + *
  94 + * Copyright (C) 2013 Maxime Ripard
  95 + *
  96 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  97 + *
  98 + * This file is licensed under the terms of the GNU General Public
  99 + * License version 2.  This program is licensed "as is" without any
 100 + * warranty of any kind, whether express or implied.
 101 + */
 102 +
 103 +#include <linux/clk.h>
 104 +#include <linux/clockchips.h>
 105 +#include <linux/delay.h>
 106 +#include <linux/interrupt.h>
 107 +#include <linux/irq.h>
 108 +#include <linux/irqreturn.h>
 109 +#include <linux/sched_clock.h>
 110 +#include <linux/of.h>
 111 +#include <linux/of_address.h>
 112 +#include <linux/of_irq.h>
 113 +
 114 +#define TIMER_IRQ_EN_REG               0x00
 115 +#define TIMER_IRQ_EN(val)                      BIT(val)
 116 +#define TIMER_IRQ_ST_REG               0x04
 117 +#define TIMER_CTL_REG(val)             (0x20 * (val) + 0x10)
 118 +#define TIMER_CTL_ENABLE                       BIT(0)
 119 +#define TIMER_CTL_RELOAD                       BIT(1)
 120 +#define TIMER_CTL_CLK_PRES(val)                        (((val) & 0x7) << 4)
 121 +#define TIMER_CTL_ONESHOT                      BIT(7)
 122 +#define TIMER_INTVAL_LO_REG(val)       (0x20 * (val) + 0x14)
 123 +#define TIMER_INTVAL_HI_REG(val)       (0x20 * (val) + 0x18)
 124 +#define TIMER_CNTVAL_LO_REG(val)       (0x20 * (val) + 0x1c)
 125 +#define TIMER_CNTVAL_HI_REG(val)       (0x20 * (val) + 0x20)
 126 +
 127 +#define TIMER_SYNC_TICKS       3
 128 +
 129 +static void __iomem *timer_base;
 130 +static u32 ticks_per_jiffy;
 131 +
 132 +/*
 133 + * When we disable a timer, we need to wait at least for 2 cycles of
 134 + * the timer source clock. We will use for that the clocksource timer
 135 + * that is already setup and runs at the same frequency than the other
 136 + * timers, and we never will be disabled.
 137 + */
 138 +static void sun5i_clkevt_sync(void)
 139 +{
 140 +       u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));
 141 +
 142 +       while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
 143 +               cpu_relax();
 144 +}
 145 +
 146 +static void sun5i_clkevt_time_stop(u8 timer)
 147 +{
 148 +       u32 val = readl(timer_base + TIMER_CTL_REG(timer));
 149 +       writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
 150 +
 151 +       sun5i_clkevt_sync();
 152 +}
 153 +
 154 +static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
 155 +{
 156 +       writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
 157 +}
 158 +
 159 +static void sun5i_clkevt_time_start(u8 timer, bool periodic)
 160 +{
 161 +       u32 val = readl(timer_base + TIMER_CTL_REG(timer));
 162 +
 163 +       if (periodic)
 164 +               val &= ~TIMER_CTL_ONESHOT;
 165 +       else
 166 +               val |= TIMER_CTL_ONESHOT;
 167 +
 168 +       writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
 169 +              timer_base + TIMER_CTL_REG(timer));
 170 +}
 171 +
 172 +static void sun5i_clkevt_mode(enum clock_event_mode mode,
 173 +                             struct clock_event_device *clk)
 174 +{
 175 +       switch (mode) {
 176 +       case CLOCK_EVT_MODE_PERIODIC:
 177 +               sun5i_clkevt_time_stop(0);
 178 +               sun5i_clkevt_time_setup(0, ticks_per_jiffy);
 179 +               sun5i_clkevt_time_start(0, true);
 180 +               break;
 181 +       case CLOCK_EVT_MODE_ONESHOT:
 182 +               sun5i_clkevt_time_stop(0);
 183 +               sun5i_clkevt_time_start(0, false);
 184 +               break;
 185 +       case CLOCK_EVT_MODE_UNUSED:
 186 +       case CLOCK_EVT_MODE_SHUTDOWN:
 187 +       default:
 188 +               sun5i_clkevt_time_stop(0);
 189 +               break;
 190 +       }
 191 +}
 192 +
 193 +static int sun5i_clkevt_next_event(unsigned long evt,
 194 +                                  struct clock_event_device *unused)
 195 +{
 196 +       sun5i_clkevt_time_stop(0);
 197 +       sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
 198 +       sun5i_clkevt_time_start(0, false);
 199 +
 200 +       return 0;
 201 +}
 202 +
 203 +static struct clock_event_device sun5i_clockevent = {
 204 +       .name = "sun5i_tick",
 205 +       .rating = 340,
 206 +       .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 207 +       .set_mode = sun5i_clkevt_mode,
 208 +       .set_next_event = sun5i_clkevt_next_event,
 209 +};
 210 +
 211 +
 212 +static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
 213 +{
 214 +       struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 215 +
 216 +       writel(0x1, timer_base + TIMER_IRQ_ST_REG);
 217 +       evt->event_handler(evt);
 218 +
 219 +       return IRQ_HANDLED;
 220 +}
 221 +
 222 +static struct irqaction sun5i_timer_irq = {
 223 +       .name = "sun5i_timer0",
 224 +       .flags = IRQF_TIMER | IRQF_IRQPOLL,
 225 +       .handler = sun5i_timer_interrupt,
 226 +       .dev_id = &sun5i_clockevent,
 227 +};
 228 +
 229 +static u32 sun5i_timer_sched_read(void)
 230 +{
 231 +       return ~readl(timer_base + TIMER_CNTVAL_LO_REG(1));
 232 +}
 233 +
 234 +static void __init sun5i_timer_init(struct device_node *node)
 235 +{
 236 +       unsigned long rate;
 237 +       struct clk *clk;
 238 +       int ret, irq;
 239 +       u32 val;
 240 +
 241 +       timer_base = of_iomap(node, 0);
 242 +       if (!timer_base)
 243 +               panic("Can't map registers");
 244 +
 245 +       irq = irq_of_parse_and_map(node, 0);
 246 +       if (irq <= 0)
 247 +               panic("Can't parse IRQ");
 248 +
 249 +       clk = of_clk_get(node, 0);
 250 +       if (IS_ERR(clk))
 251 +               panic("Can't get timer clock");
 252 +       clk_prepare_enable(clk);
 253 +       rate = clk_get_rate(clk);
 254 +
 255 +       writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
 256 +       writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
 257 +              timer_base + TIMER_CTL_REG(1));
 258 +
 259 +       setup_sched_clock(sun5i_timer_sched_read, 32, rate);
 260 +       clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
 261 +                             rate, 340, 32, clocksource_mmio_readl_down);
 262 +
 263 +       ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
 264 +
 265 +       ret = setup_irq(irq, &sun5i_timer_irq);
 266 +       if (ret)
 267 +               pr_warn("failed to setup irq %d\n", irq);
 268 +
 269 +       /* Enable timer0 interrupt */
 270 +       val = readl(timer_base + TIMER_IRQ_EN_REG);
 271 +       writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
 272 +
 273 +       sun5i_clockevent.cpumask = cpu_possible_mask;
 274 +       sun5i_clockevent.irq = irq;
 275 +
 276 +       clockevents_config_and_register(&sun5i_clockevent, rate,
 277 +                                       TIMER_SYNC_TICKS, 0xffffffff);
 278 +}
 279 +CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
 280 +                      sun5i_timer_init);
 281 +CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
 282 +                      sun5i_timer_init);