target/linux/sunxi/patches-3.13/127-4-dt-sun7i-rename-clock-node-names.patch

   1 From cb6050998de262d5acf2207c5451d4f5995a5bff Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Mon, 3 Feb 2014 09:51:44 +0800
   4 Subject: [PATCH] ARM: dts: sun7i: rename clock node names to clk@N
   5
   6 Device tree naming conventions state that node names should match
   7 node function. Change fully functioning clock nodes to match and
   8 add clock-output-names to all sunxi clock nodes.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  12 ---
  13  arch/arm/boot/dts/sun7i-a20.dtsi | 25 +++++++++++++++++--------
  14  1 file changed, 17 insertions(+), 8 deletions(-)
  15
  16 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
  17 index fe0fe47..cefd7ac 100644
  18 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  19 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  20 @@ -54,11 +54,12 @@
  21                 #size-cells = <1>;
  22                 ranges;
  23
  24 -               osc24M: osc24M@01c20050 {
  25 +               osc24M: clk@01c20050 {
  26                         #clock-cells = <0>;
  27                         compatible = "allwinner,sun4i-osc-clk";
  28                         reg = <0x01c20050 0x4>;
  29                         clock-frequency = <24000000>;
  30 +                       clock-output-names = "osc24M";
  31                 };
  32
  33                 osc32k: clk@0 {
  34 @@ -68,21 +69,23 @@
  35                         clock-output-names = "osc32k";
  36                 };
  37
  38 -               pll1: pll1@01c20000 {
  39 +               pll1: clk@01c20000 {
  40                         #clock-cells = <0>;
  41                         compatible = "allwinner,sun4i-pll1-clk";
  42                         reg = <0x01c20000 0x4>;
  43                         clocks = <&osc24M>;
  44 +                       clock-output-names = "pll1";
  45                 };
  46
  47 -               pll4: pll4@01c20018 {
  48 +               pll4: clk@01c20018 {
  49                         #clock-cells = <0>;
  50                         compatible = "allwinner,sun4i-pll1-clk";
  51                         reg = <0x01c20018 0x4>;
  52                         clocks = <&osc24M>;
  53 +                       clock-output-names = "pll4";
  54                 };
  55
  56 -               pll5: pll5@01c20020 {
  57 +               pll5: clk@01c20020 {
  58                         #clock-cells = <1>;
  59                         compatible = "allwinner,sun4i-pll5-clk";
  60                         reg = <0x01c20020 0x4>;
  61 @@ -90,7 +93,7 @@
  62                         clock-output-names = "pll5_ddr", "pll5_other";
  63                 };
  64
  65 -               pll6: pll6@01c20028 {
  66 +               pll6: clk@01c20028 {
  67                         #clock-cells = <1>;
  68                         compatible = "allwinner,sun4i-pll6-clk";
  69                         reg = <0x01c20028 0x4>;
  70 @@ -103,6 +106,7 @@
  71                         compatible = "allwinner,sun4i-cpu-clk";
  72                         reg = <0x01c20054 0x4>;
  73                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
  74 +                       clock-output-names = "cpu";
  75                 };
  76
  77                 axi: axi@01c20054 {
  78 @@ -110,6 +114,7 @@
  79                         compatible = "allwinner,sun4i-axi-clk";
  80                         reg = <0x01c20054 0x4>;
  81                         clocks = <&cpu>;
  82 +                       clock-output-names = "axi";
  83                 };
  84
  85                 ahb: ahb@01c20054 {
  86 @@ -117,9 +122,10 @@
  87                         compatible = "allwinner,sun4i-ahb-clk";
  88                         reg = <0x01c20054 0x4>;
  89                         clocks = <&axi>;
  90 +                       clock-output-names = "ahb";
  91                 };
  92
  93 -               ahb_gates: ahb_gates@01c20060 {
  94 +               ahb_gates: clk@01c20060 {
  95                         #clock-cells = <1>;
  96                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
  97                         reg = <0x01c20060 0x8>;
  98 @@ -144,9 +150,10 @@
  99                         compatible = "allwinner,sun4i-apb0-clk";
 100                         reg = <0x01c20054 0x4>;
 101                         clocks = <&ahb>;
 102 +                       clock-output-names = "apb0";
 103                 };
 104
 105 -               apb0_gates: apb0_gates@01c20068 {
 106 +               apb0_gates: clk@01c20068 {
 107                         #clock-cells = <1>;
 108                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 109                         reg = <0x01c20068 0x4>;
 110 @@ -162,6 +169,7 @@
 111                         compatible = "allwinner,sun4i-apb1-mux-clk";
 112                         reg = <0x01c20058 0x4>;
 113                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 114 +                       clock-output-names = "apb1_mux";
 115                 };
 116
 117                 apb1: apb1@01c20058 {
 118 @@ -169,9 +177,10 @@
 119                         compatible = "allwinner,sun4i-apb1-clk";
 120                         reg = <0x01c20058 0x4>;
 121                         clocks = <&apb1_mux>;
 122 +                       clock-output-names = "apb1";
 123                 };
 124
 125 -               apb1_gates: apb1_gates@01c2006c {
 126 +               apb1_gates: clk@01c2006c {
 127                         #clock-cells = <1>;
 128                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 129                         reg = <0x01c2006c 0x4>;
 130 --
 131 1.8.5.5
 132