target/linux/sunxi/patches-3.13/122-3-dt-sun7i-add-mod0.patch

   1 From d7904e075e3378bec09333b6a3247b3146b3dd91 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:43 -0300
   4 Subject: [PATCH] ARM: sun7i: dt: mod0 clocks
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds all the mod0 clocks available on A20 to its device
  10 tree. This list was created by looking at AW's code release.
  11
  12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  13 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  14 ---
  15  arch/arm/boot/dts/sun7i-a20.dtsi | 120 +++++++++++++++++++++++++++++++++++++++
  16  1 file changed, 120 insertions(+)
  17
  18 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
  19 index 9176ed0..f6ee631 100644
  20 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  21 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  22 @@ -174,6 +174,126 @@
  23                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
  24                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
  25                 };
  26 +
  27 +               nand_clk: clk@01c20080 {
  28 +                       #clock-cells = <0>;
  29 +                       compatible = "allwinner,sun4i-mod0-clk";
  30 +                       reg = <0x01c20080 0x4>;
  31 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  32 +                       clock-output-names = "nand";
  33 +               };
  34 +
  35 +               ms_clk: clk@01c20084 {
  36 +                       #clock-cells = <0>;
  37 +                       compatible = "allwinner,sun4i-mod0-clk";
  38 +                       reg = <0x01c20084 0x4>;
  39 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  40 +                       clock-output-names = "ms";
  41 +               };
  42 +
  43 +               mmc0_clk: clk@01c20088 {
  44 +                       #clock-cells = <0>;
  45 +                       compatible = "allwinner,sun4i-mod0-clk";
  46 +                       reg = <0x01c20088 0x4>;
  47 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  48 +                       clock-output-names = "mmc0";
  49 +               };
  50 +
  51 +               mmc1_clk: clk@01c2008c {
  52 +                       #clock-cells = <0>;
  53 +                       compatible = "allwinner,sun4i-mod0-clk";
  54 +                       reg = <0x01c2008c 0x4>;
  55 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  56 +                       clock-output-names = "mmc1";
  57 +               };
  58 +
  59 +               mmc2_clk: clk@01c20090 {
  60 +                       #clock-cells = <0>;
  61 +                       compatible = "allwinner,sun4i-mod0-clk";
  62 +                       reg = <0x01c20090 0x4>;
  63 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  64 +                       clock-output-names = "mmc2";
  65 +               };
  66 +
  67 +               mmc3_clk: clk@01c20094 {
  68 +                       #clock-cells = <0>;
  69 +                       compatible = "allwinner,sun4i-mod0-clk";
  70 +                       reg = <0x01c20094 0x4>;
  71 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  72 +                       clock-output-names = "mmc3";
  73 +               };
  74 +
  75 +               ts_clk: clk@01c20098 {
  76 +                       #clock-cells = <0>;
  77 +                       compatible = "allwinner,sun4i-mod0-clk";
  78 +                       reg = <0x01c20098 0x4>;
  79 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  80 +                       clock-output-names = "ts";
  81 +               };
  82 +
  83 +               ss_clk: clk@01c2009c {
  84 +                       #clock-cells = <0>;
  85 +                       compatible = "allwinner,sun4i-mod0-clk";
  86 +                       reg = <0x01c2009c 0x4>;
  87 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  88 +                       clock-output-names = "ss";
  89 +               };
  90 +
  91 +               spi0_clk: clk@01c200a0 {
  92 +                       #clock-cells = <0>;
  93 +                       compatible = "allwinner,sun4i-mod0-clk";
  94 +                       reg = <0x01c200a0 0x4>;
  95 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  96 +                       clock-output-names = "spi0";
  97 +               };
  98 +
  99 +               spi1_clk: clk@01c200a4 {
 100 +                       #clock-cells = <0>;
 101 +                       compatible = "allwinner,sun4i-mod0-clk";
 102 +                       reg = <0x01c200a4 0x4>;
 103 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 104 +                       clock-output-names = "spi1";
 105 +               };
 106 +
 107 +               spi2_clk: clk@01c200a8 {
 108 +                       #clock-cells = <0>;
 109 +                       compatible = "allwinner,sun4i-mod0-clk";
 110 +                       reg = <0x01c200a8 0x4>;
 111 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 112 +                       clock-output-names = "spi2";
 113 +               };
 114 +
 115 +               pata_clk: clk@01c200ac {
 116 +                       #clock-cells = <0>;
 117 +                       compatible = "allwinner,sun4i-mod0-clk";
 118 +                       reg = <0x01c200ac 0x4>;
 119 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 120 +                       clock-output-names = "pata";
 121 +               };
 122 +
 123 +               ir0_clk: clk@01c200b0 {
 124 +                       #clock-cells = <0>;
 125 +                       compatible = "allwinner,sun4i-mod0-clk";
 126 +                       reg = <0x01c200b0 0x4>;
 127 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 128 +                       clock-output-names = "ir0";
 129 +               };
 130 +
 131 +               ir1_clk: clk@01c200b4 {
 132 +                       #clock-cells = <0>;
 133 +                       compatible = "allwinner,sun4i-mod0-clk";
 134 +                       reg = <0x01c200b4 0x4>;
 135 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 136 +                       clock-output-names = "ir1";
 137 +               };
 138 +
 139 +               spi3_clk: clk@01c200d4 {
 140 +                       #clock-cells = <0>;
 141 +                       compatible = "allwinner,sun4i-mod0-clk";
 142 +                       reg = <0x01c200d4 0x4>;
 143 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 144 +                       clock-output-names = "spi3";
 145 +               };
 146         };
 147
 148         soc@01c00000 {
 149 --
 150 1.8.5.1
 151