target/linux/sunxi/patches-3.13/122-2-dt-sun5i-add-mod0.patch

   1 From 9a8d3f21c94099a2bcd79ac1684cc8020fd98df2 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:42 -0300
   4 Subject: [PATCH] ARM: sun5i: dt: mod0 clocks
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds all the mod0 clocks available on A10 and A13. The list
  10 has been constructed by looking at the Allwinner code release for A10S
  11 and A13.
  12
  13 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  14 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  15 ---
  16  arch/arm/boot/dts/sun5i-a10s.dtsi | 88 +++++++++++++++++++++++++++++++++++++++
  17  arch/arm/boot/dts/sun5i-a13.dtsi  | 88 +++++++++++++++++++++++++++++++++++++++
  18  2 files changed, 176 insertions(+)
  19
  20 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
  21 index ca19362..96c7185 100644
  22 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
  23 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
  24 @@ -173,6 +173,94 @@
  25                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
  26                                 "apb1_uart2", "apb1_uart3";
  27                 };
  28 +
  29 +               nand_clk: clk@01c20080 {
  30 +                       #clock-cells = <0>;
  31 +                       compatible = "allwinner,sun4i-mod0-clk";
  32 +                       reg = <0x01c20080 0x4>;
  33 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  34 +                       clock-output-names = "nand";
  35 +               };
  36 +
  37 +               ms_clk: clk@01c20084 {
  38 +                       #clock-cells = <0>;
  39 +                       compatible = "allwinner,sun4i-mod0-clk";
  40 +                       reg = <0x01c20084 0x4>;
  41 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  42 +                       clock-output-names = "ms";
  43 +               };
  44 +
  45 +               mmc0_clk: clk@01c20088 {
  46 +                       #clock-cells = <0>;
  47 +                       compatible = "allwinner,sun4i-mod0-clk";
  48 +                       reg = <0x01c20088 0x4>;
  49 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  50 +                       clock-output-names = "mmc0";
  51 +               };
  52 +
  53 +               mmc1_clk: clk@01c2008c {
  54 +                       #clock-cells = <0>;
  55 +                       compatible = "allwinner,sun4i-mod0-clk";
  56 +                       reg = <0x01c2008c 0x4>;
  57 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  58 +                       clock-output-names = "mmc1";
  59 +               };
  60 +
  61 +               mmc2_clk: clk@01c20090 {
  62 +                       #clock-cells = <0>;
  63 +                       compatible = "allwinner,sun4i-mod0-clk";
  64 +                       reg = <0x01c20090 0x4>;
  65 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  66 +                       clock-output-names = "mmc2";
  67 +               };
  68 +
  69 +               ts_clk: clk@01c20098 {
  70 +                       #clock-cells = <0>;
  71 +                       compatible = "allwinner,sun4i-mod0-clk";
  72 +                       reg = <0x01c20098 0x4>;
  73 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  74 +                       clock-output-names = "ts";
  75 +               };
  76 +
  77 +               ss_clk: clk@01c2009c {
  78 +                       #clock-cells = <0>;
  79 +                       compatible = "allwinner,sun4i-mod0-clk";
  80 +                       reg = <0x01c2009c 0x4>;
  81 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  82 +                       clock-output-names = "ss";
  83 +               };
  84 +
  85 +               spi0_clk: clk@01c200a0 {
  86 +                       #clock-cells = <0>;
  87 +                       compatible = "allwinner,sun4i-mod0-clk";
  88 +                       reg = <0x01c200a0 0x4>;
  89 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  90 +                       clock-output-names = "spi0";
  91 +               };
  92 +
  93 +               spi1_clk: clk@01c200a4 {
  94 +                       #clock-cells = <0>;
  95 +                       compatible = "allwinner,sun4i-mod0-clk";
  96 +                       reg = <0x01c200a4 0x4>;
  97 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  98 +                       clock-output-names = "spi1";
  99 +               };
 100 +
 101 +               spi2_clk: clk@01c200a8 {
 102 +                       #clock-cells = <0>;
 103 +                       compatible = "allwinner,sun4i-mod0-clk";
 104 +                       reg = <0x01c200a8 0x4>;
 105 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 106 +                       clock-output-names = "spi2";
 107 +               };
 108 +
 109 +               ir0_clk: clk@01c200b0 {
 110 +                       #clock-cells = <0>;
 111 +                       compatible = "allwinner,sun4i-mod0-clk";
 112 +                       reg = <0x01c200b0 0x4>;
 113 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 114 +                       clock-output-names = "ir0";
 115 +               };
 116         };
 117
 118         soc@01c00000 {
 119 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
 120 index 9ac706a..e2505d6 100644
 121 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
 122 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
 123 @@ -170,6 +170,94 @@
 124                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 125                                 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
 126                 };
 127 +
 128 +               nand_clk: clk@01c20080 {
 129 +                       #clock-cells = <0>;
 130 +                       compatible = "allwinner,sun4i-mod0-clk";
 131 +                       reg = <0x01c20080 0x4>;
 132 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 133 +                       clock-output-names = "nand";
 134 +               };
 135 +
 136 +               ms_clk: clk@01c20084 {
 137 +                       #clock-cells = <0>;
 138 +                       compatible = "allwinner,sun4i-mod0-clk";
 139 +                       reg = <0x01c20084 0x4>;
 140 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 141 +                       clock-output-names = "ms";
 142 +               };
 143 +
 144 +               mmc0_clk: clk@01c20088 {
 145 +                       #clock-cells = <0>;
 146 +                       compatible = "allwinner,sun4i-mod0-clk";
 147 +                       reg = <0x01c20088 0x4>;
 148 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 149 +                       clock-output-names = "mmc0";
 150 +               };
 151 +
 152 +               mmc1_clk: clk@01c2008c {
 153 +                       #clock-cells = <0>;
 154 +                       compatible = "allwinner,sun4i-mod0-clk";
 155 +                       reg = <0x01c2008c 0x4>;
 156 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 157 +                       clock-output-names = "mmc1";
 158 +               };
 159 +
 160 +               mmc2_clk: clk@01c20090 {
 161 +                       #clock-cells = <0>;
 162 +                       compatible = "allwinner,sun4i-mod0-clk";
 163 +                       reg = <0x01c20090 0x4>;
 164 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 165 +                       clock-output-names = "mmc2";
 166 +               };
 167 +
 168 +               ts_clk: clk@01c20098 {
 169 +                       #clock-cells = <0>;
 170 +                       compatible = "allwinner,sun4i-mod0-clk";
 171 +                       reg = <0x01c20098 0x4>;
 172 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 173 +                       clock-output-names = "ts";
 174 +               };
 175 +
 176 +               ss_clk: clk@01c2009c {
 177 +                       #clock-cells = <0>;
 178 +                       compatible = "allwinner,sun4i-mod0-clk";
 179 +                       reg = <0x01c2009c 0x4>;
 180 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 181 +                       clock-output-names = "ss";
 182 +               };
 183 +
 184 +               spi0_clk: clk@01c200a0 {
 185 +                       #clock-cells = <0>;
 186 +                       compatible = "allwinner,sun4i-mod0-clk";
 187 +                       reg = <0x01c200a0 0x4>;
 188 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 189 +                       clock-output-names = "spi0";
 190 +               };
 191 +
 192 +               spi1_clk: clk@01c200a4 {
 193 +                       #clock-cells = <0>;
 194 +                       compatible = "allwinner,sun4i-mod0-clk";
 195 +                       reg = <0x01c200a4 0x4>;
 196 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 197 +                       clock-output-names = "spi1";
 198 +               };
 199 +
 200 +               spi2_clk: clk@01c200a8 {
 201 +                       #clock-cells = <0>;
 202 +                       compatible = "allwinner,sun4i-mod0-clk";
 203 +                       reg = <0x01c200a8 0x4>;
 204 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 205 +                       clock-output-names = "spi2";
 206 +               };
 207 +
 208 +               ir0_clk: clk@01c200b0 {
 209 +                       #clock-cells = <0>;
 210 +                       compatible = "allwinner,sun4i-mod0-clk";
 211 +                       reg = <0x01c200b0 0x4>;
 212 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 213 +                       clock-output-names = "ir0";
 214 +               };
 215         };
 216
 217         soc@01c00000 {
 218 --
 219 1.8.5.1
 220