target/linux/sunxi/patches-3.13/122-1-dt-sun4i-add-mod0.patch

   1 From dda274b6f95902b619af1fb14f26e231bb420371 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:41 -0300
   4 Subject: [PATCH] ARM: sun4i: dt: mod0 clocks
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit adds all the mod0 clocks present on sun4i to its device tree
  10
  11 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  12 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  13 ---
  14  arch/arm/boot/dts/sun4i-a10.dtsi | 120 +++++++++++++++++++++++++++++++++++++++
  15  1 file changed, 120 insertions(+)
  16
  17 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
  18 index 07564e9e..3ba2b46 100644
  19 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  20 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  21 @@ -184,6 +184,126 @@
  22                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
  23                                 "apb1_uart7";
  24                 };
  25 +
  26 +               nand_clk: clk@01c20080 {
  27 +                       #clock-cells = <0>;
  28 +                       compatible = "allwinner,sun4i-mod0-clk";
  29 +                       reg = <0x01c20080 0x4>;
  30 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  31 +                       clock-output-names = "nand";
  32 +               };
  33 +
  34 +               ms_clk: clk@01c20084 {
  35 +                       #clock-cells = <0>;
  36 +                       compatible = "allwinner,sun4i-mod0-clk";
  37 +                       reg = <0x01c20084 0x4>;
  38 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  39 +                       clock-output-names = "ms";
  40 +               };
  41 +
  42 +               mmc0_clk: clk@01c20088 {
  43 +                       #clock-cells = <0>;
  44 +                       compatible = "allwinner,sun4i-mod0-clk";
  45 +                       reg = <0x01c20088 0x4>;
  46 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  47 +                       clock-output-names = "mmc0";
  48 +               };
  49 +
  50 +               mmc1_clk: clk@01c2008c {
  51 +                       #clock-cells = <0>;
  52 +                       compatible = "allwinner,sun4i-mod0-clk";
  53 +                       reg = <0x01c2008c 0x4>;
  54 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  55 +                       clock-output-names = "mmc1";
  56 +               };
  57 +
  58 +               mmc2_clk: clk@01c20090 {
  59 +                       #clock-cells = <0>;
  60 +                       compatible = "allwinner,sun4i-mod0-clk";
  61 +                       reg = <0x01c20090 0x4>;
  62 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  63 +                       clock-output-names = "mmc2";
  64 +               };
  65 +
  66 +               mmc3_clk: clk@01c20094 {
  67 +                       #clock-cells = <0>;
  68 +                       compatible = "allwinner,sun4i-mod0-clk";
  69 +                       reg = <0x01c20094 0x4>;
  70 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  71 +                       clock-output-names = "mmc3";
  72 +               };
  73 +
  74 +               ts_clk: clk@01c20098 {
  75 +                       #clock-cells = <0>;
  76 +                       compatible = "allwinner,sun4i-mod0-clk";
  77 +                       reg = <0x01c20098 0x4>;
  78 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  79 +                       clock-output-names = "ts";
  80 +               };
  81 +
  82 +               ss_clk: clk@01c2009c {
  83 +                       #clock-cells = <0>;
  84 +                       compatible = "allwinner,sun4i-mod0-clk";
  85 +                       reg = <0x01c2009c 0x4>;
  86 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  87 +                       clock-output-names = "ss";
  88 +               };
  89 +
  90 +               spi0_clk: clk@01c200a0 {
  91 +                       #clock-cells = <0>;
  92 +                       compatible = "allwinner,sun4i-mod0-clk";
  93 +                       reg = <0x01c200a0 0x4>;
  94 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
  95 +                       clock-output-names = "spi0";
  96 +               };
  97 +
  98 +               spi1_clk: clk@01c200a4 {
  99 +                       #clock-cells = <0>;
 100 +                       compatible = "allwinner,sun4i-mod0-clk";
 101 +                       reg = <0x01c200a4 0x4>;
 102 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 103 +                       clock-output-names = "spi1";
 104 +               };
 105 +
 106 +               spi2_clk: clk@01c200a8 {
 107 +                       #clock-cells = <0>;
 108 +                       compatible = "allwinner,sun4i-mod0-clk";
 109 +                       reg = <0x01c200a8 0x4>;
 110 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 111 +                       clock-output-names = "spi2";
 112 +               };
 113 +
 114 +               pata_clk: clk@01c200ac {
 115 +                       #clock-cells = <0>;
 116 +                       compatible = "allwinner,sun4i-mod0-clk";
 117 +                       reg = <0x01c200ac 0x4>;
 118 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 119 +                       clock-output-names = "pata";
 120 +               };
 121 +
 122 +               ir0_clk: clk@01c200b0 {
 123 +                       #clock-cells = <0>;
 124 +                       compatible = "allwinner,sun4i-mod0-clk";
 125 +                       reg = <0x01c200b0 0x4>;
 126 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 127 +                       clock-output-names = "ir0";
 128 +               };
 129 +
 130 +               ir1_clk: clk@01c200b4 {
 131 +                       #clock-cells = <0>;
 132 +                       compatible = "allwinner,sun4i-mod0-clk";
 133 +                       reg = <0x01c200b4 0x4>;
 134 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 135 +                       clock-output-names = "ir1";
 136 +               };
 137 +
 138 +               spi3_clk: clk@01c200d4 {
 139 +                       #clock-cells = <0>;
 140 +                       compatible = "allwinner,sun4i-mod0-clk";
 141 +                       reg = <0x01c200d4 0x4>;
 142 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 143 +                       clock-output-names = "spi3";
 144 +               };
 145         };
 146
 147         soc@01c00000 {
 148 --
 149 1.8.5.1
 150