target/linux/sunxi/patches-3.13/113-clk-sunxi-register-factors-clocks.patch

   1 From 9212bc4a3752e9a4db2f73afd99278eb28e5dcff Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:32 -0300
   4 Subject: [PATCH] clk: sunxi: register factors clocks behind composite
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit reworks factors clock registration to be done behind a
  10 composite clock. This allows us to additionally add a gate, mux or
  11 divisors, as it will be needed by some future PLLs.
  12
  13 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  14 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  15 ---
  16  drivers/clk/sunxi/clk-factors.c | 63 +------------------------------------
  17  drivers/clk/sunxi/clk-factors.h | 16 +++++-----
  18  drivers/clk/sunxi/clk-sunxi.c   | 70 ++++++++++++++++++++++++++++++++++++++---
  19  3 files changed, 76 insertions(+), 73 deletions(-)
  20
  21 --- a/drivers/clk/sunxi/clk-factors.c
  22 +++ b/drivers/clk/sunxi/clk-factors.c
  23 @@ -30,14 +30,6 @@
  24   * parent - fixed parent.  No clk_set_parent support
  25   */
  26
  27 -struct clk_factors {
  28 -       struct clk_hw hw;
  29 -       void __iomem *reg;
  30 -       struct clk_factors_config *config;
  31 -       void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
  32 -       spinlock_t *lock;
  33 -};
  34 -
  35  #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
  36
  37  #define SETMASK(len, pos)              (((1U << (len)) - 1) << (pos))
  38 @@ -120,61 +112,8 @@ static int clk_factors_set_rate(struct c
  39         return 0;
  40  }
  41
  42 -static const struct clk_ops clk_factors_ops = {
  43 +const struct clk_ops clk_factors_ops = {
  44         .recalc_rate = clk_factors_recalc_rate,
  45         .round_rate = clk_factors_round_rate,
  46         .set_rate = clk_factors_set_rate,
  47  };
  48 -
  49 -/**
  50 - * clk_register_factors - register a factors clock with
  51 - * the clock framework
  52 - * @dev: device registering this clock
  53 - * @name: name of this clock
  54 - * @parent_name: name of clock's parent
  55 - * @flags: framework-specific flags
  56 - * @reg: register address to adjust factors
  57 - * @config: shift and width of factors n, k, m and p
  58 - * @get_factors: function to calculate the factors for a given frequency
  59 - * @lock: shared register lock for this clock
  60 - */
  61 -struct clk *clk_register_factors(struct device *dev, const char *name,
  62 -                                const char *parent_name,
  63 -                                unsigned long flags, void __iomem *reg,
  64 -                                struct clk_factors_config *config,
  65 -                                void (*get_factors)(u32 *rate, u32 parent,
  66 -                                                    u8 *n, u8 *k, u8 *m, u8 *p),
  67 -                                spinlock_t *lock)
  68 -{
  69 -       struct clk_factors *factors;
  70 -       struct clk *clk;
  71 -       struct clk_init_data init;
  72 -
  73 -       /* allocate the factors */
  74 -       factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
  75 -       if (!factors) {
  76 -               pr_err("%s: could not allocate factors clk\n", __func__);
  77 -               return ERR_PTR(-ENOMEM);
  78 -       }
  79 -
  80 -       init.name = name;
  81 -       init.ops = &clk_factors_ops;
  82 -       init.flags = flags;
  83 -       init.parent_names = (parent_name ? &parent_name : NULL);
  84 -       init.num_parents = (parent_name ? 1 : 0);
  85 -
  86 -       /* struct clk_factors assignments */
  87 -       factors->reg = reg;
  88 -       factors->config = config;
  89 -       factors->lock = lock;
  90 -       factors->hw.init = &init;
  91 -       factors->get_factors = get_factors;
  92 -
  93 -       /* register the clock */
  94 -       clk = clk_register(dev, &factors->hw);
  95 -
  96 -       if (IS_ERR(clk))
  97 -               kfree(factors);
  98 -
  99 -       return clk;
 100 -}
 101 --- a/drivers/clk/sunxi/clk-factors.h
 102 +++ b/drivers/clk/sunxi/clk-factors.h
 103 @@ -17,11 +17,13 @@ struct clk_factors_config {
 104         u8 pwidth;
 105  };
 106
 107 -struct clk *clk_register_factors(struct device *dev, const char *name,
 108 -                                const char *parent_name,
 109 -                                unsigned long flags, void __iomem *reg,
 110 -                                struct clk_factors_config *config,
 111 -                                void (*get_factors) (u32 *rate, u32 parent_rate,
 112 -                                                     u8 *n, u8 *k, u8 *m, u8 *p),
 113 -                                spinlock_t *lock);
 114 +struct clk_factors {
 115 +       struct clk_hw hw;
 116 +       void __iomem *reg;
 117 +       struct clk_factors_config *config;
 118 +       void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
 119 +       spinlock_t *lock;
 120 +};
 121 +
 122 +extern const struct clk_ops clk_factors_ops;
 123  #endif
 124 --- a/drivers/clk/sunxi/clk-sunxi.c
 125 +++ b/drivers/clk/sunxi/clk-sunxi.c
 126 @@ -23,6 +23,9 @@
 127
 128  static DEFINE_SPINLOCK(clk_lock);
 129
 130 +/* Maximum number of parents our clocks have */
 131 +#define SUNXI_MAX_PARENTS      5
 132 +
 133  /**
 134   * sun4i_osc_clk_setup() - Setup function for gatable oscillator
 135   */
 136 @@ -261,7 +264,11 @@ static void sun4i_get_apb1_factors(u32 *
 137   * sunxi_factors_clk_setup() - Setup function for factor clocks
 138   */
 139
 140 +#define SUNXI_FACTORS_MUX_MASK 0x3
 141 +
 142  struct factors_data {
 143 +       int enable;
 144 +       int mux;
 145         struct clk_factors_config *table;
 146         void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
 147  };
 148 @@ -312,16 +319,71 @@ static void __init sunxi_factors_clk_set
 149                                            struct factors_data *data)
 150  {
 151         struct clk *clk;
 152 +       struct clk_factors *factors;
 153 +       struct clk_gate *gate = NULL;
 154 +       struct clk_mux *mux = NULL;
 155 +       struct clk_hw *gate_hw = NULL;
 156 +       struct clk_hw *mux_hw = NULL;
 157         const char *clk_name = node->name;
 158 -       const char *parent;
 159 +       const char *parents[SUNXI_MAX_PARENTS];
 160         void *reg;
 161 +       int i = 0;
 162
 163         reg = of_iomap(node, 0);
 164
 165 -       parent = of_clk_get_parent_name(node, 0);
 166 +       /* if we have a mux, we will have >1 parents */
 167 +       while (i < SUNXI_MAX_PARENTS &&
 168 +              (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 169 +               i++;
 170 +
 171 +       factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
 172 +       if (!factors)
 173 +               return;
 174 +
 175 +       /* Add a gate if this factor clock can be gated */
 176 +       if (data->enable) {
 177 +               gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
 178 +               if (!gate) {
 179 +                       kfree(factors);
 180 +                       return;
 181 +               }
 182 +
 183 +               /* set up gate properties */
 184 +               gate->reg = reg;
 185 +               gate->bit_idx = data->enable;
 186 +               gate->lock = &clk_lock;
 187 +               gate_hw = &gate->hw;
 188 +       }
 189 +
 190 +       /* Add a mux if this factor clock can be muxed */
 191 +       if (data->mux) {
 192 +               mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
 193 +               if (!mux) {
 194 +                       kfree(factors);
 195 +                       kfree(gate);
 196 +                       return;
 197 +               }
 198 +
 199 +               /* set up gate properties */
 200 +               mux->reg = reg;
 201 +               mux->shift = data->mux;
 202 +               mux->mask = SUNXI_FACTORS_MUX_MASK;
 203 +               mux->lock = &clk_lock;
 204 +               mux_hw = &mux->hw;
 205 +       }
 206
 207 -       clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
 208 -                                  data->table, data->getter, &clk_lock);
 209 +       /* set up factors properties */
 210 +       factors->reg = reg;
 211 +       factors->config = data->table;
 212 +       factors->get_factors = data->getter;
 213 +       factors->lock = &clk_lock;
 214 +
 215 +       clk = clk_register_composite(NULL, clk_name,
 216 +                       parents, i,
 217 +                       mux_hw, &clk_mux_ops,
 218 +                       &factors->hw, &clk_factors_ops,
 219 +                       gate_hw, &clk_gate_ops,
 220 +                       i ? 0 : CLK_IS_ROOT);
 221
 222         if (!IS_ERR(clk)) {
 223                 of_clk_add_provider(node, of_clk_src_simple_get, clk);