target/linux/sunxi/patches-3.13/105-reset-add-reset-ctrler.patch

   1 From 8015cea648c452bbfe0fc820dcb1185beaeb8736 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Tue, 24 Sep 2013 11:07:43 +0300
   4 Subject: [PATCH] reset: Add Allwinner SoCs Reset Controller Driver
   5
   6 The Allwinner A31 and most of the other Allwinner SoCs have an IP
   7 maintaining a few other IPs in the SoC in reset by default. Among these
   8 IPs are the A31's High Speed Timers, hence why we can't use the regular
   9 driver construct in every cases, and need to call the registering
  10 function directly during machine initialisation.
  11
  12 Apart from this, the implementation is fairly straightforward, and could
  13 easily be moved to a generic MMIO-based reset controller driver if the
  14 need ever arise.
  15
  16 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  17 Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
  18 ---
  19  drivers/reset/Makefile      |   1 +
  20  drivers/reset/reset-sunxi.c | 175 ++++++++++++++++++++++++++++++++++++++++++++
  21  2 files changed, 176 insertions(+)
  22  create mode 100644 drivers/reset/reset-sunxi.c
  23
  24 diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
  25 index 1e2d83f..cc29832 100644
  26 --- a/drivers/reset/Makefile
  27 +++ b/drivers/reset/Makefile
  28 @@ -1 +1,2 @@
  29  obj-$(CONFIG_RESET_CONTROLLER) += core.o
  30 +obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
  31 diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
  32 new file mode 100644
  33 index 0000000..695bd34
  34 --- /dev/null
  35 +++ b/drivers/reset/reset-sunxi.c
  36 @@ -0,0 +1,175 @@
  37 +/*
  38 + * Allwinner SoCs Reset Controller driver
  39 + *
  40 + * Copyright 2013 Maxime Ripard
  41 + *
  42 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  43 + *
  44 + * This program is free software; you can redistribute it and/or modify
  45 + * it under the terms of the GNU General Public License as published by
  46 + * the Free Software Foundation; either version 2 of the License, or
  47 + * (at your option) any later version.
  48 + */
  49 +
  50 +#include <linux/err.h>
  51 +#include <linux/io.h>
  52 +#include <linux/module.h>
  53 +#include <linux/of.h>
  54 +#include <linux/of_address.h>
  55 +#include <linux/platform_device.h>
  56 +#include <linux/reset-controller.h>
  57 +#include <linux/slab.h>
  58 +#include <linux/spinlock.h>
  59 +#include <linux/types.h>
  60 +
  61 +struct sunxi_reset_data {
  62 +       spinlock_t                      lock;
  63 +       void __iomem                    *membase;
  64 +       struct reset_controller_dev     rcdev;
  65 +};
  66 +
  67 +static int sunxi_reset_assert(struct reset_controller_dev *rcdev,
  68 +                             unsigned long id)
  69 +{
  70 +       struct sunxi_reset_data *data = container_of(rcdev,
  71 +                                                    struct sunxi_reset_data,
  72 +                                                    rcdev);
  73 +       int bank = id / BITS_PER_LONG;
  74 +       int offset = id % BITS_PER_LONG;
  75 +       unsigned long flags;
  76 +       u32 reg;
  77 +
  78 +       spin_lock_irqsave(&data->lock, flags);
  79 +
  80 +       reg = readl(data->membase + (bank * 4));
  81 +       writel(reg & ~BIT(offset), data->membase + (bank * 4));
  82 +
  83 +       spin_unlock_irqrestore(&data->lock, flags);
  84 +
  85 +       return 0;
  86 +}
  87 +
  88 +static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
  89 +                               unsigned long id)
  90 +{
  91 +       struct sunxi_reset_data *data = container_of(rcdev,
  92 +                                                    struct sunxi_reset_data,
  93 +                                                    rcdev);
  94 +       int bank = id / BITS_PER_LONG;
  95 +       int offset = id % BITS_PER_LONG;
  96 +       unsigned long flags;
  97 +       u32 reg;
  98 +
  99 +       spin_lock_irqsave(&data->lock, flags);
 100 +
 101 +       reg = readl(data->membase + (bank * 4));
 102 +       writel(reg | BIT(offset), data->membase + (bank * 4));
 103 +
 104 +       spin_unlock_irqrestore(&data->lock, flags);
 105 +
 106 +       return 0;
 107 +}
 108 +
 109 +static struct reset_control_ops sunxi_reset_ops = {
 110 +       .assert         = sunxi_reset_assert,
 111 +       .deassert       = sunxi_reset_deassert,
 112 +};
 113 +
 114 +static int sunxi_reset_init(struct device_node *np)
 115 +{
 116 +       struct sunxi_reset_data *data;
 117 +       struct resource res;
 118 +       resource_size_t size;
 119 +       int ret;
 120 +
 121 +       data = kzalloc(sizeof(*data), GFP_KERNEL);
 122 +       if (!data)
 123 +               return -ENOMEM;
 124 +
 125 +       ret = of_address_to_resource(np, 0, &res);
 126 +       if (ret)
 127 +               goto err_alloc;
 128 +
 129 +       size = resource_size(&res);
 130 +       if (!request_mem_region(res.start, size, np->name)) {
 131 +               ret = -EBUSY;
 132 +               goto err_alloc;
 133 +       }
 134 +
 135 +       data->membase = ioremap(res.start, size);
 136 +       if (!data->membase) {
 137 +               ret = -ENOMEM;
 138 +               goto err_alloc;
 139 +       }
 140 +
 141 +       data->rcdev.owner = THIS_MODULE;
 142 +       data->rcdev.nr_resets = size * 32;
 143 +       data->rcdev.ops = &sunxi_reset_ops;
 144 +       data->rcdev.of_node = np;
 145 +       reset_controller_register(&data->rcdev);
 146 +
 147 +       return 0;
 148 +
 149 +err_alloc:
 150 +       kfree(data);
 151 +       return ret;
 152 +};
 153 +
 154 +/*
 155 + * These are the reset controller we need to initialize early on in
 156 + * our system, before we can even think of using a regular device
 157 + * driver for it.
 158 + */
 159 +static const struct of_device_id sunxi_early_reset_dt_ids[] __initdata = {
 160 +       { .compatible = "allwinner,sun6i-a31-ahb1-reset", },
 161 +       { /* sentinel */ },
 162 +};
 163 +
 164 +void __init sun6i_reset_init(void)
 165 +{
 166 +       struct device_node *np;
 167 +
 168 +       for_each_matching_node(np, sunxi_early_reset_dt_ids)
 169 +               sunxi_reset_init(np);
 170 +}
 171 +
 172 +/*
 173 + * And these are the controllers we can register through the regular
 174 + * device model.
 175 + */
 176 +static const struct of_device_id sunxi_reset_dt_ids[] = {
 177 +        { .compatible = "allwinner,sun6i-a31-clock-reset", },
 178 +        { /* sentinel */ },
 179 +};
 180 +MODULE_DEVICE_TABLE(of, sunxi_reset_dt_ids);
 181 +
 182 +static int sunxi_reset_probe(struct platform_device *pdev)
 183 +{
 184 +       return sunxi_reset_init(pdev->dev.of_node);
 185 +}
 186 +
 187 +static int sunxi_reset_remove(struct platform_device *pdev)
 188 +{
 189 +       struct sunxi_reset_data *data = platform_get_drvdata(pdev);
 190 +
 191 +       reset_controller_unregister(&data->rcdev);
 192 +       iounmap(data->membase);
 193 +       kfree(data);
 194 +
 195 +       return 0;
 196 +}
 197 +
 198 +static struct platform_driver sunxi_reset_driver = {
 199 +       .probe  = sunxi_reset_probe,
 200 +       .remove = sunxi_reset_remove,
 201 +       .driver = {
 202 +               .name           = "sunxi-reset",
 203 +               .owner          = THIS_MODULE,
 204 +               .of_match_table = sunxi_reset_dt_ids,
 205 +       },
 206 +};
 207 +module_platform_driver(sunxi_reset_driver);
 208 +
 209 +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
 210 +MODULE_DESCRIPTION("Allwinner SoCs Reset Controller Driver");
 211 +MODULE_LICENSE("GPL");
 212 --
 213 1.8.5.1
 214