target/linux/sunxi/patches-3.12/191-add-sunxi-ahci.patch

   1 From b7f492ca20e480ea3402692e165f919f20145935 Mon Sep 17 00:00:00 2001
   2 From: Oliver Schinagl <oliver@schinagl.nl>
   3 Date: Tue, 3 Dec 2013 12:07:01 +0100
   4 Subject: [PATCH] ARM: sunxi: Add an ahci-platform compatible AHCI driver for
   5  the Allwinner SUNXi series of SoCs
   6
   7 This patch adds support for the sunxi series of SoC's by allwinner. It
   8 plugs into the ahci-platform framework.
   9
  10 Note: Currently it uses a somewhat hackish approach that probably needs
  11 a lot more work, but does the same as the IMX SoC's.
  12
  13 Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
  14 ---
  15  .../devicetree/bindings/ata/ahci-sunxi.txt         |  24 ++
  16  drivers/ata/Kconfig                                |   9 +
  17  drivers/ata/Makefile                               |   1 +
  18  drivers/ata/ahci_platform.c                        |  12 +
  19  drivers/ata/ahci_sunxi.c                           | 305 +++++++++++++++++++++
  20  5 files changed, 351 insertions(+)
  21  create mode 100644 Documentation/devicetree/bindings/ata/ahci-sunxi.txt
  22  create mode 100644 drivers/ata/ahci_sunxi.c
  23
  24 diff --git a/Documentation/devicetree/bindings/ata/ahci-sunxi.txt b/Documentation/devicetree/bindings/ata/ahci-sunxi.txt
  25 new file mode 100644
  26 index 0000000..0792fa5
  27 --- /dev/null
  28 +++ b/Documentation/devicetree/bindings/ata/ahci-sunxi.txt
  29 @@ -0,0 +1,24 @@
  30 +Allwinner SUNXI AHCI SATA Controller
  31 +
  32 +SATA nodes are defined to describe on-chip Serial ATA controllers.
  33 +Each SATA controller should have its own node.
  34 +
  35 +Required properties:
  36 +- compatible   : compatible list, contains "allwinner,sun4i-a10-ahci"
  37 +- reg          : <registers mapping>
  38 +- interrupts   : <interrupt mapping for AHCI IRQ>
  39 +- clocks       : clocks for ACHI
  40 +- clock-names  : clock names for AHCI
  41 +
  42 +Optional properties:
  43 +- pwr-supply   : regulator to control the power supply GPIO
  44 +
  45 +Example:
  46 +       ahci@01c18000 {
  47 +               compatible = "allwinner,sun4i-a10-ahci";
  48 +               reg = <0x01c18000 0x1000>;
  49 +               interrupts = <0 56 1>;
  50 +               clocks = <&ahb_gates 25>, <&pll6 0>;
  51 +               clock-names = "ahb_sata", "pll6_sata";
  52 +               pwr-supply = <&reg_ahci_5v>;
  53 +       };
  54 diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
  55 index 4e73772..b87e2ba 100644
  56 --- a/drivers/ata/Kconfig
  57 +++ b/drivers/ata/Kconfig
  58 @@ -106,6 +106,15 @@ config AHCI_IMX
  59
  60           If unsure, say N.
  61
  62 +config AHCI_SUNXI
  63 +       tristate "Allwinner sunxi AHCI SATA support"
  64 +       depends on SATA_AHCI_PLATFORM && ARCH_SUNXI
  65 +       help
  66 +         This option enables support for the Allwinner sunxi SoC's
  67 +         onboard AHCI SATA.
  68 +
  69 +         If unsure, say N.
  70 +
  71  config SATA_FSL
  72         tristate "Freescale 3.0Gbps SATA support"
  73         depends on FSL_SOC
  74 diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
  75 index 46518c6..246050b 100644
  76 --- a/drivers/ata/Makefile
  77 +++ b/drivers/ata/Makefile
  78 @@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24)      += sata_sil24.o
  79  obj-$(CONFIG_SATA_DWC)         += sata_dwc_460ex.o
  80  obj-$(CONFIG_SATA_HIGHBANK)    += sata_highbank.o libahci.o
  81  obj-$(CONFIG_AHCI_IMX)         += ahci_imx.o
  82 +obj-$(CONFIG_AHCI_SUNXI)       += ahci_sunxi.o
  83
  84  # SFF w/ custom DMA
  85  obj-$(CONFIG_PDC_ADMA)         += pdc_adma.o
  86 diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
  87 index 4b231ba..1046b44 100644
  88 --- a/drivers/ata/ahci_platform.c
  89 +++ b/drivers/ata/ahci_platform.c
  90 @@ -31,6 +31,7 @@ enum ahci_type {
  91         AHCI,           /* standard platform ahci */
  92         IMX53_AHCI,     /* ahci on i.mx53 */
  93         STRICT_AHCI,    /* delayed DMA engine start */
  94 +       SUNXI_AHCI,     /* ahci on sunxi */
  95  };
  96
  97  static struct platform_device_id ahci_devtype[] = {
  98 @@ -44,6 +45,9 @@ enum ahci_type {
  99                 .name = "strict-ahci",
 100                 .driver_data = STRICT_AHCI,
 101         }, {
 102 +               .name = "sunxi-ahci",
 103 +               .driver_data = SUNXI_AHCI,
 104 +       }, {
 105                 /* sentinel */
 106         }
 107  };
 108 @@ -81,6 +85,14 @@ struct ata_port_operations ahci_platform_ops = {
 109                 .udma_mask      = ATA_UDMA6,
 110                 .port_ops       = &ahci_platform_ops,
 111         },
 112 +       [SUNXI_AHCI] = {
 113 +               AHCI_HFLAGS     (AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
 114 +                                AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ),
 115 +               .flags          = AHCI_FLAG_COMMON,
 116 +               .pio_mask       = ATA_PIO4,
 117 +               .udma_mask      = ATA_UDMA6,
 118 +               .port_ops       = &ahci_platform_ops,
 119 +       },
 120  };
 121
 122  static struct scsi_host_template ahci_platform_sht = {
 123 diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
 124 new file mode 100644
 125 index 0000000..982641f
 126 --- /dev/null
 127 +++ b/drivers/ata/ahci_sunxi.c
 128 @@ -0,0 +1,305 @@
 129 +/*
 130 + * Allwinner sunxi AHCI SATA platform driver
 131 + * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
 132 + *
 133 + * Based on the AHCI SATA platform driver by Freescale and Allwinner
 134 + * Based on code from
 135 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 136 + * Daniel Wang <danielwang@allwinnertech.com>
 137 + *
 138 + * This program is free software; you can redistribute it and/or modify it
 139 + * under the terms and conditions of the GNU General Public License,
 140 + * version 2, as published by the Free Software Foundation.
 141 + *
 142 + * This program is distributed in the hope it will be useful, but WITHOUT
 143 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 144 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 145 + * more details.
 146 + *
 147 + * You should have received a copy of the GNU General Public License along with
 148 + * this program. If not, see <http://www.gnu.org/licenses/>.
 149 + */
 150 +
 151 +#include <linux/kernel.h>
 152 +#include <linux/regulator/consumer.h>
 153 +#include <linux/module.h>
 154 +#include <linux/platform_device.h>
 155 +#include <linux/mod_devicetable.h>
 156 +#include <linux/of_device.h>
 157 +#include <linux/ioport.h>
 158 +#include <linux/device.h>
 159 +#include <linux/gfp.h>
 160 +#include <linux/clk.h>
 161 +#include <linux/clk-provider.h>
 162 +#include <linux/errno.h>
 163 +#include <linux/ahci_platform.h>
 164 +#include "ahci.h"
 165 +
 166 +#define DRV_NAME "sunxi-sata"
 167 +
 168 +#define AHCI_BISTAFR 0x00a0
 169 +#define AHCI_BISTCR 0x00a4
 170 +#define AHCI_BISTFCTR 0x00a8
 171 +#define AHCI_BISTSR 0x00ac
 172 +#define AHCI_BISTDECR 0x00b0
 173 +#define AHCI_DIAGNR0 0x00b4
 174 +#define AHCI_DIAGNR1 0x00b8
 175 +#define AHCI_OOBR 0x00bc
 176 +#define AHCI_PHYCS0R 0x00c0
 177 +#define AHCI_PHYCS1R 0x00c4
 178 +#define AHCI_PHYCS2R 0x00c8
 179 +#define AHCI_TIMER1MS 0x00e0
 180 +#define AHCI_GPARAM1R 0x00e8
 181 +#define AHCI_GPARAM2R 0x00ec
 182 +#define AHCI_PPARAMR 0x00f0
 183 +#define AHCI_TESTR 0x00f4
 184 +#define AHCI_VERSIONR 0x00f8
 185 +#define AHCI_IDR 0x00fc
 186 +#define AHCI_RWCR 0x00fc
 187 +#define AHCI_P0DMACR 0x0170
 188 +#define AHCI_P0PHYCR 0x0178
 189 +#define AHCI_P0PHYSR 0x017c
 190 +
 191 +struct sunxi_ahci_data {
 192 +       struct platform_device *ahci_pdev;
 193 +       struct regulator *regulator;
 194 +       struct clk *sata_clk;
 195 +       struct clk *ahb_clk;
 196 +};
 197 +
 198 +static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
 199 +{
 200 +       u32 reg_val;
 201 +
 202 +       reg_val = readl(reg);
 203 +       reg_val &= ~(clr_val);
 204 +       writel(reg_val, reg);
 205 +}
 206 +
 207 +static void sunxi_setbits(void __iomem *reg, u32 set_val)
 208 +{
 209 +       u32 reg_val;
 210 +
 211 +       reg_val = readl(reg);
 212 +       reg_val |= set_val;
 213 +       writel(reg_val, reg);
 214 +}
 215 +
 216 +static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
 217 +{
 218 +       u32 reg_val;
 219 +
 220 +       reg_val = readl(reg);
 221 +       reg_val &= ~(clr_val);
 222 +       reg_val |= set_val;
 223 +       writel(reg_val, reg);
 224 +}
 225 +
 226 +static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
 227 +{
 228 +       return (readl(reg) >> shift) & mask;
 229 +}
 230 +
 231 +static int sunxi_ahci_phy_init(struct device *dev, void __iomem *reg_base)
 232 +{
 233 +       u32 reg_val;
 234 +       int timeout;
 235 +
 236 +       /* This magic is from the original code */
 237 +       writel(0, reg_base + AHCI_RWCR);
 238 +       mdelay(5);
 239 +
 240 +       sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
 241 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
 242 +                        (0x7 << 24),
 243 +                        (0x5 << 24) | BIT(23) | BIT(18));
 244 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
 245 +                        (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
 246 +                        (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
 247 +       sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
 248 +       sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
 249 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
 250 +                        (0x7 << 20), (0x3 << 20));
 251 +       sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
 252 +                        (0x1f << 5), (0x19 << 5));
 253 +       mdelay(5);
 254 +
 255 +       sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
 256 +
 257 +       timeout = 0x100000;
 258 +       do {
 259 +               reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
 260 +       } while (--timeout && (reg_val != 0x2));
 261 +       if (!timeout)
 262 +               dev_err(dev, "PHY power up failed.\n");
 263 +
 264 +       sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
 265 +
 266 +       timeout = 0x100000;
 267 +       do {
 268 +               reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
 269 +       } while (--timeout && reg_val);
 270 +       if (!timeout)
 271 +               dev_err(dev, "PHY calibration failed.\n");
 272 +       mdelay(15);
 273 +
 274 +       writel(0x7, reg_base + AHCI_RWCR);
 275 +
 276 +       return 0;
 277 +}
 278 +
 279 +static int sunxi_ahci_init(struct device *dev, void __iomem *reg_base)
 280 +{
 281 +       struct sunxi_ahci_data *ahci_data;
 282 +       int ret;
 283 +
 284 +       ahci_data = dev_get_drvdata(dev->parent);
 285 +
 286 +       ret = clk_prepare_enable(ahci_data->sata_clk);
 287 +       if (ret < 0)
 288 +               return ret;
 289 +
 290 +       ret = clk_prepare_enable(ahci_data->ahb_clk);
 291 +       if (ret < 0)
 292 +               return ret;
 293 +
 294 +       ret = regulator_enable(ahci_data->regulator);
 295 +       if (ret)
 296 +               return ret;
 297 +
 298 +       return sunxi_ahci_phy_init(dev, reg_base);
 299 +}
 300 +
 301 +static void sunxi_ahci_exit(struct device *dev)
 302 +{
 303 +       struct sunxi_ahci_data *ahci_data;
 304 +
 305 +       ahci_data = dev_get_drvdata(dev->parent);
 306 +
 307 +       regulator_disable(ahci_data->regulator);
 308 +
 309 +       clk_disable_unprepare(ahci_data->ahb_clk);
 310 +       clk_disable_unprepare(ahci_data->sata_clk);
 311 +}
 312 +
 313 +static struct ahci_platform_data sunxi_ahci_pdata = {
 314 +       .init = sunxi_ahci_init,
 315 +       .exit = sunxi_ahci_exit,
 316 +};
 317 +
 318 +static int sunxi_ahci_remove(struct platform_device *pdev)
 319 +{
 320 +       struct sunxi_ahci_data *ahci_data;
 321 +
 322 +       ahci_data = platform_get_drvdata(pdev);
 323 +       platform_device_unregister(ahci_data->ahci_pdev);
 324 +
 325 +       dev_dbg(&pdev->dev, "driver unloaded\n");
 326 +
 327 +       return 0;
 328 +}
 329 +
 330 +static const struct of_device_id sunxi_ahci_of_match[] = {
 331 +       { .compatible = "allwinner,sun4i-a10-ahci", .data = &sunxi_ahci_pdata},
 332 +       {/* sentinel */},
 333 +};
 334 +MODULE_DEVICE_TABLE(of, sunxi_ahci_of_match);
 335 +
 336 +static int sunxi_ahci_probe(struct platform_device *pdev)
 337 +{
 338 +       const struct ahci_platform_data *pdata;
 339 +       const struct of_device_id *of_dev_id;
 340 +       struct resource *mem, *irq, res[2];
 341 +       struct platform_device *ahci_pdev;
 342 +       struct sunxi_ahci_data *ahci_data;
 343 +       struct regulator *regulator;
 344 +       int ret;
 345 +
 346 +       regulator = devm_regulator_get(&pdev->dev, "pwr");
 347 +       if (IS_ERR(regulator)) {
 348 +               ret = PTR_ERR(regulator);
 349 +               if (ret != -EPROBE_DEFER)
 350 +                       dev_err(&pdev->dev, "no regulator found (%d)\n", ret);
 351 +               return ret;
 352 +       }
 353 +
 354 +       ahci_data = devm_kzalloc(&pdev->dev, sizeof(*ahci_data), GFP_KERNEL);
 355 +       if (!ahci_data)
 356 +               return -ENOMEM;
 357 +
 358 +       ahci_pdev = platform_device_alloc("sunxi-ahci", -1);
 359 +       if (!ahci_pdev)
 360 +               return -ENODEV;
 361 +
 362 +       ahci_pdev->dev.parent = &pdev->dev;
 363 +
 364 +       ahci_data->regulator = regulator;
 365 +       ahci_data->ahb_clk = devm_clk_get(&pdev->dev, "ahb_sata");
 366 +       if (IS_ERR(ahci_data->ahb_clk)) {
 367 +               ret = PTR_ERR(ahci_data->ahb_clk);
 368 +               goto err_out;
 369 +       }
 370 +
 371 +       ahci_data->sata_clk = devm_clk_get(&pdev->dev, "pll6_sata");
 372 +       if (IS_ERR(ahci_data->sata_clk)) {
 373 +               ret = PTR_ERR(ahci_data->sata_clk);
 374 +               goto err_out;
 375 +       }
 376 +
 377 +       ahci_data->ahci_pdev = ahci_pdev;
 378 +       platform_set_drvdata(pdev, ahci_data);
 379 +
 380 +       ahci_pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 381 +       ahci_pdev->dev.dma_mask = &ahci_pdev->dev.coherent_dma_mask;
 382 +       ahci_pdev->dev.of_node = pdev->dev.of_node;
 383 +
 384 +       of_dev_id = of_match_device(sunxi_ahci_of_match, &pdev->dev);
 385 +       if (of_dev_id) {
 386 +               pdata = of_dev_id->data;
 387 +       } else {
 388 +               ret = -EINVAL;
 389 +               goto err_out;
 390 +       }
 391 +
 392 +       mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 393 +       irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 394 +       if (!mem || !irq) {
 395 +               ret = -ENOMEM;
 396 +               goto err_out;
 397 +       }
 398 +       res[0] = *mem;
 399 +       res[1] = *irq;
 400 +       ret = platform_device_add_resources(ahci_pdev, res, 2);
 401 +       if (ret)
 402 +               goto err_out;
 403 +
 404 +       ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
 405 +       if (ret)
 406 +               goto err_out;
 407 +
 408 +       ret = platform_device_add(ahci_pdev);
 409 +       if (ret)
 410 +               goto err_out;
 411 +
 412 +       return 0;
 413 +
 414 +err_out:
 415 +       platform_device_put(ahci_pdev);
 416 +       return ret;
 417 +}
 418 +
 419 +static struct platform_driver sunxi_ahci_driver = {
 420 +       .probe = sunxi_ahci_probe,
 421 +       .remove = sunxi_ahci_remove,
 422 +       .driver = {
 423 +               .name = DRV_NAME,
 424 +               .owner = THIS_MODULE,
 425 +               .of_match_table = sunxi_ahci_of_match,
 426 +       },
 427 +};
 428 +module_platform_driver(sunxi_ahci_driver);
 429 +
 430 +MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA platform driver");
 431 +MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
 432 +MODULE_LICENSE("GPL");
 433 +MODULE_ALIAS("ahci:sunxi");
 434 --
 435 1.8.5.1
 436