1 From 73bff3c4c33a2bfbddc593fad53c6c58af93bfab Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Mon, 6 May 2013 11:03:41 -0300
4 Subject: [PATCH] ARM: sunxi: add PLL4 support
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
10 device trees. PLL4 is compatible with PLL1.
12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
14 arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++++++
15 arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++
16 arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++
17 arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++
18 4 files changed, 28 insertions(+)
20 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
21 index 319cc6b..a6c1cae 100644
22 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
23 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
28 + pll4: pll4@01c20018 {
30 + compatible = "allwinner,sun4i-pll1-clk";
31 + reg = <0x01c20018 0x4>;
38 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
39 index 5247674..c3f4eed 100644
40 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
41 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
46 + pll4: pll4@01c20018 {
48 + compatible = "allwinner,sun4i-pll1-clk";
49 + reg = <0x01c20018 0x4>;
56 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
57 index ce8ef2a..8c4a9c3 100644
58 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
59 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
64 + pll4: pll4@01c20018 {
66 + compatible = "allwinner,sun4i-pll1-clk";
67 + reg = <0x01c20018 0x4>;
74 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
75 index 282c775..21bf143 100644
76 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
77 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
82 + pll4: pll4@01c20018 {
84 + compatible = "allwinner,sun4i-pll1-clk";
85 + reg = <0x01c20018 0x4>;
90 * This is a dummy clock, to be used as placeholder on
91 * other mux clocks when a specific parent clock is not