get rid of $Id$ - it has never helped us and it has broken too many patches ;)
[openwrt.git] / target / linux / rb532 / files-2.6.24 / include / asm-mips / rc32434 / eth.h
1 #ifndef __IDT_ETH_H__
2 #define __IDT_ETH_H__
3
4 /*******************************************************************************
5  *
6  * Copyright 2002 Integrated Device Technology, Inc.
7  *              All rights reserved.
8  *
9  * Ethernet register definition.
10  *
11  *
12  * Author : Allen.Stichter@idt.com
13  * Date   : 20020605
14  * Update :
15  *          $Log: eth.h,v $
16  *          Revision 1.3  2002/06/06 18:34:04  astichte
17  *          Added XXX_PhysicalAddress and XXX_VirtualAddress
18  *      
19  *          Revision 1.2  2002/06/05 18:19:46  astichte
20  *          Added
21  *      
22  *          Revision 1.1  2002/05/29 17:33:22  sysarch
23  *          jba File moved from vcode/include/idt/acacia
24  *
25  ******************************************************************************/
26
27 enum
28 {
29         ETH0_PhysicalAddress    = 0x18060000,
30         ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
31
32         ETH0_VirtualAddress     = 0xb8060000,
33         ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
34 } ;
35
36 typedef struct
37 {
38         u32 ethintfc            ;
39         u32 ethfifott           ;
40         u32 etharc              ;
41         u32 ethhash0            ;
42         u32 ethhash1            ;
43         u32 ethu0 [4]           ;       // Reserved.    
44         u32 ethpfs              ;
45         u32 ethmcp              ;
46         u32 eth_u1 [10]         ;       // Reserved.
47         u32 ethspare            ;
48         u32 eth_u2 [42]         ;       // Reserved. 
49         u32 ethsal0             ;
50         u32 ethsah0             ;
51         u32 ethsal1             ;
52         u32 ethsah1             ;
53         u32 ethsal2             ;
54         u32 ethsah2             ;
55         u32 ethsal3             ;
56         u32 ethsah3             ;
57         u32 ethrbc              ;
58         u32 ethrpc              ;
59         u32 ethrupc             ;
60         u32 ethrfc              ;
61         u32 ethtbc              ;
62         u32 ethgpf              ;
63         u32 eth_u9 [50]         ;       // Reserved.    
64         u32 ethmac1             ;
65         u32 ethmac2             ;
66         u32 ethipgt             ;
67         u32 ethipgr             ;
68         u32 ethclrt             ;
69         u32 ethmaxf             ;
70         u32 eth_u10             ;       // Reserved.    
71         u32 ethmtest            ;
72         u32 miimcfg             ;
73         u32 miimcmd             ;
74         u32 miimaddr            ;
75         u32 miimwtd             ;
76         u32 miimrdd             ;
77         u32 miimind             ;
78         u32 eth_u11             ;       // Reserved.
79         u32 eth_u12             ;       // Reserved.
80         u32 ethcfsa0            ;
81         u32 ethcfsa1            ;
82         u32 ethcfsa2            ;
83 } volatile *ETH_t;
84
85 enum
86 {
87         ETHINTFC_en_b           = 0,
88         ETHINTFC_en_m           = 0x00000001,
89         ETHINTFC_its_b          = 1,
90         ETHINTFC_its_m          = 0x00000002,
91         ETHINTFC_rip_b          = 2,
92         ETHINTFC_rip_m          = 0x00000004,
93         ETHINTFC_jam_b          = 3,
94         ETHINTFC_jam_m          = 0x00000008,
95         ETHINTFC_ovr_b          = 4,
96         ETHINTFC_ovr_m          = 0x00000010,
97         ETHINTFC_und_b          = 5,
98         ETHINTFC_und_m          = 0x00000020,
99         ETHINTFC_iom_b          = 6,
100         ETHINTFC_iom_m          = 0x000000c0,
101
102         ETHFIFOTT_tth_b         = 0,
103         ETHFIFOTT_tth_m         = 0x0000007f,
104
105         ETHARC_pro_b            = 0,
106         ETHARC_pro_m            = 0x00000001,
107         ETHARC_am_b             = 1,
108         ETHARC_am_m             = 0x00000002,
109         ETHARC_afm_b            = 2,
110         ETHARC_afm_m            = 0x00000004,
111         ETHARC_ab_b             = 3,
112         ETHARC_ab_m             = 0x00000008,
113
114         ETHSAL_byte5_b          = 0,
115         ETHSAL_byte5_m          = 0x000000ff,
116         ETHSAL_byte4_b          = 8,
117         ETHSAL_byte4_m          = 0x0000ff00,
118         ETHSAL_byte3_b          = 16,
119         ETHSAL_byte3_m          = 0x00ff0000,
120         ETHSAL_byte2_b          = 24,
121         ETHSAL_byte2_m          = 0xff000000,
122
123         ETHSAH_byte1_b          = 0,
124         ETHSAH_byte1_m          = 0x000000ff,
125         ETHSAH_byte0_b          = 8,
126         ETHSAH_byte0_m          = 0x0000ff00,
127         
128         ETHGPF_ptv_b            = 0,
129         ETHGPF_ptv_m            = 0x0000ffff,
130
131         ETHPFS_pfd_b            = 0,
132         ETHPFS_pfd_m            = 0x00000001,
133
134         ETHCFSA0_cfsa4_b        = 0,
135         ETHCFSA0_cfsa4_m        = 0x000000ff,
136         ETHCFSA0_cfsa5_b        = 8,
137         ETHCFSA0_cfsa5_m        = 0x0000ff00,
138
139         ETHCFSA1_cfsa2_b        = 0,
140         ETHCFSA1_cfsa2_m        = 0x000000ff,
141         ETHCFSA1_cfsa3_b        = 8,
142         ETHCFSA1_cfsa3_m        = 0x0000ff00,
143
144         ETHCFSA2_cfsa0_b        = 0,
145         ETHCFSA2_cfsa0_m        = 0x000000ff,
146         ETHCFSA2_cfsa1_b        = 8,
147         ETHCFSA2_cfsa1_m        = 0x0000ff00,
148
149         ETHMAC1_re_b            = 0,
150         ETHMAC1_re_m            = 0x00000001,
151         ETHMAC1_paf_b           = 1,
152         ETHMAC1_paf_m           = 0x00000002,
153         ETHMAC1_rfc_b           = 2,
154         ETHMAC1_rfc_m           = 0x00000004,
155         ETHMAC1_tfc_b           = 3,
156         ETHMAC1_tfc_m           = 0x00000008,
157         ETHMAC1_lb_b            = 4,
158         ETHMAC1_lb_m            = 0x00000010,
159         ETHMAC1_mr_b            = 31,
160         ETHMAC1_mr_m            = 0x80000000,
161
162         ETHMAC2_fd_b            = 0,
163         ETHMAC2_fd_m            = 0x00000001,
164         ETHMAC2_flc_b           = 1,
165         ETHMAC2_flc_m           = 0x00000002,
166         ETHMAC2_hfe_b           = 2,
167         ETHMAC2_hfe_m           = 0x00000004,
168         ETHMAC2_dc_b            = 3,
169         ETHMAC2_dc_m            = 0x00000008,
170         ETHMAC2_cen_b           = 4,
171         ETHMAC2_cen_m           = 0x00000010,
172         ETHMAC2_pe_b            = 5,
173         ETHMAC2_pe_m            = 0x00000020,
174         ETHMAC2_vpe_b           = 6,
175         ETHMAC2_vpe_m           = 0x00000040,
176         ETHMAC2_ape_b           = 7,
177         ETHMAC2_ape_m           = 0x00000080,
178         ETHMAC2_ppe_b           = 8,
179         ETHMAC2_ppe_m           = 0x00000100,
180         ETHMAC2_lpe_b           = 9,
181         ETHMAC2_lpe_m           = 0x00000200,
182         ETHMAC2_nb_b            = 12,
183         ETHMAC2_nb_m            = 0x00001000,
184         ETHMAC2_bp_b            = 13,
185         ETHMAC2_bp_m            = 0x00002000,
186         ETHMAC2_ed_b            = 14,
187         ETHMAC2_ed_m            = 0x00004000,
188
189         ETHIPGT_ipgt_b          = 0,
190         ETHIPGT_ipgt_m          = 0x0000007f,
191
192         ETHIPGR_ipgr2_b         = 0,
193         ETHIPGR_ipgr2_m         = 0x0000007f,
194         ETHIPGR_ipgr1_b         = 8,
195         ETHIPGR_ipgr1_m         = 0x00007f00,
196
197         ETHCLRT_maxret_b        = 0,
198         ETHCLRT_maxret_m        = 0x0000000f,
199         ETHCLRT_colwin_b        = 8,
200         ETHCLRT_colwin_m        = 0x00003f00,
201
202         ETHMAXF_maxf_b          = 0,
203         ETHMAXF_maxf_m          = 0x0000ffff,
204
205         ETHMTEST_tb_b           = 2,
206         ETHMTEST_tb_m           = 0x00000004,
207
208         ETHMCP_div_b            = 0,
209         ETHMCP_div_m            = 0x000000ff,
210         
211         MIIMCFG_rsv_b           = 0,
212         MIIMCFG_rsv_m           = 0x0000000c,
213
214         MIIMCMD_rd_b            = 0,
215         MIIMCMD_rd_m            = 0x00000001,
216         MIIMCMD_scn_b           = 1,
217         MIIMCMD_scn_m           = 0x00000002,
218
219         MIIMADDR_regaddr_b      = 0,
220         MIIMADDR_regaddr_m      = 0x0000001f,
221         MIIMADDR_phyaddr_b      = 8,
222         MIIMADDR_phyaddr_m      = 0x00001f00,
223
224         MIIMWTD_wdata_b         = 0,
225         MIIMWTD_wdata_m         = 0x0000ffff,
226
227         MIIMRDD_rdata_b         = 0,
228         MIIMRDD_rdata_m         = 0x0000ffff,
229
230         MIIMIND_bsy_b           = 0,
231         MIIMIND_bsy_m           = 0x00000001,
232         MIIMIND_scn_b           = 1,
233         MIIMIND_scn_m           = 0x00000002,
234         MIIMIND_nv_b            = 2,
235         MIIMIND_nv_m            = 0x00000004,
236
237 } ;
238
239 /*
240  * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
241  */
242 enum
243 {
244         ETHRX_fd_b              = 0,
245         ETHRX_fd_m              = 0x00000001,
246         ETHRX_ld_b              = 1,
247         ETHRX_ld_m              = 0x00000002,
248         ETHRX_rok_b             = 2,
249         ETHRX_rok_m             = 0x00000004,
250         ETHRX_fm_b              = 3,
251         ETHRX_fm_m              = 0x00000008,
252         ETHRX_mp_b              = 4,
253         ETHRX_mp_m              = 0x00000010,
254         ETHRX_bp_b              = 5,
255         ETHRX_bp_m              = 0x00000020,
256         ETHRX_vlt_b             = 6,
257         ETHRX_vlt_m             = 0x00000040,
258         ETHRX_cf_b              = 7,
259         ETHRX_cf_m              = 0x00000080,
260         ETHRX_ovr_b             = 8,
261         ETHRX_ovr_m             = 0x00000100,
262         ETHRX_crc_b             = 9,
263         ETHRX_crc_m             = 0x00000200,
264         ETHRX_cv_b              = 10,
265         ETHRX_cv_m              = 0x00000400,
266         ETHRX_db_b              = 11,
267         ETHRX_db_m              = 0x00000800,
268         ETHRX_le_b              = 12,
269         ETHRX_le_m              = 0x00001000,
270         ETHRX_lor_b             = 13,
271         ETHRX_lor_m             = 0x00002000,
272         ETHRX_ces_b             = 14,
273         ETHRX_ces_m             = 0x00004000,
274         ETHRX_length_b          = 16,
275         ETHRX_length_m          = 0xffff0000,
276
277         ETHTX_fd_b              = 0,
278         ETHTX_fd_m              = 0x00000001,
279         ETHTX_ld_b              = 1,
280         ETHTX_ld_m              = 0x00000002,
281         ETHTX_oen_b             = 2,
282         ETHTX_oen_m             = 0x00000004,
283         ETHTX_pen_b             = 3,
284         ETHTX_pen_m             = 0x00000008,
285         ETHTX_cen_b             = 4,
286         ETHTX_cen_m             = 0x00000010,
287         ETHTX_hen_b             = 5,
288         ETHTX_hen_m             = 0x00000020,
289         ETHTX_tok_b             = 6,
290         ETHTX_tok_m             = 0x00000040,
291         ETHTX_mp_b              = 7,
292         ETHTX_mp_m              = 0x00000080,
293         ETHTX_bp_b              = 8,
294         ETHTX_bp_m              = 0x00000100,
295         ETHTX_und_b             = 9,
296         ETHTX_und_m             = 0x00000200,
297         ETHTX_of_b              = 10,
298         ETHTX_of_m              = 0x00000400,
299         ETHTX_ed_b              = 11,
300         ETHTX_ed_m              = 0x00000800,
301         ETHTX_ec_b              = 12,
302         ETHTX_ec_m              = 0x00001000,
303         ETHTX_lc_b              = 13,
304         ETHTX_lc_m              = 0x00002000,
305         ETHTX_td_b              = 14,
306         ETHTX_td_m              = 0x00004000,
307         ETHTX_crc_b             = 15,
308         ETHTX_crc_m             = 0x00008000,
309         ETHTX_le_b              = 16,
310         ETHTX_le_m              = 0x00010000,
311         ETHTX_cc_b              = 17,
312         ETHTX_cc_m              = 0x001E0000,
313 } ;
314
315 #endif  // __IDT_ETH_H__
316
317
318
319