1 From 776726ff626249276936a7e1f865103ea4e1b7e9 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 3 Dec 2013 17:05:05 +0100
4 Subject: [PATCH] DMA: add rt2880 dma engine
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/dma/Kconfig | 6 +
9 drivers/dma/Makefile | 1 +
10 drivers/dma/ralink-gdma.c | 596 +++++++++++++++++++++++++++++++++++++++++++++
11 3 files changed, 603 insertions(+)
12 create mode 100644 drivers/dma/ralink-gdma.c
14 Index: linux-3.10.18/drivers/dma/Kconfig
15 ===================================================================
16 --- linux-3.10.18.orig/drivers/dma/Kconfig 2013-11-04 13:31:29.000000000 +0100
17 +++ linux-3.10.18/drivers/dma/Kconfig 2013-12-04 17:52:32.852756567 +0100
20 Support the MMP PDMA engine for PXA and MMP platfrom.
23 + tristate "RALINK DMA support"
24 + depends on RALINK && SOC_MT7620
26 + select DMA_VIRTUAL_CHANNELS
31 Index: linux-3.10.18/drivers/dma/ralink-gdma.c
32 ===================================================================
33 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
34 +++ linux-3.10.18/drivers/dma/ralink-gdma.c 2013-12-05 21:17:22.245128605 +0100
37 + * Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
38 + * GDMA4740 DMAC support
40 + * This program is free software; you can redistribute it and/or modify it
41 + * under the terms of the GNU General Public License as published by the
42 + * Free Software Foundation; either version 2 of the License, or (at your
43 + * option) any later version.
45 + * You should have received a copy of the GNU General Public License along
46 + * with this program; if not, write to the Free Software Foundation, Inc.,
47 + * 675 Mass Ave, Cambridge, MA 02139, USA.
51 +#include <linux/dmaengine.h>
52 +#include <linux/dma-mapping.h>
53 +#include <linux/err.h>
54 +#include <linux/init.h>
55 +#include <linux/list.h>
56 +#include <linux/module.h>
57 +#include <linux/platform_device.h>
58 +#include <linux/slab.h>
59 +#include <linux/spinlock.h>
60 +#include <linux/irq.h>
61 +#include <linux/of_dma.h>
63 +#include "virt-dma.h"
65 +#define GDMA_NR_CHANS 16
67 +#define GDMA_REG_SRC_ADDR(x) (0x00 + (x) * 0x10)
68 +#define GDMA_REG_DST_ADDR(x) (0x04 + (x) * 0x10)
70 +#define GDMA_REG_CTRL0(x) (0x08 + (x) * 0x10)
71 +#define GDMA_REG_CTRL0_TX_MASK 0xffff
72 +#define GDMA_REG_CTRL0_TX_SHIFT 16
73 +#define GDMA_REG_CTRL0_CURR_MASK 0xff
74 +#define GDMA_REG_CTRL0_CURR_SHIFT 8
75 +#define GDMA_REG_CTRL0_SRC_ADDR_FIXED BIT(7)
76 +#define GDMA_REG_CTRL0_DST_ADDR_FIXED BIT(6)
77 +#define GDMA_REG_CTRL0_BURST_MASK 0x7
78 +#define GDMA_REG_CTRL0_BURST_SHIFT 3
79 +#define GDMA_REG_CTRL0_DONE_INT BIT(2)
80 +#define GDMA_REG_CTRL0_ENABLE BIT(1)
81 +#define GDMA_REG_CTRL0_HW_MODE 0
83 +#define GDMA_REG_CTRL1(x) (0x0c + (x) * 0x10)
84 +#define GDMA_REG_CTRL1_SEG_MASK 0xf
85 +#define GDMA_REG_CTRL1_SEG_SHIFT 22
86 +#define GDMA_REG_CTRL1_REQ_MASK 0x3f
87 +#define GDMA_REG_CTRL1_SRC_REQ_SHIFT 16
88 +#define GDMA_REG_CTRL1_DST_REQ_SHIFT 8
89 +#define GDMA_REG_CTRL1_CONTINOUS BIT(14)
90 +#define GDMA_REG_CTRL1_NEXT_MASK 0x1f
91 +#define GDMA_REG_CTRL1_NEXT_SHIFT 3
92 +#define GDMA_REG_CTRL1_COHERENT BIT(2)
93 +#define GDMA_REG_CTRL1_FAIL BIT(1)
94 +#define GDMA_REG_CTRL1_MASK BIT(0)
96 +#define GDMA_REG_UNMASK_INT 0x200
97 +#define GDMA_REG_DONE_INT 0x204
99 +#define GDMA_REG_GCT 0x220
100 +#define GDMA_REG_GCT_CHAN_MASK 0x3
101 +#define GDMA_REG_GCT_CHAN_SHIFT 3
102 +#define GDMA_REG_GCT_VER_MASK 0x3
103 +#define GDMA_REG_GCT_VER_SHIFT 1
104 +#define GDMA_REG_GCT_ARBIT_RR BIT(0)
106 +enum gdma_dma_transfer_size {
107 + GDMA_TRANSFER_SIZE_4BYTE = 0,
108 + GDMA_TRANSFER_SIZE_8BYTE = 1,
109 + GDMA_TRANSFER_SIZE_16BYTE = 2,
110 + GDMA_TRANSFER_SIZE_32BYTE = 3,
113 +struct gdma_dma_sg {
118 +struct gdma_dma_desc {
119 + struct virt_dma_desc vdesc;
121 + enum dma_transfer_direction direction;
124 + unsigned int num_sgs;
125 + struct gdma_dma_sg sg[];
128 +struct gdma_dmaengine_chan {
129 + struct virt_dma_chan vchan;
132 + dma_addr_t fifo_addr;
133 + unsigned int transfer_shift;
135 + struct gdma_dma_desc *desc;
136 + unsigned int next_sg;
139 +struct gdma_dma_dev {
140 + struct dma_device ddev;
141 + void __iomem *base;
144 + struct gdma_dmaengine_chan chan[GDMA_NR_CHANS];
147 +static struct gdma_dma_dev *gdma_dma_chan_get_dev(
148 + struct gdma_dmaengine_chan *chan)
150 + return container_of(chan->vchan.chan.device, struct gdma_dma_dev,
154 +static struct gdma_dmaengine_chan *to_gdma_dma_chan(struct dma_chan *c)
156 + return container_of(c, struct gdma_dmaengine_chan, vchan.chan);
159 +static struct gdma_dma_desc *to_gdma_dma_desc(struct virt_dma_desc *vdesc)
161 + return container_of(vdesc, struct gdma_dma_desc, vdesc);
164 +static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev,
167 + return readl(dma_dev->base + reg);
170 +static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev,
171 + unsigned reg, uint32_t val)
173 + //printk("gdma --> %p = 0x%08X\n", dma_dev->base + reg, val);
174 + writel(val, dma_dev->base + reg);
177 +static inline void gdma_dma_write_mask(struct gdma_dma_dev *dma_dev,
178 + unsigned int reg, uint32_t val, uint32_t mask)
182 + tmp = gdma_dma_read(dma_dev, reg);
185 + gdma_dma_write(dma_dev, reg, tmp);
188 +static struct gdma_dma_desc *gdma_dma_alloc_desc(unsigned int num_sgs)
190 + return kzalloc(sizeof(struct gdma_dma_desc) +
191 + sizeof(struct gdma_dma_sg) * num_sgs, GFP_ATOMIC);
194 +static enum gdma_dma_transfer_size gdma_dma_maxburst(u32 maxburst)
197 + return GDMA_TRANSFER_SIZE_4BYTE;
198 + else if (maxburst <= 15)
199 + return GDMA_TRANSFER_SIZE_8BYTE;
200 + else if (maxburst <= 31)
201 + return GDMA_TRANSFER_SIZE_16BYTE;
203 + return GDMA_TRANSFER_SIZE_32BYTE;
206 +static int gdma_dma_slave_config(struct dma_chan *c,
207 + const struct dma_slave_config *config)
209 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
210 + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
211 + enum gdma_dma_transfer_size transfer_size;
213 + uint32_t ctrl0, ctrl1;
215 + switch (config->direction) {
216 + case DMA_MEM_TO_DEV:
217 + ctrl1 = 32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
218 + ctrl1 |= config->slave_id << GDMA_REG_CTRL1_DST_REQ_SHIFT;
219 + flags = GDMA_REG_CTRL0_DST_ADDR_FIXED;
220 + transfer_size = gdma_dma_maxburst(config->dst_maxburst);
221 + chan->fifo_addr = config->dst_addr;
224 + case DMA_DEV_TO_MEM:
225 + ctrl1 = config->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT;
226 + ctrl1 |= 32 << GDMA_REG_CTRL1_DST_REQ_SHIFT;
227 + flags = GDMA_REG_CTRL0_SRC_ADDR_FIXED;
228 + transfer_size = gdma_dma_maxburst(config->src_maxburst);
229 + chan->fifo_addr = config->src_addr;
236 + chan->transfer_shift = 1 + transfer_size;
238 + ctrl0 = flags | GDMA_REG_CTRL0_HW_MODE;
239 + ctrl0 |= GDMA_REG_CTRL0_DONE_INT;
241 + ctrl1 &= ~(GDMA_REG_CTRL1_NEXT_MASK << GDMA_REG_CTRL1_NEXT_SHIFT);
242 + ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
243 + ctrl1 |= GDMA_REG_CTRL1_FAIL;
244 + ctrl1 &= ~GDMA_REG_CTRL1_CONTINOUS;
245 + gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
246 + gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
251 +static int gdma_dma_terminate_all(struct dma_chan *c)
253 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
254 + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
255 + unsigned long flags;
258 + spin_lock_irqsave(&chan->vchan.lock, flags);
259 + gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
260 + GDMA_REG_CTRL0_ENABLE);
262 + vchan_get_all_descriptors(&chan->vchan, &head);
263 + spin_unlock_irqrestore(&chan->vchan.lock, flags);
265 + vchan_dma_desc_free_list(&chan->vchan, &head);
270 +static int gdma_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
273 + struct dma_slave_config *config = (struct dma_slave_config *)arg;
276 + case DMA_SLAVE_CONFIG:
277 + return gdma_dma_slave_config(chan, config);
278 + case DMA_TERMINATE_ALL:
279 + return gdma_dma_terminate_all(chan);
285 +static int gdma_dma_start_transfer(struct gdma_dmaengine_chan *chan)
287 + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
288 + dma_addr_t src_addr, dst_addr;
289 + struct virt_dma_desc *vdesc;
290 + struct gdma_dma_sg *sg;
292 + gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id), 0,
293 + GDMA_REG_CTRL0_ENABLE);
296 + vdesc = vchan_next_desc(&chan->vchan);
299 + chan->desc = to_gdma_dma_desc(vdesc);
303 + if (chan->next_sg == chan->desc->num_sgs)
306 + sg = &chan->desc->sg[chan->next_sg];
308 + if (chan->desc->direction == DMA_MEM_TO_DEV) {
309 + src_addr = sg->addr;
310 + dst_addr = chan->fifo_addr;
312 + src_addr = chan->fifo_addr;
313 + dst_addr = sg->addr;
315 + gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
316 + gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
317 + gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL0(chan->id),
318 + (sg->len << GDMA_REG_CTRL0_TX_SHIFT) | GDMA_REG_CTRL0_ENABLE,
319 + GDMA_REG_CTRL0_TX_MASK << GDMA_REG_CTRL0_TX_SHIFT);
321 + gdma_dma_write_mask(dma_dev, GDMA_REG_CTRL1(chan->id), 0, GDMA_REG_CTRL1_MASK);
326 +static void gdma_dma_chan_irq(struct gdma_dmaengine_chan *chan)
328 + spin_lock(&chan->vchan.lock);
330 + if (chan->desc && chan->desc->cyclic) {
331 + vchan_cyclic_callback(&chan->desc->vdesc);
333 + if (chan->next_sg == chan->desc->num_sgs) {
335 + vchan_cookie_complete(&chan->desc->vdesc);
339 + gdma_dma_start_transfer(chan);
340 + spin_unlock(&chan->vchan.lock);
343 +static irqreturn_t gdma_dma_irq(int irq, void *devid)
345 + struct gdma_dma_dev *dma_dev = devid;
346 + uint32_t unmask, done;
349 + unmask = gdma_dma_read(dma_dev, GDMA_REG_UNMASK_INT);
350 + gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, unmask);
351 + done = gdma_dma_read(dma_dev, GDMA_REG_DONE_INT);
353 + for (i = 0; i < GDMA_NR_CHANS; ++i)
355 + gdma_dma_chan_irq(&dma_dev->chan[i]);
356 + gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, done);
358 + return IRQ_HANDLED;
361 +static void gdma_dma_issue_pending(struct dma_chan *c)
363 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
364 + unsigned long flags;
366 + spin_lock_irqsave(&chan->vchan.lock, flags);
367 + if (vchan_issue_pending(&chan->vchan) && !chan->desc)
368 + gdma_dma_start_transfer(chan);
369 + spin_unlock_irqrestore(&chan->vchan.lock, flags);
372 +static struct dma_async_tx_descriptor *gdma_dma_prep_slave_sg(
373 + struct dma_chan *c, struct scatterlist *sgl,
374 + unsigned int sg_len, enum dma_transfer_direction direction,
375 + unsigned long flags, void *context)
377 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
378 + struct gdma_dma_desc *desc;
379 + struct scatterlist *sg;
382 + desc = gdma_dma_alloc_desc(sg_len);
386 + for_each_sg(sgl, sg, sg_len, i) {
387 + desc->sg[i].addr = sg_dma_address(sg);
388 + desc->sg[i].len = sg_dma_len(sg);
391 + desc->num_sgs = sg_len;
392 + desc->direction = direction;
393 + desc->cyclic = false;
395 + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
398 +static struct dma_async_tx_descriptor *gdma_dma_prep_dma_cyclic(
399 + struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
400 + size_t period_len, enum dma_transfer_direction direction,
401 + unsigned long flags, void *context)
403 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
404 + struct gdma_dma_desc *desc;
405 + unsigned int num_periods, i;
407 + if (buf_len % period_len)
410 + num_periods = buf_len / period_len;
412 + desc = gdma_dma_alloc_desc(num_periods);
416 + for (i = 0; i < num_periods; i++) {
417 + desc->sg[i].addr = buf_addr;
418 + desc->sg[i].len = period_len;
419 + buf_addr += period_len;
422 + desc->num_sgs = num_periods;
423 + desc->direction = direction;
424 + desc->cyclic = true;
426 + return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
429 +static size_t gdma_dma_desc_residue(struct gdma_dmaengine_chan *chan,
430 + struct gdma_dma_desc *desc, unsigned int next_sg)
432 + struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
433 + unsigned int residue, count;
438 + for (i = next_sg; i < desc->num_sgs; i++)
439 + residue += desc->sg[i].len;
441 + if (next_sg != 0) {
442 + count = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
443 + count >>= GDMA_REG_CTRL0_CURR_SHIFT;
444 + count &= GDMA_REG_CTRL0_CURR_MASK;
445 + residue += count << chan->transfer_shift;
451 +static enum dma_status gdma_dma_tx_status(struct dma_chan *c,
452 + dma_cookie_t cookie, struct dma_tx_state *state)
454 + struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
455 + struct virt_dma_desc *vdesc;
456 + enum dma_status status;
457 + unsigned long flags;
459 + status = dma_cookie_status(c, cookie, state);
460 + if (status == DMA_SUCCESS || !state)
463 + spin_lock_irqsave(&chan->vchan.lock, flags);
464 + vdesc = vchan_find_desc(&chan->vchan, cookie);
465 + if (cookie == chan->desc->vdesc.tx.cookie) {
466 + state->residue = gdma_dma_desc_residue(chan, chan->desc,
468 + } else if (vdesc) {
469 + state->residue = gdma_dma_desc_residue(chan,
470 + to_gdma_dma_desc(vdesc), 0);
472 + state->residue = 0;
474 + spin_unlock_irqrestore(&chan->vchan.lock, flags);
479 +static int gdma_dma_alloc_chan_resources(struct dma_chan *c)
484 +static void gdma_dma_free_chan_resources(struct dma_chan *c)
486 + vchan_free_chan_resources(to_virt_chan(c));
489 +static void gdma_dma_desc_free(struct virt_dma_desc *vdesc)
491 + kfree(container_of(vdesc, struct gdma_dma_desc, vdesc));
494 +static struct dma_chan *
495 +of_dma_xlate_by_chan_id(struct of_phandle_args *dma_spec,
496 + struct of_dma *ofdma)
498 + struct gdma_dma_dev *dma_dev = ofdma->of_dma_data;
499 + unsigned int request = dma_spec->args[0];
501 + if (request >= GDMA_NR_CHANS)
504 + return dma_get_slave_channel(&(dma_dev->chan[request].vchan.chan));
507 +static int gdma_dma_probe(struct platform_device *pdev)
509 + struct gdma_dmaengine_chan *chan;
510 + struct gdma_dma_dev *dma_dev;
511 + struct dma_device *dd;
513 + struct resource *res;
519 + dma_dev = devm_kzalloc(&pdev->dev, sizeof(*dma_dev), GFP_KERNEL);
523 + dd = &dma_dev->ddev;
525 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
526 + dma_dev->base = devm_ioremap_resource(&pdev->dev, res);
527 + if (IS_ERR(dma_dev->base))
528 + return PTR_ERR(dma_dev->base);
530 + dma_cap_set(DMA_SLAVE, dd->cap_mask);
531 + dma_cap_set(DMA_CYCLIC, dd->cap_mask);
532 + dd->device_alloc_chan_resources = gdma_dma_alloc_chan_resources;
533 + dd->device_free_chan_resources = gdma_dma_free_chan_resources;
534 + dd->device_tx_status = gdma_dma_tx_status;
535 + dd->device_issue_pending = gdma_dma_issue_pending;
536 + dd->device_prep_slave_sg = gdma_dma_prep_slave_sg;
537 + dd->device_prep_dma_cyclic = gdma_dma_prep_dma_cyclic;
538 + dd->device_control = gdma_dma_control;
539 + dd->dev = &pdev->dev;
540 + dd->chancnt = GDMA_NR_CHANS;
541 + INIT_LIST_HEAD(&dd->channels);
543 + for (i = 0; i < dd->chancnt; i++) {
544 + chan = &dma_dev->chan[i];
546 + chan->vchan.desc_free = gdma_dma_desc_free;
547 + vchan_init(&chan->vchan, dd);
550 + ret = dma_async_device_register(dd);
554 + ret = of_dma_controller_register(pdev->dev.of_node,
555 + of_dma_xlate_by_chan_id, dma_dev);
557 + goto err_unregister;
559 + irq = platform_get_irq(pdev, 0);
560 + ret = request_irq(irq, gdma_dma_irq, 0, dev_name(&pdev->dev), dma_dev);
562 + goto err_unregister;
564 + gdma_dma_write(dma_dev, GDMA_REG_UNMASK_INT, 0);
565 + gdma_dma_write(dma_dev, GDMA_REG_DONE_INT, BIT(dd->chancnt) - 1);
567 + gct = gdma_dma_read(dma_dev, GDMA_REG_GCT);
568 + dev_info(&pdev->dev, "revision: %d, channels: %d\n",
569 + (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
570 + 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) & GDMA_REG_GCT_CHAN_MASK));
571 + platform_set_drvdata(pdev, dma_dev);
573 + gdma_dma_write(dma_dev, GDMA_REG_GCT, GDMA_REG_GCT_ARBIT_RR);
578 + dma_async_device_unregister(dd);
582 +static int gdma_dma_remove(struct platform_device *pdev)
584 + struct gdma_dma_dev *dma_dev = platform_get_drvdata(pdev);
585 + int irq = platform_get_irq(pdev, 0);
587 + free_irq(irq, dma_dev);
588 + of_dma_controller_free(pdev->dev.of_node);
589 + dma_async_device_unregister(&dma_dev->ddev);
594 +static const struct of_device_id gdma_of_match_table[] = {
595 + { .compatible = "ralink,rt2880-gdma" },
599 +static struct platform_driver gdma_dma_driver = {
600 + .probe = gdma_dma_probe,
601 + .remove = gdma_dma_remove,
603 + .name = "gdma-rt2880",
604 + .owner = THIS_MODULE,
605 + .of_match_table = gdma_of_match_table,
608 +module_platform_driver(gdma_dma_driver);
610 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
611 +MODULE_DESCRIPTION("GDMA4740 DMA driver");
612 +MODULE_LICENSE("GPLv2");
613 Index: linux-3.10.18/drivers/dma/dmaengine.c
614 ===================================================================
615 --- linux-3.10.18.orig/drivers/dma/dmaengine.c 2013-11-04 13:31:29.000000000 +0100
616 +++ linux-3.10.18/drivers/dma/dmaengine.c 2013-12-04 17:52:32.856756568 +0100
621 + * dma_request_slave_channel - try to get specific channel exclusively
622 + * @chan: target channel
624 +struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
628 + /* lock against __dma_request_channel */
629 + mutex_lock(&dma_list_mutex);
631 + if (chan->client_count == 0) {
632 + err = dma_chan_get(chan);
634 + pr_debug("%s: failed to get %s: (%d)\n",
635 + __func__, dma_chan_name(chan), err);
639 + mutex_unlock(&dma_list_mutex);
643 +EXPORT_SYMBOL_GPL(dma_get_slave_channel);
647 * dma_request_channel - try to allocate an exclusive channel
648 * @mask: capabilities that the channel must satisfy
649 * @fn: optional callback to disposition available channels
650 Index: linux-3.10.18/include/linux/dmaengine.h
651 ===================================================================
652 --- linux-3.10.18.orig/include/linux/dmaengine.h 2013-11-04 13:31:29.000000000 +0100
653 +++ linux-3.10.18/include/linux/dmaengine.h 2013-12-04 17:52:32.856756568 +0100
655 int dma_async_device_register(struct dma_device *device);
656 void dma_async_device_unregister(struct dma_device *device);
657 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
658 +struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
659 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
660 struct dma_chan *net_dma_find_channel(void);
661 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
662 Index: linux-3.10.18/drivers/dma/Makefile
663 ===================================================================
664 --- linux-3.10.18.orig/drivers/dma/Makefile 2013-11-04 13:31:29.000000000 +0100
665 +++ linux-3.10.18/drivers/dma/Makefile 2013-12-04 17:52:32.856756568 +0100
667 obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
668 obj-$(CONFIG_DMA_OMAP) += omap-dma.o
669 obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
670 +obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o