1 From 4596818bca07e0928168970839e08875cf51b4cc Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 29 Apr 2013 14:40:43 +0200
4 Subject: [PATCH 26/33] i2c: MIPS: adds ralink I2C driver
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++
9 drivers/i2c/busses/Kconfig | 4 +
10 drivers/i2c/busses/Makefile | 1 +
11 drivers/i2c/busses/i2c-ralink.c | 274 ++++++++++++++++++++
12 4 files changed, 306 insertions(+)
13 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
14 create mode 100644 drivers/i2c/busses/i2c-ralink.c
17 +++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
19 +I2C for Ralink platforms
21 +Required properties :
22 +- compatible : Must be "link,rt3052-i2c"
23 +- reg: physical base address of the controller and length of memory mapped
25 +- #address-cells = <1>;
29 +- Child nodes conforming to i2c bus binding
35 + compatible = "link,rt3052-i2c";
36 + reg = <0x900 0x100>;
37 + #address-cells = <1>;
41 + compatible = "national,lm92";
46 --- a/drivers/i2c/busses/Kconfig
47 +++ b/drivers/i2c/busses/Kconfig
48 @@ -628,6 +628,10 @@ config I2C_PXA_SLAVE
49 is necessary for systems where the PXA may be a target on the
53 + tristate "Ralink I2C Controller"
56 config HAVE_S3C2410_I2C
59 --- a/drivers/i2c/busses/Makefile
60 +++ b/drivers/i2c/busses/Makefile
61 @@ -62,6 +62,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
62 obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
63 obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
64 obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
65 +obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
66 obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o
67 obj-$(CONFIG_I2C_S6000) += i2c-s6000.o
68 obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
70 +++ b/drivers/i2c/busses/i2c-ralink.c
73 + * drivers/i2c/busses/i2c-ralink.c
75 + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
77 + * This software is licensed under the terms of the GNU General Public
78 + * License version 2, as published by the Free Software Foundation, and
79 + * may be copied, distributed, and modified under those terms.
81 + * This program is distributed in the hope that it will be useful,
82 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
83 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
84 + * GNU General Public License for more details.
88 +#include <linux/interrupt.h>
89 +#include <linux/kernel.h>
90 +#include <linux/module.h>
91 +#include <linux/reset.h>
92 +#include <linux/delay.h>
93 +#include <linux/slab.h>
94 +#include <linux/init.h>
95 +#include <linux/errno.h>
96 +#include <linux/platform_device.h>
97 +#include <linux/i2c.h>
98 +#include <linux/io.h>
99 +#include <linux/of_i2c.h>
100 +#include <linux/err.h>
102 +#include <asm/mach-ralink/ralink_regs.h>
104 +#define REG_CONFIG_REG 0x00
105 +#define REG_CLKDIV_REG 0x04
106 +#define REG_DEVADDR_REG 0x08
107 +#define REG_ADDR_REG 0x0C
108 +#define REG_DATAOUT_REG 0x10
109 +#define REG_DATAIN_REG 0x14
110 +#define REG_STATUS_REG 0x18
111 +#define REG_STARTXFR_REG 0x1C
112 +#define REG_BYTECNT_REG 0x20
114 +#define I2C_STARTERR BIT(4)
115 +#define I2C_ACKERR BIT(3)
116 +#define I2C_DATARDY BIT(2)
117 +#define I2C_SDOEMPTY BIT(1)
118 +#define I2C_BUSY BIT(0)
120 +#define I2C_DEVADLEN_7 (6 << 2)
121 +#define I2C_ADDRDIS BIT(1)
123 +#define I2C_RETRY 0x400
125 +#define CLKDIV_VALUE 200 // clock rate is 40M, 40M / (200*2) = 100k (standard i2c bus rate).
126 +//#define CLKDIV_VALUE 50 // clock rate is 40M, 40M / (50*2) = 400k (fast i2c bus rate).
128 +#define READ_CMD 0x01
129 +#define WRITE_CMD 0x00
130 +#define READ_BLOCK 64
132 +static void __iomem *membase;
133 +static struct i2c_adapter *adapter;
135 +static void rt_i2c_w32(u32 val, unsigned reg)
137 + iowrite32(val, membase + reg);
140 +static u32 rt_i2c_r32(unsigned reg)
142 + return ioread32(membase + reg);
145 +static inline int rt_i2c_wait_rx_done(void)
147 + int retries = I2C_RETRY;
152 + } while(!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY));
154 + return (retries < 0);
157 +static inline int rt_i2c_wait_idle(void)
159 + int retries = I2C_RETRY;
164 + } while(rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY);
166 + return (retries < 0);
169 +static inline int rt_i2c_wait_tx_done(void)
171 + int retries = I2C_RETRY;
176 + } while(!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY));
178 + return (retries < 0);
181 +static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
183 + int i = 0, j = 0, pos = 0;
184 + int nblock = msg->len / READ_BLOCK;
185 + int rem = msg->len % READ_BLOCK;
187 + if (msg->flags & I2C_M_TEN) {
188 + printk("10 bits addr not supported\n");
192 + if (msg->flags & I2C_M_RD) {
193 + for (i = 0; i < nblock; i++) {
194 + rt_i2c_wait_idle();
195 + rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
196 + rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
197 + for (j = 0; j < READ_BLOCK; j++) {
198 + if (rt_i2c_wait_rx_done())
200 + msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
204 + rt_i2c_wait_idle();
205 + rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
206 + rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
207 + for (i = 0; i < rem; i++) {
208 + if (rt_i2c_wait_rx_done())
210 + msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
213 + rt_i2c_wait_idle();
214 + rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
215 + for (i = 0; i < msg->len; i++) {
216 + rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
217 + rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
218 + if (rt_i2c_wait_tx_done())
226 +static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
231 + if (rt_i2c_wait_idle()) {
232 + printk("i2c transfer failed\n");
236 + device_reset(a->dev.parent);
238 + rt_i2c_w32(m->addr, REG_DEVADDR_REG);
239 + rt_i2c_w32(I2C_DEVADLEN_7 | I2C_ADDRDIS, REG_CONFIG_REG);
240 + rt_i2c_w32(CLKDIV_VALUE, REG_CLKDIV_REG);
242 + for (i = 0; i < n && !ret; i++)
243 + ret = rt_i2c_handle_msg(a, &m[i]);
246 + printk("i2c transfer failed\n");
253 +static u32 rt_i2c_func(struct i2c_adapter *a)
255 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
258 +static const struct i2c_algorithm rt_i2c_algo = {
259 + .master_xfer = rt_i2c_master_xfer,
260 + .functionality = rt_i2c_func,
263 +static int rt_i2c_probe(struct platform_device *pdev)
265 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
269 + dev_err(&pdev->dev, "no memory resource found\n");
273 + adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter), GFP_KERNEL);
275 + dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
279 + membase = devm_request_and_ioremap(&pdev->dev, res);
280 + if (IS_ERR(membase))
281 + return PTR_ERR(membase);
283 + strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
284 + adapter->owner = THIS_MODULE;
285 + adapter->nr = pdev->id;
286 + adapter->timeout = HZ;
287 + adapter->algo = &rt_i2c_algo;
288 + adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
289 + adapter->dev.parent = &pdev->dev;
290 + adapter->dev.of_node = pdev->dev.of_node;
292 + ret = i2c_add_numbered_adapter(adapter);
296 + of_i2c_register_devices(adapter);
298 + platform_set_drvdata(pdev, adapter);
300 + dev_info(&pdev->dev, "loaded\n");
305 +static int rt_i2c_remove(struct platform_device *pdev)
307 + platform_set_drvdata(pdev, NULL);
312 +static const struct of_device_id i2c_rt_dt_ids[] = {
313 + { .compatible = "ralink,rt2880-i2c", },
317 +MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
319 +static struct platform_driver rt_i2c_driver = {
320 + .probe = rt_i2c_probe,
321 + .remove = rt_i2c_remove,
323 + .owner = THIS_MODULE,
324 + .name = "i2c-ralink",
325 + .of_match_table = i2c_rt_dt_ids,
329 +static int __init i2c_rt_init (void)
331 + return platform_driver_register(&rt_i2c_driver);
333 +subsys_initcall(i2c_rt_init);
335 +static void __exit i2c_rt_exit (void)
337 + platform_driver_unregister(&rt_i2c_driver);
340 +module_exit (i2c_rt_exit);
342 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
343 +MODULE_DESCRIPTION("Ralink I2c host driver");
344 +MODULE_LICENSE("GPL");
345 +MODULE_ALIAS("platform:Ralink-I2C");