target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.c

   1 #include "xhci-mtk.h"
   2 #include "xhci-mtk-power.h"
   3 #include "xhci.h"
   4 #include <linux/kernel.h>       /* printk() */
   5 #include <linux/slab.h>
   6 #include <linux/delay.h>
   7
   8 static int g_num_u3_port;
   9 static int g_num_u2_port;
  10
  11
  12 void enableXhciAllPortPower(struct xhci_hcd *xhci){
  13         int i;
  14         u32 port_id, temp;
  15         u32 __iomem *addr;
  16
  17         g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
  18         g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
  19
  20         for(i=1; i<=g_num_u3_port; i++){
  21                 port_id=i;
  22                 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
  23                 temp = xhci_readl(xhci, addr);
  24                 temp = xhci_port_state_to_neutral(temp);
  25                 temp |= PORT_POWER;
  26                 xhci_writel(xhci, temp, addr);
  27         }
  28         for(i=1; i<=g_num_u2_port; i++){
  29                 port_id=i+g_num_u3_port;
  30                 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
  31                 temp = xhci_readl(xhci, addr);
  32                 temp = xhci_port_state_to_neutral(temp);
  33                 temp |= PORT_POWER;
  34                 xhci_writel(xhci, temp, addr);
  35         }
  36 }
  37
  38 void enableAllClockPower(){
  39
  40         int i;
  41         u32 temp;
  42
  43         g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
  44         g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
  45
  46         //2.    Enable xHC
  47         writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
  48         writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
  49         writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
  50
  51         //1.    Enable target ports
  52         for(i=0; i<g_num_u3_port; i++){
  53                 temp = readl(SSUSB_U3_CTRL(i));
  54                 temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
  55                 writel(temp, SSUSB_U3_CTRL(i));
  56         }
  57         for(i=0; i<g_num_u2_port; i++){
  58                 temp = readl(SSUSB_U2_CTRL(i));
  59                 temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
  60                 writel(temp, SSUSB_U2_CTRL(i));
  61         }
  62         msleep(100);
  63 }
  64
  65
  66 //(X)disable clock/power of a port
  67 //(X)if all ports are disabled, disable IP ctrl power
  68 //disable all ports and IP clock/power, this is just mention HW that the power/clock of port
  69 //and IP could be disable if suspended.
  70 //If doesn't not disable all ports at first, the IP clock/power will never be disabled
  71 //(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
  72 //port_index: port number
  73 //port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
  74 void disablePortClockPower(void){
  75         int i;
  76         u32 temp;
  77
  78         g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
  79         g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
  80
  81         for(i=0; i<g_num_u3_port; i++){
  82                 temp = readl(SSUSB_U3_CTRL(i));
  83                 temp = temp | (SSUSB_U3_PORT_PDN);
  84                 writel(temp, SSUSB_U3_CTRL(i));
  85         }
  86         for(i=0; i<g_num_u2_port; i++){
  87                 temp = readl(SSUSB_U2_CTRL(i));
  88                 temp = temp | (SSUSB_U2_PORT_PDN);
  89                 writel(temp, SSUSB_U2_CTRL(i));
  90         }
  91         writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
  92 }
  93
  94 //if IP ctrl power is disabled, enable it
  95 //enable clock/power of a port
  96 //port_index: port number
  97 //port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
  98 void enablePortClockPower(int port_index, int port_rev){
  99         int i;
 100         u32 temp;
 101
 102         writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
 103
 104         if(port_rev == 0x3){
 105                 temp = readl(SSUSB_U3_CTRL(port_index));
 106                 temp = temp & (~SSUSB_U3_PORT_PDN);
 107                 writel(temp, SSUSB_U3_CTRL(port_index));
 108         }
 109         else if(port_rev == 0x2){
 110                 temp = readl(SSUSB_U2_CTRL(port_index));
 111                 temp = temp & (~SSUSB_U2_PORT_PDN);
 112                 writel(temp, SSUSB_U2_CTRL(port_index));
 113         }
 114 }
 115