target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.h

   1 #ifdef CONFIG_PROJECT_7621
   2 #ifndef __MTK_PHY_7621_H
   3 #define __MTK_PHY_7621_H
   4
   5 #define U2_SR_COEF_7621 28
   6
   7 ///////////////////////////////////////////////////////////////////////////////
   8
   9 struct u2phy_reg {
  10         //0x0
  11         PHY_LE32 u2phyac0;
  12         PHY_LE32 u2phyac1;
  13         PHY_LE32 u2phyac2;
  14         PHY_LE32 reserve0;
  15         //0x10
  16         PHY_LE32 u2phyacr0;
  17         PHY_LE32 u2phyacr1;
  18         PHY_LE32 u2phyacr2;
  19         PHY_LE32 u2phyacr3;
  20         //0x20
  21         PHY_LE32 u2phyacr4;
  22         PHY_LE32 u2phyamon0;
  23         PHY_LE32 reserve1[2];
  24         //0x30~0x50
  25         PHY_LE32 reserve2[12];
  26         //0x60
  27         PHY_LE32 u2phydcr0;
  28         PHY_LE32 u2phydcr1;
  29         PHY_LE32 u2phydtm0;
  30         PHY_LE32 u2phydtm1;
  31         //0x70
  32         PHY_LE32 u2phydmon0;
  33         PHY_LE32 u2phydmon1;
  34         PHY_LE32 u2phydmon2;
  35         PHY_LE32 u2phydmon3;
  36         //0x80
  37         PHY_LE32 u2phybc12c;
  38         PHY_LE32 u2phybc12c1;
  39         PHY_LE32 reserve3[2];
  40         //0x90~0xe0
  41         PHY_LE32 reserve4[24];
  42         //0xf0
  43         PHY_LE32 reserve6[3];
  44         PHY_LE32 regfcom;
  45 };
  46
  47 //U3D_U2PHYAC0
  48 #define RG_USB20_USBPLL_DIVEN                     (0x7<<28) //30:28
  49 #define RG_USB20_USBPLL_CKCTRL                    (0x3<<26) //27:26
  50 #define RG_USB20_USBPLL_PREDIV                    (0x3<<24) //25:24
  51 #define RG_USB20_USBPLL_FORCE_ON                  (0x1<<23) //23:23
  52 #define RG_USB20_USBPLL_FBDIV                     (0x7f<<16) //22:16
  53 #define RG_USB20_REF_EN                           (0x1<<15) //15:15
  54 #define RG_USB20_INTR_EN                          (0x1<<14) //14:14
  55 #define RG_USB20_BG_TRIM                          (0xf<<8) //11:8
  56 #define RG_USB20_BG_RBSEL                         (0x3<<6) //7:6
  57 #define RG_USB20_BG_RASEL                         (0x3<<4) //5:4
  58 #define RG_USB20_BGR_DIV                          (0x3<<2) //3:2
  59 #define RG_SIFSLV_CHP_EN                          (0x1<<1) //1:1
  60 #define RG_SIFSLV_BGR_EN                          (0x1<<0) //0:0
  61
  62 //U3D_U2PHYAC1
  63 #define RG_USB20_VRT_VREF_SEL                     (0x7<<28) //30:28
  64 #define RG_USB20_TERM_VREF_SEL                    (0x7<<24) //26:24
  65 #define RG_USB20_MPX_SEL                          (0xff<<16) //23:16
  66 #define RG_USB20_MPX_OUT_SEL                      (0x3<<12) //13:12
  67 #define RG_USB20_TX_PH_ROT_SEL                    (0x7<<8) //10:8
  68 #define RG_USB20_USBPLL_ACCEN                     (0x1<<3) //3:3
  69 #define RG_USB20_USBPLL_LF                        (0x1<<2) //2:2
  70 #define RG_USB20_USBPLL_BR                        (0x1<<1) //1:1
  71 #define RG_USB20_USBPLL_BP                        (0x1<<0) //0:0
  72
  73 //U3D_U2PHYAC2
  74 #define RG_SIFSLV_MAC_BANDGAP_EN                  (0x1<<17) //17:17
  75 #define RG_SIFSLV_MAC_CHOPPER_EN                  (0x1<<16) //16:16
  76 #define RG_USB20_CLKREF_REV                       (0xff<<0) //7:0
  77
  78 //U3D_U2PHYACR0
  79 #define RG_USB20_ICUSB_EN                         (0x1<<24) //24:24
  80 #define RG_USB20_HSTX_SRCAL_EN                    (0x1<<23) //23:23
  81 #define RG_USB20_HSTX_SRCTRL                      (0x7<<16) //18:16
  82 #define RG_USB20_LS_CR                            (0x7<<12) //14:12
  83 #define RG_USB20_FS_CR                            (0x7<<8) //10:8
  84 #define RG_USB20_LS_SR                            (0x7<<4) //6:4
  85 #define RG_USB20_FS_SR                            (0x7<<0) //2:0
  86
  87 //U3D_U2PHYACR1
  88 #define RG_USB20_INIT_SQ_EN_DG                    (0x3<<28) //29:28
  89 #define RG_USB20_SQD                              (0x3<<24) //25:24
  90 #define RG_USB20_HSTX_TMODE_SEL                   (0x3<<20) //21:20
  91 #define RG_USB20_HSTX_TMODE_EN                    (0x1<<19) //19:19
  92 #define RG_USB20_PHYD_MONEN                       (0x1<<18) //18:18
  93 #define RG_USB20_INLPBK_EN                        (0x1<<17) //17:17
  94 #define RG_USB20_CHIRP_EN                         (0x1<<16) //16:16
  95 #define RG_USB20_DM_ABIST_SOURCE_EN               (0x1<<15) //15:15
  96 #define RG_USB20_DM_ABIST_SELE                    (0xf<<8) //11:8
  97 #define RG_USB20_DP_ABIST_SOURCE_EN               (0x1<<7) //7:7
  98 #define RG_USB20_DP_ABIST_SELE                    (0xf<<0) //3:0
  99
 100 //U3D_U2PHYACR2
 101 #define RG_USB20_OTG_ABIST_SELE                   (0x7<<29) //31:29
 102 #define RG_USB20_OTG_ABIST_EN                     (0x1<<28) //28:28
 103 #define RG_USB20_OTG_VBUSCMP_EN                   (0x1<<27) //27:27
 104 #define RG_USB20_OTG_VBUSTH                       (0x7<<24) //26:24
 105 #define RG_USB20_DISC_FIT_EN                      (0x1<<22) //22:22
 106 #define RG_USB20_DISCD                            (0x3<<20) //21:20
 107 #define RG_USB20_DISCTH                           (0xf<<16) //19:16
 108 #define RG_USB20_SQCAL_EN                         (0x1<<15) //15:15
 109 #define RG_USB20_SQCAL                            (0xf<<8) //11:8
 110 #define RG_USB20_SQTH                             (0xf<<0) //3:0
 111
 112 //U3D_U2PHYACR3
 113 #define RG_USB20_HSTX_DBIST                       (0xf<<28) //31:28
 114 #define RG_USB20_HSTX_BIST_EN                     (0x1<<26) //26:26
 115 #define RG_USB20_HSTX_I_EN_MODE                   (0x3<<24) //25:24
 116 #define RG_USB20_HSRX_TMODE_EN                    (0x1<<23) //23:23
 117 #define RG_USB20_HSRX_BIAS_EN_SEL                 (0x3<<20) //21:20
 118 #define RG_USB20_USB11_TMODE_EN                   (0x1<<19) //19:19
 119 #define RG_USB20_TMODE_FS_LS_TX_EN                (0x1<<18) //18:18
 120 #define RG_USB20_TMODE_FS_LS_RCV_EN               (0x1<<17) //17:17
 121 #define RG_USB20_TMODE_FS_LS_MODE                 (0x1<<16) //16:16
 122 #define RG_USB20_HS_TERM_EN_MODE                  (0x3<<13) //14:13
 123 #define RG_USB20_PUPD_BIST_EN                     (0x1<<12) //12:12
 124 #define RG_USB20_EN_PU_DM                         (0x1<<11) //11:11
 125 #define RG_USB20_EN_PD_DM                         (0x1<<10) //10:10
 126 #define RG_USB20_EN_PU_DP                         (0x1<<9) //9:9
 127 #define RG_USB20_EN_PD_DP                         (0x1<<8) //8:8
 128 #define RG_USB20_PHY_REV                          (0xff<<0) //7:0
 129
 130 //U3D_U2PHYACR4
 131 #define RG_USB20_DP_100K_MODE                     (0x1<<18) //18:18
 132 #define RG_USB20_DM_100K_EN                       (0x1<<17) //17:17
 133 #define USB20_DP_100K_EN                          (0x1<<16) //16:16
 134 #define USB20_GPIO_DM_I                           (0x1<<15) //15:15
 135 #define USB20_GPIO_DP_I                           (0x1<<14) //14:14
 136 #define USB20_GPIO_DM_OE                          (0x1<<13) //13:13
 137 #define USB20_GPIO_DP_OE                          (0x1<<12) //12:12
 138 #define RG_USB20_GPIO_CTL                         (0x1<<9) //9:9
 139 #define USB20_GPIO_MODE                           (0x1<<8) //8:8
 140 #define RG_USB20_TX_BIAS_EN                       (0x1<<5) //5:5
 141 #define RG_USB20_TX_VCMPDN_EN                     (0x1<<4) //4:4
 142 #define RG_USB20_HS_SQ_EN_MODE                    (0x3<<2) //3:2
 143 #define RG_USB20_HS_RCV_EN_MODE                   (0x3<<0) //1:0
 144
 145 //U3D_U2PHYAMON0
 146 #define RGO_USB20_GPIO_DM_O                       (0x1<<1) //1:1
 147 #define RGO_USB20_GPIO_DP_O                       (0x1<<0) //0:0
 148
 149 //U3D_U2PHYDCR0
 150 #define RG_USB20_CDR_TST                          (0x3<<30) //31:30
 151 #define RG_USB20_GATED_ENB                        (0x1<<29) //29:29
 152 #define RG_USB20_TESTMODE                         (0x3<<26) //27:26
 153 #define RG_USB20_PLL_STABLE                       (0x1<<25) //25:25
 154 #define RG_USB20_PLL_FORCE_ON                     (0x1<<24) //24:24
 155 #define RG_USB20_PHYD_RESERVE                     (0xffff<<8) //23:8
 156 #define RG_USB20_EBTHRLD                          (0x1<<7) //7:7
 157 #define RG_USB20_EARLY_HSTX_I                     (0x1<<6) //6:6
 158 #define RG_USB20_TX_TST                           (0x1<<5) //5:5
 159 #define RG_USB20_NEGEDGE_ENB                      (0x1<<4) //4:4
 160 #define RG_USB20_CDR_FILT                         (0xf<<0) //3:0
 161
 162 //U3D_U2PHYDCR1
 163 #define RG_USB20_PROBE_SEL                        (0xff<<24) //31:24
 164 #define RG_USB20_DRVVBUS                          (0x1<<23) //23:23
 165 #define RG_DEBUG_EN                               (0x1<<22) //22:22
 166 #define RG_USB20_OTG_PROBE                        (0x3<<20) //21:20
 167 #define RG_USB20_SW_PLLMODE                       (0x3<<18) //19:18
 168 #define RG_USB20_BERTH                            (0x3<<16) //17:16
 169 #define RG_USB20_LBMODE                           (0x3<<13) //14:13
 170 #define RG_USB20_FORCE_TAP                        (0x1<<12) //12:12
 171 #define RG_USB20_TAPSEL                           (0xfff<<0) //11:0
 172
 173 //U3D_U2PHYDTM0
 174 #define RG_UART_MODE                              (0x3<<30) //31:30
 175 #define FORCE_UART_I                              (0x1<<29) //29:29
 176 #define FORCE_UART_BIAS_EN                        (0x1<<28) //28:28
 177 #define FORCE_UART_TX_OE                          (0x1<<27) //27:27
 178 #define FORCE_UART_EN                             (0x1<<26) //26:26
 179 #define FORCE_USB_CLKEN                           (0x1<<25) //25:25
 180 #define FORCE_DRVVBUS                             (0x1<<24) //24:24
 181 #define FORCE_DATAIN                              (0x1<<23) //23:23
 182 #define FORCE_TXVALID                             (0x1<<22) //22:22
 183 #define FORCE_DM_PULLDOWN                         (0x1<<21) //21:21
 184 #define FORCE_DP_PULLDOWN                         (0x1<<20) //20:20
 185 #define FORCE_XCVRSEL                             (0x1<<19) //19:19
 186 #define FORCE_SUSPENDM                            (0x1<<18) //18:18
 187 #define FORCE_TERMSEL                             (0x1<<17) //17:17
 188 #define FORCE_OPMODE                              (0x1<<16) //16:16
 189 #define UTMI_MUXSEL                               (0x1<<15) //15:15
 190 #define RG_RESET                                  (0x1<<14) //14:14
 191 #define RG_DATAIN                                 (0xf<<10) //13:10
 192 #define RG_TXVALIDH                               (0x1<<9) //9:9
 193 #define RG_TXVALID                                (0x1<<8) //8:8
 194 #define RG_DMPULLDOWN                             (0x1<<7) //7:7
 195 #define RG_DPPULLDOWN                             (0x1<<6) //6:6
 196 #define RG_XCVRSEL                                (0x3<<4) //5:4
 197 #define RG_SUSPENDM                               (0x1<<3) //3:3
 198 #define RG_TERMSEL                                (0x1<<2) //2:2
 199 #define RG_OPMODE                                 (0x3<<0) //1:0
 200
 201 //U3D_U2PHYDTM1
 202 #define RG_USB20_PRBS7_EN                         (0x1<<31) //31:31
 203 #define RG_USB20_PRBS7_BITCNT                     (0x3f<<24) //29:24
 204 #define RG_USB20_CLK48M_EN                        (0x1<<23) //23:23
 205 #define RG_USB20_CLK60M_EN                        (0x1<<22) //22:22
 206 #define RG_UART_I                                 (0x1<<19) //19:19
 207 #define RG_UART_BIAS_EN                           (0x1<<18) //18:18
 208 #define RG_UART_TX_OE                             (0x1<<17) //17:17
 209 #define RG_UART_EN                                (0x1<<16) //16:16
 210 #define FORCE_VBUSVALID                           (0x1<<13) //13:13
 211 #define FORCE_SESSEND                             (0x1<<12) //12:12
 212 #define FORCE_BVALID                              (0x1<<11) //11:11
 213 #define FORCE_AVALID                              (0x1<<10) //10:10
 214 #define FORCE_IDDIG                               (0x1<<9) //9:9
 215 #define FORCE_IDPULLUP                            (0x1<<8) //8:8
 216 #define RG_VBUSVALID                              (0x1<<5) //5:5
 217 #define RG_SESSEND                                (0x1<<4) //4:4
 218 #define RG_BVALID                                 (0x1<<3) //3:3
 219 #define RG_AVALID                                 (0x1<<2) //2:2
 220 #define RG_IDDIG                                  (0x1<<1) //1:1
 221 #define RG_IDPULLUP                               (0x1<<0) //0:0
 222
 223 //U3D_U2PHYDMON0
 224 #define RG_USB20_PRBS7_BERTH                      (0xff<<0) //7:0
 225
 226 //U3D_U2PHYDMON1
 227 #define USB20_UART_O                              (0x1<<31) //31:31
 228 #define RGO_USB20_LB_PASS                         (0x1<<30) //30:30
 229 #define RGO_USB20_LB_DONE                         (0x1<<29) //29:29
 230 #define AD_USB20_BVALID                           (0x1<<28) //28:28
 231 #define USB20_IDDIG                               (0x1<<27) //27:27
 232 #define AD_USB20_VBUSVALID                        (0x1<<26) //26:26
 233 #define AD_USB20_SESSEND                          (0x1<<25) //25:25
 234 #define AD_USB20_AVALID                           (0x1<<24) //24:24
 235 #define USB20_LINE_STATE                          (0x3<<22) //23:22
 236 #define USB20_HST_DISCON                          (0x1<<21) //21:21
 237 #define USB20_TX_READY                            (0x1<<20) //20:20
 238 #define USB20_RX_ERROR                            (0x1<<19) //19:19
 239 #define USB20_RX_ACTIVE                           (0x1<<18) //18:18
 240 #define USB20_RX_VALIDH                           (0x1<<17) //17:17
 241 #define USB20_RX_VALID                            (0x1<<16) //16:16
 242 #define USB20_DATA_OUT                            (0xffff<<0) //15:0
 243
 244 //U3D_U2PHYDMON2
 245 #define RGO_TXVALID_CNT                           (0xff<<24) //31:24
 246 #define RGO_RXACTIVE_CNT                          (0xff<<16) //23:16
 247 #define RGO_USB20_LB_BERCNT                       (0xff<<8) //15:8
 248 #define USB20_PROBE_OUT                           (0xff<<0) //7:0
 249
 250 //U3D_U2PHYDMON3
 251 #define RGO_USB20_PRBS7_ERRCNT                    (0xffff<<16) //31:16
 252 #define RGO_USB20_PRBS7_DONE                      (0x1<<3) //3:3
 253 #define RGO_USB20_PRBS7_LOCK                      (0x1<<2) //2:2
 254 #define RGO_USB20_PRBS7_PASS                      (0x1<<1) //1:1
 255 #define RGO_USB20_PRBS7_PASSTH                    (0x1<<0) //0:0
 256
 257 //U3D_U2PHYBC12C
 258 #define RG_SIFSLV_CHGDT_DEGLCH_CNT                (0xf<<28) //31:28
 259 #define RG_SIFSLV_CHGDT_CTRL_CNT                  (0xf<<24) //27:24
 260 #define RG_SIFSLV_CHGDT_FORCE_MODE                (0x1<<16) //16:16
 261 #define RG_CHGDT_ISRC_LEV                         (0x3<<14) //15:14
 262 #define RG_CHGDT_VDATSRC                          (0x1<<13) //13:13
 263 #define RG_CHGDT_BGVREF_SEL                       (0x7<<10) //12:10
 264 #define RG_CHGDT_RDVREF_SEL                       (0x3<<8) //9:8
 265 #define RG_CHGDT_ISRC_DP                          (0x1<<7) //7:7
 266 #define RG_SIFSLV_CHGDT_OPOUT_DM                  (0x1<<6) //6:6
 267 #define RG_CHGDT_VDAT_DM                          (0x1<<5) //5:5
 268 #define RG_CHGDT_OPOUT_DP                         (0x1<<4) //4:4
 269 #define RG_SIFSLV_CHGDT_VDAT_DP                   (0x1<<3) //3:3
 270 #define RG_SIFSLV_CHGDT_COMP_EN                   (0x1<<2) //2:2
 271 #define RG_SIFSLV_CHGDT_OPDRV_EN                  (0x1<<1) //1:1
 272 #define RG_CHGDT_EN                               (0x1<<0) //0:0
 273
 274 //U3D_U2PHYBC12C1
 275 #define RG_CHGDT_REV                              (0xff<<0) //7:0
 276
 277 //U3D_REGFCOM
 278 #define RG_PAGE                                   (0xff<<24) //31:24
 279 #define I2C_MODE                                  (0x1<<16) //16:16
 280
 281
 282 /* OFFSET  */
 283
 284 //U3D_U2PHYAC0
 285 #define RG_USB20_USBPLL_DIVEN_OFST                (28)
 286 #define RG_USB20_USBPLL_CKCTRL_OFST               (26)
 287 #define RG_USB20_USBPLL_PREDIV_OFST               (24)
 288 #define RG_USB20_USBPLL_FORCE_ON_OFST             (23)
 289 #define RG_USB20_USBPLL_FBDIV_OFST                (16)
 290 #define RG_USB20_REF_EN_OFST                      (15)
 291 #define RG_USB20_INTR_EN_OFST                     (14)
 292 #define RG_USB20_BG_TRIM_OFST                     (8)
 293 #define RG_USB20_BG_RBSEL_OFST                    (6)
 294 #define RG_USB20_BG_RASEL_OFST                    (4)
 295 #define RG_USB20_BGR_DIV_OFST                     (2)
 296 #define RG_SIFSLV_CHP_EN_OFST                     (1)
 297 #define RG_SIFSLV_BGR_EN_OFST                     (0)
 298
 299 //U3D_U2PHYAC1
 300 #define RG_USB20_VRT_VREF_SEL_OFST                (28)
 301 #define RG_USB20_TERM_VREF_SEL_OFST               (24)
 302 #define RG_USB20_MPX_SEL_OFST                     (16)
 303 #define RG_USB20_MPX_OUT_SEL_OFST                 (12)
 304 #define RG_USB20_TX_PH_ROT_SEL_OFST               (8)
 305 #define RG_USB20_USBPLL_ACCEN_OFST                (3)
 306 #define RG_USB20_USBPLL_LF_OFST                   (2)
 307 #define RG_USB20_USBPLL_BR_OFST                   (1)
 308 #define RG_USB20_USBPLL_BP_OFST                   (0)
 309
 310 //U3D_U2PHYAC2
 311 #define RG_SIFSLV_MAC_BANDGAP_EN_OFST             (17)
 312 #define RG_SIFSLV_MAC_CHOPPER_EN_OFST             (16)
 313 #define RG_USB20_CLKREF_REV_OFST                  (0)
 314
 315 //U3D_U2PHYACR0
 316 #define RG_USB20_ICUSB_EN_OFST                    (24)
 317 #define RG_USB20_HSTX_SRCAL_EN_OFST               (23)
 318 #define RG_USB20_HSTX_SRCTRL_OFST                 (16)
 319 #define RG_USB20_LS_CR_OFST                       (12)
 320 #define RG_USB20_FS_CR_OFST                       (8)
 321 #define RG_USB20_LS_SR_OFST                       (4)
 322 #define RG_USB20_FS_SR_OFST                       (0)
 323
 324 //U3D_U2PHYACR1
 325 #define RG_USB20_INIT_SQ_EN_DG_OFST               (28)
 326 #define RG_USB20_SQD_OFST                         (24)
 327 #define RG_USB20_HSTX_TMODE_SEL_OFST              (20)
 328 #define RG_USB20_HSTX_TMODE_EN_OFST               (19)
 329 #define RG_USB20_PHYD_MONEN_OFST                  (18)
 330 #define RG_USB20_INLPBK_EN_OFST                   (17)
 331 #define RG_USB20_CHIRP_EN_OFST                    (16)
 332 #define RG_USB20_DM_ABIST_SOURCE_EN_OFST          (15)
 333 #define RG_USB20_DM_ABIST_SELE_OFST               (8)
 334 #define RG_USB20_DP_ABIST_SOURCE_EN_OFST          (7)
 335 #define RG_USB20_DP_ABIST_SELE_OFST               (0)
 336
 337 //U3D_U2PHYACR2
 338 #define RG_USB20_OTG_ABIST_SELE_OFST              (29)
 339 #define RG_USB20_OTG_ABIST_EN_OFST                (28)
 340 #define RG_USB20_OTG_VBUSCMP_EN_OFST              (27)
 341 #define RG_USB20_OTG_VBUSTH_OFST                  (24)
 342 #define RG_USB20_DISC_FIT_EN_OFST                 (22)
 343 #define RG_USB20_DISCD_OFST                       (20)
 344 #define RG_USB20_DISCTH_OFST                      (16)
 345 #define RG_USB20_SQCAL_EN_OFST                    (15)
 346 #define RG_USB20_SQCAL_OFST                       (8)
 347 #define RG_USB20_SQTH_OFST                        (0)
 348
 349 //U3D_U2PHYACR3
 350 #define RG_USB20_HSTX_DBIST_OFST                  (28)
 351 #define RG_USB20_HSTX_BIST_EN_OFST                (26)
 352 #define RG_USB20_HSTX_I_EN_MODE_OFST              (24)
 353 #define RG_USB20_HSRX_TMODE_EN_OFST               (23)
 354 #define RG_USB20_HSRX_BIAS_EN_SEL_OFST            (20)
 355 #define RG_USB20_USB11_TMODE_EN_OFST              (19)
 356 #define RG_USB20_TMODE_FS_LS_TX_EN_OFST           (18)
 357 #define RG_USB20_TMODE_FS_LS_RCV_EN_OFST          (17)
 358 #define RG_USB20_TMODE_FS_LS_MODE_OFST            (16)
 359 #define RG_USB20_HS_TERM_EN_MODE_OFST             (13)
 360 #define RG_USB20_PUPD_BIST_EN_OFST                (12)
 361 #define RG_USB20_EN_PU_DM_OFST                    (11)
 362 #define RG_USB20_EN_PD_DM_OFST                    (10)
 363 #define RG_USB20_EN_PU_DP_OFST                    (9)
 364 #define RG_USB20_EN_PD_DP_OFST                    (8)
 365 #define RG_USB20_PHY_REV_OFST                     (0)
 366
 367 //U3D_U2PHYACR4
 368 #define RG_USB20_DP_100K_MODE_OFST                (18)
 369 #define RG_USB20_DM_100K_EN_OFST                  (17)
 370 #define USB20_DP_100K_EN_OFST                     (16)
 371 #define USB20_GPIO_DM_I_OFST                      (15)
 372 #define USB20_GPIO_DP_I_OFST                      (14)
 373 #define USB20_GPIO_DM_OE_OFST                     (13)
 374 #define USB20_GPIO_DP_OE_OFST                     (12)
 375 #define RG_USB20_GPIO_CTL_OFST                    (9)
 376 #define USB20_GPIO_MODE_OFST                      (8)
 377 #define RG_USB20_TX_BIAS_EN_OFST                  (5)
 378 #define RG_USB20_TX_VCMPDN_EN_OFST                (4)
 379 #define RG_USB20_HS_SQ_EN_MODE_OFST               (2)
 380 #define RG_USB20_HS_RCV_EN_MODE_OFST              (0)
 381
 382 //U3D_U2PHYAMON0
 383 #define RGO_USB20_GPIO_DM_O_OFST                  (1)
 384 #define RGO_USB20_GPIO_DP_O_OFST                  (0)
 385
 386 //U3D_U2PHYDCR0
 387 #define RG_USB20_CDR_TST_OFST                     (30)
 388 #define RG_USB20_GATED_ENB_OFST                   (29)
 389 #define RG_USB20_TESTMODE_OFST                    (26)
 390 #define RG_USB20_PLL_STABLE_OFST                  (25)
 391 #define RG_USB20_PLL_FORCE_ON_OFST                (24)
 392 #define RG_USB20_PHYD_RESERVE_OFST                (8)
 393 #define RG_USB20_EBTHRLD_OFST                     (7)
 394 #define RG_USB20_EARLY_HSTX_I_OFST                (6)
 395 #define RG_USB20_TX_TST_OFST                      (5)
 396 #define RG_USB20_NEGEDGE_ENB_OFST                 (4)
 397 #define RG_USB20_CDR_FILT_OFST                    (0)
 398
 399 //U3D_U2PHYDCR1
 400 #define RG_USB20_PROBE_SEL_OFST                   (24)
 401 #define RG_USB20_DRVVBUS_OFST                     (23)
 402 #define RG_DEBUG_EN_OFST                          (22)
 403 #define RG_USB20_OTG_PROBE_OFST                   (20)
 404 #define RG_USB20_SW_PLLMODE_OFST                  (18)
 405 #define RG_USB20_BERTH_OFST                       (16)
 406 #define RG_USB20_LBMODE_OFST                      (13)
 407 #define RG_USB20_FORCE_TAP_OFST                   (12)
 408 #define RG_USB20_TAPSEL_OFST                      (0)
 409
 410 //U3D_U2PHYDTM0
 411 #define RG_UART_MODE_OFST                         (30)
 412 #define FORCE_UART_I_OFST                         (29)
 413 #define FORCE_UART_BIAS_EN_OFST                   (28)
 414 #define FORCE_UART_TX_OE_OFST                     (27)
 415 #define FORCE_UART_EN_OFST                        (26)
 416 #define FORCE_USB_CLKEN_OFST                      (25)
 417 #define FORCE_DRVVBUS_OFST                        (24)
 418 #define FORCE_DATAIN_OFST                         (23)
 419 #define FORCE_TXVALID_OFST                        (22)
 420 #define FORCE_DM_PULLDOWN_OFST                    (21)
 421 #define FORCE_DP_PULLDOWN_OFST                    (20)
 422 #define FORCE_XCVRSEL_OFST                        (19)
 423 #define FORCE_SUSPENDM_OFST                       (18)
 424 #define FORCE_TERMSEL_OFST                        (17)
 425 #define FORCE_OPMODE_OFST                         (16)
 426 #define UTMI_MUXSEL_OFST                          (15)
 427 #define RG_RESET_OFST                             (14)
 428 #define RG_DATAIN_OFST                            (10)
 429 #define RG_TXVALIDH_OFST                          (9)
 430 #define RG_TXVALID_OFST                           (8)
 431 #define RG_DMPULLDOWN_OFST                        (7)
 432 #define RG_DPPULLDOWN_OFST                        (6)
 433 #define RG_XCVRSEL_OFST                           (4)
 434 #define RG_SUSPENDM_OFST                          (3)
 435 #define RG_TERMSEL_OFST                           (2)
 436 #define RG_OPMODE_OFST                            (0)
 437
 438 //U3D_U2PHYDTM1
 439 #define RG_USB20_PRBS7_EN_OFST                    (31)
 440 #define RG_USB20_PRBS7_BITCNT_OFST                (24)
 441 #define RG_USB20_CLK48M_EN_OFST                   (23)
 442 #define RG_USB20_CLK60M_EN_OFST                   (22)
 443 #define RG_UART_I_OFST                            (19)
 444 #define RG_UART_BIAS_EN_OFST                      (18)
 445 #define RG_UART_TX_OE_OFST                        (17)
 446 #define RG_UART_EN_OFST                           (16)
 447 #define FORCE_VBUSVALID_OFST                      (13)
 448 #define FORCE_SESSEND_OFST                        (12)
 449 #define FORCE_BVALID_OFST                         (11)
 450 #define FORCE_AVALID_OFST                         (10)
 451 #define FORCE_IDDIG_OFST                          (9)
 452 #define FORCE_IDPULLUP_OFST                       (8)
 453 #define RG_VBUSVALID_OFST                         (5)
 454 #define RG_SESSEND_OFST                           (4)
 455 #define RG_BVALID_OFST                            (3)
 456 #define RG_AVALID_OFST                            (2)
 457 #define RG_IDDIG_OFST                             (1)
 458 #define RG_IDPULLUP_OFST                          (0)
 459
 460 //U3D_U2PHYDMON0
 461 #define RG_USB20_PRBS7_BERTH_OFST                 (0)
 462
 463 //U3D_U2PHYDMON1
 464 #define USB20_UART_O_OFST                         (31)
 465 #define RGO_USB20_LB_PASS_OFST                    (30)
 466 #define RGO_USB20_LB_DONE_OFST                    (29)
 467 #define AD_USB20_BVALID_OFST                      (28)
 468 #define USB20_IDDIG_OFST                          (27)
 469 #define AD_USB20_VBUSVALID_OFST                   (26)
 470 #define AD_USB20_SESSEND_OFST                     (25)
 471 #define AD_USB20_AVALID_OFST                      (24)
 472 #define USB20_LINE_STATE_OFST                     (22)
 473 #define USB20_HST_DISCON_OFST                     (21)
 474 #define USB20_TX_READY_OFST                       (20)
 475 #define USB20_RX_ERROR_OFST                       (19)
 476 #define USB20_RX_ACTIVE_OFST                      (18)
 477 #define USB20_RX_VALIDH_OFST                      (17)
 478 #define USB20_RX_VALID_OFST                       (16)
 479 #define USB20_DATA_OUT_OFST                       (0)
 480
 481 //U3D_U2PHYDMON2
 482 #define RGO_TXVALID_CNT_OFST                      (24)
 483 #define RGO_RXACTIVE_CNT_OFST                     (16)
 484 #define RGO_USB20_LB_BERCNT_OFST                  (8)
 485 #define USB20_PROBE_OUT_OFST                      (0)
 486
 487 //U3D_U2PHYDMON3
 488 #define RGO_USB20_PRBS7_ERRCNT_OFST               (16)
 489 #define RGO_USB20_PRBS7_DONE_OFST                 (3)
 490 #define RGO_USB20_PRBS7_LOCK_OFST                 (2)
 491 #define RGO_USB20_PRBS7_PASS_OFST                 (1)
 492 #define RGO_USB20_PRBS7_PASSTH_OFST               (0)
 493
 494 //U3D_U2PHYBC12C
 495 #define RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST           (28)
 496 #define RG_SIFSLV_CHGDT_CTRL_CNT_OFST             (24)
 497 #define RG_SIFSLV_CHGDT_FORCE_MODE_OFST           (16)
 498 #define RG_CHGDT_ISRC_LEV_OFST                    (14)
 499 #define RG_CHGDT_VDATSRC_OFST                     (13)
 500 #define RG_CHGDT_BGVREF_SEL_OFST                  (10)
 501 #define RG_CHGDT_RDVREF_SEL_OFST                  (8)
 502 #define RG_CHGDT_ISRC_DP_OFST                     (7)
 503 #define RG_SIFSLV_CHGDT_OPOUT_DM_OFST             (6)
 504 #define RG_CHGDT_VDAT_DM_OFST                     (5)
 505 #define RG_CHGDT_OPOUT_DP_OFST                    (4)
 506 #define RG_SIFSLV_CHGDT_VDAT_DP_OFST              (3)
 507 #define RG_SIFSLV_CHGDT_COMP_EN_OFST              (2)
 508 #define RG_SIFSLV_CHGDT_OPDRV_EN_OFST             (1)
 509 #define RG_CHGDT_EN_OFST                          (0)
 510
 511 //U3D_U2PHYBC12C1
 512 #define RG_CHGDT_REV_OFST                         (0)
 513
 514 //U3D_REGFCOM
 515 #define RG_PAGE_OFST                              (24)
 516 #define I2C_MODE_OFST                             (16)
 517
 518
 519 ///////////////////////////////////////////////////////////////////////////////
 520
 521 struct u3phya_reg {
 522         //0x0
 523         PHY_LE32 reg0;
 524         PHY_LE32 reg1;
 525         PHY_LE32 reg2;
 526         PHY_LE32 reg3;
 527         //0x10
 528         PHY_LE32 reg4;
 529         PHY_LE32 reg5;
 530         PHY_LE32 reg6;
 531         PHY_LE32 reg7;
 532         //0x20
 533         PHY_LE32 reg8;
 534         PHY_LE32 reg9;
 535         PHY_LE32 rega;
 536         PHY_LE32 regb;
 537         //0x30
 538         PHY_LE32 regc;
 539         PHY_LE32 regd;
 540         PHY_LE32 rege;
 541 };
 542
 543 //U3D_reg0
 544 #define RG_SSUSB_BGR_EN                           (0x1<<31) //31:31
 545 #define RG_SSUSB_CHPEN                            (0x1<<30) //30:30
 546 #define RG_SSUSB_BG_DIV                           (0x3<<28) //29:28
 547 #define RG_SSUSB_INTR_EN                          (0x1<<26) //26:26
 548 #define RG_SSUSB_MPX_OUT_SEL                      (0x3<<24) //25:24
 549 #define RG_SSUSB_MPX_SEL                          (0xff<<16) //23:16
 550 #define RG_SSUSB_REF_EN                           (0x1<<15) //15:15
 551 #define RG_SSUSB_VRT_VREF_SEL                     (0xf<<11) //14:11
 552 #define RG_SSUSB_BG_RASEL                         (0x3<<9) //10:9
 553 #define RG_SSUSB_BG_RBSEL                         (0x3<<7) //8:7
 554 #define RG_SSUSB_BG_MONEN                         (0x1<<6) //6:6
 555 #define RG_PCIE_CLKDRV_OFFSET                     (0x3<<0) //1:0
 556
 557 //U3D_reg1
 558 #define RG_PCIE_CLKDRV_SLEW                       (0x3<<30) //31:30
 559 #define RG_PCIE_CLKDRV_AMP                        (0x7<<27) //29:27
 560 #define RG_SSUSB_XTAL_TST_A2DCK_EN                (0x1<<26) //26:26
 561 #define RG_SSUSB_XTAL_MON_EN                      (0x1<<25) //25:25
 562 #define RG_SSUSB_XTAL_HYS                         (0x1<<24) //24:24
 563 #define RG_SSUSB_XTAL_TOP_RESERVE                 (0xffff<<8) //23:8
 564 #define RG_SSUSB_SYSPLL_RESERVE                   (0xf<<4) //7:4
 565 #define RG_SSUSB_SYSPLL_FBSEL                     (0x3<<2) //3:2
 566 #define RG_SSUSB_SYSPLL_PREDIV                    (0x3<<0) //1:0
 567
 568 //U3D_reg2
 569 #define RG_SSUSB_SYSPLL_LF                        (0x1<<31) //31:31
 570 #define RG_SSUSB_SYSPLL_FBDIV                     (0x7f<<24) //30:24
 571 #define RG_SSUSB_SYSPLL_POSDIV                    (0x3<<22) //23:22
 572 #define RG_SSUSB_SYSPLL_VCO_DIV_SEL               (0x1<<21) //21:21
 573 #define RG_SSUSB_SYSPLL_BLP                       (0x1<<20) //20:20
 574 #define RG_SSUSB_SYSPLL_BP                        (0x1<<19) //19:19
 575 #define RG_SSUSB_SYSPLL_BR                        (0x1<<18) //18:18
 576 #define RG_SSUSB_SYSPLL_BC                        (0x1<<17) //17:17
 577 #define RG_SSUSB_SYSPLL_DIVEN                     (0x7<<14) //16:14
 578 #define RG_SSUSB_SYSPLL_FPEN                      (0x1<<13) //13:13
 579 #define RG_SSUSB_SYSPLL_MONCK_EN                  (0x1<<12) //12:12
 580 #define RG_SSUSB_SYSPLL_MONVC_EN                  (0x1<<11) //11:11
 581 #define RG_SSUSB_SYSPLL_MONREF_EN                 (0x1<<10) //10:10
 582 #define RG_SSUSB_SYSPLL_VOD_EN                    (0x1<<9) //9:9
 583 #define RG_SSUSB_SYSPLL_CK_SEL                    (0x1<<8) //8:8
 584
 585 //U3D_reg3
 586 #define RG_SSUSB_SYSPLL_TOP_RESERVE               (0xffff<<16) //31:16
 587
 588 //U3D_reg4
 589 #define RG_SSUSB_SYSPLL_PCW_NCPO                  (0x7fffffff<<1) //31:1
 590
 591 //U3D_reg5
 592 #define RG_SSUSB_SYSPLL_DDS_PI_C                  (0x7<<29) //31:29
 593 #define RG_SSUSB_SYSPLL_DDS_HF_EN                 (0x1<<28) //28:28
 594 #define RG_SSUSB_SYSPLL_DDS_PREDIV2               (0x1<<27) //27:27
 595 #define RG_SSUSB_SYSPLL_DDS_POSTDIV2              (0x1<<26) //26:26
 596 #define RG_SSUSB_SYSPLL_DDS_PI_PL_EN              (0x1<<25) //25:25
 597 #define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL            (0x1<<24) //24:24
 598 #define RG_SSUSB_SYSPLL_DDS_MONEN                 (0x1<<23) //23:23
 599 #define RG_SSUSB_SYSPLL_DDS_LPF_EN                (0x1<<22) //22:22
 600 #define RG_SSUSB_SYSPLL_CLK_PH_INV                (0x1<<21) //21:21
 601 #define RG_SSUSB_SYSPLL_DDS_SEL_EXT               (0x1<<20) //20:20
 602 #define RG_SSUSB_SYSPLL_DDS_DMY                   (0xffff<<0) //15:0
 603
 604 //U3D_reg6
 605 #define RG_SSUSB_TX250MCK_INVB                    (0x1<<31) //31:31
 606 #define RG_SSUSB_IDRV_ITAILOP_EN                  (0x1<<30) //30:30
 607 #define RG_SSUSB_IDRV_CALIB                       (0x3f<<24) //29:24
 608 #define RG_SSUSB_TX_R50_FON                       (0x1<<23) //23:23
 609 #define RG_SSUSB_TX_SR                            (0x7<<20) //22:20
 610 #define RG_SSUSB_TX_EIDLE_CM                      (0xf<<16) //19:16
 611 #define RG_SSUSB_RXDET_RSEL                       (0x3<<14) //15:14
 612 #define RG_SSUSB_RXDET_VTHSEL                     (0x3<<12) //13:12
 613 #define RG_SSUSB_CKMON_EN                         (0x1<<11) //11:11
 614 #define RG_SSUSB_CKMON_SEL                        (0x7<<8) //10:8
 615 #define RG_SSUSB_TX_VLMON_EN                      (0x1<<7) //7:7
 616 #define RG_SSUSB_TX_VLMON_SEL                     (0x1<<6) //6:6
 617 #define RG_SSUSB_RXLBTX_EN                        (0x1<<5) //5:5
 618 #define RG_SSUSB_TXLBRX_EN                        (0x1<<4) //4:4
 619
 620 //U3D_reg7
 621 #define RG_SSUSB_RESERVE                          (0xfffff<<12) //31:12
 622 #define RG_SSUSB_PLL_CKCTRL                       (0x3<<10) //11:10
 623 #define RG_SSUSB_PLL_POSDIV                       (0x3<<8) //9:8
 624 #define RG_SSUSB_PLL_AUTOK_LOAD                   (0x1<<7) //7:7
 625 #define RG_SSUSB_PLL_LOAD_RSTB                    (0x1<<6) //6:6
 626 #define RG_SSUSB_PLL_EP_EN                        (0x1<<5) //5:5
 627 #define RG_SSUSB_PLL_VOD_EN                       (0x1<<4) //4:4
 628 #define RG_SSUSB_PLL_V11_EN                       (0x1<<3) //3:3
 629 #define RG_SSUSB_PLL_MONREF_EN                    (0x1<<2) //2:2
 630 #define RG_SSUSB_PLL_MONCK_EN                     (0x1<<1) //1:1
 631 #define RG_SSUSB_PLL_MONVC_EN                     (0x1<<0) //0:0
 632
 633 //U3D_reg8
 634 #define RG_SSUSB_PLL_RESERVE                      (0xffff<<0) //15:0
 635
 636 //U3D_reg9
 637 #define RG_SSUSB_PLL_DDS_DMY                      (0xffff<<16) //31:16
 638 #define RG_SSUSB_PLL_SSC_PRD                      (0xffff<<0) //15:0
 639
 640 //U3D_regA
 641 #define RG_SSUSB_PLL_SSC_PHASE_INI                (0x1<<31) //31:31
 642 #define RG_SSUSB_PLL_SSC_TRI_EN                   (0x1<<30) //30:30
 643 #define RG_SSUSB_PLL_CLK_PH_INV                   (0x1<<29) //29:29
 644 #define RG_SSUSB_PLL_DDS_LPF_EN                   (0x1<<28) //28:28
 645 #define RG_SSUSB_PLL_DDS_VADJ                     (0x7<<21) //23:21
 646 #define RG_SSUSB_PLL_DDS_MONEN                    (0x1<<20) //20:20
 647 #define RG_SSUSB_PLL_DDS_PS_VADJ                  (0x7<<17) //19:17
 648 #define RG_SSUSB_PLL_DDS_SEL_EXT                  (0x1<<16) //16:16
 649 #define RG_SSUSB_CDR_PD_DIV_BYPASS                (0x1<<15) //15:15
 650 #define RG_SSUSB_CDR_PD_DIV_SEL                   (0x1<<14) //14:14
 651 #define RG_SSUSB_CDR_CPBIAS_SEL                   (0x1<<13) //13:13
 652 #define RG_SSUSB_CDR_OSCDET_EN                    (0x1<<12) //12:12
 653 #define RG_SSUSB_CDR_MONMUX                       (0x1<<11) //11:11
 654 #define RG_SSUSB_CDR_CKCTRL                       (0x3<<9) //10:9
 655 #define RG_SSUSB_CDR_ACCEN                        (0x1<<8) //8:8
 656 #define RG_SSUSB_CDR_BYPASS                       (0x3<<6) //7:6
 657 #define RG_SSUSB_CDR_PI_SLEW                      (0x3<<4) //5:4
 658 #define RG_SSUSB_CDR_EPEN                         (0x1<<3) //3:3
 659 #define RG_SSUSB_CDR_AUTOK_LOAD                   (0x1<<2) //2:2
 660 #define RG_SSUSB_CDR_LOAD_RSTB                    (0x1<<1) //1:1
 661 #define RG_SSUSB_CDR_MONEN                        (0x1<<0) //0:0
 662
 663 //U3D_regB
 664 #define RG_SSUSB_CDR_MONEN_DIG                    (0x1<<31) //31:31
 665 #define RG_SSUSB_CDR_REGOD                        (0x3<<29) //30:29
 666 #define RG_SSUSB_RX_DAC_EN                        (0x1<<26) //26:26
 667 #define RG_SSUSB_RX_DAC_PWD                       (0x1<<25) //25:25
 668 #define RG_SSUSB_EQ_CURSEL                        (0x1<<24) //24:24
 669 #define RG_SSUSB_RX_DAC_MUX                       (0x1f<<19) //23:19
 670 #define RG_SSUSB_RX_R2T_EN                        (0x1<<18) //18:18
 671 #define RG_SSUSB_RX_T2R_EN                        (0x1<<17) //17:17
 672 #define RG_SSUSB_RX_50_LOWER                      (0x7<<14) //16:14
 673 #define RG_SSUSB_RX_50_TAR                        (0x3<<12) //13:12
 674 #define RG_SSUSB_RX_SW_CTRL                       (0xf<<7) //10:7
 675 #define RG_PCIE_SIGDET_VTH                        (0x3<<5) //6:5
 676 #define RG_PCIE_SIGDET_LPF                        (0x3<<3) //4:3
 677 #define RG_SSUSB_LFPS_MON_EN                      (0x1<<2) //2:2
 678
 679 //U3D_regC
 680 #define RG_SSUSB_RXAFE_DCMON_SEL                  (0xf<<28) //31:28
 681 #define RG_SSUSB_CDR_RESERVE                      (0xff<<16) //23:16
 682 #define RG_SSUSB_RXAFE_RESERVE                    (0xff<<8) //15:8
 683 #define RG_PCIE_RX_RESERVE                        (0xff<<0) //7:0
 684
 685 //U3D_redD
 686 #define RGS_SSUSB_CDR_NO_OSC                      (0x1<<8) //8:8
 687 #define RGS_SSUSB_RX_DEBUG_RESERVE                (0xff<<0) //7:0
 688
 689 //U3D_regE
 690 #define RG_SSUSB_INT_BIAS_SEL                     (0x1<<4) //4:4
 691 #define RG_SSUSB_EXT_BIAS_SEL                     (0x1<<3) //3:3
 692 #define RG_SSUSB_RX_P1_ENTRY_PASS                 (0x1<<2) //2:2
 693 #define RG_SSUSB_RX_PD_RST                        (0x1<<1) //1:1
 694 #define RG_SSUSB_RX_PD_RST_PASS                   (0x1<<0) //0:0
 695
 696
 697 /* OFFSET */
 698
 699 //U3D_reg0
 700 #define RG_SSUSB_BGR_EN_OFST                      (31)
 701 #define RG_SSUSB_CHPEN_OFST                       (30)
 702 #define RG_SSUSB_BG_DIV_OFST                      (28)
 703 #define RG_SSUSB_INTR_EN_OFST                     (26)
 704 #define RG_SSUSB_MPX_OUT_SEL_OFST                 (24)
 705 #define RG_SSUSB_MPX_SEL_OFST                     (16)
 706 #define RG_SSUSB_REF_EN_OFST                      (15)
 707 #define RG_SSUSB_VRT_VREF_SEL_OFST                (11)
 708 #define RG_SSUSB_BG_RASEL_OFST                    (9)
 709 #define RG_SSUSB_BG_RBSEL_OFST                    (7)
 710 #define RG_SSUSB_BG_MONEN_OFST                    (6)
 711 #define RG_PCIE_CLKDRV_OFFSET_OFST                (0)
 712
 713 //U3D_reg1
 714 #define RG_PCIE_CLKDRV_SLEW_OFST                  (30)
 715 #define RG_PCIE_CLKDRV_AMP_OFST                   (27)
 716 #define RG_SSUSB_XTAL_TST_A2DCK_EN_OFST           (26)
 717 #define RG_SSUSB_XTAL_MON_EN_OFST                 (25)
 718 #define RG_SSUSB_XTAL_HYS_OFST                    (24)
 719 #define RG_SSUSB_XTAL_TOP_RESERVE_OFST            (8)
 720 #define RG_SSUSB_SYSPLL_RESERVE_OFST              (4)
 721 #define RG_SSUSB_SYSPLL_FBSEL_OFST                (2)
 722 #define RG_SSUSB_SYSPLL_PREDIV_OFST               (0)
 723
 724 //U3D_reg2
 725 #define RG_SSUSB_SYSPLL_LF_OFST                   (31)
 726 #define RG_SSUSB_SYSPLL_FBDIV_OFST                (24)
 727 #define RG_SSUSB_SYSPLL_POSDIV_OFST               (22)
 728 #define RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST          (21)
 729 #define RG_SSUSB_SYSPLL_BLP_OFST                  (20)
 730 #define RG_SSUSB_SYSPLL_BP_OFST                   (19)
 731 #define RG_SSUSB_SYSPLL_BR_OFST                   (18)
 732 #define RG_SSUSB_SYSPLL_BC_OFST                   (17)
 733 #define RG_SSUSB_SYSPLL_DIVEN_OFST                (14)
 734 #define RG_SSUSB_SYSPLL_FPEN_OFST                 (13)
 735 #define RG_SSUSB_SYSPLL_MONCK_EN_OFST             (12)
 736 #define RG_SSUSB_SYSPLL_MONVC_EN_OFST             (11)
 737 #define RG_SSUSB_SYSPLL_MONREF_EN_OFST            (10)
 738 #define RG_SSUSB_SYSPLL_VOD_EN_OFST               (9)
 739 #define RG_SSUSB_SYSPLL_CK_SEL_OFST               (8)
 740
 741 //U3D_reg3
 742 #define RG_SSUSB_SYSPLL_TOP_RESERVE_OFST          (16)
 743
 744 //U3D_reg4
 745 #define RG_SSUSB_SYSPLL_PCW_NCPO_OFST             (1)
 746
 747 //U3D_reg5
 748 #define RG_SSUSB_SYSPLL_DDS_PI_C_OFST             (29)
 749 #define RG_SSUSB_SYSPLL_DDS_HF_EN_OFST            (28)
 750 #define RG_SSUSB_SYSPLL_DDS_PREDIV2_OFST          (27)
 751 #define RG_SSUSB_SYSPLL_DDS_POSTDIV2_OFST         (26)
 752 #define RG_SSUSB_SYSPLL_DDS_PI_PL_EN_OFST         (25)
 753 #define RG_SSUSB_SYSPLL_DDS_PI_RST_SEL_OFST       (24)
 754 #define RG_SSUSB_SYSPLL_DDS_MONEN_OFST            (23)
 755 #define RG_SSUSB_SYSPLL_DDS_LPF_EN_OFST           (22)
 756 #define RG_SSUSB_SYSPLL_CLK_PH_INV_OFST           (21)
 757 #define RG_SSUSB_SYSPLL_DDS_SEL_EXT_OFST          (20)
 758 #define RG_SSUSB_SYSPLL_DDS_DMY_OFST              (0)
 759
 760 //U3D_reg6
 761 #define RG_SSUSB_TX250MCK_INVB_OFST               (31)
 762 #define RG_SSUSB_IDRV_ITAILOP_EN_OFST             (30)
 763 #define RG_SSUSB_IDRV_CALIB_OFST                  (24)
 764 #define RG_SSUSB_TX_R50_FON_OFST                  (23)
 765 #define RG_SSUSB_TX_SR_OFST                       (20)
 766 #define RG_SSUSB_TX_EIDLE_CM_OFST                 (16)
 767 #define RG_SSUSB_RXDET_RSEL_OFST                  (14)
 768 #define RG_SSUSB_RXDET_VTHSEL_OFST                (12)
 769 #define RG_SSUSB_CKMON_EN_OFST                    (11)
 770 #define RG_SSUSB_CKMON_SEL_OFST                   (8)
 771 #define RG_SSUSB_TX_VLMON_EN_OFST                 (7)
 772 #define RG_SSUSB_TX_VLMON_SEL_OFST                (6)
 773 #define RG_SSUSB_RXLBTX_EN_OFST                   (5)
 774 #define RG_SSUSB_TXLBRX_EN_OFST                   (4)
 775
 776 //U3D_reg7
 777 #define RG_SSUSB_RESERVE_OFST                     (12)
 778 #define RG_SSUSB_PLL_CKCTRL_OFST                  (10)
 779 #define RG_SSUSB_PLL_POSDIV_OFST                  (8)
 780 #define RG_SSUSB_PLL_AUTOK_LOAD_OFST              (7)
 781 #define RG_SSUSB_PLL_LOAD_RSTB_OFST               (6)
 782 #define RG_SSUSB_PLL_EP_EN_OFST                   (5)
 783 #define RG_SSUSB_PLL_VOD_EN_OFST                  (4)
 784 #define RG_SSUSB_PLL_V11_EN_OFST                  (3)
 785 #define RG_SSUSB_PLL_MONREF_EN_OFST               (2)
 786 #define RG_SSUSB_PLL_MONCK_EN_OFST                (1)
 787 #define RG_SSUSB_PLL_MONVC_EN_OFST                (0)
 788
 789 //U3D_reg8
 790 #define RG_SSUSB_PLL_RESERVE_OFST                 (0)
 791
 792 //U3D_reg9
 793 #define RG_SSUSB_PLL_DDS_DMY_OFST                 (16)
 794 #define RG_SSUSB_PLL_SSC_PRD_OFST                 (0)
 795
 796 //U3D_regA
 797 #define RG_SSUSB_PLL_SSC_PHASE_INI_OFST           (31)
 798 #define RG_SSUSB_PLL_SSC_TRI_EN_OFST              (30)
 799 #define RG_SSUSB_PLL_CLK_PH_INV_OFST              (29)
 800 #define RG_SSUSB_PLL_DDS_LPF_EN_OFST              (28)
 801 #define RG_SSUSB_PLL_DDS_VADJ_OFST                (21)
 802 #define RG_SSUSB_PLL_DDS_MONEN_OFST               (20)
 803 #define RG_SSUSB_PLL_DDS_PS_VADJ_OFST             (17)
 804 #define RG_SSUSB_PLL_DDS_SEL_EXT_OFST             (16)
 805 #define RG_SSUSB_CDR_PD_DIV_BYPASS_OFST           (15)
 806 #define RG_SSUSB_CDR_PD_DIV_SEL_OFST              (14)
 807 #define RG_SSUSB_CDR_CPBIAS_SEL_OFST              (13)
 808 #define RG_SSUSB_CDR_OSCDET_EN_OFST               (12)
 809 #define RG_SSUSB_CDR_MONMUX_OFST                  (11)
 810 #define RG_SSUSB_CDR_CKCTRL_OFST                  (9)
 811 #define RG_SSUSB_CDR_ACCEN_OFST                   (8)
 812 #define RG_SSUSB_CDR_BYPASS_OFST                  (6)
 813 #define RG_SSUSB_CDR_PI_SLEW_OFST                 (4)
 814 #define RG_SSUSB_CDR_EPEN_OFST                    (3)
 815 #define RG_SSUSB_CDR_AUTOK_LOAD_OFST              (2)
 816 #define RG_SSUSB_CDR_LOAD_RSTB_OFST               (1)
 817 #define RG_SSUSB_CDR_MONEN_OFST                   (0)
 818
 819 //U3D_regB
 820 #define RG_SSUSB_CDR_MONEN_DIG_OFST               (31)
 821 #define RG_SSUSB_CDR_REGOD_OFST                   (29)
 822 #define RG_SSUSB_RX_DAC_EN_OFST                   (26)
 823 #define RG_SSUSB_RX_DAC_PWD_OFST                  (25)
 824 #define RG_SSUSB_EQ_CURSEL_OFST                   (24)
 825 #define RG_SSUSB_RX_DAC_MUX_OFST                  (19)
 826 #define RG_SSUSB_RX_R2T_EN_OFST                   (18)
 827 #define RG_SSUSB_RX_T2R_EN_OFST                   (17)
 828 #define RG_SSUSB_RX_50_LOWER_OFST                 (14)
 829 #define RG_SSUSB_RX_50_TAR_OFST                   (12)
 830 #define RG_SSUSB_RX_SW_CTRL_OFST                  (7)
 831 #define RG_PCIE_SIGDET_VTH_OFST                   (5)
 832 #define RG_PCIE_SIGDET_LPF_OFST                   (3)
 833 #define RG_SSUSB_LFPS_MON_EN_OFST                 (2)
 834
 835 //U3D_regC
 836 #define RG_SSUSB_RXAFE_DCMON_SEL_OFST             (28)
 837 #define RG_SSUSB_CDR_RESERVE_OFST                 (16)
 838 #define RG_SSUSB_RXAFE_RESERVE_OFST               (8)
 839 #define RG_PCIE_RX_RESERVE_OFST                   (0)
 840
 841 //U3D_redD
 842 #define RGS_SSUSB_CDR_NO_OSC_OFST                 (8)
 843 #define RGS_SSUSB_RX_DEBUG_RESERVE_OFST           (0)
 844
 845 //U3D_regE
 846 #define RG_SSUSB_INT_BIAS_SEL_OFST                (4)
 847 #define RG_SSUSB_EXT_BIAS_SEL_OFST                (3)
 848 #define RG_SSUSB_RX_P1_ENTRY_PASS_OFST            (2)
 849 #define RG_SSUSB_RX_PD_RST_OFST                   (1)
 850 #define RG_SSUSB_RX_PD_RST_PASS_OFST              (0)
 851
 852 ///////////////////////////////////////////////////////////////////////////////
 853
 854 struct u3phya_da_reg {
 855         //0x0
 856         PHY_LE32 reg0;
 857         PHY_LE32 reg1;
 858         PHY_LE32 reg4;
 859         PHY_LE32 reg5;
 860         //0x10
 861         PHY_LE32 reg6;
 862         PHY_LE32 reg7;
 863         PHY_LE32 reg8;
 864         PHY_LE32 reg9;
 865         //0x20
 866         PHY_LE32 reg10;
 867         PHY_LE32 reg12;
 868         PHY_LE32 reg13;
 869         PHY_LE32 reg14;
 870         //0x30
 871         PHY_LE32 reg15;
 872         PHY_LE32 reg16;
 873         PHY_LE32 reg19;
 874         PHY_LE32 reg20;
 875         //0x40
 876         PHY_LE32 reg21;
 877         PHY_LE32 reg23;
 878         PHY_LE32 reg25;
 879         PHY_LE32 reg26;
 880         //0x50
 881         PHY_LE32 reg28;
 882         PHY_LE32 reg29;
 883         PHY_LE32 reg30;
 884         PHY_LE32 reg31;
 885         //0x60
 886         PHY_LE32 reg32;
 887         PHY_LE32 reg33;
 888 };
 889
 890 //U3D_reg0
 891 #define RG_PCIE_SPEED_PE2D                        (0x1<<24) //24:24
 892 #define RG_PCIE_SPEED_PE2H                        (0x1<<23) //23:23
 893 #define RG_PCIE_SPEED_PE1D                        (0x1<<22) //22:22
 894 #define RG_PCIE_SPEED_PE1H                        (0x1<<21) //21:21
 895 #define RG_PCIE_SPEED_U3                          (0x1<<20) //20:20
 896 #define RG_SSUSB_XTAL_EXT_EN_PE2D                 (0x3<<18) //19:18
 897 #define RG_SSUSB_XTAL_EXT_EN_PE2H                 (0x3<<16) //17:16
 898 #define RG_SSUSB_XTAL_EXT_EN_PE1D                 (0x3<<14) //15:14
 899 #define RG_SSUSB_XTAL_EXT_EN_PE1H                 (0x3<<12) //13:12
 900 #define RG_SSUSB_XTAL_EXT_EN_U3                   (0x3<<10) //11:10
 901 #define RG_SSUSB_CDR_REFCK_SEL_PE2D               (0x3<<8) //9:8
 902 #define RG_SSUSB_CDR_REFCK_SEL_PE2H               (0x3<<6) //7:6
 903 #define RG_SSUSB_CDR_REFCK_SEL_PE1D               (0x3<<4) //5:4
 904 #define RG_SSUSB_CDR_REFCK_SEL_PE1H               (0x3<<2) //3:2
 905 #define RG_SSUSB_CDR_REFCK_SEL_U3                 (0x3<<0) //1:0
 906
 907 //U3D_reg1
 908 #define RG_USB20_REFCK_SEL_PE2D                   (0x1<<30) //30:30
 909 #define RG_USB20_REFCK_SEL_PE2H                   (0x1<<29) //29:29
 910 #define RG_USB20_REFCK_SEL_PE1D                   (0x1<<28) //28:28
 911 #define RG_USB20_REFCK_SEL_PE1H                   (0x1<<27) //27:27
 912 #define RG_USB20_REFCK_SEL_U3                     (0x1<<26) //26:26
 913 #define RG_PCIE_REFCK_DIV4_PE2D                   (0x1<<25) //25:25
 914 #define RG_PCIE_REFCK_DIV4_PE2H                   (0x1<<24) //24:24
 915 #define RG_PCIE_REFCK_DIV4_PE1D                   (0x1<<18) //18:18
 916 #define RG_PCIE_REFCK_DIV4_PE1H                   (0x1<<17) //17:17
 917 #define RG_PCIE_REFCK_DIV4_U3                     (0x1<<16) //16:16
 918 #define RG_PCIE_MODE_PE2D                         (0x1<<8) //8:8
 919 #define RG_PCIE_MODE_PE2H                         (0x1<<3) //3:3
 920 #define RG_PCIE_MODE_PE1D                         (0x1<<2) //2:2
 921 #define RG_PCIE_MODE_PE1H                         (0x1<<1) //1:1
 922 #define RG_PCIE_MODE_U3                           (0x1<<0) //0:0
 923
 924 //U3D_reg4
 925 #define RG_SSUSB_PLL_DIVEN_PE2D                   (0x7<<22) //24:22
 926 #define RG_SSUSB_PLL_DIVEN_PE2H                   (0x7<<19) //21:19
 927 #define RG_SSUSB_PLL_DIVEN_PE1D                   (0x7<<16) //18:16
 928 #define RG_SSUSB_PLL_DIVEN_PE1H                   (0x7<<13) //15:13
 929 #define RG_SSUSB_PLL_DIVEN_U3                     (0x7<<10) //12:10
 930 #define RG_SSUSB_PLL_BC_PE2D                      (0x3<<8) //9:8
 931 #define RG_SSUSB_PLL_BC_PE2H                      (0x3<<6) //7:6
 932 #define RG_SSUSB_PLL_BC_PE1D                      (0x3<<4) //5:4
 933 #define RG_SSUSB_PLL_BC_PE1H                      (0x3<<2) //3:2
 934 #define RG_SSUSB_PLL_BC_U3                        (0x3<<0) //1:0
 935
 936 //U3D_reg5
 937 #define RG_SSUSB_PLL_BR_PE2D                      (0x7<<27) //29:27
 938 #define RG_SSUSB_PLL_BR_PE2H                      (0x7<<24) //26:24
 939 #define RG_SSUSB_PLL_BR_PE1D                      (0x7<<21) //23:21
 940 #define RG_SSUSB_PLL_BR_PE1H                      (0x7<<18) //20:18
 941 #define RG_SSUSB_PLL_BR_U3                        (0x7<<15) //17:15
 942 #define RG_SSUSB_PLL_IC_PE2D                      (0x7<<12) //14:12
 943 #define RG_SSUSB_PLL_IC_PE2H                      (0x7<<9) //11:9
 944 #define RG_SSUSB_PLL_IC_PE1D                      (0x7<<6) //8:6
 945 #define RG_SSUSB_PLL_IC_PE1H                      (0x7<<3) //5:3
 946 #define RG_SSUSB_PLL_IC_U3                        (0x7<<0) //2:0
 947
 948 //U3D_reg6
 949 #define RG_SSUSB_PLL_IR_PE2D                      (0xf<<24) //27:24
 950 #define RG_SSUSB_PLL_IR_PE2H                      (0xf<<16) //19:16
 951 #define RG_SSUSB_PLL_IR_PE1D                      (0xf<<8) //11:8
 952 #define RG_SSUSB_PLL_IR_PE1H                      (0xf<<4) //7:4
 953 #define RG_SSUSB_PLL_IR_U3                        (0xf<<0) //3:0
 954
 955 //U3D_reg7
 956 #define RG_SSUSB_PLL_BP_PE2D                      (0xf<<24) //27:24
 957 #define RG_SSUSB_PLL_BP_PE2H                      (0xf<<16) //19:16
 958 #define RG_SSUSB_PLL_BP_PE1D                      (0xf<<8) //11:8
 959 #define RG_SSUSB_PLL_BP_PE1H                      (0xf<<4) //7:4
 960 #define RG_SSUSB_PLL_BP_U3                        (0xf<<0) //3:0
 961
 962 //U3D_reg8
 963 #define RG_SSUSB_PLL_FBKSEL_PE2D                  (0x3<<24) //25:24
 964 #define RG_SSUSB_PLL_FBKSEL_PE2H                  (0x3<<16) //17:16
 965 #define RG_SSUSB_PLL_FBKSEL_PE1D                  (0x3<<8) //9:8
 966 #define RG_SSUSB_PLL_FBKSEL_PE1H                  (0x3<<2) //3:2
 967 #define RG_SSUSB_PLL_FBKSEL_U3                    (0x3<<0) //1:0
 968
 969 //U3D_reg9
 970 #define RG_SSUSB_PLL_FBKDIV_PE2H                  (0x7f<<24) //30:24
 971 #define RG_SSUSB_PLL_FBKDIV_PE1D                  (0x7f<<16) //22:16
 972 #define RG_SSUSB_PLL_FBKDIV_PE1H                  (0x7f<<8) //14:8
 973 #define RG_SSUSB_PLL_FBKDIV_U3                    (0x7f<<0) //6:0
 974
 975 //U3D_reg10
 976 #define RG_SSUSB_PLL_PREDIV_PE2D                  (0x3<<26) //27:26
 977 #define RG_SSUSB_PLL_PREDIV_PE2H                  (0x3<<24) //25:24
 978 #define RG_SSUSB_PLL_PREDIV_PE1D                  (0x3<<18) //19:18
 979 #define RG_SSUSB_PLL_PREDIV_PE1H                  (0x3<<16) //17:16
 980 #define RG_SSUSB_PLL_PREDIV_U3                    (0x3<<8) //9:8
 981 #define RG_SSUSB_PLL_FBKDIV_PE2D                  (0x7f<<0) //6:0
 982
 983 //U3D_reg12
 984 #define RG_SSUSB_PLL_PCW_NCPO_U3                  (0x7fffffff<<0) //30:0
 985
 986 //U3D_reg13
 987 #define RG_SSUSB_PLL_PCW_NCPO_PE1H                (0x7fffffff<<0) //30:0
 988
 989 //U3D_reg14
 990 #define RG_SSUSB_PLL_PCW_NCPO_PE1D                (0x7fffffff<<0) //30:0
 991
 992 //U3D_reg15
 993 #define RG_SSUSB_PLL_PCW_NCPO_PE2H                (0x7fffffff<<0) //30:0
 994
 995 //U3D_reg16
 996 #define RG_SSUSB_PLL_PCW_NCPO_PE2D                (0x7fffffff<<0) //30:0
 997
 998 //U3D_reg19
 999 #define RG_SSUSB_PLL_SSC_DELTA1_PE1H              (0xffff<<16) //31:16
1000 #define RG_SSUSB_PLL_SSC_DELTA1_U3                (0xffff<<0) //15:0
1001
1002 //U3D_reg20
1003 #define RG_SSUSB_PLL_SSC_DELTA1_PE2H              (0xffff<<16) //31:16
1004 #define RG_SSUSB_PLL_SSC_DELTA1_PE1D              (0xffff<<0) //15:0
1005
1006 //U3D_reg21
1007 #define RG_SSUSB_PLL_SSC_DELTA_U3                 (0xffff<<16) //31:16
1008 #define RG_SSUSB_PLL_SSC_DELTA1_PE2D              (0xffff<<0) //15:0
1009
1010 //U3D_reg23
1011 #define RG_SSUSB_PLL_SSC_DELTA_PE1D               (0xffff<<16) //31:16
1012 #define RG_SSUSB_PLL_SSC_DELTA_PE1H               (0xffff<<0) //15:0
1013
1014 //U3D_reg25
1015 #define RG_SSUSB_PLL_SSC_DELTA_PE2D               (0xffff<<16) //31:16
1016 #define RG_SSUSB_PLL_SSC_DELTA_PE2H               (0xffff<<0) //15:0
1017
1018 //U3D_reg26
1019 #define RG_SSUSB_PLL_REFCKDIV_PE2D                (0x1<<25) //25:25
1020 #define RG_SSUSB_PLL_REFCKDIV_PE2H                (0x1<<24) //24:24
1021 #define RG_SSUSB_PLL_REFCKDIV_PE1D                (0x1<<16) //16:16
1022 #define RG_SSUSB_PLL_REFCKDIV_PE1H                (0x1<<8) //8:8
1023 #define RG_SSUSB_PLL_REFCKDIV_U3                  (0x1<<0) //0:0
1024
1025 //U3D_reg28
1026 #define RG_SSUSB_CDR_BPA_PE2D                     (0x3<<24) //25:24
1027 #define RG_SSUSB_CDR_BPA_PE2H                     (0x3<<16) //17:16
1028 #define RG_SSUSB_CDR_BPA_PE1D                     (0x3<<10) //11:10
1029 #define RG_SSUSB_CDR_BPA_PE1H                     (0x3<<8) //9:8
1030 #define RG_SSUSB_CDR_BPA_U3                       (0x3<<0) //1:0
1031
1032 //U3D_reg29
1033 #define RG_SSUSB_CDR_BPB_PE2D                     (0x7<<24) //26:24
1034 #define RG_SSUSB_CDR_BPB_PE2H                     (0x7<<16) //18:16
1035 #define RG_SSUSB_CDR_BPB_PE1D                     (0x7<<6) //8:6
1036 #define RG_SSUSB_CDR_BPB_PE1H                     (0x7<<3) //5:3
1037 #define RG_SSUSB_CDR_BPB_U3                       (0x7<<0) //2:0
1038
1039 //U3D_reg30
1040 #define RG_SSUSB_CDR_BR_PE2D                      (0x7<<24) //26:24
1041 #define RG_SSUSB_CDR_BR_PE2H                      (0x7<<16) //18:16
1042 #define RG_SSUSB_CDR_BR_PE1D                      (0x7<<6) //8:6
1043 #define RG_SSUSB_CDR_BR_PE1H                      (0x7<<3) //5:3
1044 #define RG_SSUSB_CDR_BR_U3                        (0x7<<0) //2:0
1045
1046 //U3D_reg31
1047 #define RG_SSUSB_CDR_FBDIV_PE2H                   (0x7f<<24) //30:24
1048 #define RG_SSUSB_CDR_FBDIV_PE1D                   (0x7f<<16) //22:16
1049 #define RG_SSUSB_CDR_FBDIV_PE1H                   (0x7f<<8) //14:8
1050 #define RG_SSUSB_CDR_FBDIV_U3                     (0x7f<<0) //6:0
1051
1052 //U3D_reg32
1053 #define RG_SSUSB_EQ_RSTEP1_PE2D                   (0x3<<30) //31:30
1054 #define RG_SSUSB_EQ_RSTEP1_PE2H                   (0x3<<28) //29:28
1055 #define RG_SSUSB_EQ_RSTEP1_PE1D                   (0x3<<26) //27:26
1056 #define RG_SSUSB_EQ_RSTEP1_PE1H                   (0x3<<24) //25:24
1057 #define RG_SSUSB_EQ_RSTEP1_U3                     (0x3<<22) //23:22
1058 #define RG_SSUSB_LFPS_DEGLITCH_PE2D               (0x3<<20) //21:20
1059 #define RG_SSUSB_LFPS_DEGLITCH_PE2H               (0x3<<18) //19:18
1060 #define RG_SSUSB_LFPS_DEGLITCH_PE1D               (0x3<<16) //17:16
1061 #define RG_SSUSB_LFPS_DEGLITCH_PE1H               (0x3<<14) //15:14
1062 #define RG_SSUSB_LFPS_DEGLITCH_U3                 (0x3<<12) //13:12
1063 #define RG_SSUSB_CDR_KVSEL_PE2D                   (0x1<<11) //11:11
1064 #define RG_SSUSB_CDR_KVSEL_PE2H                   (0x1<<10) //10:10
1065 #define RG_SSUSB_CDR_KVSEL_PE1D                   (0x1<<9) //9:9
1066 #define RG_SSUSB_CDR_KVSEL_PE1H                   (0x1<<8) //8:8
1067 #define RG_SSUSB_CDR_KVSEL_U3                     (0x1<<7) //7:7
1068 #define RG_SSUSB_CDR_FBDIV_PE2D                   (0x7f<<0) //6:0
1069
1070 //U3D_reg33
1071 #define RG_SSUSB_RX_CMPWD_PE2D                    (0x1<<26) //26:26
1072 #define RG_SSUSB_RX_CMPWD_PE2H                    (0x1<<25) //25:25
1073 #define RG_SSUSB_RX_CMPWD_PE1D                    (0x1<<24) //24:24
1074 #define RG_SSUSB_RX_CMPWD_PE1H                    (0x1<<23) //23:23
1075 #define RG_SSUSB_RX_CMPWD_U3                      (0x1<<16) //16:16
1076 #define RG_SSUSB_EQ_RSTEP2_PE2D                   (0x3<<8) //9:8
1077 #define RG_SSUSB_EQ_RSTEP2_PE2H                   (0x3<<6) //7:6
1078 #define RG_SSUSB_EQ_RSTEP2_PE1D                   (0x3<<4) //5:4
1079 #define RG_SSUSB_EQ_RSTEP2_PE1H                   (0x3<<2) //3:2
1080 #define RG_SSUSB_EQ_RSTEP2_U3                     (0x3<<0) //1:0
1081
1082
1083 /* OFFSET  */
1084
1085 //U3D_reg0
1086 #define RG_PCIE_SPEED_PE2D_OFST                   (24)
1087 #define RG_PCIE_SPEED_PE2H_OFST                   (23)
1088 #define RG_PCIE_SPEED_PE1D_OFST                   (22)
1089 #define RG_PCIE_SPEED_PE1H_OFST                   (21)
1090 #define RG_PCIE_SPEED_U3_OFST                     (20)
1091 #define RG_SSUSB_XTAL_EXT_EN_PE2D_OFST            (18)
1092 #define RG_SSUSB_XTAL_EXT_EN_PE2H_OFST            (16)
1093 #define RG_SSUSB_XTAL_EXT_EN_PE1D_OFST            (14)
1094 #define RG_SSUSB_XTAL_EXT_EN_PE1H_OFST            (12)
1095 #define RG_SSUSB_XTAL_EXT_EN_U3_OFST              (10)
1096 #define RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST          (8)
1097 #define RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST          (6)
1098 #define RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST          (4)
1099 #define RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST          (2)
1100 #define RG_SSUSB_CDR_REFCK_SEL_U3_OFST            (0)
1101
1102 //U3D_reg1
1103 #define RG_USB20_REFCK_SEL_PE2D_OFST              (30)
1104 #define RG_USB20_REFCK_SEL_PE2H_OFST              (29)
1105 #define RG_USB20_REFCK_SEL_PE1D_OFST              (28)
1106 #define RG_USB20_REFCK_SEL_PE1H_OFST              (27)
1107 #define RG_USB20_REFCK_SEL_U3_OFST                (26)
1108 #define RG_PCIE_REFCK_DIV4_PE2D_OFST              (25)
1109 #define RG_PCIE_REFCK_DIV4_PE2H_OFST              (24)
1110 #define RG_PCIE_REFCK_DIV4_PE1D_OFST              (18)
1111 #define RG_PCIE_REFCK_DIV4_PE1H_OFST              (17)
1112 #define RG_PCIE_REFCK_DIV4_U3_OFST                (16)
1113 #define RG_PCIE_MODE_PE2D_OFST                    (8)
1114 #define RG_PCIE_MODE_PE2H_OFST                    (3)
1115 #define RG_PCIE_MODE_PE1D_OFST                    (2)
1116 #define RG_PCIE_MODE_PE1H_OFST                    (1)
1117 #define RG_PCIE_MODE_U3_OFST                      (0)
1118
1119 //U3D_reg4
1120 #define RG_SSUSB_PLL_DIVEN_PE2D_OFST              (22)
1121 #define RG_SSUSB_PLL_DIVEN_PE2H_OFST              (19)
1122 #define RG_SSUSB_PLL_DIVEN_PE1D_OFST              (16)
1123 #define RG_SSUSB_PLL_DIVEN_PE1H_OFST              (13)
1124 #define RG_SSUSB_PLL_DIVEN_U3_OFST                (10)
1125 #define RG_SSUSB_PLL_BC_PE2D_OFST                 (8)
1126 #define RG_SSUSB_PLL_BC_PE2H_OFST                 (6)
1127 #define RG_SSUSB_PLL_BC_PE1D_OFST                 (4)
1128 #define RG_SSUSB_PLL_BC_PE1H_OFST                 (2)
1129 #define RG_SSUSB_PLL_BC_U3_OFST                   (0)
1130
1131 //U3D_reg5
1132 #define RG_SSUSB_PLL_BR_PE2D_OFST                 (27)
1133 #define RG_SSUSB_PLL_BR_PE2H_OFST                 (24)
1134 #define RG_SSUSB_PLL_BR_PE1D_OFST                 (21)
1135 #define RG_SSUSB_PLL_BR_PE1H_OFST                 (18)
1136 #define RG_SSUSB_PLL_BR_U3_OFST                   (15)
1137 #define RG_SSUSB_PLL_IC_PE2D_OFST                 (12)
1138 #define RG_SSUSB_PLL_IC_PE2H_OFST                 (9)
1139 #define RG_SSUSB_PLL_IC_PE1D_OFST                 (6)
1140 #define RG_SSUSB_PLL_IC_PE1H_OFST                 (3)
1141 #define RG_SSUSB_PLL_IC_U3_OFST                   (0)
1142
1143 //U3D_reg6
1144 #define RG_SSUSB_PLL_IR_PE2D_OFST                 (24)
1145 #define RG_SSUSB_PLL_IR_PE2H_OFST                 (16)
1146 #define RG_SSUSB_PLL_IR_PE1D_OFST                 (8)
1147 #define RG_SSUSB_PLL_IR_PE1H_OFST                 (4)
1148 #define RG_SSUSB_PLL_IR_U3_OFST                   (0)
1149
1150 //U3D_reg7
1151 #define RG_SSUSB_PLL_BP_PE2D_OFST                 (24)
1152 #define RG_SSUSB_PLL_BP_PE2H_OFST                 (16)
1153 #define RG_SSUSB_PLL_BP_PE1D_OFST                 (8)
1154 #define RG_SSUSB_PLL_BP_PE1H_OFST                 (4)
1155 #define RG_SSUSB_PLL_BP_U3_OFST                   (0)
1156
1157 //U3D_reg8
1158 #define RG_SSUSB_PLL_FBKSEL_PE2D_OFST             (24)
1159 #define RG_SSUSB_PLL_FBKSEL_PE2H_OFST             (16)
1160 #define RG_SSUSB_PLL_FBKSEL_PE1D_OFST             (8)
1161 #define RG_SSUSB_PLL_FBKSEL_PE1H_OFST             (2)
1162 #define RG_SSUSB_PLL_FBKSEL_U3_OFST               (0)
1163
1164 //U3D_reg9
1165 #define RG_SSUSB_PLL_FBKDIV_PE2H_OFST             (24)
1166 #define RG_SSUSB_PLL_FBKDIV_PE1D_OFST             (16)
1167 #define RG_SSUSB_PLL_FBKDIV_PE1H_OFST             (8)
1168 #define RG_SSUSB_PLL_FBKDIV_U3_OFST               (0)
1169
1170 //U3D_reg10
1171 #define RG_SSUSB_PLL_PREDIV_PE2D_OFST             (26)
1172 #define RG_SSUSB_PLL_PREDIV_PE2H_OFST             (24)
1173 #define RG_SSUSB_PLL_PREDIV_PE1D_OFST             (18)
1174 #define RG_SSUSB_PLL_PREDIV_PE1H_OFST             (16)
1175 #define RG_SSUSB_PLL_PREDIV_U3_OFST               (8)
1176 #define RG_SSUSB_PLL_FBKDIV_PE2D_OFST             (0)
1177
1178 //U3D_reg12
1179 #define RG_SSUSB_PLL_PCW_NCPO_U3_OFST             (0)
1180
1181 //U3D_reg13
1182 #define RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST           (0)
1183
1184 //U3D_reg14
1185 #define RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST           (0)
1186
1187 //U3D_reg15
1188 #define RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST           (0)
1189
1190 //U3D_reg16
1191 #define RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST           (0)
1192
1193 //U3D_reg19
1194 #define RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST         (16)
1195 #define RG_SSUSB_PLL_SSC_DELTA1_U3_OFST           (0)
1196
1197 //U3D_reg20
1198 #define RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST         (16)
1199 #define RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST         (0)
1200
1201 //U3D_reg21
1202 #define RG_SSUSB_PLL_SSC_DELTA_U3_OFST            (16)
1203 #define RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST         (0)
1204
1205 //U3D_reg23
1206 #define RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST          (16)
1207 #define RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST          (0)
1208
1209 //U3D_reg25
1210 #define RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST          (16)
1211 #define RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST          (0)
1212
1213 //U3D_reg26
1214 #define RG_SSUSB_PLL_REFCKDIV_PE2D_OFST           (25)
1215 #define RG_SSUSB_PLL_REFCKDIV_PE2H_OFST           (24)
1216 #define RG_SSUSB_PLL_REFCKDIV_PE1D_OFST           (16)
1217 #define RG_SSUSB_PLL_REFCKDIV_PE1H_OFST           (8)
1218 #define RG_SSUSB_PLL_REFCKDIV_U3_OFST             (0)
1219
1220 //U3D_reg28
1221 #define RG_SSUSB_CDR_BPA_PE2D_OFST                (24)
1222 #define RG_SSUSB_CDR_BPA_PE2H_OFST                (16)
1223 #define RG_SSUSB_CDR_BPA_PE1D_OFST                (10)
1224 #define RG_SSUSB_CDR_BPA_PE1H_OFST                (8)
1225 #define RG_SSUSB_CDR_BPA_U3_OFST                  (0)
1226
1227 //U3D_reg29
1228 #define RG_SSUSB_CDR_BPB_PE2D_OFST                (24)
1229 #define RG_SSUSB_CDR_BPB_PE2H_OFST                (16)
1230 #define RG_SSUSB_CDR_BPB_PE1D_OFST                (6)
1231 #define RG_SSUSB_CDR_BPB_PE1H_OFST                (3)
1232 #define RG_SSUSB_CDR_BPB_U3_OFST                  (0)
1233
1234 //U3D_reg30
1235 #define RG_SSUSB_CDR_BR_PE2D_OFST                 (24)
1236 #define RG_SSUSB_CDR_BR_PE2H_OFST                 (16)
1237 #define RG_SSUSB_CDR_BR_PE1D_OFST                 (6)
1238 #define RG_SSUSB_CDR_BR_PE1H_OFST                 (3)
1239 #define RG_SSUSB_CDR_BR_U3_OFST                   (0)
1240
1241 //U3D_reg31
1242 #define RG_SSUSB_CDR_FBDIV_PE2H_OFST              (24)
1243 #define RG_SSUSB_CDR_FBDIV_PE1D_OFST              (16)
1244 #define RG_SSUSB_CDR_FBDIV_PE1H_OFST              (8)
1245 #define RG_SSUSB_CDR_FBDIV_U3_OFST                (0)
1246
1247 //U3D_reg32
1248 #define RG_SSUSB_EQ_RSTEP1_PE2D_OFST              (30)
1249 #define RG_SSUSB_EQ_RSTEP1_PE2H_OFST              (28)
1250 #define RG_SSUSB_EQ_RSTEP1_PE1D_OFST              (26)
1251 #define RG_SSUSB_EQ_RSTEP1_PE1H_OFST              (24)
1252 #define RG_SSUSB_EQ_RSTEP1_U3_OFST                (22)
1253 #define RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST          (20)
1254 #define RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST          (18)
1255 #define RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST          (16)
1256 #define RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST          (14)
1257 #define RG_SSUSB_LFPS_DEGLITCH_U3_OFST            (12)
1258 #define RG_SSUSB_CDR_KVSEL_PE2D_OFST              (11)
1259 #define RG_SSUSB_CDR_KVSEL_PE2H_OFST              (10)
1260 #define RG_SSUSB_CDR_KVSEL_PE1D_OFST              (9)
1261 #define RG_SSUSB_CDR_KVSEL_PE1H_OFST              (8)
1262 #define RG_SSUSB_CDR_KVSEL_U3_OFST                (7)
1263 #define RG_SSUSB_CDR_FBDIV_PE2D_OFST              (0)
1264
1265 //U3D_reg33
1266 #define RG_SSUSB_RX_CMPWD_PE2D_OFST               (26)
1267 #define RG_SSUSB_RX_CMPWD_PE2H_OFST               (25)
1268 #define RG_SSUSB_RX_CMPWD_PE1D_OFST               (24)
1269 #define RG_SSUSB_RX_CMPWD_PE1H_OFST               (23)
1270 #define RG_SSUSB_RX_CMPWD_U3_OFST                 (16)
1271 #define RG_SSUSB_EQ_RSTEP2_PE2D_OFST              (8)
1272 #define RG_SSUSB_EQ_RSTEP2_PE2H_OFST              (6)
1273 #define RG_SSUSB_EQ_RSTEP2_PE1D_OFST              (4)
1274 #define RG_SSUSB_EQ_RSTEP2_PE1H_OFST              (2)
1275 #define RG_SSUSB_EQ_RSTEP2_U3_OFST                (0)
1276
1277
1278 ///////////////////////////////////////////////////////////////////////////////
1279
1280 struct u3phyd_reg {
1281         //0x0
1282         PHY_LE32 phyd_mix0;
1283         PHY_LE32 phyd_mix1;
1284         PHY_LE32 phyd_lfps0;
1285         PHY_LE32 phyd_lfps1;
1286         //0x10
1287         PHY_LE32 phyd_impcal0;
1288         PHY_LE32 phyd_impcal1;
1289         PHY_LE32 phyd_txpll0;
1290         PHY_LE32 phyd_txpll1;
1291         //0x20
1292         PHY_LE32 phyd_txpll2;
1293         PHY_LE32 phyd_fl0;
1294         PHY_LE32 phyd_mix2;
1295         PHY_LE32 phyd_rx0;
1296         //0x30
1297         PHY_LE32 phyd_t2rlb;
1298         PHY_LE32 phyd_cppat;
1299         PHY_LE32 phyd_mix3;
1300         PHY_LE32 phyd_ebufctl;
1301         //0x40
1302         PHY_LE32 phyd_pipe0;
1303         PHY_LE32 phyd_pipe1;
1304         PHY_LE32 phyd_mix4;
1305         PHY_LE32 phyd_ckgen0;
1306         //0x50
1307         PHY_LE32 phyd_mix5;
1308         PHY_LE32 phyd_reserved;
1309         PHY_LE32 phyd_cdr0;
1310         PHY_LE32 phyd_cdr1;
1311         //0x60
1312         PHY_LE32 phyd_pll_0;
1313         PHY_LE32 phyd_pll_1;
1314         PHY_LE32 phyd_bcn_det_1;
1315         PHY_LE32 phyd_bcn_det_2;
1316         //0x70
1317         PHY_LE32 eq0;
1318         PHY_LE32 eq1;
1319         PHY_LE32 eq2;
1320         PHY_LE32 eq3;
1321         //0x80
1322         PHY_LE32 eq_eye0;
1323         PHY_LE32 eq_eye1;
1324         PHY_LE32 eq_eye2;
1325         PHY_LE32 eq_dfe0;
1326         //0x90
1327         PHY_LE32 eq_dfe1;
1328         PHY_LE32 eq_dfe2;
1329         PHY_LE32 eq_dfe3;
1330         PHY_LE32 reserve0;
1331         //0xa0
1332         PHY_LE32 phyd_mon0;
1333         PHY_LE32 phyd_mon1;
1334         PHY_LE32 phyd_mon2;
1335         PHY_LE32 phyd_mon3;
1336         //0xb0
1337         PHY_LE32 phyd_mon4;
1338         PHY_LE32 phyd_mon5;
1339         PHY_LE32 phyd_mon6;
1340         PHY_LE32 phyd_mon7;
1341         //0xc0
1342         PHY_LE32 phya_rx_mon0;
1343         PHY_LE32 phya_rx_mon1;
1344         PHY_LE32 phya_rx_mon2;
1345         PHY_LE32 phya_rx_mon3;
1346         //0xd0
1347         PHY_LE32 phya_rx_mon4;
1348         PHY_LE32 phya_rx_mon5;
1349         PHY_LE32 phyd_cppat2;
1350         PHY_LE32 eq_eye3;
1351         //0xe0
1352         PHY_LE32 kband_out;
1353         PHY_LE32 kband_out1;
1354 };
1355
1356 //U3D_PHYD_MIX0
1357 #define RG_SSUSB_P_P3_TX_NG                       (0x1<<31) //31:31
1358 #define RG_SSUSB_TSEQ_EN                          (0x1<<30) //30:30
1359 #define RG_SSUSB_TSEQ_POLEN                       (0x1<<29) //29:29
1360 #define RG_SSUSB_TSEQ_POL                         (0x1<<28) //28:28
1361 #define RG_SSUSB_P_P3_PCLK_NG                     (0x1<<27) //27:27
1362 #define RG_SSUSB_TSEQ_TH                          (0x7<<24) //26:24
1363 #define RG_SSUSB_PRBS_BERTH                       (0xff<<16) //23:16
1364 #define RG_SSUSB_DISABLE_PHY_U2_ON                (0x1<<15) //15:15
1365 #define RG_SSUSB_DISABLE_PHY_U2_OFF               (0x1<<14) //14:14
1366 #define RG_SSUSB_PRBS_EN                          (0x1<<13) //13:13
1367 #define RG_SSUSB_BPSLOCK                          (0x1<<12) //12:12
1368 #define RG_SSUSB_RTCOMCNT                         (0xf<<8) //11:8
1369 #define RG_SSUSB_COMCNT                           (0xf<<4) //7:4
1370 #define RG_SSUSB_PRBSEL_CALIB                     (0xf<<0) //3:0
1371
1372 //U3D_PHYD_MIX1
1373 #define RG_SSUSB_SLEEP_EN                         (0x1<<31) //31:31
1374 #define RG_SSUSB_PRBSEL_PCS                       (0x7<<28) //30:28
1375 #define RG_SSUSB_TXLFPS_PRD                       (0xf<<24) //27:24
1376 #define RG_SSUSB_P_RX_P0S_CK                      (0x1<<23) //23:23
1377 #define RG_SSUSB_P_TX_P0S_CK                      (0x1<<22) //22:22
1378 #define RG_SSUSB_PDNCTL                           (0x3f<<16) //21:16
1379 #define RG_SSUSB_TX_DRV_EN                        (0x1<<15) //15:15
1380 #define RG_SSUSB_TX_DRV_SEL                       (0x1<<14) //14:14
1381 #define RG_SSUSB_TX_DRV_DLY                       (0x3f<<8) //13:8
1382 #define RG_SSUSB_BERT_EN                          (0x1<<7) //7:7
1383 #define RG_SSUSB_SCP_TH                           (0x7<<4) //6:4
1384 #define RG_SSUSB_SCP_EN                           (0x1<<3) //3:3
1385 #define RG_SSUSB_RXANSIDEC_TEST                   (0x7<<0) //2:0
1386
1387 //U3D_PHYD_LFPS0
1388 #define RG_SSUSB_LFPS_PWD                         (0x1<<30) //30:30
1389 #define RG_SSUSB_FORCE_LFPS_PWD                   (0x1<<29) //29:29
1390 #define RG_SSUSB_RXLFPS_OVF                       (0x1f<<24) //28:24
1391 #define RG_SSUSB_P3_ENTRY_SEL                     (0x1<<23) //23:23
1392 #define RG_SSUSB_P3_ENTRY                         (0x1<<22) //22:22
1393 #define RG_SSUSB_RXLFPS_CDRSEL                    (0x3<<20) //21:20
1394 #define RG_SSUSB_RXLFPS_CDRTH                     (0xf<<16) //19:16
1395 #define RG_SSUSB_LOCK5G_BLOCK                     (0x1<<15) //15:15
1396 #define RG_SSUSB_TFIFO_EXT_D_SEL                  (0x1<<14) //14:14
1397 #define RG_SSUSB_TFIFO_NO_EXTEND                  (0x1<<13) //13:13
1398 #define RG_SSUSB_RXLFPS_LOB                       (0x1f<<8) //12:8
1399 #define RG_SSUSB_TXLFPS_EN                        (0x1<<7) //7:7
1400 #define RG_SSUSB_TXLFPS_SEL                       (0x1<<6) //6:6
1401 #define RG_SSUSB_RXLFPS_CDRLOCK                   (0x1<<5) //5:5
1402 #define RG_SSUSB_RXLFPS_UPB                       (0x1f<<0) //4:0
1403
1404 //U3D_PHYD_LFPS1
1405 #define RG_SSUSB_RX_IMP_BIAS                      (0xf<<28) //31:28
1406 #define RG_SSUSB_TX_IMP_BIAS                      (0xf<<24) //27:24
1407 #define RG_SSUSB_FWAKE_TH                         (0x3f<<16) //21:16
1408 #define RG_SSUSB_RXLFPS_UDF                       (0x1f<<8) //12:8
1409 #define RG_SSUSB_RXLFPS_P0IDLETH                  (0xff<<0) //7:0
1410
1411 //U3D_PHYD_IMPCAL0
1412 #define RG_SSUSB_FORCE_TX_IMPSEL                  (0x1<<31) //31:31
1413 #define RG_SSUSB_TX_IMPCAL_EN                     (0x1<<30) //30:30
1414 #define RG_SSUSB_FORCE_TX_IMPCAL_EN               (0x1<<29) //29:29
1415 #define RG_SSUSB_TX_IMPSEL                        (0x1f<<24) //28:24
1416 #define RG_SSUSB_TX_IMPCAL_CALCYC                 (0x3f<<16) //21:16
1417 #define RG_SSUSB_TX_IMPCAL_STBCYC                 (0x1f<<10) //14:10
1418 #define RG_SSUSB_TX_IMPCAL_CYCCNT                 (0x3ff<<0) //9:0
1419
1420 //U3D_PHYD_IMPCAL1
1421 #define RG_SSUSB_FORCE_RX_IMPSEL                  (0x1<<31) //31:31
1422 #define RG_SSUSB_RX_IMPCAL_EN                     (0x1<<30) //30:30
1423 #define RG_SSUSB_FORCE_RX_IMPCAL_EN               (0x1<<29) //29:29
1424 #define RG_SSUSB_RX_IMPSEL                        (0x1f<<24) //28:24
1425 #define RG_SSUSB_RX_IMPCAL_CALCYC                 (0x3f<<16) //21:16
1426 #define RG_SSUSB_RX_IMPCAL_STBCYC                 (0x1f<<10) //14:10
1427 #define RG_SSUSB_RX_IMPCAL_CYCCNT                 (0x3ff<<0) //9:0
1428
1429 //U3D_PHYD_TXPLL0
1430 #define RG_SSUSB_TXPLL_DDSEN_CYC                  (0x1f<<27) //31:27
1431 #define RG_SSUSB_TXPLL_ON                         (0x1<<26) //26:26
1432 #define RG_SSUSB_FORCE_TXPLLON                    (0x1<<25) //25:25
1433 #define RG_SSUSB_TXPLL_STBCYC                     (0x1ff<<16) //24:16
1434 #define RG_SSUSB_TXPLL_NCPOCHG_CYC                (0xf<<12) //15:12
1435 #define RG_SSUSB_TXPLL_NCPOEN_CYC                 (0x3<<10) //11:10
1436 #define RG_SSUSB_TXPLL_DDSRSTB_CYC                (0x7<<0) //2:0
1437
1438 //U3D_PHYD_TXPLL1
1439 #define RG_SSUSB_PLL_NCPO_EN                      (0x1<<31) //31:31
1440 #define RG_SSUSB_PLL_FIFO_START_MAN               (0x1<<30) //30:30
1441 #define RG_SSUSB_PLL_NCPO_CHG                     (0x1<<28) //28:28
1442 #define RG_SSUSB_PLL_DDS_RSTB                     (0x1<<27) //27:27
1443 #define RG_SSUSB_PLL_DDS_PWDB                     (0x1<<26) //26:26
1444 #define RG_SSUSB_PLL_DDSEN                        (0x1<<25) //25:25
1445 #define RG_SSUSB_PLL_AUTOK_VCO                    (0x1<<24) //24:24
1446 #define RG_SSUSB_PLL_PWD                          (0x1<<23) //23:23
1447 #define RG_SSUSB_RX_AFE_PWD                       (0x1<<22) //22:22
1448 #define RG_SSUSB_PLL_TCADJ                        (0x3f<<16) //21:16
1449 #define RG_SSUSB_FORCE_CDR_TCADJ                  (0x1<<15) //15:15
1450 #define RG_SSUSB_FORCE_CDR_AUTOK_VCO              (0x1<<14) //14:14
1451 #define RG_SSUSB_FORCE_CDR_PWD                    (0x1<<13) //13:13
1452 #define RG_SSUSB_FORCE_PLL_NCPO_EN                (0x1<<12) //12:12
1453 #define RG_SSUSB_FORCE_PLL_FIFO_START_MAN         (0x1<<11) //11:11
1454 #define RG_SSUSB_FORCE_PLL_NCPO_CHG               (0x1<<9) //9:9
1455 #define RG_SSUSB_FORCE_PLL_DDS_RSTB               (0x1<<8) //8:8
1456 #define RG_SSUSB_FORCE_PLL_DDS_PWDB               (0x1<<7) //7:7
1457 #define RG_SSUSB_FORCE_PLL_DDSEN                  (0x1<<6) //6:6
1458 #define RG_SSUSB_FORCE_PLL_TCADJ                  (0x1<<5) //5:5
1459 #define RG_SSUSB_FORCE_PLL_AUTOK_VCO              (0x1<<4) //4:4
1460 #define RG_SSUSB_FORCE_PLL_PWD                    (0x1<<3) //3:3
1461 #define RG_SSUSB_FLT_1_DISPERR_B                  (0x1<<2) //2:2
1462
1463 //U3D_PHYD_TXPLL2
1464 #define RG_SSUSB_TX_LFPS_EN                       (0x1<<31) //31:31
1465 #define RG_SSUSB_FORCE_TX_LFPS_EN                 (0x1<<30) //30:30
1466 #define RG_SSUSB_TX_LFPS                          (0x1<<29) //29:29
1467 #define RG_SSUSB_FORCE_TX_LFPS                    (0x1<<28) //28:28
1468 #define RG_SSUSB_RXPLL_STB                        (0x1<<27) //27:27
1469 #define RG_SSUSB_TXPLL_STB                        (0x1<<26) //26:26
1470 #define RG_SSUSB_FORCE_RXPLL_STB                  (0x1<<25) //25:25
1471 #define RG_SSUSB_FORCE_TXPLL_STB                  (0x1<<24) //24:24
1472 #define RG_SSUSB_RXPLL_REFCKSEL                   (0x1<<16) //16:16
1473 #define RG_SSUSB_RXPLL_STBMODE                    (0x1<<11) //11:11
1474 #define RG_SSUSB_RXPLL_ON                         (0x1<<10) //10:10
1475 #define RG_SSUSB_FORCE_RXPLLON                    (0x1<<9) //9:9
1476 #define RG_SSUSB_FORCE_RX_AFE_PWD                 (0x1<<8) //8:8
1477 #define RG_SSUSB_CDR_AUTOK_VCO                    (0x1<<7) //7:7
1478 #define RG_SSUSB_CDR_PWD                          (0x1<<6) //6:6
1479 #define RG_SSUSB_CDR_TCADJ                        (0x3f<<0) //5:0
1480
1481 //U3D_PHYD_FL0
1482 #define RG_SSUSB_RX_FL_TARGET                     (0xffff<<16) //31:16
1483 #define RG_SSUSB_RX_FL_CYCLECNT                   (0xffff<<0) //15:0
1484
1485 //U3D_PHYD_MIX2
1486 #define RG_SSUSB_RX_EQ_RST                        (0x1<<31) //31:31
1487 #define RG_SSUSB_RX_EQ_RST_SEL                    (0x1<<30) //30:30
1488 #define RG_SSUSB_RXVAL_RST                        (0x1<<29) //29:29
1489 #define RG_SSUSB_RXVAL_CNT                        (0x1f<<24) //28:24
1490 #define RG_SSUSB_CDROS_EN                         (0x1<<18) //18:18
1491 #define RG_SSUSB_CDR_LCKOP                        (0x3<<16) //17:16
1492 #define RG_SSUSB_RX_FL_LOCKTH                     (0xf<<8) //11:8
1493 #define RG_SSUSB_RX_FL_OFFSET                     (0xff<<0) //7:0
1494
1495 //U3D_PHYD_RX0
1496 #define RG_SSUSB_T2RLB_BERTH                      (0xff<<24) //31:24
1497 #define RG_SSUSB_T2RLB_PAT                        (0xff<<16) //23:16
1498 #define RG_SSUSB_T2RLB_EN                         (0x1<<15) //15:15
1499 #define RG_SSUSB_T2RLB_BPSCRAMB                   (0x1<<14) //14:14
1500 #define RG_SSUSB_T2RLB_SERIAL                     (0x1<<13) //13:13
1501 #define RG_SSUSB_T2RLB_MODE                       (0x3<<11) //12:11
1502 #define RG_SSUSB_RX_SAOSC_EN                      (0x1<<10) //10:10
1503 #define RG_SSUSB_RX_SAOSC_EN_SEL                  (0x1<<9) //9:9
1504 #define RG_SSUSB_RX_DFE_OPTION                    (0x1<<8) //8:8
1505 #define RG_SSUSB_RX_DFE_EN                        (0x1<<7) //7:7
1506 #define RG_SSUSB_RX_DFE_EN_SEL                    (0x1<<6) //6:6
1507 #define RG_SSUSB_RX_EQ_EN                         (0x1<<5) //5:5
1508 #define RG_SSUSB_RX_EQ_EN_SEL                     (0x1<<4) //4:4
1509 #define RG_SSUSB_RX_SAOSC_RST                     (0x1<<3) //3:3
1510 #define RG_SSUSB_RX_SAOSC_RST_SEL                 (0x1<<2) //2:2
1511 #define RG_SSUSB_RX_DFE_RST                       (0x1<<1) //1:1
1512 #define RG_SSUSB_RX_DFE_RST_SEL                   (0x1<<0) //0:0
1513
1514 //U3D_PHYD_T2RLB
1515 #define RG_SSUSB_EQTRAIN_CH_MODE                  (0x1<<28) //28:28
1516 #define RG_SSUSB_PRB_OUT_CPPAT                    (0x1<<27) //27:27
1517 #define RG_SSUSB_BPANSIENC                        (0x1<<26) //26:26
1518 #define RG_SSUSB_VALID_EN                         (0x1<<25) //25:25
1519 #define RG_SSUSB_EBUF_SRST                        (0x1<<24) //24:24
1520 #define RG_SSUSB_K_EMP                            (0xf<<20) //23:20
1521 #define RG_SSUSB_K_FUL                            (0xf<<16) //19:16
1522 #define RG_SSUSB_T2RLB_BDATRST                    (0xf<<12) //15:12
1523 #define RG_SSUSB_P_T2RLB_SKP_EN                   (0x1<<10) //10:10
1524 #define RG_SSUSB_T2RLB_PATMODE                    (0x3<<8) //9:8
1525 #define RG_SSUSB_T2RLB_TSEQCNT                    (0xff<<0) //7:0
1526
1527 //U3D_PHYD_CPPAT
1528 #define RG_SSUSB_CPPAT_PROGRAM_EN                 (0x1<<24) //24:24
1529 #define RG_SSUSB_CPPAT_TOZ                        (0x3<<21) //22:21
1530 #define RG_SSUSB_CPPAT_PRBS_EN                    (0x1<<20) //20:20
1531 #define RG_SSUSB_CPPAT_OUT_TMP2                   (0xf<<16) //19:16
1532 #define RG_SSUSB_CPPAT_OUT_TMP1                   (0xff<<8) //15:8
1533 #define RG_SSUSB_CPPAT_OUT_TMP0                   (0xff<<0) //7:0
1534
1535 //U3D_PHYD_MIX3
1536 #define RG_SSUSB_CDR_TCADJ_MINUS                  (0x1<<31) //31:31
1537 #define RG_SSUSB_P_CDROS_EN                       (0x1<<30) //30:30
1538 #define RG_SSUSB_P_P2_TX_DRV_DIS                  (0x1<<28) //28:28
1539 #define RG_SSUSB_CDR_TCADJ_OFFSET                 (0x7<<24) //26:24
1540 #define RG_SSUSB_PLL_TCADJ_MINUS                  (0x1<<23) //23:23
1541 #define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN            (0x1<<20) //20:20
1542 #define RG_SSUSB_PLL_BIAS_LPF_EN                  (0x1<<19) //19:19
1543 #define RG_SSUSB_PLL_TCADJ_OFFSET                 (0x7<<16) //18:16
1544 #define RG_SSUSB_FORCE_PLL_SSCEN                  (0x1<<15) //15:15
1545 #define RG_SSUSB_PLL_SSCEN                        (0x1<<14) //14:14
1546 #define RG_SSUSB_FORCE_CDR_PI_PWD                 (0x1<<13) //13:13
1547 #define RG_SSUSB_CDR_PI_PWD                       (0x1<<12) //12:12
1548 #define RG_SSUSB_CDR_PI_MODE                      (0x1<<11) //11:11
1549 #define RG_SSUSB_TXPLL_SSCEN_CYC                  (0x3ff<<0) //9:0
1550
1551 //U3D_PHYD_EBUFCTL
1552 #define RG_SSUSB_EBUFCTL                          (0xffffffff<<0) //31:0
1553
1554 //U3D_PHYD_PIPE0
1555 #define RG_SSUSB_RXTERMINATION                    (0x1<<30) //30:30
1556 #define RG_SSUSB_RXEQTRAINING                     (0x1<<29) //29:29
1557 #define RG_SSUSB_RXPOLARITY                       (0x1<<28) //28:28
1558 #define RG_SSUSB_TXDEEMPH                         (0x3<<26) //27:26
1559 #define RG_SSUSB_POWERDOWN                        (0x3<<24) //25:24
1560 #define RG_SSUSB_TXONESZEROS                      (0x1<<23) //23:23
1561 #define RG_SSUSB_TXELECIDLE                       (0x1<<22) //22:22
1562 #define RG_SSUSB_TXDETECTRX                       (0x1<<21) //21:21
1563 #define RG_SSUSB_PIPE_SEL                         (0x1<<20) //20:20
1564 #define RG_SSUSB_TXDATAK                          (0xf<<16) //19:16
1565 #define RG_SSUSB_CDR_STABLE_SEL                   (0x1<<15) //15:15
1566 #define RG_SSUSB_CDR_STABLE                       (0x1<<14) //14:14
1567 #define RG_SSUSB_CDR_RSTB_SEL                     (0x1<<13) //13:13
1568 #define RG_SSUSB_CDR_RSTB                         (0x1<<12) //12:12
1569 #define RG_SSUSB_P_ERROR_SEL                      (0x3<<4) //5:4
1570 #define RG_SSUSB_TXMARGIN                         (0x7<<1) //3:1
1571 #define RG_SSUSB_TXCOMPLIANCE                     (0x1<<0) //0:0
1572
1573 //U3D_PHYD_PIPE1
1574 #define RG_SSUSB_TXDATA                           (0xffffffff<<0) //31:0
1575
1576 //U3D_PHYD_MIX4
1577 #define RG_SSUSB_CDROS_CNT                        (0x3f<<24) //29:24
1578 #define RG_SSUSB_T2RLB_BER_EN                     (0x1<<16) //16:16
1579 #define RG_SSUSB_T2RLB_BER_RATE                   (0xffff<<0) //15:0
1580
1581 //U3D_PHYD_CKGEN0
1582 #define RG_SSUSB_RFIFO_IMPLAT                     (0x1<<27) //27:27
1583 #define RG_SSUSB_TFIFO_PSEL                       (0x7<<24) //26:24
1584 #define RG_SSUSB_CKGEN_PSEL                       (0x3<<8) //9:8
1585 #define RG_SSUSB_RXCK_INV                         (0x1<<0) //0:0
1586
1587 //U3D_PHYD_MIX5
1588 #define RG_SSUSB_PRB_SEL                          (0xffff<<16) //31:16
1589 #define RG_SSUSB_RXPLL_STBCYC                     (0x7ff<<0) //10:0
1590
1591 //U3D_PHYD_RESERVED
1592 #define RG_SSUSB_PHYD_RESERVE                     (0xffffffff<<0) //31:0
1593 //#define RG_SSUSB_RX_SIGDET_SEL                    (0x1<<11)
1594 //#define RG_SSUSB_RX_SIGDET_EN                     (0x1<<12)
1595 //#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL             (0x1<<9)
1596 //#define RG_SSUSB_RX_PI_CAL_MANUAL_EN              (0x1<<10)
1597
1598 //U3D_PHYD_CDR0
1599 #define RG_SSUSB_CDR_BIC_LTR                      (0xf<<28) //31:28
1600 #define RG_SSUSB_CDR_BIC_LTD0                     (0xf<<24) //27:24
1601 #define RG_SSUSB_CDR_BC_LTD1                      (0x1f<<16) //20:16
1602 #define RG_SSUSB_CDR_BC_LTR                       (0x1f<<8) //12:8
1603 #define RG_SSUSB_CDR_BC_LTD0                      (0x1f<<0) //4:0
1604
1605 //U3D_PHYD_CDR1
1606 #define RG_SSUSB_CDR_BIR_LTD1                     (0x1f<<24) //28:24
1607 #define RG_SSUSB_CDR_BIR_LTR                      (0x1f<<16) //20:16
1608 #define RG_SSUSB_CDR_BIR_LTD0                     (0x1f<<8) //12:8
1609 #define RG_SSUSB_CDR_BW_SEL                       (0x3<<6) //7:6
1610 #define RG_SSUSB_CDR_BIC_LTD1                     (0xf<<0) //3:0
1611
1612 //U3D_PHYD_PLL_0
1613 #define RG_SSUSB_FORCE_CDR_BAND_5G                (0x1<<28) //28:28
1614 #define RG_SSUSB_FORCE_CDR_BAND_2P5G              (0x1<<27) //27:27
1615 #define RG_SSUSB_FORCE_PLL_BAND_5G                (0x1<<26) //26:26
1616 #define RG_SSUSB_FORCE_PLL_BAND_2P5G              (0x1<<25) //25:25
1617 #define RG_SSUSB_P_EQ_T_SEL                       (0x3ff<<15) //24:15
1618 #define RG_SSUSB_PLL_ISO_EN_CYC                   (0x3ff<<5) //14:5
1619 #define RG_SSUSB_PLLBAND_RECAL                    (0x1<<4) //4:4
1620 #define RG_SSUSB_PLL_DDS_ISO_EN                   (0x1<<3) //3:3
1621 #define RG_SSUSB_FORCE_PLL_DDS_ISO_EN             (0x1<<2) //2:2
1622 #define RG_SSUSB_PLL_DDS_PWR_ON                   (0x1<<1) //1:1
1623 #define RG_SSUSB_FORCE_PLL_DDS_PWR_ON             (0x1<<0) //0:0
1624
1625 //U3D_PHYD_PLL_1
1626 #define RG_SSUSB_CDR_BAND_5G                      (0xff<<24) //31:24
1627 #define RG_SSUSB_CDR_BAND_2P5G                    (0xff<<16) //23:16
1628 #define RG_SSUSB_PLL_BAND_5G                      (0xff<<8) //15:8
1629 #define RG_SSUSB_PLL_BAND_2P5G                    (0xff<<0) //7:0
1630
1631 //U3D_PHYD_BCN_DET_1
1632 #define RG_SSUSB_P_BCN_OBS_PRD                    (0xffff<<16) //31:16
1633 #define RG_SSUSB_U_BCN_OBS_PRD                    (0xffff<<0) //15:0
1634
1635 //U3D_PHYD_BCN_DET_2
1636 #define RG_SSUSB_P_BCN_OBS_SEL                    (0xfff<<16) //27:16
1637 #define RG_SSUSB_BCN_DET_DIS                      (0x1<<12) //12:12
1638 #define RG_SSUSB_U_BCN_OBS_SEL                    (0xfff<<0) //11:0
1639
1640 //U3D_EQ0
1641 #define RG_SSUSB_EQ_DLHL_LFI                      (0x7f<<24) //30:24
1642 #define RG_SSUSB_EQ_DHHL_LFI                      (0x7f<<16) //22:16
1643 #define RG_SSUSB_EQ_DD0HOS_LFI                    (0x7f<<8) //14:8
1644 #define RG_SSUSB_EQ_DD0LOS_LFI                    (0x7f<<0) //6:0
1645
1646 //U3D_EQ1
1647 #define RG_SSUSB_EQ_DD1HOS_LFI                    (0x7f<<24) //30:24
1648 #define RG_SSUSB_EQ_DD1LOS_LFI                    (0x7f<<16) //22:16
1649 #define RG_SSUSB_EQ_DE0OS_LFI                     (0x7f<<8) //14:8
1650 #define RG_SSUSB_EQ_DE1OS_LFI                     (0x7f<<0) //6:0
1651
1652 //U3D_EQ2
1653 #define RG_SSUSB_EQ_DLHLOS_LFI                    (0x7f<<24) //30:24
1654 #define RG_SSUSB_EQ_DHHLOS_LFI                    (0x7f<<16) //22:16
1655 #define RG_SSUSB_EQ_STOPTIME                      (0x1<<14) //14:14
1656 #define RG_SSUSB_EQ_DHHL_LF_SEL                   (0x7<<11) //13:11
1657 #define RG_SSUSB_EQ_DSAOS_LF_SEL                  (0x7<<8) //10:8
1658 #define RG_SSUSB_EQ_STARTTIME                     (0x3<<6) //7:6
1659 #define RG_SSUSB_EQ_DLEQ_LF_SEL                   (0x7<<3) //5:3
1660 #define RG_SSUSB_EQ_DLHL_LF_SEL                   (0x7<<0) //2:0
1661
1662 //U3D_EQ3
1663 #define RG_SSUSB_EQ_DLEQ_LFI_GEN2                 (0xf<<28) //31:28
1664 #define RG_SSUSB_EQ_DLEQ_LFI_GEN1                 (0xf<<24) //27:24
1665 #define RG_SSUSB_EQ_DEYE0OS_LFI                   (0x7f<<16) //22:16
1666 #define RG_SSUSB_EQ_DEYE1OS_LFI                   (0x7f<<8) //14:8
1667 #define RG_SSUSB_EQ_TRI_DET_EN                    (0x1<<7) //7:7
1668 #define RG_SSUSB_EQ_TRI_DET_TH                    (0x7f<<0) //6:0
1669
1670 //U3D_EQ_EYE0
1671 #define RG_SSUSB_EQ_EYE_XOFFSET                   (0x7f<<25) //31:25
1672 #define RG_SSUSB_EQ_EYE_MON_EN                    (0x1<<24) //24:24
1673 #define RG_SSUSB_EQ_EYE0_Y                        (0x7f<<16) //22:16
1674 #define RG_SSUSB_EQ_EYE1_Y                        (0x7f<<8) //14:8
1675 #define RG_SSUSB_EQ_PILPO_ROUT                    (0x1<<7) //7:7
1676 #define RG_SSUSB_EQ_PI_KPGAIN                     (0x7<<4) //6:4
1677 #define RG_SSUSB_EQ_EYE_CNT_EN                    (0x1<<3) //3:3
1678
1679 //U3D_EQ_EYE1
1680 #define RG_SSUSB_EQ_SIGDET                        (0x7f<<24) //30:24
1681 #define RG_SSUSB_EQ_EYE_MASK                      (0x3ff<<7) //16:7
1682
1683 //U3D_EQ_EYE2
1684 #define RG_SSUSB_EQ_RX500M_CK_SEL                 (0x1<<31) //31:31
1685 #define RG_SSUSB_EQ_SD_CNT1                       (0x3f<<24) //29:24
1686 #define RG_SSUSB_EQ_ISIFLAG_SEL                   (0x3<<22) //23:22
1687 #define RG_SSUSB_EQ_SD_CNT0                       (0x3f<<16) //21:16
1688
1689 //U3D_EQ_DFE0
1690 #define RG_SSUSB_EQ_LEQMAX                        (0xf<<28) //31:28
1691 #define RG_SSUSB_EQ_DFEX_EN                       (0x1<<27) //27:27
1692 #define RG_SSUSB_EQ_DFEX_LF_SEL                   (0x7<<24) //26:24
1693 #define RG_SSUSB_EQ_CHK_EYE_H                     (0x1<<23) //23:23
1694 #define RG_SSUSB_EQ_PIEYE_INI                     (0x7f<<16) //22:16
1695 #define RG_SSUSB_EQ_PI90_INI                      (0x7f<<8) //14:8
1696 #define RG_SSUSB_EQ_PI0_INI                       (0x7f<<0) //6:0
1697
1698 //U3D_EQ_DFE1
1699 #define RG_SSUSB_EQ_REV                           (0xffff<<16) //31:16
1700 #define RG_SSUSB_EQ_DFEYEN_DUR                    (0x7<<12) //14:12
1701 #define RG_SSUSB_EQ_DFEXEN_DUR                    (0x7<<8) //10:8
1702 #define RG_SSUSB_EQ_DFEX_RST                      (0x1<<7) //7:7
1703 #define RG_SSUSB_EQ_GATED_RXD_B                   (0x1<<6) //6:6
1704 #define RG_SSUSB_EQ_PI90CK_SEL                    (0x3<<4) //5:4
1705 #define RG_SSUSB_EQ_DFEX_DIS                      (0x1<<2) //2:2
1706 #define RG_SSUSB_EQ_DFEYEN_STOP_DIS               (0x1<<1) //1:1
1707 #define RG_SSUSB_EQ_DFEXEN_SEL                    (0x1<<0) //0:0
1708
1709 //U3D_EQ_DFE2
1710 #define RG_SSUSB_EQ_MON_SEL                       (0x1f<<24) //28:24
1711 #define RG_SSUSB_EQ_LEQOSC_DLYCNT                 (0x7<<16) //18:16
1712 #define RG_SSUSB_EQ_DLEQOS_LFI                    (0x1f<<8) //12:8
1713 #define RG_SSUSB_EQ_LEQ_STOP_TO                   (0x3<<0) //1:0
1714
1715 //U3D_EQ_DFE3
1716 #define RG_SSUSB_EQ_RESERVED                      (0xffffffff<<0) //31:0
1717
1718 //U3D_PHYD_MON0
1719 #define RGS_SSUSB_BERT_BERC                       (0xffff<<16) //31:16
1720 #define RGS_SSUSB_LFPS                            (0xf<<12) //15:12
1721 #define RGS_SSUSB_TRAINDEC                        (0x7<<8) //10:8
1722 #define RGS_SSUSB_SCP_PAT                         (0xff<<0) //7:0
1723
1724 //U3D_PHYD_MON1
1725 #define RGS_SSUSB_RX_FL_OUT                       (0xffff<<0) //15:0
1726
1727 //U3D_PHYD_MON2
1728 #define RGS_SSUSB_T2RLB_ERRCNT                    (0xffff<<16) //31:16
1729 #define RGS_SSUSB_RETRACK                         (0xf<<12) //15:12
1730 #define RGS_SSUSB_RXPLL_LOCK                      (0x1<<10) //10:10
1731 #define RGS_SSUSB_CDR_VCOCAL_CPLT_D               (0x1<<9) //9:9
1732 #define RGS_SSUSB_PLL_VCOCAL_CPLT_D               (0x1<<8) //8:8
1733 #define RGS_SSUSB_PDNCTL                          (0xff<<0) //7:0
1734
1735 //U3D_PHYD_MON3
1736 #define RGS_SSUSB_TSEQ_ERRCNT                     (0xffff<<16) //31:16
1737 #define RGS_SSUSB_PRBS_ERRCNT                     (0xffff<<0) //15:0
1738
1739 //U3D_PHYD_MON4
1740 #define RGS_SSUSB_RX_LSLOCK_CNT                   (0xf<<24) //27:24
1741 #define RGS_SSUSB_SCP_DETCNT                      (0xff<<16) //23:16
1742 #define RGS_SSUSB_TSEQ_DETCNT                     (0xffff<<0) //15:0
1743
1744 //U3D_PHYD_MON5
1745 #define RGS_SSUSB_EBUFMSG                         (0xffff<<16) //31:16
1746 #define RGS_SSUSB_BERT_LOCK                       (0x1<<15) //15:15
1747 #define RGS_SSUSB_SCP_DET                         (0x1<<14) //14:14
1748 #define RGS_SSUSB_TSEQ_DET                        (0x1<<13) //13:13
1749 #define RGS_SSUSB_EBUF_UDF                        (0x1<<12) //12:12
1750 #define RGS_SSUSB_EBUF_OVF                        (0x1<<11) //11:11
1751 #define RGS_SSUSB_PRBS_PASSTH                     (0x1<<10) //10:10
1752 #define RGS_SSUSB_PRBS_PASS                       (0x1<<9) //9:9
1753 #define RGS_SSUSB_PRBS_LOCK                       (0x1<<8) //8:8
1754 #define RGS_SSUSB_T2RLB_ERR                       (0x1<<6) //6:6
1755 #define RGS_SSUSB_T2RLB_PASSTH                    (0x1<<5) //5:5
1756 #define RGS_SSUSB_T2RLB_PASS                      (0x1<<4) //4:4
1757 #define RGS_SSUSB_T2RLB_LOCK                      (0x1<<3) //3:3
1758 #define RGS_SSUSB_RX_IMPCAL_DONE                  (0x1<<2) //2:2
1759 #define RGS_SSUSB_TX_IMPCAL_DONE                  (0x1<<1) //1:1
1760 #define RGS_SSUSB_RXDETECTED                      (0x1<<0) //0:0
1761
1762 //U3D_PHYD_MON6
1763 #define RGS_SSUSB_SIGCAL_DONE                     (0x1<<30) //30:30
1764 #define RGS_SSUSB_SIGCAL_CAL_OUT                  (0x1<<29) //29:29
1765 #define RGS_SSUSB_SIGCAL_OFFSET                   (0x1f<<24) //28:24
1766 #define RGS_SSUSB_RX_IMP_SEL                      (0x1f<<16) //20:16
1767 #define RGS_SSUSB_TX_IMP_SEL                      (0x1f<<8) //12:8
1768 #define RGS_SSUSB_TFIFO_MSG                       (0xf<<4) //7:4
1769 #define RGS_SSUSB_RFIFO_MSG                       (0xf<<0) //3:0
1770
1771 //U3D_PHYD_MON7
1772 #define RGS_SSUSB_FT_OUT                          (0xff<<8) //15:8
1773 #define RGS_SSUSB_PRB_OUT                         (0xff<<0) //7:0
1774
1775 //U3D_PHYA_RX_MON0
1776 #define RGS_SSUSB_EQ_DCLEQ                        (0xf<<24) //27:24
1777 #define RGS_SSUSB_EQ_DCD0H                        (0x7f<<16) //22:16
1778 #define RGS_SSUSB_EQ_DCD0L                        (0x7f<<8) //14:8
1779 #define RGS_SSUSB_EQ_DCD1H                        (0x7f<<0) //6:0
1780
1781 //U3D_PHYA_RX_MON1
1782 #define RGS_SSUSB_EQ_DCD1L                        (0x7f<<24) //30:24
1783 #define RGS_SSUSB_EQ_DCE0                         (0x7f<<16) //22:16
1784 #define RGS_SSUSB_EQ_DCE1                         (0x7f<<8) //14:8
1785 #define RGS_SSUSB_EQ_DCHHL                        (0x7f<<0) //6:0
1786
1787 //U3D_PHYA_RX_MON2
1788 #define RGS_SSUSB_EQ_LEQ_STOP                     (0x1<<31) //31:31
1789 #define RGS_SSUSB_EQ_DCLHL                        (0x7f<<24) //30:24
1790 #define RGS_SSUSB_EQ_STATUS                       (0xff<<16) //23:16
1791 #define RGS_SSUSB_EQ_DCEYE0                       (0x7f<<8) //14:8
1792 #define RGS_SSUSB_EQ_DCEYE1                       (0x7f<<0) //6:0
1793
1794 //U3D_PHYA_RX_MON3
1795 #define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0         (0xfffff<<0) //19:0
1796
1797 //U3D_PHYA_RX_MON4
1798 #define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1         (0xfffff<<0) //19:0
1799
1800 //U3D_PHYA_RX_MON5
1801 #define RGS_SSUSB_EQ_DCLEQOS                      (0x1f<<8) //12:8
1802 #define RGS_SSUSB_EQ_EYE_CNT_RDY                  (0x1<<7) //7:7
1803 #define RGS_SSUSB_EQ_PILPO                        (0x7f<<0) //6:0
1804
1805 //U3D_PHYD_CPPAT2
1806 #define RG_SSUSB_CPPAT_OUT_H_TMP2                 (0xf<<16) //19:16
1807 #define RG_SSUSB_CPPAT_OUT_H_TMP1                 (0xff<<8) //15:8
1808 #define RG_SSUSB_CPPAT_OUT_H_TMP0                 (0xff<<0) //7:0
1809
1810 //U3D_EQ_EYE3
1811 #define RG_SSUSB_EQ_LEQ_SHIFT                     (0x7<<24) //26:24
1812 #define RG_SSUSB_EQ_EYE_CNT                       (0xfffff<<0) //19:0
1813
1814 //U3D_KBAND_OUT
1815 #define RGS_SSUSB_CDR_BAND_5G                     (0xff<<24) //31:24
1816 #define RGS_SSUSB_CDR_BAND_2P5G                   (0xff<<16) //23:16
1817 #define RGS_SSUSB_PLL_BAND_5G                     (0xff<<8) //15:8
1818 #define RGS_SSUSB_PLL_BAND_2P5G                   (0xff<<0) //7:0
1819
1820 //U3D_KBAND_OUT1
1821 #define RGS_SSUSB_CDR_VCOCAL_FAIL                 (0x1<<24) //24:24
1822 #define RGS_SSUSB_CDR_VCOCAL_STATE                (0xff<<16) //23:16
1823 #define RGS_SSUSB_PLL_VCOCAL_FAIL                 (0x1<<8) //8:8
1824 #define RGS_SSUSB_PLL_VCOCAL_STATE                (0xff<<0) //7:0
1825
1826
1827 /* OFFSET */
1828
1829 //U3D_PHYD_MIX0
1830 #define RG_SSUSB_P_P3_TX_NG_OFST                  (31)
1831 #define RG_SSUSB_TSEQ_EN_OFST                     (30)
1832 #define RG_SSUSB_TSEQ_POLEN_OFST                  (29)
1833 #define RG_SSUSB_TSEQ_POL_OFST                    (28)
1834 #define RG_SSUSB_P_P3_PCLK_NG_OFST                (27)
1835 #define RG_SSUSB_TSEQ_TH_OFST                     (24)
1836 #define RG_SSUSB_PRBS_BERTH_OFST                  (16)
1837 #define RG_SSUSB_DISABLE_PHY_U2_ON_OFST           (15)
1838 #define RG_SSUSB_DISABLE_PHY_U2_OFF_OFST          (14)
1839 #define RG_SSUSB_PRBS_EN_OFST                     (13)
1840 #define RG_SSUSB_BPSLOCK_OFST                     (12)
1841 #define RG_SSUSB_RTCOMCNT_OFST                    (8)
1842 #define RG_SSUSB_COMCNT_OFST                      (4)
1843 #define RG_SSUSB_PRBSEL_CALIB_OFST                (0)
1844
1845 //U3D_PHYD_MIX1
1846 #define RG_SSUSB_SLEEP_EN_OFST                    (31)
1847 #define RG_SSUSB_PRBSEL_PCS_OFST                  (28)
1848 #define RG_SSUSB_TXLFPS_PRD_OFST                  (24)
1849 #define RG_SSUSB_P_RX_P0S_CK_OFST                 (23)
1850 #define RG_SSUSB_P_TX_P0S_CK_OFST                 (22)
1851 #define RG_SSUSB_PDNCTL_OFST                      (16)
1852 #define RG_SSUSB_TX_DRV_EN_OFST                   (15)
1853 #define RG_SSUSB_TX_DRV_SEL_OFST                  (14)
1854 #define RG_SSUSB_TX_DRV_DLY_OFST                  (8)
1855 #define RG_SSUSB_BERT_EN_OFST                     (7)
1856 #define RG_SSUSB_SCP_TH_OFST                      (4)
1857 #define RG_SSUSB_SCP_EN_OFST                      (3)
1858 #define RG_SSUSB_RXANSIDEC_TEST_OFST              (0)
1859
1860 //U3D_PHYD_LFPS0
1861 #define RG_SSUSB_LFPS_PWD_OFST                    (30)
1862 #define RG_SSUSB_FORCE_LFPS_PWD_OFST              (29)
1863 #define RG_SSUSB_RXLFPS_OVF_OFST                  (24)
1864 #define RG_SSUSB_P3_ENTRY_SEL_OFST                (23)
1865 #define RG_SSUSB_P3_ENTRY_OFST                    (22)
1866 #define RG_SSUSB_RXLFPS_CDRSEL_OFST               (20)
1867 #define RG_SSUSB_RXLFPS_CDRTH_OFST                (16)
1868 #define RG_SSUSB_LOCK5G_BLOCK_OFST                (15)
1869 #define RG_SSUSB_TFIFO_EXT_D_SEL_OFST             (14)
1870 #define RG_SSUSB_TFIFO_NO_EXTEND_OFST             (13)
1871 #define RG_SSUSB_RXLFPS_LOB_OFST                  (8)
1872 #define RG_SSUSB_TXLFPS_EN_OFST                   (7)
1873 #define RG_SSUSB_TXLFPS_SEL_OFST                  (6)
1874 #define RG_SSUSB_RXLFPS_CDRLOCK_OFST              (5)
1875 #define RG_SSUSB_RXLFPS_UPB_OFST                  (0)
1876
1877 //U3D_PHYD_LFPS1
1878 #define RG_SSUSB_RX_IMP_BIAS_OFST                 (28)
1879 #define RG_SSUSB_TX_IMP_BIAS_OFST                 (24)
1880 #define RG_SSUSB_FWAKE_TH_OFST                    (16)
1881 #define RG_SSUSB_RXLFPS_UDF_OFST                  (8)
1882 #define RG_SSUSB_RXLFPS_P0IDLETH_OFST             (0)
1883
1884 //U3D_PHYD_IMPCAL0
1885 #define RG_SSUSB_FORCE_TX_IMPSEL_OFST             (31)
1886 #define RG_SSUSB_TX_IMPCAL_EN_OFST                (30)
1887 #define RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST          (29)
1888 #define RG_SSUSB_TX_IMPSEL_OFST                   (24)
1889 #define RG_SSUSB_TX_IMPCAL_CALCYC_OFST            (16)
1890 #define RG_SSUSB_TX_IMPCAL_STBCYC_OFST            (10)
1891 #define RG_SSUSB_TX_IMPCAL_CYCCNT_OFST            (0)
1892
1893 //U3D_PHYD_IMPCAL1
1894 #define RG_SSUSB_FORCE_RX_IMPSEL_OFST             (31)
1895 #define RG_SSUSB_RX_IMPCAL_EN_OFST                (30)
1896 #define RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST          (29)
1897 #define RG_SSUSB_RX_IMPSEL_OFST                   (24)
1898 #define RG_SSUSB_RX_IMPCAL_CALCYC_OFST            (16)
1899 #define RG_SSUSB_RX_IMPCAL_STBCYC_OFST            (10)
1900 #define RG_SSUSB_RX_IMPCAL_CYCCNT_OFST            (0)
1901
1902 //U3D_PHYD_TXPLL0
1903 #define RG_SSUSB_TXPLL_DDSEN_CYC_OFST             (27)
1904 #define RG_SSUSB_TXPLL_ON_OFST                    (26)
1905 #define RG_SSUSB_FORCE_TXPLLON_OFST               (25)
1906 #define RG_SSUSB_TXPLL_STBCYC_OFST                (16)
1907 #define RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST           (12)
1908 #define RG_SSUSB_TXPLL_NCPOEN_CYC_OFST            (10)
1909 #define RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST           (0)
1910
1911 //U3D_PHYD_TXPLL1
1912 #define RG_SSUSB_PLL_NCPO_EN_OFST                 (31)
1913 #define RG_SSUSB_PLL_FIFO_START_MAN_OFST          (30)
1914 #define RG_SSUSB_PLL_NCPO_CHG_OFST                (28)
1915 #define RG_SSUSB_PLL_DDS_RSTB_OFST                (27)
1916 #define RG_SSUSB_PLL_DDS_PWDB_OFST                (26)
1917 #define RG_SSUSB_PLL_DDSEN_OFST                   (25)
1918 #define RG_SSUSB_PLL_AUTOK_VCO_OFST               (24)
1919 #define RG_SSUSB_PLL_PWD_OFST                     (23)
1920 #define RG_SSUSB_RX_AFE_PWD_OFST                  (22)
1921 #define RG_SSUSB_PLL_TCADJ_OFST                   (16)
1922 #define RG_SSUSB_FORCE_CDR_TCADJ_OFST             (15)
1923 #define RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST         (14)
1924 #define RG_SSUSB_FORCE_CDR_PWD_OFST               (13)
1925 #define RG_SSUSB_FORCE_PLL_NCPO_EN_OFST           (12)
1926 #define RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST    (11)
1927 #define RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST          (9)
1928 #define RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST          (8)
1929 #define RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST          (7)
1930 #define RG_SSUSB_FORCE_PLL_DDSEN_OFST             (6)
1931 #define RG_SSUSB_FORCE_PLL_TCADJ_OFST             (5)
1932 #define RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST         (4)
1933 #define RG_SSUSB_FORCE_PLL_PWD_OFST               (3)
1934 #define RG_SSUSB_FLT_1_DISPERR_B_OFST             (2)
1935
1936 //U3D_PHYD_TXPLL2
1937 #define RG_SSUSB_TX_LFPS_EN_OFST                  (31)
1938 #define RG_SSUSB_FORCE_TX_LFPS_EN_OFST            (30)
1939 #define RG_SSUSB_TX_LFPS_OFST                     (29)
1940 #define RG_SSUSB_FORCE_TX_LFPS_OFST               (28)
1941 #define RG_SSUSB_RXPLL_STB_OFST                   (27)
1942 #define RG_SSUSB_TXPLL_STB_OFST                   (26)
1943 #define RG_SSUSB_FORCE_RXPLL_STB_OFST             (25)
1944 #define RG_SSUSB_FORCE_TXPLL_STB_OFST             (24)
1945 #define RG_SSUSB_RXPLL_REFCKSEL_OFST              (16)
1946 #define RG_SSUSB_RXPLL_STBMODE_OFST               (11)
1947 #define RG_SSUSB_RXPLL_ON_OFST                    (10)
1948 #define RG_SSUSB_FORCE_RXPLLON_OFST               (9)
1949 #define RG_SSUSB_FORCE_RX_AFE_PWD_OFST            (8)
1950 #define RG_SSUSB_CDR_AUTOK_VCO_OFST               (7)
1951 #define RG_SSUSB_CDR_PWD_OFST                     (6)
1952 #define RG_SSUSB_CDR_TCADJ_OFST                   (0)
1953
1954 //U3D_PHYD_FL0
1955 #define RG_SSUSB_RX_FL_TARGET_OFST                (16)
1956 #define RG_SSUSB_RX_FL_CYCLECNT_OFST              (0)
1957
1958 //U3D_PHYD_MIX2
1959 #define RG_SSUSB_RX_EQ_RST_OFST                   (31)
1960 #define RG_SSUSB_RX_EQ_RST_SEL_OFST               (30)
1961 #define RG_SSUSB_RXVAL_RST_OFST                   (29)
1962 #define RG_SSUSB_RXVAL_CNT_OFST                   (24)
1963 #define RG_SSUSB_CDROS_EN_OFST                    (18)
1964 #define RG_SSUSB_CDR_LCKOP_OFST                   (16)
1965 #define RG_SSUSB_RX_FL_LOCKTH_OFST                (8)
1966 #define RG_SSUSB_RX_FL_OFFSET_OFST                (0)
1967
1968 //U3D_PHYD_RX0
1969 #define RG_SSUSB_T2RLB_BERTH_OFST                 (24)
1970 #define RG_SSUSB_T2RLB_PAT_OFST                   (16)
1971 #define RG_SSUSB_T2RLB_EN_OFST                    (15)
1972 #define RG_SSUSB_T2RLB_BPSCRAMB_OFST              (14)
1973 #define RG_SSUSB_T2RLB_SERIAL_OFST                (13)
1974 #define RG_SSUSB_T2RLB_MODE_OFST                  (11)
1975 #define RG_SSUSB_RX_SAOSC_EN_OFST                 (10)
1976 #define RG_SSUSB_RX_SAOSC_EN_SEL_OFST             (9)
1977 #define RG_SSUSB_RX_DFE_OPTION_OFST               (8)
1978 #define RG_SSUSB_RX_DFE_EN_OFST                   (7)
1979 #define RG_SSUSB_RX_DFE_EN_SEL_OFST               (6)
1980 #define RG_SSUSB_RX_EQ_EN_OFST                    (5)
1981 #define RG_SSUSB_RX_EQ_EN_SEL_OFST                (4)
1982 #define RG_SSUSB_RX_SAOSC_RST_OFST                (3)
1983 #define RG_SSUSB_RX_SAOSC_RST_SEL_OFST            (2)
1984 #define RG_SSUSB_RX_DFE_RST_OFST                  (1)
1985 #define RG_SSUSB_RX_DFE_RST_SEL_OFST              (0)
1986
1987 //U3D_PHYD_T2RLB
1988 #define RG_SSUSB_EQTRAIN_CH_MODE_OFST             (28)
1989 #define RG_SSUSB_PRB_OUT_CPPAT_OFST               (27)
1990 #define RG_SSUSB_BPANSIENC_OFST                   (26)
1991 #define RG_SSUSB_VALID_EN_OFST                    (25)
1992 #define RG_SSUSB_EBUF_SRST_OFST                   (24)
1993 #define RG_SSUSB_K_EMP_OFST                       (20)
1994 #define RG_SSUSB_K_FUL_OFST                       (16)
1995 #define RG_SSUSB_T2RLB_BDATRST_OFST               (12)
1996 #define RG_SSUSB_P_T2RLB_SKP_EN_OFST              (10)
1997 #define RG_SSUSB_T2RLB_PATMODE_OFST               (8)
1998 #define RG_SSUSB_T2RLB_TSEQCNT_OFST               (0)
1999
2000 //U3D_PHYD_CPPAT
2001 #define RG_SSUSB_CPPAT_PROGRAM_EN_OFST            (24)
2002 #define RG_SSUSB_CPPAT_TOZ_OFST                   (21)
2003 #define RG_SSUSB_CPPAT_PRBS_EN_OFST               (20)
2004 #define RG_SSUSB_CPPAT_OUT_TMP2_OFST              (16)
2005 #define RG_SSUSB_CPPAT_OUT_TMP1_OFST              (8)
2006 #define RG_SSUSB_CPPAT_OUT_TMP0_OFST              (0)
2007
2008 //U3D_PHYD_MIX3
2009 #define RG_SSUSB_CDR_TCADJ_MINUS_OFST             (31)
2010 #define RG_SSUSB_P_CDROS_EN_OFST                  (30)
2011 #define RG_SSUSB_P_P2_TX_DRV_DIS_OFST             (28)
2012 #define RG_SSUSB_CDR_TCADJ_OFFSET_OFST            (24)
2013 #define RG_SSUSB_PLL_TCADJ_MINUS_OFST             (23)
2014 #define RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST       (20)
2015 #define RG_SSUSB_PLL_BIAS_LPF_EN_OFST             (19)
2016 #define RG_SSUSB_PLL_TCADJ_OFFSET_OFST            (16)
2017 #define RG_SSUSB_FORCE_PLL_SSCEN_OFST             (15)
2018 #define RG_SSUSB_PLL_SSCEN_OFST                   (14)
2019 #define RG_SSUSB_FORCE_CDR_PI_PWD_OFST            (13)
2020 #define RG_SSUSB_CDR_PI_PWD_OFST                  (12)
2021 #define RG_SSUSB_CDR_PI_MODE_OFST                 (11)
2022 #define RG_SSUSB_TXPLL_SSCEN_CYC_OFST             (0)
2023
2024 //U3D_PHYD_EBUFCTL
2025 #define RG_SSUSB_EBUFCTL_OFST                     (0)
2026
2027 //U3D_PHYD_PIPE0
2028 #define RG_SSUSB_RXTERMINATION_OFST               (30)
2029 #define RG_SSUSB_RXEQTRAINING_OFST                (29)
2030 #define RG_SSUSB_RXPOLARITY_OFST                  (28)
2031 #define RG_SSUSB_TXDEEMPH_OFST                    (26)
2032 #define RG_SSUSB_POWERDOWN_OFST                   (24)
2033 #define RG_SSUSB_TXONESZEROS_OFST                 (23)
2034 #define RG_SSUSB_TXELECIDLE_OFST                  (22)
2035 #define RG_SSUSB_TXDETECTRX_OFST                  (21)
2036 #define RG_SSUSB_PIPE_SEL_OFST                    (20)
2037 #define RG_SSUSB_TXDATAK_OFST                     (16)
2038 #define RG_SSUSB_CDR_STABLE_SEL_OFST              (15)
2039 #define RG_SSUSB_CDR_STABLE_OFST                  (14)
2040 #define RG_SSUSB_CDR_RSTB_SEL_OFST                (13)
2041 #define RG_SSUSB_CDR_RSTB_OFST                    (12)
2042 #define RG_SSUSB_P_ERROR_SEL_OFST                 (4)
2043 #define RG_SSUSB_TXMARGIN_OFST                    (1)
2044 #define RG_SSUSB_TXCOMPLIANCE_OFST                (0)
2045
2046 //U3D_PHYD_PIPE1
2047 #define RG_SSUSB_TXDATA_OFST                      (0)
2048
2049 //U3D_PHYD_MIX4
2050 #define RG_SSUSB_CDROS_CNT_OFST                   (24)
2051 #define RG_SSUSB_T2RLB_BER_EN_OFST                (16)
2052 #define RG_SSUSB_T2RLB_BER_RATE_OFST              (0)
2053
2054 //U3D_PHYD_CKGEN0
2055 #define RG_SSUSB_RFIFO_IMPLAT_OFST                (27)
2056 #define RG_SSUSB_TFIFO_PSEL_OFST                  (24)
2057 #define RG_SSUSB_CKGEN_PSEL_OFST                  (8)
2058 #define RG_SSUSB_RXCK_INV_OFST                    (0)
2059
2060 //U3D_PHYD_MIX5
2061 #define RG_SSUSB_PRB_SEL_OFST                     (16)
2062 #define RG_SSUSB_RXPLL_STBCYC_OFST                (0)
2063
2064 //U3D_PHYD_RESERVED
2065 #define RG_SSUSB_PHYD_RESERVE_OFST                (0)
2066 //#define RG_SSUSB_RX_SIGDET_SEL_OFST               (11)
2067 //#define RG_SSUSB_RX_SIGDET_EN_OFST                (12)
2068 //#define RG_SSUSB_RX_PI_CAL_MANUAL_SEL_OFST        (9)
2069 //#define RG_SSUSB_RX_PI_CAL_MANUAL_EN_OFST         (10)
2070
2071 //U3D_PHYD_CDR0
2072 #define RG_SSUSB_CDR_BIC_LTR_OFST                 (28)
2073 #define RG_SSUSB_CDR_BIC_LTD0_OFST                (24)
2074 #define RG_SSUSB_CDR_BC_LTD1_OFST                 (16)
2075 #define RG_SSUSB_CDR_BC_LTR_OFST                  (8)
2076 #define RG_SSUSB_CDR_BC_LTD0_OFST                 (0)
2077
2078 //U3D_PHYD_CDR1
2079 #define RG_SSUSB_CDR_BIR_LTD1_OFST                (24)
2080 #define RG_SSUSB_CDR_BIR_LTR_OFST                 (16)
2081 #define RG_SSUSB_CDR_BIR_LTD0_OFST                (8)
2082 #define RG_SSUSB_CDR_BW_SEL_OFST                  (6)
2083 #define RG_SSUSB_CDR_BIC_LTD1_OFST                (0)
2084
2085 //U3D_PHYD_PLL_0
2086 #define RG_SSUSB_FORCE_CDR_BAND_5G_OFST           (28)
2087 #define RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST         (27)
2088 #define RG_SSUSB_FORCE_PLL_BAND_5G_OFST           (26)
2089 #define RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST         (25)
2090 #define RG_SSUSB_P_EQ_T_SEL_OFST                  (15)
2091 #define RG_SSUSB_PLL_ISO_EN_CYC_OFST              (5)
2092 #define RG_SSUSB_PLLBAND_RECAL_OFST               (4)
2093 #define RG_SSUSB_PLL_DDS_ISO_EN_OFST              (3)
2094 #define RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST        (2)
2095 #define RG_SSUSB_PLL_DDS_PWR_ON_OFST              (1)
2096 #define RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST        (0)
2097
2098 //U3D_PHYD_PLL_1
2099 #define RG_SSUSB_CDR_BAND_5G_OFST                 (24)
2100 #define RG_SSUSB_CDR_BAND_2P5G_OFST               (16)
2101 #define RG_SSUSB_PLL_BAND_5G_OFST                 (8)
2102 #define RG_SSUSB_PLL_BAND_2P5G_OFST               (0)
2103
2104 //U3D_PHYD_BCN_DET_1
2105 #define RG_SSUSB_P_BCN_OBS_PRD_OFST               (16)
2106 #define RG_SSUSB_U_BCN_OBS_PRD_OFST               (0)
2107
2108 //U3D_PHYD_BCN_DET_2
2109 #define RG_SSUSB_P_BCN_OBS_SEL_OFST               (16)
2110 #define RG_SSUSB_BCN_DET_DIS_OFST                 (12)
2111 #define RG_SSUSB_U_BCN_OBS_SEL_OFST               (0)
2112
2113 //U3D_EQ0
2114 #define RG_SSUSB_EQ_DLHL_LFI_OFST                 (24)
2115 #define RG_SSUSB_EQ_DHHL_LFI_OFST                 (16)
2116 #define RG_SSUSB_EQ_DD0HOS_LFI_OFST               (8)
2117 #define RG_SSUSB_EQ_DD0LOS_LFI_OFST               (0)
2118
2119 //U3D_EQ1
2120 #define RG_SSUSB_EQ_DD1HOS_LFI_OFST               (24)
2121 #define RG_SSUSB_EQ_DD1LOS_LFI_OFST               (16)
2122 #define RG_SSUSB_EQ_DE0OS_LFI_OFST                (8)
2123 #define RG_SSUSB_EQ_DE1OS_LFI_OFST                (0)
2124
2125 //U3D_EQ2
2126 #define RG_SSUSB_EQ_DLHLOS_LFI_OFST               (24)
2127 #define RG_SSUSB_EQ_DHHLOS_LFI_OFST               (16)
2128 #define RG_SSUSB_EQ_STOPTIME_OFST                 (14)
2129 #define RG_SSUSB_EQ_DHHL_LF_SEL_OFST              (11)
2130 #define RG_SSUSB_EQ_DSAOS_LF_SEL_OFST             (8)
2131 #define RG_SSUSB_EQ_STARTTIME_OFST                (6)
2132 #define RG_SSUSB_EQ_DLEQ_LF_SEL_OFST              (3)
2133 #define RG_SSUSB_EQ_DLHL_LF_SEL_OFST              (0)
2134
2135 //U3D_EQ3
2136 #define RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST            (28)
2137 #define RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST            (24)
2138 #define RG_SSUSB_EQ_DEYE0OS_LFI_OFST              (16)
2139 #define RG_SSUSB_EQ_DEYE1OS_LFI_OFST              (8)
2140 #define RG_SSUSB_EQ_TRI_DET_EN_OFST               (7)
2141 #define RG_SSUSB_EQ_TRI_DET_TH_OFST               (0)
2142
2143 //U3D_EQ_EYE0
2144 #define RG_SSUSB_EQ_EYE_XOFFSET_OFST              (25)
2145 #define RG_SSUSB_EQ_EYE_MON_EN_OFST               (24)
2146 #define RG_SSUSB_EQ_EYE0_Y_OFST                   (16)
2147 #define RG_SSUSB_EQ_EYE1_Y_OFST                   (8)
2148 #define RG_SSUSB_EQ_PILPO_ROUT_OFST               (7)
2149 #define RG_SSUSB_EQ_PI_KPGAIN_OFST                (4)
2150 #define RG_SSUSB_EQ_EYE_CNT_EN_OFST               (3)
2151
2152 //U3D_EQ_EYE1
2153 #define RG_SSUSB_EQ_SIGDET_OFST                   (24)
2154 #define RG_SSUSB_EQ_EYE_MASK_OFST                 (7)
2155
2156 //U3D_EQ_EYE2
2157 #define RG_SSUSB_EQ_RX500M_CK_SEL_OFST            (31)
2158 #define RG_SSUSB_EQ_SD_CNT1_OFST                  (24)
2159 #define RG_SSUSB_EQ_ISIFLAG_SEL_OFST              (22)
2160 #define RG_SSUSB_EQ_SD_CNT0_OFST                  (16)
2161
2162 //U3D_EQ_DFE0
2163 #define RG_SSUSB_EQ_LEQMAX_OFST                   (28)
2164 #define RG_SSUSB_EQ_DFEX_EN_OFST                  (27)
2165 #define RG_SSUSB_EQ_DFEX_LF_SEL_OFST              (24)
2166 #define RG_SSUSB_EQ_CHK_EYE_H_OFST                (23)
2167 #define RG_SSUSB_EQ_PIEYE_INI_OFST                (16)
2168 #define RG_SSUSB_EQ_PI90_INI_OFST                 (8)
2169 #define RG_SSUSB_EQ_PI0_INI_OFST                  (0)
2170
2171 //U3D_EQ_DFE1
2172 #define RG_SSUSB_EQ_REV_OFST                      (16)
2173 #define RG_SSUSB_EQ_DFEYEN_DUR_OFST               (12)
2174 #define RG_SSUSB_EQ_DFEXEN_DUR_OFST               (8)
2175 #define RG_SSUSB_EQ_DFEX_RST_OFST                 (7)
2176 #define RG_SSUSB_EQ_GATED_RXD_B_OFST              (6)
2177 #define RG_SSUSB_EQ_PI90CK_SEL_OFST               (4)
2178 #define RG_SSUSB_EQ_DFEX_DIS_OFST                 (2)
2179 #define RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST          (1)
2180 #define RG_SSUSB_EQ_DFEXEN_SEL_OFST               (0)
2181
2182 //U3D_EQ_DFE2
2183 #define RG_SSUSB_EQ_MON_SEL_OFST                  (24)
2184 #define RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST            (16)
2185 #define RG_SSUSB_EQ_DLEQOS_LFI_OFST               (8)
2186 #define RG_SSUSB_EQ_LEQ_STOP_TO_OFST              (0)
2187
2188 //U3D_EQ_DFE3
2189 #define RG_SSUSB_EQ_RESERVED_OFST                 (0)
2190
2191 //U3D_PHYD_MON0
2192 #define RGS_SSUSB_BERT_BERC_OFST                  (16)
2193 #define RGS_SSUSB_LFPS_OFST                       (12)
2194 #define RGS_SSUSB_TRAINDEC_OFST                   (8)
2195 #define RGS_SSUSB_SCP_PAT_OFST                    (0)
2196
2197 //U3D_PHYD_MON1
2198 #define RGS_SSUSB_RX_FL_OUT_OFST                  (0)
2199
2200 //U3D_PHYD_MON2
2201 #define RGS_SSUSB_T2RLB_ERRCNT_OFST               (16)
2202 #define RGS_SSUSB_RETRACK_OFST                    (12)
2203 #define RGS_SSUSB_RXPLL_LOCK_OFST                 (10)
2204 #define RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST          (9)
2205 #define RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST          (8)
2206 #define RGS_SSUSB_PDNCTL_OFST                     (0)
2207
2208 //U3D_PHYD_MON3
2209 #define RGS_SSUSB_TSEQ_ERRCNT_OFST                (16)
2210 #define RGS_SSUSB_PRBS_ERRCNT_OFST                (0)
2211
2212 //U3D_PHYD_MON4
2213 #define RGS_SSUSB_RX_LSLOCK_CNT_OFST              (24)
2214 #define RGS_SSUSB_SCP_DETCNT_OFST                 (16)
2215 #define RGS_SSUSB_TSEQ_DETCNT_OFST                (0)
2216
2217 //U3D_PHYD_MON5
2218 #define RGS_SSUSB_EBUFMSG_OFST                    (16)
2219 #define RGS_SSUSB_BERT_LOCK_OFST                  (15)
2220 #define RGS_SSUSB_SCP_DET_OFST                    (14)
2221 #define RGS_SSUSB_TSEQ_DET_OFST                   (13)
2222 #define RGS_SSUSB_EBUF_UDF_OFST                   (12)
2223 #define RGS_SSUSB_EBUF_OVF_OFST                   (11)
2224 #define RGS_SSUSB_PRBS_PASSTH_OFST                (10)
2225 #define RGS_SSUSB_PRBS_PASS_OFST                  (9)
2226 #define RGS_SSUSB_PRBS_LOCK_OFST                  (8)
2227 #define RGS_SSUSB_T2RLB_ERR_OFST                  (6)
2228 #define RGS_SSUSB_T2RLB_PASSTH_OFST               (5)
2229 #define RGS_SSUSB_T2RLB_PASS_OFST                 (4)
2230 #define RGS_SSUSB_T2RLB_LOCK_OFST                 (3)
2231 #define RGS_SSUSB_RX_IMPCAL_DONE_OFST             (2)
2232 #define RGS_SSUSB_TX_IMPCAL_DONE_OFST             (1)
2233 #define RGS_SSUSB_RXDETECTED_OFST                 (0)
2234
2235 //U3D_PHYD_MON6
2236 #define RGS_SSUSB_SIGCAL_DONE_OFST                (30)
2237 #define RGS_SSUSB_SIGCAL_CAL_OUT_OFST             (29)
2238 #define RGS_SSUSB_SIGCAL_OFFSET_OFST              (24)
2239 #define RGS_SSUSB_RX_IMP_SEL_OFST                 (16)
2240 #define RGS_SSUSB_TX_IMP_SEL_OFST                 (8)
2241 #define RGS_SSUSB_TFIFO_MSG_OFST                  (4)
2242 #define RGS_SSUSB_RFIFO_MSG_OFST                  (0)
2243
2244 //U3D_PHYD_MON7
2245 #define RGS_SSUSB_FT_OUT_OFST                     (8)
2246 #define RGS_SSUSB_PRB_OUT_OFST                    (0)
2247
2248 //U3D_PHYA_RX_MON0
2249 #define RGS_SSUSB_EQ_DCLEQ_OFST                   (24)
2250 #define RGS_SSUSB_EQ_DCD0H_OFST                   (16)
2251 #define RGS_SSUSB_EQ_DCD0L_OFST                   (8)
2252 #define RGS_SSUSB_EQ_DCD1H_OFST                   (0)
2253
2254 //U3D_PHYA_RX_MON1
2255 #define RGS_SSUSB_EQ_DCD1L_OFST                   (24)
2256 #define RGS_SSUSB_EQ_DCE0_OFST                    (16)
2257 #define RGS_SSUSB_EQ_DCE1_OFST                    (8)
2258 #define RGS_SSUSB_EQ_DCHHL_OFST                   (0)
2259
2260 //U3D_PHYA_RX_MON2
2261 #define RGS_SSUSB_EQ_LEQ_STOP_OFST                (31)
2262 #define RGS_SSUSB_EQ_DCLHL_OFST                   (24)
2263 #define RGS_SSUSB_EQ_STATUS_OFST                  (16)
2264 #define RGS_SSUSB_EQ_DCEYE0_OFST                  (8)
2265 #define RGS_SSUSB_EQ_DCEYE1_OFST                  (0)
2266
2267 //U3D_PHYA_RX_MON3
2268 #define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST    (0)
2269
2270 //U3D_PHYA_RX_MON4
2271 #define RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST    (0)
2272
2273 //U3D_PHYA_RX_MON5
2274 #define RGS_SSUSB_EQ_DCLEQOS_OFST                 (8)
2275 #define RGS_SSUSB_EQ_EYE_CNT_RDY_OFST             (7)
2276 #define RGS_SSUSB_EQ_PILPO_OFST                   (0)
2277
2278 //U3D_PHYD_CPPAT2
2279 #define RG_SSUSB_CPPAT_OUT_H_TMP2_OFST            (16)
2280 #define RG_SSUSB_CPPAT_OUT_H_TMP1_OFST            (8)
2281 #define RG_SSUSB_CPPAT_OUT_H_TMP0_OFST            (0)
2282
2283 //U3D_EQ_EYE3
2284 #define RG_SSUSB_EQ_LEQ_SHIFT_OFST                (24)
2285 #define RG_SSUSB_EQ_EYE_CNT_OFST                  (0)
2286
2287 //U3D_KBAND_OUT
2288 #define RGS_SSUSB_CDR_BAND_5G_OFST                (24)
2289 #define RGS_SSUSB_CDR_BAND_2P5G_OFST              (16)
2290 #define RGS_SSUSB_PLL_BAND_5G_OFST                (8)
2291 #define RGS_SSUSB_PLL_BAND_2P5G_OFST              (0)
2292
2293 //U3D_KBAND_OUT1
2294 #define RGS_SSUSB_CDR_VCOCAL_FAIL_OFST            (24)
2295 #define RGS_SSUSB_CDR_VCOCAL_STATE_OFST           (16)
2296 #define RGS_SSUSB_PLL_VCOCAL_FAIL_OFST            (8)
2297 #define RGS_SSUSB_PLL_VCOCAL_STATE_OFST           (0)
2298
2299
2300 ///////////////////////////////////////////////////////////////////////////////
2301
2302 struct u3phyd_bank2_reg {
2303         //0x0
2304         PHY_LE32 b2_phyd_top1;
2305         PHY_LE32 b2_phyd_top2;
2306         PHY_LE32 b2_phyd_top3;
2307         PHY_LE32 b2_phyd_top4;
2308         //0x10
2309         PHY_LE32 b2_phyd_top5;
2310         PHY_LE32 b2_phyd_top6;
2311         PHY_LE32 b2_phyd_top7;
2312         PHY_LE32 b2_phyd_p_sigdet1;
2313         //0x20
2314         PHY_LE32 b2_phyd_p_sigdet2;
2315         PHY_LE32 b2_phyd_p_sigdet_cal1;
2316         PHY_LE32 b2_phyd_rxdet1;
2317         PHY_LE32 b2_phyd_rxdet2;
2318         //0x30
2319         PHY_LE32 b2_phyd_misc0;
2320         PHY_LE32 b2_phyd_misc2;
2321         PHY_LE32 b2_phyd_misc3;
2322         PHY_LE32 reserve0;
2323         //0x40
2324         PHY_LE32 b2_rosc_0;
2325         PHY_LE32 b2_rosc_1;
2326         PHY_LE32 b2_rosc_2;
2327         PHY_LE32 b2_rosc_3;
2328         //0x50
2329         PHY_LE32 b2_rosc_4;
2330         PHY_LE32 b2_rosc_5;
2331         PHY_LE32 b2_rosc_6;
2332         PHY_LE32 b2_rosc_7;
2333         //0x60
2334         PHY_LE32 b2_rosc_8;
2335         PHY_LE32 b2_rosc_9;
2336         PHY_LE32 b2_rosc_a;
2337         PHY_LE32 reserve1;
2338         //0x70~0xd0
2339         PHY_LE32 reserve2[28];
2340         //0xe0
2341         PHY_LE32 phyd_version;
2342         PHY_LE32 phyd_model;
2343 };
2344
2345 //U3D_B2_PHYD_TOP1
2346 #define RG_SSUSB_PCIE2_K_EMP                      (0xf<<28) //31:28
2347 #define RG_SSUSB_PCIE2_K_FUL                      (0xf<<24) //27:24
2348 #define RG_SSUSB_TX_EIDLE_LP_EN                   (0x1<<17) //17:17
2349 #define RG_SSUSB_FORCE_TX_EIDLE_LP_EN             (0x1<<16) //16:16
2350 #define RG_SSUSB_SIGDET_EN                        (0x1<<15) //15:15
2351 #define RG_SSUSB_FORCE_SIGDET_EN                  (0x1<<14) //14:14
2352 #define RG_SSUSB_CLKRX_EN                         (0x1<<13) //13:13
2353 #define RG_SSUSB_FORCE_CLKRX_EN                   (0x1<<12) //12:12
2354 #define RG_SSUSB_CLKTX_EN                         (0x1<<11) //11:11
2355 #define RG_SSUSB_FORCE_CLKTX_EN                   (0x1<<10) //10:10
2356 #define RG_SSUSB_CLK_REQ_N_I                      (0x1<<9) //9:9
2357 #define RG_SSUSB_FORCE_CLK_REQ_N_I                (0x1<<8) //8:8
2358 #define RG_SSUSB_RATE                             (0x1<<6) //6:6
2359 #define RG_SSUSB_FORCE_RATE                       (0x1<<5) //5:5
2360 #define RG_SSUSB_PCIE_MODE_SEL                    (0x1<<4) //4:4
2361 #define RG_SSUSB_FORCE_PCIE_MODE_SEL              (0x1<<3) //3:3
2362 #define RG_SSUSB_PHY_MODE                         (0x3<<1) //2:1
2363 #define RG_SSUSB_FORCE_PHY_MODE                   (0x1<<0) //0:0
2364
2365 //U3D_B2_PHYD_TOP2
2366 #define RG_SSUSB_FORCE_IDRV_6DB                   (0x1<<30) //30:30
2367 #define RG_SSUSB_IDRV_6DB                         (0x3f<<24) //29:24
2368 #define RG_SSUSB_FORCE_IDEM_3P5DB                 (0x1<<22) //22:22
2369 #define RG_SSUSB_IDEM_3P5DB                       (0x3f<<16) //21:16
2370 #define RG_SSUSB_FORCE_IDRV_3P5DB                 (0x1<<14) //14:14
2371 #define RG_SSUSB_IDRV_3P5DB                       (0x3f<<8) //13:8
2372 #define RG_SSUSB_FORCE_IDRV_0DB                   (0x1<<6) //6:6
2373 #define RG_SSUSB_IDRV_0DB                         (0x3f<<0) //5:0
2374
2375 //U3D_B2_PHYD_TOP3
2376 #define RG_SSUSB_TX_BIASI                         (0x7<<25) //27:25
2377 #define RG_SSUSB_FORCE_TX_BIASI_EN                (0x1<<24) //24:24
2378 #define RG_SSUSB_TX_BIASI_EN                      (0x1<<16) //16:16
2379 #define RG_SSUSB_FORCE_TX_BIASI                   (0x1<<13) //13:13
2380 #define RG_SSUSB_FORCE_IDEM_6DB                   (0x1<<8) //8:8
2381 #define RG_SSUSB_IDEM_6DB                         (0x3f<<0) //5:0
2382
2383 //U3D_B2_PHYD_TOP4
2384 #define RG_SSUSB_G1_CDR_BIC_LTR                   (0xf<<28) //31:28
2385 #define RG_SSUSB_G1_CDR_BIC_LTD0                  (0xf<<24) //27:24
2386 #define RG_SSUSB_G1_CDR_BC_LTD1                   (0x1f<<16) //20:16
2387 #define RG_SSUSB_G1_CDR_BC_LTR                    (0x1f<<8) //12:8
2388 #define RG_SSUSB_G1_CDR_BC_LTD0                   (0x1f<<0) //4:0
2389
2390 //U3D_B2_PHYD_TOP5
2391 #define RG_SSUSB_G1_CDR_BIR_LTD1                  (0x1f<<24) //28:24
2392 #define RG_SSUSB_G1_CDR_BIR_LTR                   (0x1f<<16) //20:16
2393 #define RG_SSUSB_G1_CDR_BIR_LTD0                  (0x1f<<8) //12:8
2394 #define RG_SSUSB_G1_CDR_BIC_LTD1                  (0xf<<0) //3:0
2395
2396 //U3D_B2_PHYD_TOP6
2397 #define RG_SSUSB_G2_CDR_BIC_LTR                   (0xf<<28) //31:28
2398 #define RG_SSUSB_G2_CDR_BIC_LTD0                  (0xf<<24) //27:24
2399 #define RG_SSUSB_G2_CDR_BC_LTD1                   (0x1f<<16) //20:16
2400 #define RG_SSUSB_G2_CDR_BC_LTR                    (0x1f<<8) //12:8
2401 #define RG_SSUSB_G2_CDR_BC_LTD0                   (0x1f<<0) //4:0
2402
2403 //U3D_B2_PHYD_TOP7
2404 #define RG_SSUSB_G2_CDR_BIR_LTD1                  (0x1f<<24) //28:24
2405 #define RG_SSUSB_G2_CDR_BIR_LTR                   (0x1f<<16) //20:16
2406 #define RG_SSUSB_G2_CDR_BIR_LTD0                  (0x1f<<8) //12:8
2407 #define RG_SSUSB_G2_CDR_BIC_LTD1                  (0xf<<0) //3:0
2408
2409 //U3D_B2_PHYD_P_SIGDET1
2410 #define RG_SSUSB_P_SIGDET_FLT_DIS                 (0x1<<31) //31:31
2411 #define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL        (0x7f<<24) //30:24
2412 #define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL        (0x7f<<16) //22:16
2413 #define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL          (0x7f<<8) //14:8
2414 #define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL          (0x7f<<0) //6:0
2415
2416 //U3D_B2_PHYD_P_SIGDET2
2417 #define RG_SSUSB_P_SIGDET_RX_VAL_S                (0x1<<29) //29:29
2418 #define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL            (0x1<<28) //28:28
2419 #define RG_SSUSB_P_SIGDET_L0_EXIT_S               (0x1<<27) //27:27
2420 #define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S            (0x3<<25) //26:25
2421 #define RG_SSUSB_P_SIGDET_L0S_EXIT_S              (0x1<<24) //24:24
2422 #define RG_SSUSB_P_SIGDET_L0S_ENTRY_S             (0x1<<16) //16:16
2423 #define RG_SSUSB_P_SIGDET_PRB_SEL                 (0x1<<10) //10:10
2424 #define RG_SSUSB_P_SIGDET_BK_SIG_T                (0x3<<8) //9:8
2425 #define RG_SSUSB_P_SIGDET_P2_RXLFPS               (0x1<<6) //6:6
2426 #define RG_SSUSB_P_SIGDET_NON_BK_AD               (0x1<<5) //5:5
2427 #define RG_SSUSB_P_SIGDET_BK_B_RXEQ               (0x1<<4) //4:4
2428 #define RG_SSUSB_P_SIGDET_G2_KO_SEL               (0x3<<2) //3:2
2429 #define RG_SSUSB_P_SIGDET_G1_KO_SEL               (0x3<<0) //1:0
2430
2431 //U3D_B2_PHYD_P_SIGDET_CAL1
2432 #define RG_SSUSB_P_SIGDET_CAL_OFFSET              (0x1f<<24) //28:24
2433 #define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET        (0x1<<16) //16:16
2434 #define RG_SSUSB_P_SIGDET_CAL_EN                  (0x1<<8) //8:8
2435 #define RG_SSUSB_P_FORCE_SIGDET_CAL_EN            (0x1<<3) //3:3
2436 #define RG_SSUSB_P_SIGDET_FLT_EN                  (0x1<<2) //2:2
2437 #define RG_SSUSB_P_SIGDET_SAMPLE_PRD              (0x1<<1) //1:1
2438 #define RG_SSUSB_P_SIGDET_REK                     (0x1<<0) //0:0
2439
2440 //U3D_B2_PHYD_RXDET1
2441 #define RG_SSUSB_RXDET_PRB_SEL                    (0x1<<31) //31:31
2442 #define RG_SSUSB_FORCE_CMDET                      (0x1<<30) //30:30
2443 #define RG_SSUSB_RXDET_EN                         (0x1<<29) //29:29
2444 #define RG_SSUSB_FORCE_RXDET_EN                   (0x1<<28) //28:28
2445 #define RG_SSUSB_RXDET_K_TWICE                    (0x1<<27) //27:27
2446 #define RG_SSUSB_RXDET_STB3_SET                   (0x1ff<<18) //26:18
2447 #define RG_SSUSB_RXDET_STB2_SET                   (0x1ff<<9) //17:9
2448 #define RG_SSUSB_RXDET_STB1_SET                   (0x1ff<<0) //8:0
2449
2450 //U3D_B2_PHYD_RXDET2
2451 #define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN         (0x1<<31) //31:31
2452 #define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN           (0x1<<30) //30:30
2453 #define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN            (0x1<<29) //29:29
2454 #define RG_SSUSB_PDN_T_SEL                        (0x3<<18) //19:18
2455 #define RG_SSUSB_RXDET_STB3_SET_P3                (0x1ff<<9) //17:9
2456 #define RG_SSUSB_RXDET_STB2_SET_P3                (0x1ff<<0) //8:0
2457
2458 //U3D_B2_PHYD_MISC0
2459 #define RG_SSUSB_FORCE_PLL_DDS_HF_EN              (0x1<<22) //22:22
2460 #define RG_SSUSB_PLL_DDS_HF_EN_MAN                (0x1<<21) //21:21
2461 #define RG_SSUSB_RXLFPS_ENTXDRV                   (0x1<<20) //20:20
2462 #define RG_SSUSB_RX_FL_UNLOCKTH                   (0xf<<16) //19:16
2463 #define RG_SSUSB_LFPS_PSEL                        (0x1<<15) //15:15
2464 #define RG_SSUSB_RX_SIGDET_EN                     (0x1<<14) //14:14
2465 #define RG_SSUSB_RX_SIGDET_EN_SEL                 (0x1<<13) //13:13
2466 #define RG_SSUSB_RX_PI_CAL_EN                     (0x1<<12) //12:12
2467 #define RG_SSUSB_RX_PI_CAL_EN_SEL                 (0x1<<11) //11:11
2468 #define RG_SSUSB_P3_CLS_CK_SEL                    (0x1<<10) //10:10
2469 #define RG_SSUSB_T2RLB_PSEL                       (0x3<<8) //9:8
2470 #define RG_SSUSB_PPCTL_PSEL                       (0x7<<5) //7:5
2471 #define RG_SSUSB_PHYD_TX_DATA_INV                 (0x1<<4) //4:4
2472 #define RG_SSUSB_BERTLB_PSEL                      (0x3<<2) //3:2
2473 #define RG_SSUSB_RETRACK_DIS                      (0x1<<1) //1:1
2474 #define RG_SSUSB_PPERRCNT_CLR                     (0x1<<0) //0:0
2475
2476 //U3D_B2_PHYD_MISC2
2477 #define RG_SSUSB_FRC_PLL_DDS_PREDIV2              (0x1<<31) //31:31
2478 #define RG_SSUSB_FRC_PLL_DDS_IADJ                 (0xf<<27) //30:27
2479 #define RG_SSUSB_P_SIGDET_125FILTER               (0x1<<26) //26:26
2480 #define RG_SSUSB_P_SIGDET_RST_FILTER              (0x1<<25) //25:25
2481 #define RG_SSUSB_P_SIGDET_EID_USE_RAW             (0x1<<24) //24:24
2482 #define RG_SSUSB_P_SIGDET_LTD_USE_RAW             (0x1<<23) //23:23
2483 #define RG_SSUSB_EIDLE_BF_RXDET                   (0x1<<22) //22:22
2484 #define RG_SSUSB_EIDLE_LP_STBCYC                  (0x1ff<<13) //21:13
2485 #define RG_SSUSB_TX_EIDLE_LP_POSTDLY              (0x3f<<7) //12:7
2486 #define RG_SSUSB_TX_EIDLE_LP_PREDLY               (0x3f<<1) //6:1
2487 #define RG_SSUSB_TX_EIDLE_LP_EN_ADV               (0x1<<0) //0:0
2488
2489 //U3D_B2_PHYD_MISC3
2490 #define RGS_SSUSB_DDS_CALIB_C_STATE               (0x7<<16) //18:16
2491 #define RGS_SSUSB_PPERRCNT                        (0xffff<<0) //15:0
2492
2493 //U3D_B2_ROSC_0
2494 #define RG_SSUSB_RING_OSC_CNTEND                  (0x1ff<<23) //31:23
2495 #define RG_SSUSB_XTAL_OSC_CNTEND                  (0x7f<<16) //22:16
2496 #define RG_SSUSB_RING_OSC_EN                      (0x1<<3) //3:3
2497 #define RG_SSUSB_RING_OSC_FORCE_EN                (0x1<<2) //2:2
2498 #define RG_SSUSB_FRC_RING_BYPASS_DET              (0x1<<1) //1:1
2499 #define RG_SSUSB_RING_BYPASS_DET                  (0x1<<0) //0:0
2500
2501 //U3D_B2_ROSC_1
2502 #define RG_SSUSB_RING_OSC_FRC_P3                  (0x1<<20) //20:20
2503 #define RG_SSUSB_RING_OSC_P3                      (0x1<<19) //19:19
2504 #define RG_SSUSB_RING_OSC_FRC_RECAL               (0x3<<17) //18:17
2505 #define RG_SSUSB_RING_OSC_RECAL                   (0x1<<16) //16:16
2506 #define RG_SSUSB_RING_OSC_SEL                     (0xff<<8) //15:8
2507 #define RG_SSUSB_RING_OSC_FRC_SEL                 (0x1<<0) //0:0
2508
2509 //U3D_B2_ROSC_2
2510 #define RG_SSUSB_RING_DET_STRCYC2                 (0xffff<<16) //31:16
2511 #define RG_SSUSB_RING_DET_STRCYC1                 (0xffff<<0) //15:0
2512
2513 //U3D_B2_ROSC_3
2514 #define RG_SSUSB_RING_DET_DETWIN1                 (0xffff<<16) //31:16
2515 #define RG_SSUSB_RING_DET_STRCYC3                 (0xffff<<0) //15:0
2516
2517 //U3D_B2_ROSC_4
2518 #define RG_SSUSB_RING_DET_DETWIN3                 (0xffff<<16) //31:16
2519 #define RG_SSUSB_RING_DET_DETWIN2                 (0xffff<<0) //15:0
2520
2521 //U3D_B2_ROSC_5
2522 #define RG_SSUSB_RING_DET_LBOND1                  (0xffff<<16) //31:16
2523 #define RG_SSUSB_RING_DET_UBOND1                  (0xffff<<0) //15:0
2524
2525 //U3D_B2_ROSC_6
2526 #define RG_SSUSB_RING_DET_LBOND2                  (0xffff<<16) //31:16
2527 #define RG_SSUSB_RING_DET_UBOND2                  (0xffff<<0) //15:0
2528
2529 //U3D_B2_ROSC_7
2530 #define RG_SSUSB_RING_DET_LBOND3                  (0xffff<<16) //31:16
2531 #define RG_SSUSB_RING_DET_UBOND3                  (0xffff<<0) //15:0
2532
2533 //U3D_B2_ROSC_8
2534 #define RG_SSUSB_RING_RESERVE                     (0xffff<<16) //31:16
2535 #define RG_SSUSB_ROSC_PROB_SEL                    (0xf<<2) //5:2
2536 #define RG_SSUSB_RING_FREQMETER_EN                (0x1<<1) //1:1
2537 #define RG_SSUSB_RING_DET_BPS_UBOND               (0x1<<0) //0:0
2538
2539 //U3D_B2_ROSC_9
2540 #define RGS_FM_RING_CNT                           (0xffff<<16) //31:16
2541 #define RGS_SSUSB_RING_OSC_STATE                  (0x3<<10) //11:10
2542 #define RGS_SSUSB_RING_OSC_STABLE                 (0x1<<9) //9:9
2543 #define RGS_SSUSB_RING_OSC_CAL_FAIL               (0x1<<8) //8:8
2544 #define RGS_SSUSB_RING_OSC_CAL                    (0xff<<0) //7:0
2545
2546 //U3D_B2_ROSC_A
2547 #define RGS_SSUSB_ROSC_PROB_OUT                   (0xff<<0) //7:0
2548
2549 //U3D_PHYD_VERSION
2550 #define RGS_SSUSB_PHYD_VERSION                    (0xffffffff<<0) //31:0
2551
2552 //U3D_PHYD_MODEL
2553 #define RGS_SSUSB_PHYD_MODEL                      (0xffffffff<<0) //31:0
2554
2555
2556 /* OFFSET */
2557
2558 //U3D_B2_PHYD_TOP1
2559 #define RG_SSUSB_PCIE2_K_EMP_OFST                 (28)
2560 #define RG_SSUSB_PCIE2_K_FUL_OFST                 (24)
2561 #define RG_SSUSB_TX_EIDLE_LP_EN_OFST              (17)
2562 #define RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST        (16)
2563 #define RG_SSUSB_SIGDET_EN_OFST                   (15)
2564 #define RG_SSUSB_FORCE_SIGDET_EN_OFST             (14)
2565 #define RG_SSUSB_CLKRX_EN_OFST                    (13)
2566 #define RG_SSUSB_FORCE_CLKRX_EN_OFST              (12)
2567 #define RG_SSUSB_CLKTX_EN_OFST                    (11)
2568 #define RG_SSUSB_FORCE_CLKTX_EN_OFST              (10)
2569 #define RG_SSUSB_CLK_REQ_N_I_OFST                 (9)
2570 #define RG_SSUSB_FORCE_CLK_REQ_N_I_OFST           (8)
2571 #define RG_SSUSB_RATE_OFST                        (6)
2572 #define RG_SSUSB_FORCE_RATE_OFST                  (5)
2573 #define RG_SSUSB_PCIE_MODE_SEL_OFST               (4)
2574 #define RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST         (3)
2575 #define RG_SSUSB_PHY_MODE_OFST                    (1)
2576 #define RG_SSUSB_FORCE_PHY_MODE_OFST              (0)
2577
2578 //U3D_B2_PHYD_TOP2
2579 #define RG_SSUSB_FORCE_IDRV_6DB_OFST              (30)
2580 #define RG_SSUSB_IDRV_6DB_OFST                    (24)
2581 #define RG_SSUSB_FORCE_IDEM_3P5DB_OFST            (22)
2582 #define RG_SSUSB_IDEM_3P5DB_OFST                  (16)
2583 #define RG_SSUSB_FORCE_IDRV_3P5DB_OFST            (14)
2584 #define RG_SSUSB_IDRV_3P5DB_OFST                  (8)
2585 #define RG_SSUSB_FORCE_IDRV_0DB_OFST              (6)
2586 #define RG_SSUSB_IDRV_0DB_OFST                    (0)
2587
2588 //U3D_B2_PHYD_TOP3
2589 #define RG_SSUSB_TX_BIASI_OFST                    (25)
2590 #define RG_SSUSB_FORCE_TX_BIASI_EN_OFST           (24)
2591 #define RG_SSUSB_TX_BIASI_EN_OFST                 (16)
2592 #define RG_SSUSB_FORCE_TX_BIASI_OFST              (13)
2593 #define RG_SSUSB_FORCE_IDEM_6DB_OFST              (8)
2594 #define RG_SSUSB_IDEM_6DB_OFST                    (0)
2595
2596 //U3D_B2_PHYD_TOP4
2597 #define RG_SSUSB_G1_CDR_BIC_LTR_OFST              (28)
2598 #define RG_SSUSB_G1_CDR_BIC_LTD0_OFST             (24)
2599 #define RG_SSUSB_G1_CDR_BC_LTD1_OFST              (16)
2600 #define RG_SSUSB_G1_CDR_BC_LTR_OFST               (8)
2601 #define RG_SSUSB_G1_CDR_BC_LTD0_OFST              (0)
2602
2603 //U3D_B2_PHYD_TOP5
2604 #define RG_SSUSB_G1_CDR_BIR_LTD1_OFST             (24)
2605 #define RG_SSUSB_G1_CDR_BIR_LTR_OFST              (16)
2606 #define RG_SSUSB_G1_CDR_BIR_LTD0_OFST             (8)
2607 #define RG_SSUSB_G1_CDR_BIC_LTD1_OFST             (0)
2608
2609 //U3D_B2_PHYD_TOP6
2610 #define RG_SSUSB_G2_CDR_BIC_LTR_OFST              (28)
2611 #define RG_SSUSB_G2_CDR_BIC_LTD0_OFST             (24)
2612 #define RG_SSUSB_G2_CDR_BC_LTD1_OFST              (16)
2613 #define RG_SSUSB_G2_CDR_BC_LTR_OFST               (8)
2614 #define RG_SSUSB_G2_CDR_BC_LTD0_OFST              (0)
2615
2616 //U3D_B2_PHYD_TOP7
2617 #define RG_SSUSB_G2_CDR_BIR_LTD1_OFST             (24)
2618 #define RG_SSUSB_G2_CDR_BIR_LTR_OFST              (16)
2619 #define RG_SSUSB_G2_CDR_BIR_LTD0_OFST             (8)
2620 #define RG_SSUSB_G2_CDR_BIC_LTD1_OFST             (0)
2621
2622 //U3D_B2_PHYD_P_SIGDET1
2623 #define RG_SSUSB_P_SIGDET_FLT_DIS_OFST            (31)
2624 #define RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST   (24)
2625 #define RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST   (16)
2626 #define RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST     (8)
2627 #define RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST     (0)
2628
2629 //U3D_B2_PHYD_P_SIGDET2
2630 #define RG_SSUSB_P_SIGDET_RX_VAL_S_OFST           (29)
2631 #define RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST       (28)
2632 #define RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST          (27)
2633 #define RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST       (25)
2634 #define RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST         (24)
2635 #define RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST        (16)
2636 #define RG_SSUSB_P_SIGDET_PRB_SEL_OFST            (10)
2637 #define RG_SSUSB_P_SIGDET_BK_SIG_T_OFST           (8)
2638 #define RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST          (6)
2639 #define RG_SSUSB_P_SIGDET_NON_BK_AD_OFST          (5)
2640 #define RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST          (4)
2641 #define RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST          (2)
2642 #define RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST          (0)
2643
2644 //U3D_B2_PHYD_P_SIGDET_CAL1
2645 #define RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST         (24)
2646 #define RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST   (16)
2647 #define RG_SSUSB_P_SIGDET_CAL_EN_OFST             (8)
2648 #define RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST       (3)
2649 #define RG_SSUSB_P_SIGDET_FLT_EN_OFST             (2)
2650 #define RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST         (1)
2651 #define RG_SSUSB_P_SIGDET_REK_OFST                (0)
2652
2653 //U3D_B2_PHYD_RXDET1
2654 #define RG_SSUSB_RXDET_PRB_SEL_OFST               (31)
2655 #define RG_SSUSB_FORCE_CMDET_OFST                 (30)
2656 #define RG_SSUSB_RXDET_EN_OFST                    (29)
2657 #define RG_SSUSB_FORCE_RXDET_EN_OFST              (28)
2658 #define RG_SSUSB_RXDET_K_TWICE_OFST               (27)
2659 #define RG_SSUSB_RXDET_STB3_SET_OFST              (18)
2660 #define RG_SSUSB_RXDET_STB2_SET_OFST              (9)
2661 #define RG_SSUSB_RXDET_STB1_SET_OFST              (0)
2662
2663 //U3D_B2_PHYD_RXDET2
2664 #define RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST    (31)
2665 #define RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST      (30)
2666 #define RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST       (29)
2667 #define RG_SSUSB_PDN_T_SEL_OFST                   (18)
2668 #define RG_SSUSB_RXDET_STB3_SET_P3_OFST           (9)
2669 #define RG_SSUSB_RXDET_STB2_SET_P3_OFST           (0)
2670
2671 //U3D_B2_PHYD_MISC0
2672 #define RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST         (22)
2673 #define RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST           (21)
2674 #define RG_SSUSB_RXLFPS_ENTXDRV_OFST              (20)
2675 #define RG_SSUSB_RX_FL_UNLOCKTH_OFST              (16)
2676 #define RG_SSUSB_LFPS_PSEL_OFST                   (15)
2677 #define RG_SSUSB_RX_SIGDET_EN_OFST                (14)
2678 #define RG_SSUSB_RX_SIGDET_EN_SEL_OFST            (13)
2679 #define RG_SSUSB_RX_PI_CAL_EN_OFST                (12)
2680 #define RG_SSUSB_RX_PI_CAL_EN_SEL_OFST            (11)
2681 #define RG_SSUSB_P3_CLS_CK_SEL_OFST               (10)
2682 #define RG_SSUSB_T2RLB_PSEL_OFST                  (8)
2683 #define RG_SSUSB_PPCTL_PSEL_OFST                  (5)
2684 #define RG_SSUSB_PHYD_TX_DATA_INV_OFST            (4)
2685 #define RG_SSUSB_BERTLB_PSEL_OFST                 (2)
2686 #define RG_SSUSB_RETRACK_DIS_OFST                 (1)
2687 #define RG_SSUSB_PPERRCNT_CLR_OFST                (0)
2688
2689 //U3D_B2_PHYD_MISC2
2690 #define RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST         (31)
2691 #define RG_SSUSB_FRC_PLL_DDS_IADJ_OFST            (27)
2692 #define RG_SSUSB_P_SIGDET_125FILTER_OFST          (26)
2693 #define RG_SSUSB_P_SIGDET_RST_FILTER_OFST         (25)
2694 #define RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST        (24)
2695 #define RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST        (23)
2696 #define RG_SSUSB_EIDLE_BF_RXDET_OFST              (22)
2697 #define RG_SSUSB_EIDLE_LP_STBCYC_OFST             (13)
2698 #define RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST         (7)
2699 #define RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST          (1)
2700 #define RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST          (0)
2701
2702 //U3D_B2_PHYD_MISC3
2703 #define RGS_SSUSB_DDS_CALIB_C_STATE_OFST          (16)
2704 #define RGS_SSUSB_PPERRCNT_OFST                   (0)
2705
2706 //U3D_B2_ROSC_0
2707 #define RG_SSUSB_RING_OSC_CNTEND_OFST             (23)
2708 #define RG_SSUSB_XTAL_OSC_CNTEND_OFST             (16)
2709 #define RG_SSUSB_RING_OSC_EN_OFST                 (3)
2710 #define RG_SSUSB_RING_OSC_FORCE_EN_OFST           (2)
2711 #define RG_SSUSB_FRC_RING_BYPASS_DET_OFST         (1)
2712 #define RG_SSUSB_RING_BYPASS_DET_OFST             (0)
2713
2714 //U3D_B2_ROSC_1
2715 #define RG_SSUSB_RING_OSC_FRC_P3_OFST             (20)
2716 #define RG_SSUSB_RING_OSC_P3_OFST                 (19)
2717 #define RG_SSUSB_RING_OSC_FRC_RECAL_OFST          (17)
2718 #define RG_SSUSB_RING_OSC_RECAL_OFST              (16)
2719 #define RG_SSUSB_RING_OSC_SEL_OFST                (8)
2720 #define RG_SSUSB_RING_OSC_FRC_SEL_OFST            (0)
2721
2722 //U3D_B2_ROSC_2
2723 #define RG_SSUSB_RING_DET_STRCYC2_OFST            (16)
2724 #define RG_SSUSB_RING_DET_STRCYC1_OFST            (0)
2725
2726 //U3D_B2_ROSC_3
2727 #define RG_SSUSB_RING_DET_DETWIN1_OFST            (16)
2728 #define RG_SSUSB_RING_DET_STRCYC3_OFST            (0)
2729
2730 //U3D_B2_ROSC_4
2731 #define RG_SSUSB_RING_DET_DETWIN3_OFST            (16)
2732 #define RG_SSUSB_RING_DET_DETWIN2_OFST            (0)
2733
2734 //U3D_B2_ROSC_5
2735 #define RG_SSUSB_RING_DET_LBOND1_OFST             (16)
2736 #define RG_SSUSB_RING_DET_UBOND1_OFST             (0)
2737
2738 //U3D_B2_ROSC_6
2739 #define RG_SSUSB_RING_DET_LBOND2_OFST             (16)
2740 #define RG_SSUSB_RING_DET_UBOND2_OFST             (0)
2741
2742 //U3D_B2_ROSC_7
2743 #define RG_SSUSB_RING_DET_LBOND3_OFST             (16)
2744 #define RG_SSUSB_RING_DET_UBOND3_OFST             (0)
2745
2746 //U3D_B2_ROSC_8
2747 #define RG_SSUSB_RING_RESERVE_OFST                (16)
2748 #define RG_SSUSB_ROSC_PROB_SEL_OFST               (2)
2749 #define RG_SSUSB_RING_FREQMETER_EN_OFST           (1)
2750 #define RG_SSUSB_RING_DET_BPS_UBOND_OFST          (0)
2751
2752 //U3D_B2_ROSC_9
2753 #define RGS_FM_RING_CNT_OFST                      (16)
2754 #define RGS_SSUSB_RING_OSC_STATE_OFST             (10)
2755 #define RGS_SSUSB_RING_OSC_STABLE_OFST            (9)
2756 #define RGS_SSUSB_RING_OSC_CAL_FAIL_OFST          (8)
2757 #define RGS_SSUSB_RING_OSC_CAL_OFST               (0)
2758
2759 //U3D_B2_ROSC_A
2760 #define RGS_SSUSB_ROSC_PROB_OUT_OFST              (0)
2761
2762 //U3D_PHYD_VERSION
2763 #define RGS_SSUSB_PHYD_VERSION_OFST               (0)
2764
2765 //U3D_PHYD_MODEL
2766 #define RGS_SSUSB_PHYD_MODEL_OFST                 (0)
2767
2768
2769 ///////////////////////////////////////////////////////////////////////////////
2770
2771 struct sifslv_chip_reg {
2772         PHY_LE32 xtalbias;
2773         PHY_LE32 syspll1;
2774         PHY_LE32 gpio_ctla;
2775         PHY_LE32 gpio_ctlb;
2776         PHY_LE32 gpio_ctlc;
2777 };
2778
2779 //U3D_GPIO_CTLA
2780 #define RG_C60802_GPIO_CTLA                       (0xffffffff<<0) //31:0
2781
2782 //U3D_GPIO_CTLB
2783 #define RG_C60802_GPIO_CTLB                       (0xffffffff<<0) //31:0
2784
2785 //U3D_GPIO_CTLC
2786 #define RG_C60802_GPIO_CTLC                       (0xffffffff<<0) //31:0
2787
2788 /* OFFSET */
2789
2790 //U3D_GPIO_CTLA
2791 #define RG_C60802_GPIO_CTLA_OFST                  (0)
2792
2793 //U3D_GPIO_CTLB
2794 #define RG_C60802_GPIO_CTLB_OFST                  (0)
2795
2796 //U3D_GPIO_CTLC
2797 #define RG_C60802_GPIO_CTLC_OFST                  (0)
2798
2799 ///////////////////////////////////////////////////////////////////////////////
2800
2801 struct sifslv_fm_feg {
2802         //0x0
2803         PHY_LE32 fmcr0;
2804         PHY_LE32 fmcr1;
2805         PHY_LE32 fmcr2;
2806         PHY_LE32 fmmonr0;
2807         //0x10
2808         PHY_LE32 fmmonr1;
2809 };
2810
2811 //U3D_FMCR0
2812 #define RG_LOCKTH                                 (0xf<<28) //31:28
2813 #define RG_MONCLK_SEL                             (0x3<<26) //27:26
2814 #define RG_FM_MODE                                (0x1<<25) //25:25
2815 #define RG_FREQDET_EN                             (0x1<<24) //24:24
2816 #define RG_CYCLECNT                               (0xffffff<<0) //23:0
2817
2818 //U3D_FMCR1
2819 #define RG_TARGET                                 (0xffffffff<<0) //31:0
2820
2821 //U3D_FMCR2
2822 #define RG_OFFSET                                 (0xffffffff<<0) //31:0
2823
2824 //U3D_FMMONR0
2825 #define USB_FM_OUT                                (0xffffffff<<0) //31:0
2826
2827 //U3D_FMMONR1
2828 #define RG_MONCLK_SEL_3                           (0x1<<9) //9:9
2829 #define RG_FRCK_EN                                (0x1<<8) //8:8
2830 #define USBPLL_LOCK                               (0x1<<1) //1:1
2831 #define USB_FM_VLD                                (0x1<<0) //0:0
2832
2833
2834 /* OFFSET */
2835
2836 //U3D_FMCR0
2837 #define RG_LOCKTH_OFST                            (28)
2838 #define RG_MONCLK_SEL_OFST                        (26)
2839 #define RG_FM_MODE_OFST                           (25)
2840 #define RG_FREQDET_EN_OFST                        (24)
2841 #define RG_CYCLECNT_OFST                          (0)
2842
2843 //U3D_FMCR1
2844 #define RG_TARGET_OFST                            (0)
2845
2846 //U3D_FMCR2
2847 #define RG_OFFSET_OFST                            (0)
2848
2849 //U3D_FMMONR0
2850 #define USB_FM_OUT_OFST                           (0)
2851
2852 //U3D_FMMONR1
2853 #define RG_MONCLK_SEL_3_OFST                      (9)
2854 #define RG_FRCK_EN_OFST                           (8)
2855 #define USBPLL_LOCK_OFST                          (1)
2856 #define USB_FM_VLD_OFST                           (0)
2857
2858
2859 ///////////////////////////////////////////////////////////////////////////////
2860
2861 PHY_INT32 phy_init(struct u3phy_info *info);
2862 PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
2863 PHY_INT32 eyescan_init(struct u3phy_info *info);
2864 PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
2865                 , PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
2866 PHY_INT32 u2_save_cur_en(struct u3phy_info *info);
2867 PHY_INT32 u2_save_cur_re(struct u3phy_info *info);
2868 PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
2869
2870 #endif
2871 #endif