1 #include <linux/types.h>
4 #include <linux/init.h>
6 #include <asm/mach-ralink/rt288x.h>
8 #define RT2880_PCI_SLOT1_BASE 0x20000000
9 #define RALINK_PCI_BASE 0xA0440000
10 #define RT2880_PCI_PCICFG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0000))
11 #define RT2880_PCI_ARBCTL ((unsigned long*)(RALINK_PCI_BASE + 0x0080))
12 #define RT2880_PCI_BAR0SETUP_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0010))
13 #define RT2880_PCI_CONFIG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0020))
14 #define RT2880_PCI_CONFIG_DATA ((unsigned long*)(RALINK_PCI_BASE + 0x0024))
15 #define RT2880_PCI_MEMBASE ((unsigned long*)(RALINK_PCI_BASE + 0x0028))
16 #define RT2880_PCI_IOBASE ((unsigned long*)(RALINK_PCI_BASE + 0x002C))
17 #define RT2880_PCI_IMBASEBAR0_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0018))
18 #define RT2880_PCI_ID ((unsigned long*)(RALINK_PCI_BASE + 0x0030))
19 #define RT2880_PCI_CLASS ((unsigned long*)(RALINK_PCI_BASE + 0x0034))
20 #define RT2880_PCI_SUBID ((unsigned long*)(RALINK_PCI_BASE + 0x0038))
21 #define RT2880_PCI_PCIMSK_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x000C))
23 #define PCI_ACCESS_READ 0
24 #define PCI_ACCESS_WRITE 1
26 static int config_access(unsigned char access_type, struct pci_bus *bus,
27 unsigned int devfn, unsigned char where, u32 * data)
29 unsigned int slot = PCI_SLOT(devfn);
31 u8 func = PCI_FUNC(devfn);
32 address = (bus->number << 16) | (slot << 11) | (func << 8) | (where& 0xfc) | 0x80000000;
33 writel(address, RT2880_PCI_CONFIG_ADDR);
34 if (access_type == PCI_ACCESS_WRITE)
35 writel(*data, RT2880_PCI_CONFIG_DATA);
37 *data = readl(RT2880_PCI_CONFIG_DATA);
42 pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
45 if(config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
46 return PCIBIOS_DEVICE_NOT_FOUND;
48 *val = (data >> ((where & 3) << 3)) & 0xff;
50 *val = (data >> ((where & 3) << 3)) & 0xffff;
53 return PCIBIOS_SUCCESSFUL;
57 pci_config_write(struct pci_bus *bus, unsigned int devfn,
58 int where, int size, u32 val)
65 if(config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
66 return PCIBIOS_DEVICE_NOT_FOUND;
68 data = (data & ~(0xff << ((where & 3) << 3))) |
69 (val << ((where & 3) << 3));
71 data = (data & ~(0xffff << ((where & 3) << 3))) |
72 (val << ((where & 3) << 3));
74 if(config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
75 return PCIBIOS_DEVICE_NOT_FOUND;
76 return PCIBIOS_SUCCESSFUL;
79 struct pci_ops rt2880_pci_ops = {
80 .read = pci_config_read,
81 .write = pci_config_write,
84 static struct resource pci_io_resource = {
85 .name = "pci MEM space",
88 .flags = IORESOURCE_MEM,
91 static struct resource pci_mem_resource = {
92 .name = "pci IO space",
95 .flags = IORESOURCE_IO,
98 struct pci_controller rt2880_controller = {
99 .pci_ops = &rt2880_pci_ops,
100 .mem_resource = &pci_io_resource,
101 .io_resource = &pci_mem_resource,
102 .mem_offset = 0x00000000UL,
103 .io_offset = 0x00000000UL,
107 read_config(unsigned long bus, unsigned long dev, unsigned long func,
108 unsigned long reg, unsigned long *val)
110 unsigned long address =
111 (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
112 writel(address, RT2880_PCI_CONFIG_ADDR);
113 *val = readl(RT2880_PCI_CONFIG_DATA);
117 write_config(unsigned long bus, unsigned long dev, unsigned long func,
118 unsigned long reg, unsigned long val)
120 unsigned long address =
121 (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
122 writel(address, RT2880_PCI_CONFIG_ADDR);
123 writel(val, RT2880_PCI_CONFIG_DATA);
127 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
132 if (dev->bus->number != 0)
135 switch(PCI_SLOT(dev->devfn))
138 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
139 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
142 irq = RT288X_CPU_IRQ_PCI;
145 printk("%s:%s[%d] trying to alloc unknown pci irq\n", __FILE__, __func__, __LINE__);
150 pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
151 pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
152 pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
153 cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
154 PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK | PCI_COMMAND_SERR |
155 PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
156 pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
157 pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE, dev->irq);
164 unsigned long val = 0;
166 writel(0, RT2880_PCI_PCICFG_ADDR);
167 for(i = 0; i < 0xfffff; i++) {}
168 writel(0x79, RT2880_PCI_ARBCTL);
169 writel(0x07FF0001, RT2880_PCI_BAR0SETUP_ADDR);
170 writel(RT2880_PCI_SLOT1_BASE, RT2880_PCI_MEMBASE);
171 writel(0x00460000, RT2880_PCI_IOBASE);
172 writel(0x08000000, RT2880_PCI_IMBASEBAR0_ADDR);
173 writel(0x08021814, RT2880_PCI_ID);
174 writel(0x00800001, RT2880_PCI_CLASS);
175 writel(0x28801814, RT2880_PCI_SUBID);
176 writel(0x000c0000, RT2880_PCI_PCIMSK_ADDR);
177 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
178 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
179 register_pci_controller(&rt2880_controller);
184 pcibios_plat_dev_init(struct pci_dev *dev)
189 struct pci_fixup pcibios_fixups[] = {
193 arch_initcall(init_rt2880pci);