1 #include <linux/types.h>
3 #include <linux/kernel.h>
4 #include <linux/slab.h>
5 #include <linux/version.h>
8 #include <linux/init.h>
9 #include <linux/mod_devicetable.h>
11 #include <asm/mach-ralink/rt288x.h>
12 #include <asm/mach-ralink/rt288x_pci.h>
16 extern int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
17 extern int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
19 struct pci_ops rt2880_pci_ops = {
20 .read = pci_config_read,
21 .write = pci_config_write,
24 static struct resource pci_io_resource = {
25 .name = "pci MEM space",
28 .flags = IORESOURCE_MEM,
31 static struct resource pci_mem_resource = {
32 .name = "pci IO space",
35 .flags = IORESOURCE_IO,
38 struct pci_controller rt2880_controller = {
39 .pci_ops = &rt2880_pci_ops,
40 .mem_resource = &pci_io_resource,
41 .io_resource = &pci_mem_resource,
42 .mem_offset = 0x00000000UL,
43 .io_offset = 0x00000000UL,
47 read_config(unsigned long bus, unsigned long dev, unsigned long func,
48 unsigned long reg, unsigned long *val)
50 unsigned long address =
51 (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
52 writel(address, RT2880_PCI_CONFIG_ADDR);
53 *val = readl(RT2880_PCI_CONFIG_DATA);
57 write_config(unsigned long bus, unsigned long dev, unsigned long func,
58 unsigned long reg, unsigned long val)
60 unsigned long address =
61 (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
62 writel(address, RT2880_PCI_CONFIG_ADDR);
63 writel(val, RT2880_PCI_CONFIG_DATA);
67 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
72 if (dev->bus->number != 0)
75 switch(PCI_SLOT(dev->devfn))
78 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
79 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
82 irq = RT288X_CPU_IRQ_PCI;
85 printk("%s:%s[%d] trying to alloc unknown pci irq\n", __FILE__, __func__, __LINE__);
90 pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
91 pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
92 pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
93 cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
94 PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK | PCI_COMMAND_SERR |
95 PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
96 pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
97 pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE, dev->irq);
104 unsigned long val = 0;
106 writel(0, RT2880_PCI_PCICFG_ADDR);
107 for(i = 0; i < 0xfffff; i++) {}
108 writel(0x79, RT2880_PCI_ARBCTL);
109 writel(0x07FF0001, RT2880_PCI_BAR0SETUP_ADDR);
110 writel(RT2880_PCI_SLOT1_BASE, RT2880_PCI_MEMBASE);
111 writel(0x00460000, RT2880_PCI_IOBASE);
112 writel(0x08000000, RT2880_PCI_IMBASEBAR0_ADDR);
113 writel(0x08021814, RT2880_PCI_ID);
114 writel(0x00800001, RT2880_PCI_CLASS);
115 writel(0x28801814, RT2880_PCI_SUBID);
116 writel(0x000c0000, RT2880_PCI_PCIMSK_ADDR);
117 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
118 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
119 register_pci_controller(&rt2880_controller);
124 pcibios_plat_dev_init(struct pci_dev *dev)
129 struct pci_fixup pcibios_fixups[] = {
133 arch_initcall(init_rt2880pci);