target/linux/omap/patches-3.12/201-ARM-dts-omap-Add-new-bindings-for-OMAP.patch

   1 On OMAP we have co-processor IPs, memory controllers,
   2 GPIOs which control regulators and power switches to
   3 PMIC, and SoC internal Bus IPs, some or most of which
   4 should either not be reset or idled or both at init.
   5 (In some cases there are erratas which prevent an IP
   6 from being reset)
   7 Have a way to pass this information from DT.
   8
   9 Update the am33xx/omap4 and omap5 dtsi files with the
  10 new bindings for modules which either should not be
  11 idled. reset or both. A later patch would cleanup the
  12 same information that exists today as part of the hwmod
  13 data files.
  14
  15 Signed-off-by: Rajendra Nayak <rnayak@ti.com>
  16
  17 ---
  18 .../devicetree/bindings/arm/omap/omap.txt          |    3 ++-
  19  arch/arm/boot/dts/am33xx.dtsi                      |    2 ++
  20  arch/arm/boot/dts/omap4.dtsi                       |    3 +++
  21  arch/arm/boot/dts/omap5.dtsi                       |    2 ++
  22  4 files changed, 9 insertions(+), 1 deletion(-)
  23
  24 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt
  25 +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
  26 @@ -21,7 +21,8 @@ Required properties:
  27  Optional properties:
  28  - ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
  29    during suspend.
  30 -
  31 +- ti,no-reset-on-init: When present, the module should not be reset at init
  32 +- ti,no-idle-on-init: When present, the module should not be idled at init
  33
  34  Example:
  35
  36 --- a/arch/arm/boot/dts/am33xx.dtsi
  37 +++ b/arch/arm/boot/dts/am33xx.dtsi
  38 @@ -667,6 +667,7 @@
  39                         reg = <0x44d00000 0x4000        /* M3 UMEM */
  40                                0x44d80000 0x2000>;      /* M3 DMEM */
  41                         ti,hwmods = "wkup_m3";
  42 +                       ti,no-reset-on-init;
  43                 };
  44
  45                 elm: elm@48080000 {
  46 @@ -697,6 +698,7 @@
  47                 gpmc: gpmc@50000000 {
  48                         compatible = "ti,am3352-gpmc";
  49                         ti,hwmods = "gpmc";
  50 +                       ti,no-idle-on-init;
  51                         reg = <0x50000000 0x2000>;
  52                         interrupts = <100>;
  53                         gpmc,num-cs = <7>;
  54 --- a/arch/arm/boot/dts/omap4.dtsi
  55 +++ b/arch/arm/boot/dts/omap4.dtsi
  56 @@ -214,6 +214,7 @@
  57                         gpmc,num-cs = <8>;
  58                         gpmc,num-waitpins = <4>;
  59                         ti,hwmods = "gpmc";
  60 +                       ti,no-idle-on-init;
  61                 };
  62
  63                 uart1: serial@4806a000 {
  64 @@ -492,6 +493,7 @@
  65                         reg = <0x4c000000 0x100>;
  66                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  67                         ti,hwmods = "emif1";
  68 +                       ti,no-idle-on-init;
  69                         phy-type = <1>;
  70                         hw-caps-read-idle-ctrl;
  71                         hw-caps-ll-interface;
  72 @@ -503,6 +505,7 @@
  73                         reg = <0x4d000000 0x100>;
  74                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  75                         ti,hwmods = "emif2";
  76 +                       ti,no-idle-on-init;
  77                         phy-type = <1>;
  78                         hw-caps-read-idle-ctrl;
  79                         hw-caps-ll-interface;
  80 --- a/arch/arm/boot/dts/omap5.dtsi
  81 +++ b/arch/arm/boot/dts/omap5.dtsi
  82 @@ -607,6 +607,7 @@
  83                 emif1: emif@0x4c000000 {
  84                         compatible      = "ti,emif-4d5";
  85                         ti,hwmods       = "emif1";
  86 +                       ti,no-idle-on-init;
  87                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
  88                         reg = <0x4c000000 0x400>;
  89                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  90 @@ -618,6 +619,7 @@
  91                 emif2: emif@0x4d000000 {
  92                         compatible      = "ti,emif-4d5";
  93                         ti,hwmods       = "emif2";
  94 +                       ti,no-idle-on-init;
  95                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
  96                         reg = <0x4d000000 0x400>;
  97                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;