target/linux/mvebu/patches-3.8/016-arm_cache_l2x0_aurora_invalidate.patch

   1 From e84ed03e1c5d45305fdd9b872e0b7be97bcfda16 Mon Sep 17 00:00:00 2001
   2 From: Gregory CLEMENT <gregory.clement@free-electrons.com>
   3 Date: Thu, 13 Dec 2012 15:03:27 +0100
   4 Subject: [PATCH] arm: cache-l2x0: aurora: Invalidate during clean operation
   5  with WT enable
   6
   7 This patch fixes a bug for Aurora L2 cache controller when the
   8 write-through mode is enable. For the clean operation even if we don't
   9 have to flush the lines we still need to invalidate them.
  10
  11 Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
  12 ---
  13  arch/arm/mm/cache-l2x0.c |   22 ++++++++++++++--------
  14  1 file changed, 14 insertions(+), 8 deletions(-)
  15
  16 diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
  17 index 6911b8b..7ffe943 100644
  18 --- a/arch/arm/mm/cache-l2x0.c
  19 +++ b/arch/arm/mm/cache-l2x0.c
  20 @@ -505,15 +505,21 @@ static void aurora_clean_range(unsigned long start, unsigned long end)
  21
  22  static void aurora_flush_range(unsigned long start, unsigned long end)
  23  {
  24 -       if (!l2_wt_override) {
  25 -               start &= ~(CACHE_LINE_SIZE - 1);
  26 -               end = ALIGN(end, CACHE_LINE_SIZE);
  27 -               while (start != end) {
  28 -                       unsigned long range_end = calc_range_end(start, end);
  29 +       start &= ~(CACHE_LINE_SIZE - 1);
  30 +       end = ALIGN(end, CACHE_LINE_SIZE);
  31 +       while (start != end) {
  32 +               unsigned long range_end = calc_range_end(start, end);
  33 +               /*
  34 +                * If L2 is forced to WT, the L2 will always be clean and we
  35 +                * just need to invalidate.
  36 +                */
  37 +               if (l2_wt_override)
  38                         aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
  39 -                                       AURORA_FLUSH_RANGE_REG);
  40 -                       start = range_end;
  41 -               }
  42 +                                                       AURORA_INVAL_RANGE_REG);
  43 +               else
  44 +                       aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
  45 +                                                       AURORA_FLUSH_RANGE_REG);
  46 +               start = range_end;
  47         }
  48  }
  49
  50 --
  51 1.7.10.4
  52