target/linux/mvebu/patches-3.10/0200-PCI-mvebu-move-clock-enable-before-register-access.patch

   1 From c524c5790d413b37702013e7e83a845fd3f007ac Mon Sep 17 00:00:00 2001
   2 From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   3 Date: Tue, 13 Aug 2013 14:25:20 +0200
   4 Subject: [PATCH 200/203] PCI: mvebu: move clock enable before register access
   5
   6 The clock passed to PCI controller found on MVEBU SoCs may come from a
   7 clock gate. This requires the clock to be enabled before any registers
   8 are accessed. Therefore, move the clock enable before register iomap to
   9 ensure it is enabled.
  10
  11 Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  12 Signed-off-by: Jason Cooper <jason@lakedaemon.net>
  13 ---
  14  drivers/pci/host/pci-mvebu.c | 25 ++++++++++++-------------
  15  1 file changed, 12 insertions(+), 13 deletions(-)
  16
  17 --- a/drivers/pci/host/pci-mvebu.c
  18 +++ b/drivers/pci/host/pci-mvebu.c
  19 @@ -896,11 +896,23 @@ static int __init mvebu_pcie_probe(struc
  20                         continue;
  21                 }
  22
  23 +               port->clk = of_clk_get_by_name(child, NULL);
  24 +               if (IS_ERR(port->clk)) {
  25 +                       dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
  26 +                              port->port, port->lane);
  27 +                       continue;
  28 +               }
  29 +
  30 +               ret = clk_prepare_enable(port->clk);
  31 +               if (ret)
  32 +                       continue;
  33 +
  34                 port->base = mvebu_pcie_map_registers(pdev, child, port);
  35                 if (IS_ERR(port->base)) {
  36                         dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
  37                                 port->port, port->lane);
  38                         port->base = NULL;
  39 +                       clk_disable_unprepare(port->clk);
  40                         continue;
  41                 }
  42
  43 @@ -916,22 +928,9 @@ static int __init mvebu_pcie_probe(struc
  44                                  port->port, port->lane);
  45                 }
  46
  47 -               port->clk = of_clk_get_by_name(child, NULL);
  48 -               if (!port->clk) {
  49 -                       dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
  50 -                              port->port, port->lane);
  51 -                       iounmap(port->base);
  52 -                       port->haslink = 0;
  53 -                       continue;
  54 -               }
  55 -
  56                 port->dn = child;
  57 -
  58 -               clk_prepare_enable(port->clk);
  59                 spin_lock_init(&port->conf_lock);
  60 -
  61                 mvebu_sw_pci_bridge_init(port);
  62 -
  63                 i++;
  64         }
  65