target/linux/mvebu/patches-3.10/0138-mtd-nand-pxa3xx-Replace-host-page_size-by-mtd-writes.patch

   1 From ad40a597cbfeb2374c799ba6dad3a69f131511c8 Mon Sep 17 00:00:00 2001
   2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
   3 Date: Thu, 7 Nov 2013 12:17:17 -0300
   4 Subject: [PATCH 138/203] mtd: nand: pxa3xx: Replace host->page_size by
   5  mtd->writesize
   6
   7 There's no need to privately store the device page size as it's
   8 available in mtd structure field mtd->writesize.
   9 Also, this removes the hardcoded page size value, leaving the
  10 auto-detected value only.
  11
  12 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
  13 Tested-by: Daniel Mack <zonque@gmail.com>
  14 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
  15 ---
  16  drivers/mtd/nand/pxa3xx_nand.c | 10 +++-------
  17  1 file changed, 3 insertions(+), 7 deletions(-)
  18
  19 --- a/drivers/mtd/nand/pxa3xx_nand.c
  20 +++ b/drivers/mtd/nand/pxa3xx_nand.c
  21 @@ -151,7 +151,6 @@ struct pxa3xx_nand_host {
  22         void                    *info_data;
  23
  24         /* page size of attached chip */
  25 -       unsigned int            page_size;
  26         int                     use_ecc;
  27         int                     cs;
  28
  29 @@ -614,12 +613,12 @@ static int prepare_command_pool(struct p
  30                         info->buf_start += mtd->writesize;
  31
  32                 /* Second command setting for large pages */
  33 -               if (host->page_size >= PAGE_CHUNK_SIZE)
  34 +               if (mtd->writesize >= PAGE_CHUNK_SIZE)
  35                         info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
  36
  37         case NAND_CMD_SEQIN:
  38                 /* small page addr setting */
  39 -               if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
  40 +               if (unlikely(mtd->writesize < PAGE_CHUNK_SIZE)) {
  41                         info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
  42                                         | (column & 0xFF);
  43
  44 @@ -895,7 +894,6 @@ static int pxa3xx_nand_config_flash(stru
  45         }
  46
  47         /* calculate flash information */
  48 -       host->page_size = f->page_size;
  49         host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
  50
  51         /* calculate addressing information */
  52 @@ -934,11 +932,9 @@ static int pxa3xx_nand_detect_config(str
  53         if (ndcr & NDCR_PAGE_SZ) {
  54                 /* Controller's FIFO size */
  55                 info->fifo_size = 2048;
  56 -               host->page_size = 2048;
  57                 host->read_id_bytes = 4;
  58         } else {
  59                 info->fifo_size = 512;
  60 -               host->page_size = 512;
  61                 host->read_id_bytes = 2;
  62         }
  63
  64 @@ -1106,7 +1102,7 @@ static int pxa3xx_nand_scan(struct mtd_i
  65         def = pxa3xx_flash_ids;
  66  KEEP_CONFIG:
  67         chip->ecc.mode = NAND_ECC_HW;
  68 -       chip->ecc.size = host->page_size;
  69 +       chip->ecc.size = info->fifo_size;
  70         chip->ecc.strength = 1;
  71
  72         if (info->reg_ndcr & NDCR_DWIDTH_M)