mvebu: backport mainline patches from kernel 3.13
[openwrt.git] / target / linux / mvebu / patches-3.10 / 0137-mtd-nand-pxa3xx-Split-FIFO-size-from-to-be-read-FIFO.patch
1 From 496f307424d3958ef43ad06ae6a0be98ede2a92c Mon Sep 17 00:00:00 2001
2 From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
3 Date: Thu, 7 Nov 2013 12:17:16 -0300
4 Subject: [PATCH 137/203] mtd: nand: pxa3xx: Split FIFO size from to-be-read
5  FIFO count
6
7 Introduce a fifo_size field to represent the size of the controller's
8 FIFO buffer, and use it to distinguish that size from the amount
9 of data bytes to be read from the FIFO.
10
11 This is important to support devices with pages larger than the
12 controller's internal FIFO, that need to read the pages in FIFO-sized
13 chunks.
14
15 In particular, the current code is at least confusing, for it mixes
16 all the different sizes involved: FIFO size, page size and data size.
17
18 This commit starts the cleaning by removing the info->page_size field
19 that is not currently used. The host->page_size field should also
20 be removed and use always mtd->writesize instead. Follow up commits
21 will clean this up.
22
23 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
24 Tested-by: Daniel Mack <zonque@gmail.com>
25 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
26 ---
27  drivers/mtd/nand/pxa3xx_nand.c | 12 +++++++-----
28  1 file changed, 7 insertions(+), 5 deletions(-)
29
30 --- a/drivers/mtd/nand/pxa3xx_nand.c
31 +++ b/drivers/mtd/nand/pxa3xx_nand.c
32 @@ -201,8 +201,8 @@ struct pxa3xx_nand_info {
33         int                     use_spare;      /* use spare ? */
34         int                     is_ready;
35  
36 -       unsigned int            page_size;      /* page size of attached chip */
37 -       unsigned int            data_size;      /* data size in FIFO */
38 +       unsigned int            fifo_size;      /* max. data size in the FIFO */
39 +       unsigned int            data_size;      /* data to be read from FIFO */
40         unsigned int            oob_size;
41         int                     retcode;
42  
43 @@ -307,16 +307,15 @@ static void pxa3xx_nand_set_timing(struc
44  
45  static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
46  {
47 -       struct pxa3xx_nand_host *host = info->host[info->cs];
48         int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
49  
50 -       info->data_size = host->page_size;
51 +       info->data_size = info->fifo_size;
52         if (!oob_enable) {
53                 info->oob_size = 0;
54                 return;
55         }
56  
57 -       switch (host->page_size) {
58 +       switch (info->fifo_size) {
59         case 2048:
60                 info->oob_size = (info->use_ecc) ? 40 : 64;
61                 break;
62 @@ -933,9 +932,12 @@ static int pxa3xx_nand_detect_config(str
63         uint32_t ndcr = nand_readl(info, NDCR);
64  
65         if (ndcr & NDCR_PAGE_SZ) {
66 +               /* Controller's FIFO size */
67 +               info->fifo_size = 2048;
68                 host->page_size = 2048;
69                 host->read_id_bytes = 4;
70         } else {
71 +               info->fifo_size = 512;
72                 host->page_size = 512;
73                 host->read_id_bytes = 2;
74         }