target/linux/mpc83xx/patches/002-mpc8377e-wlan_support.patch

   1 From fda4bd9bac78efd2f9d566c52956d297bc03e8d9 Mon Sep 17 00:00:00 2001
   2 From: Anton Vorontsov <avorontsov@ru.mvista.com>
   3 Date: Sat, 25 Jul 2009 01:42:17 +0400
   4 Subject: [PATCH] powerpc/83xx: Add support for MPC8377E-WLAN boards
   5
   6 MPC8377E-WLAN are basically RDB boards except:
   7
   8 - RAM extended to 512 MB;
   9 - NAND flash removed, NOR flash extended to 64 MB;
  10 - Vitesse VSC7385 5-port switch removed, RTL8211B PHY added;
  11 - Power management MCU removed;
  12 - PCI slot removed, another mini-PCI slot added (IRQ routing changed);
  13 - USB3300 PHY's ID pin grounded, thus USB port is host-only.
  14
  15 Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
  16 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
  17 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
  18 ---
  19  arch/powerpc/boot/dts/mpc8377_wlan.dts    |  464 +++++++++++++++++++++++++++++
  20  arch/powerpc/platforms/83xx/Kconfig       |    4 +-
  21  arch/powerpc/platforms/83xx/mpc837x_rdb.c |    5 +-
  22  3 files changed, 469 insertions(+), 4 deletions(-)
  23  create mode 100644 arch/powerpc/boot/dts/mpc8377_wlan.dts
  24
  25 --- /dev/null
  26 +++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
  27 @@ -0,0 +1,464 @@
  28 +/*
  29 + * MPC8377E WLAN Device Tree Source
  30 + *
  31 + * Copyright 2007-2009 Freescale Semiconductor Inc.
  32 + * Copyright 2009 MontaVista Software, Inc.
  33 + *
  34 + * This program is free software; you can redistribute  it and/or modify it
  35 + * under  the terms of  the GNU General  Public License as published by the
  36 + * Free Software Foundation;  either version 2 of the  License, or (at your
  37 + * option) any later version.
  38 + */
  39 +
  40 +/dts-v1/;
  41 +
  42 +/ {
  43 +       compatible = "fsl,mpc8377wlan";
  44 +       #address-cells = <1>;
  45 +       #size-cells = <1>;
  46 +
  47 +       aliases {
  48 +               ethernet0 = &enet0;
  49 +               ethernet1 = &enet1;
  50 +               serial0 = &serial0;
  51 +               serial1 = &serial1;
  52 +               pci0 = &pci0;
  53 +               pci1 = &pci1;
  54 +               pci2 = &pci2;
  55 +       };
  56 +
  57 +       cpus {
  58 +               #address-cells = <1>;
  59 +               #size-cells = <0>;
  60 +
  61 +               PowerPC,8377@0 {
  62 +                       device_type = "cpu";
  63 +                       reg = <0x0>;
  64 +                       d-cache-line-size = <32>;
  65 +                       i-cache-line-size = <32>;
  66 +                       d-cache-size = <32768>;
  67 +                       i-cache-size = <32768>;
  68 +                       timebase-frequency = <0>;
  69 +                       bus-frequency = <0>;
  70 +                       clock-frequency = <0>;
  71 +               };
  72 +       };
  73 +
  74 +       memory {
  75 +               device_type = "memory";
  76 +               reg = <0x00000000 0x20000000>;  // 512MB at 0
  77 +       };
  78 +
  79 +       localbus@e0005000 {
  80 +               #address-cells = <2>;
  81 +               #size-cells = <1>;
  82 +               compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
  83 +               reg = <0xe0005000 0x1000>;
  84 +               interrupts = <77 0x8>;
  85 +               interrupt-parent = <&ipic>;
  86 +               ranges = <0x0 0x0 0xfc000000 0x04000000>;
  87 +
  88 +               flash@0,0 {
  89 +                       #address-cells = <1>;
  90 +                       #size-cells = <1>;
  91 +                       compatible = "cfi-flash";
  92 +                       reg = <0x0 0x0 0x4000000>;
  93 +                       bank-width = <2>;
  94 +                       device-width = <1>;
  95 +
  96 +                       partition@0 {
  97 +                               reg = <0 0x8000>;
  98 +                               label = "u-boot";
  99 +                               read-only;
 100 +                       };
 101 +
 102 +                       partition@a0000 {
 103 +                               reg = <0xa0000 0x300000>;
 104 +                               label = "kernel";
 105 +                       };
 106 +
 107 +                       partition@3a0000 {
 108 +                               reg = <0x3a0000 0x3c60000>;
 109 +                               label = "rootfs";
 110 +                       };
 111 +               };
 112 +       };
 113 +
 114 +       immr@e0000000 {
 115 +               #address-cells = <1>;
 116 +               #size-cells = <1>;
 117 +               device_type = "soc";
 118 +               compatible = "simple-bus";
 119 +               ranges = <0x0 0xe0000000 0x00100000>;
 120 +               reg = <0xe0000000 0x00000200>;
 121 +               bus-frequency = <0>;
 122 +
 123 +               wdt@200 {
 124 +                       device_type = "watchdog";
 125 +                       compatible = "mpc83xx_wdt";
 126 +                       reg = <0x200 0x100>;
 127 +               };
 128 +
 129 +               gpio1: gpio-controller@c00 {
 130 +                       #gpio-cells = <2>;
 131 +                       compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
 132 +                       reg = <0xc00 0x100>;
 133 +                       interrupts = <74 0x8>;
 134 +                       interrupt-parent = <&ipic>;
 135 +                       gpio-controller;
 136 +               };
 137 +
 138 +               gpio2: gpio-controller@d00 {
 139 +                       #gpio-cells = <2>;
 140 +                       compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
 141 +                       reg = <0xd00 0x100>;
 142 +                       interrupts = <75 0x8>;
 143 +                       interrupt-parent = <&ipic>;
 144 +                       gpio-controller;
 145 +               };
 146 +
 147 +               sleep-nexus {
 148 +                       #address-cells = <1>;
 149 +                       #size-cells = <1>;
 150 +                       compatible = "simple-bus";
 151 +                       sleep = <&pmc 0x0c000000>;
 152 +                       ranges;
 153 +
 154 +                       i2c@3000 {
 155 +                               #address-cells = <1>;
 156 +                               #size-cells = <0>;
 157 +                               cell-index = <0>;
 158 +                               compatible = "fsl-i2c";
 159 +                               reg = <0x3000 0x100>;
 160 +                               interrupts = <14 0x8>;
 161 +                               interrupt-parent = <&ipic>;
 162 +                               dfsrr;
 163 +
 164 +                               at24@50 {
 165 +                                       compatible = "at24,24c256";
 166 +                                       reg = <0x50>;
 167 +                               };
 168 +
 169 +                               rtc@68 {
 170 +                                       compatible = "dallas,ds1339";
 171 +                                       reg = <0x68>;
 172 +                               };
 173 +                       };
 174 +
 175 +                       sdhci@2e000 {
 176 +                               compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
 177 +                               reg = <0x2e000 0x1000>;
 178 +                               interrupts = <42 0x8>;
 179 +                               interrupt-parent = <&ipic>;
 180 +                               clock-frequency = <133333333>;
 181 +                       };
 182 +               };
 183 +
 184 +               i2c@3100 {
 185 +                       #address-cells = <1>;
 186 +                       #size-cells = <0>;
 187 +                       cell-index = <1>;
 188 +                       compatible = "fsl-i2c";
 189 +                       reg = <0x3100 0x100>;
 190 +                       interrupts = <15 0x8>;
 191 +                       interrupt-parent = <&ipic>;
 192 +                       dfsrr;
 193 +               };
 194 +
 195 +               spi@7000 {
 196 +                       cell-index = <0>;
 197 +                       compatible = "fsl,spi";
 198 +                       reg = <0x7000 0x1000>;
 199 +                       interrupts = <16 0x8>;
 200 +                       interrupt-parent = <&ipic>;
 201 +                       mode = "cpu";
 202 +               };
 203 +
 204 +               dma@82a8 {
 205 +                       #address-cells = <1>;
 206 +                       #size-cells = <1>;
 207 +                       compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
 208 +                       reg = <0x82a8 4>;
 209 +                       ranges = <0 0x8100 0x1a8>;
 210 +                       interrupt-parent = <&ipic>;
 211 +                       interrupts = <71 8>;
 212 +                       cell-index = <0>;
 213 +                       dma-channel@0 {
 214 +                               compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 215 +                               reg = <0 0x80>;
 216 +                               cell-index = <0>;
 217 +                               interrupt-parent = <&ipic>;
 218 +                               interrupts = <71 8>;
 219 +                       };
 220 +                       dma-channel@80 {
 221 +                               compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 222 +                               reg = <0x80 0x80>;
 223 +                               cell-index = <1>;
 224 +                               interrupt-parent = <&ipic>;
 225 +                               interrupts = <71 8>;
 226 +                       };
 227 +                       dma-channel@100 {
 228 +                               compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 229 +                               reg = <0x100 0x80>;
 230 +                               cell-index = <2>;
 231 +                               interrupt-parent = <&ipic>;
 232 +                               interrupts = <71 8>;
 233 +                       };
 234 +                       dma-channel@180 {
 235 +                               compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 236 +                               reg = <0x180 0x28>;
 237 +                               cell-index = <3>;
 238 +                               interrupt-parent = <&ipic>;
 239 +                               interrupts = <71 8>;
 240 +                       };
 241 +               };
 242 +
 243 +               usb@23000 {
 244 +                       compatible = "fsl-usb2-dr";
 245 +                       reg = <0x23000 0x1000>;
 246 +                       #address-cells = <1>;
 247 +                       #size-cells = <0>;
 248 +                       interrupt-parent = <&ipic>;
 249 +                       interrupts = <38 0x8>;
 250 +                       phy_type = "ulpi";
 251 +                       sleep = <&pmc 0x00c00000>;
 252 +               };
 253 +
 254 +               enet0: ethernet@24000 {
 255 +                       #address-cells = <1>;
 256 +                       #size-cells = <1>;
 257 +                       cell-index = <0>;
 258 +                       device_type = "network";
 259 +                       model = "eTSEC";
 260 +                       compatible = "gianfar";
 261 +                       reg = <0x24000 0x1000>;
 262 +                       ranges = <0x0 0x24000 0x1000>;
 263 +                       local-mac-address = [ 00 00 00 00 00 00 ];
 264 +                       interrupts = <32 0x8 33 0x8 34 0x8>;
 265 +                       phy-connection-type = "mii";
 266 +                       interrupt-parent = <&ipic>;
 267 +                       tbi-handle = <&tbi0>;
 268 +                       phy-handle = <&phy2>;
 269 +                       sleep = <&pmc 0xc0000000>;
 270 +                       fsl,magic-packet;
 271 +
 272 +                       mdio@520 {
 273 +                               #address-cells = <1>;
 274 +                               #size-cells = <0>;
 275 +                               compatible = "fsl,gianfar-mdio";
 276 +                               reg = <0x520 0x20>;
 277 +
 278 +                               phy2: ethernet-phy@2 {
 279 +                                       interrupt-parent = <&ipic>;
 280 +                                       interrupts = <17 0x8>;
 281 +                                       reg = <0x2>;
 282 +                                       device_type = "ethernet-phy";
 283 +                               };
 284 +
 285 +                               phy3: ethernet-phy@3 {
 286 +                                       interrupt-parent = <&ipic>;
 287 +                                       interrupts = <18 0x8>;
 288 +                                       reg = <0x3>;
 289 +                                       device_type = "ethernet-phy";
 290 +                               };
 291 +
 292 +                               tbi0: tbi-phy@11 {
 293 +                                       reg = <0x11>;
 294 +                                       device_type = "tbi-phy";
 295 +                               };
 296 +                       };
 297 +               };
 298 +
 299 +               enet1: ethernet@25000 {
 300 +                       #address-cells = <1>;
 301 +                       #size-cells = <1>;
 302 +                       cell-index = <1>;
 303 +                       device_type = "network";
 304 +                       model = "eTSEC";
 305 +                       compatible = "gianfar";
 306 +                       reg = <0x25000 0x1000>;
 307 +                       ranges = <0x0 0x25000 0x1000>;
 308 +                       local-mac-address = [ 00 00 00 00 00 00 ];
 309 +                       interrupts = <35 0x8 36 0x8 37 0x8>;
 310 +                       phy-connection-type = "mii";
 311 +                       interrupt-parent = <&ipic>;
 312 +                       phy-handle = <&phy3>;
 313 +                       tbi-handle = <&tbi1>;
 314 +                       sleep = <&pmc 0x30000000>;
 315 +                       fsl,magic-packet;
 316 +
 317 +                       mdio@520 {
 318 +                               #address-cells = <1>;
 319 +                               #size-cells = <0>;
 320 +                               compatible = "fsl,gianfar-tbi";
 321 +                               reg = <0x520 0x20>;
 322 +
 323 +                               tbi1: tbi-phy@11 {
 324 +                                       reg = <0x11>;
 325 +                                       device_type = "tbi-phy";
 326 +                               };
 327 +                       };
 328 +               };
 329 +
 330 +               serial0: serial@4500 {
 331 +                       cell-index = <0>;
 332 +                       device_type = "serial";
 333 +                       compatible = "ns16550";
 334 +                       reg = <0x4500 0x100>;
 335 +                       clock-frequency = <0>;
 336 +                       interrupts = <9 0x8>;
 337 +                       interrupt-parent = <&ipic>;
 338 +               };
 339 +
 340 +               serial1: serial@4600 {
 341 +                       cell-index = <1>;
 342 +                       device_type = "serial";
 343 +                       compatible = "ns16550";
 344 +                       reg = <0x4600 0x100>;
 345 +                       clock-frequency = <0>;
 346 +                       interrupts = <10 0x8>;
 347 +                       interrupt-parent = <&ipic>;
 348 +               };
 349 +
 350 +               crypto@30000 {
 351 +                       compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
 352 +                                    "fsl,sec2.1", "fsl,sec2.0";
 353 +                       reg = <0x30000 0x10000>;
 354 +                       interrupts = <11 0x8>;
 355 +                       interrupt-parent = <&ipic>;
 356 +                       fsl,num-channels = <4>;
 357 +                       fsl,channel-fifo-len = <24>;
 358 +                       fsl,exec-units-mask = <0x9fe>;
 359 +                       fsl,descriptor-types-mask = <0x3ab0ebf>;
 360 +                       sleep = <&pmc 0x03000000>;
 361 +               };
 362 +
 363 +               sata@18000 {
 364 +                       compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
 365 +                       reg = <0x18000 0x1000>;
 366 +                       interrupts = <44 0x8>;
 367 +                       interrupt-parent = <&ipic>;
 368 +                       sleep = <&pmc 0x000000c0>;
 369 +               };
 370 +
 371 +               sata@19000 {
 372 +                       compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
 373 +                       reg = <0x19000 0x1000>;
 374 +                       interrupts = <45 0x8>;
 375 +                       interrupt-parent = <&ipic>;
 376 +                       sleep = <&pmc 0x00000030>;
 377 +               };
 378 +
 379 +               /* IPIC
 380 +                * interrupts cell = <intr #, sense>
 381 +                * sense values match linux IORESOURCE_IRQ_* defines:
 382 +                * sense == 8: Level, low assertion
 383 +                * sense == 2: Edge, high-to-low change
 384 +                */
 385 +               ipic: interrupt-controller@700 {
 386 +                       compatible = "fsl,ipic";
 387 +                       interrupt-controller;
 388 +                       #address-cells = <0>;
 389 +                       #interrupt-cells = <2>;
 390 +                       reg = <0x700 0x100>;
 391 +               };
 392 +
 393 +               pmc: power@b00 {
 394 +                       compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
 395 +                       reg = <0xb00 0x100 0xa00 0x100>;
 396 +                       interrupts = <80 0x8>;
 397 +                       interrupt-parent = <&ipic>;
 398 +               };
 399 +       };
 400 +
 401 +       pci0: pci@e0008500 {
 402 +               interrupt-map-mask = <0xf800 0 0 7>;
 403 +               interrupt-map = <
 404 +                               /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
 405 +
 406 +                               /* IDSEL AD14 IRQ6 inta */
 407 +                                0x7000 0x0 0x0 0x1 &ipic 22 0x8
 408 +
 409 +                               /* IDSEL AD15 IRQ5 inta */
 410 +                                0x7800 0x0 0x0 0x1 &ipic 21 0x8>;
 411 +               interrupt-parent = <&ipic>;
 412 +               interrupts = <66 0x8>;
 413 +               bus-range = <0 0>;
 414 +               ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 415 +                         0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 416 +                         0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
 417 +               sleep = <&pmc 0x00010000>;
 418 +               clock-frequency = <66666666>;
 419 +               #interrupt-cells = <1>;
 420 +               #size-cells = <2>;
 421 +               #address-cells = <3>;
 422 +               reg = <0xe0008500 0x100         /* internal registers */
 423 +                      0xe0008300 0x8>;         /* config space access registers */
 424 +               compatible = "fsl,mpc8349-pci";
 425 +               device_type = "pci";
 426 +       };
 427 +
 428 +       pci1: pcie@e0009000 {
 429 +               #address-cells = <3>;
 430 +               #size-cells = <2>;
 431 +               #interrupt-cells = <1>;
 432 +               device_type = "pci";
 433 +               compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
 434 +               reg = <0xe0009000 0x00001000>;
 435 +               ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
 436 +                         0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
 437 +               bus-range = <0 255>;
 438 +               interrupt-map-mask = <0xf800 0 0 7>;
 439 +               interrupt-map = <0 0 0 1 &ipic 1 8
 440 +                                0 0 0 2 &ipic 1 8
 441 +                                0 0 0 3 &ipic 1 8
 442 +                                0 0 0 4 &ipic 1 8>;
 443 +               sleep = <&pmc 0x00300000>;
 444 +               clock-frequency = <0>;
 445 +
 446 +               pcie@0 {
 447 +                       #address-cells = <3>;
 448 +                       #size-cells = <2>;
 449 +                       device_type = "pci";
 450 +                       reg = <0 0 0 0 0>;
 451 +                       ranges = <0x02000000 0 0xa8000000
 452 +                                 0x02000000 0 0xa8000000
 453 +                                 0 0x10000000
 454 +                                 0x01000000 0 0x00000000
 455 +                                 0x01000000 0 0x00000000
 456 +                                 0 0x00800000>;
 457 +               };
 458 +       };
 459 +
 460 +       pci2: pcie@e000a000 {
 461 +               #address-cells = <3>;
 462 +               #size-cells = <2>;
 463 +               #interrupt-cells = <1>;
 464 +               device_type = "pci";
 465 +               compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
 466 +               reg = <0xe000a000 0x00001000>;
 467 +               ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
 468 +                         0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
 469 +               bus-range = <0 255>;
 470 +               interrupt-map-mask = <0xf800 0 0 7>;
 471 +               interrupt-map = <0 0 0 1 &ipic 2 8
 472 +                                0 0 0 2 &ipic 2 8
 473 +                                0 0 0 3 &ipic 2 8
 474 +                                0 0 0 4 &ipic 2 8>;
 475 +               sleep = <&pmc 0x000c0000>;
 476 +               clock-frequency = <0>;
 477 +
 478 +               pcie@0 {
 479 +                       #address-cells = <3>;
 480 +                       #size-cells = <2>;
 481 +                       device_type = "pci";
 482 +                       reg = <0 0 0 0 0>;
 483 +                       ranges = <0x02000000 0 0xc8000000
 484 +                                 0x02000000 0 0xc8000000
 485 +                                 0 0x10000000
 486 +                                 0x01000000 0 0x00000000
 487 +                                 0x01000000 0 0x00000000
 488 +                                 0 0x00800000>;
 489 +               };
 490 +       };
 491 +};
 492 --- a/arch/powerpc/platforms/83xx/Kconfig
 493 +++ b/arch/powerpc/platforms/83xx/Kconfig
 494 @@ -84,11 +84,11 @@ config MPC837x_MDS
 495           This option enables support for the MPC837x MDS Processor Board.
 496
 497  config MPC837x_RDB
 498 -       bool "Freescale MPC837x RDB"
 499 +       bool "Freescale MPC837x RDB/WLAN"
 500         select DEFAULT_UIMAGE
 501         select PPC_MPC837x
 502         help
 503 -         This option enables support for the MPC837x RDB Board.
 504 +         This option enables support for the MPC837x RDB and WLAN Boards.
 505
 506  config SBC834x
 507         bool "Wind River SBC834x"
 508 --- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
 509 +++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
 510 @@ -86,11 +86,12 @@ static int __init mpc837x_rdb_probe(void
 511
 512         return of_flat_dt_is_compatible(root, "fsl,mpc8377rdb") ||
 513                of_flat_dt_is_compatible(root, "fsl,mpc8378rdb") ||
 514 -              of_flat_dt_is_compatible(root, "fsl,mpc8379rdb");
 515 +              of_flat_dt_is_compatible(root, "fsl,mpc8379rdb") ||
 516 +              of_flat_dt_is_compatible(root, "fsl,mpc8377wlan");
 517  }
 518
 519  define_machine(mpc837x_rdb) {
 520 -       .name                   = "MPC837x RDB",
 521 +       .name                   = "MPC837x RDB/WLAN",
 522         .probe                  = mpc837x_rdb_probe,
 523         .setup_arch             = mpc837x_rdb_setup_arch,
 524         .init_IRQ               = mpc837x_rdb_init_IRQ,