target/linux/lantiq/patches/0004-MIPS-lantiq-reorganize-xway-code.patch

   1 From d90739a8962b541969b4c5f7ef1df8fec9c7f153 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 10 Aug 2011 14:57:04 +0200
   4 Subject: [PATCH 04/24] MIPS: lantiq: reorganize xway code
   5
   6 Inside the folder arch/mips/lantiq/xway, there were alot of small files with
   7 lots of duplicated code. This patch adds a wrapper function for inserting and
   8 requesting resources and unifies the small files into one bigger file.
   9
  10 This patch makes the xway code consistent with the falcon support added later
  11 in this series.
  12
  13 Signed-off-by: John Crispin <blogic@openwrt.org>
  14 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  15 Cc: linux-mips@linux-mips.org
  16 ---
  17  arch/mips/include/asm/mach-lantiq/lantiq.h         |   14 +---
  18  .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   14 ++++
  19  arch/mips/lantiq/clk.c                             |   25 +------
  20  arch/mips/lantiq/devices.c                         |   30 ++------
  21  arch/mips/lantiq/devices.h                         |    4 +
  22  arch/mips/lantiq/prom.c                            |   50 +++++++++++--
  23  arch/mips/lantiq/prom.h                            |    4 +
  24  arch/mips/lantiq/xway/Makefile                     |    6 +-
  25  arch/mips/lantiq/xway/devices.c                    |   42 ++---------
  26  arch/mips/lantiq/xway/dma.c                        |   21 ++----
  27  arch/mips/lantiq/xway/ebu.c                        |   53 --------------
  28  arch/mips/lantiq/xway/pmu.c                        |   70 ------------------
  29  arch/mips/lantiq/xway/prom-ase.c                   |    9 +++
  30  arch/mips/lantiq/xway/prom-xway.c                  |   10 +++
  31  arch/mips/lantiq/xway/reset.c                      |   21 ++----
  32  arch/mips/lantiq/xway/setup-ase.c                  |   19 -----
  33  arch/mips/lantiq/xway/setup-xway.c                 |   20 -----
  34  arch/mips/lantiq/xway/sysctrl.c                    |   77 ++++++++++++++++++++
  35  drivers/watchdog/lantiq_wdt.c                      |    2 +-
  36  19 files changed, 197 insertions(+), 294 deletions(-)
  37  delete mode 100644 arch/mips/lantiq/xway/ebu.c
  38  delete mode 100644 arch/mips/lantiq/xway/pmu.c
  39  delete mode 100644 arch/mips/lantiq/xway/setup-ase.c
  40  delete mode 100644 arch/mips/lantiq/xway/setup-xway.c
  41  create mode 100644 arch/mips/lantiq/xway/sysctrl.c
  42
  43 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
  44 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
  45 @@ -9,6 +9,7 @@
  46  #define _LANTIQ_H__
  47
  48  #include <linux/irq.h>
  49 +#include <linux/ioport.h>
  50
  51  /* generic reg access functions */
  52  #define ltq_r32(reg)           __raw_readl(reg)
  53 @@ -18,15 +19,6 @@
  54  #define ltq_r8(reg)            __raw_readb(reg)
  55  #define ltq_w8(val, reg)       __raw_writeb(val, reg)
  56
  57 -/* register access macros for EBU and CGU */
  58 -#define ltq_ebu_w32(x, y)      ltq_w32((x), ltq_ebu_membase + (y))
  59 -#define ltq_ebu_r32(x)         ltq_r32(ltq_ebu_membase + (x))
  60 -#define ltq_cgu_w32(x, y)      ltq_w32((x), ltq_cgu_membase + (y))
  61 -#define ltq_cgu_r32(x)         ltq_r32(ltq_cgu_membase + (x))
  62 -
  63 -extern __iomem void *ltq_ebu_membase;
  64 -extern __iomem void *ltq_cgu_membase;
  65 -
  66  extern unsigned int ltq_get_cpu_ver(void);
  67  extern unsigned int ltq_get_soc_type(void);
  68
  69 @@ -51,7 +43,9 @@ extern void ltq_enable_irq(struct irq_da
  70
  71  /* find out what caused the last cpu reset */
  72  extern int ltq_reset_cause(void);
  73 -#define LTQ_RST_CAUSE_WDTRST   0x20
  74 +
  75 +/* helper for requesting and remapping resources */
  76 +extern void __iomem *ltq_remap_resource(struct resource *res);
  77
  78  #define IOPORT_RESOURCE_START  0x10000000
  79  #define IOPORT_RESOURCE_END    0xffffffff
  80 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  81 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
  82 @@ -65,6 +65,8 @@
  83  #define LTQ_CGU_BASE_ADDR      0x1F103000
  84  #define LTQ_CGU_SIZE           0x1000
  85
  86 +#define CGU_EPHY               0x10
  87 +
  88  /* ICU - interrupt control unit */
  89  #define LTQ_ICU_BASE_ADDR      0x1F880200
  90  #define LTQ_ICU_SIZE           0x100
  91 @@ -101,6 +103,8 @@
  92  #define LTQ_WDT_BASE_ADDR      0x1F8803F0
  93  #define LTQ_WDT_SIZE           0x10
  94
  95 +#define LTQ_RST_CAUSE_WDTRST   0x20
  96 +
  97  /* STP - serial to parallel conversion unit */
  98  #define LTQ_STP_BASE_ADDR      0x1E100BB0
  99  #define LTQ_STP_SIZE           0x40
 100 @@ -125,11 +129,21 @@
 101  #define LTQ_MPS_BASE_ADDR      (KSEG1 + 0x1F107000)
 102  #define LTQ_MPS_CHIPID         ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
 103
 104 +/* register access macros for EBU and CGU */
 105 +#define ltq_ebu_w32(x, y)      ltq_w32((x), ltq_ebu_membase + (y))
 106 +#define ltq_ebu_r32(x)         ltq_r32(ltq_ebu_membase + (x))
 107 +#define ltq_cgu_w32(x, y)      ltq_w32((x), ltq_cgu_membase + (y))
 108 +#define ltq_cgu_r32(x)         ltq_r32(ltq_cgu_membase + (x))
 109 +
 110 +extern __iomem void *ltq_ebu_membase;
 111 +extern __iomem void *ltq_cgu_membase;
 112 +
 113  /* request a non-gpio and set the PIO config */
 114  extern int  ltq_gpio_request(unsigned int pin, unsigned int alt0,
 115         unsigned int alt1, unsigned int dir, const char *name);
 116  extern void ltq_pmu_enable(unsigned int module);
 117  extern void ltq_pmu_disable(unsigned int module);
 118 +extern void ltq_cgu_enable(unsigned int clk);
 119
 120  static inline int ltq_is_ar9(void)
 121  {
 122 --- a/arch/mips/lantiq/clk.c
 123 +++ b/arch/mips/lantiq/clk.c
 124 @@ -22,6 +22,7 @@
 125  #include <lantiq_soc.h>
 126
 127  #include "clk.h"
 128 +#include "prom.h"
 129
 130  struct clk {
 131         const char *name;
 132 @@ -46,16 +47,6 @@ static struct clk cpu_clk_generic[] = {
 133         },
 134  };
 135
 136 -static struct resource ltq_cgu_resource = {
 137 -       .name   = "cgu",
 138 -       .start  = LTQ_CGU_BASE_ADDR,
 139 -       .end    = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1,
 140 -       .flags  = IORESOURCE_MEM,
 141 -};
 142 -
 143 -/* remapped clock register range */
 144 -void __iomem *ltq_cgu_membase;
 145 -
 146  void clk_init(void)
 147  {
 148         cpu_clk = cpu_clk_generic;
 149 @@ -133,21 +124,11 @@ void __init plat_time_init(void)
 150  {
 151         struct clk *clk;
 152
 153 -       if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0)
 154 -               panic("Failed to insert cgu memory\n");
 155 +       ltq_soc_init();
 156
 157 -       if (request_mem_region(ltq_cgu_resource.start,
 158 -                       resource_size(&ltq_cgu_resource), "cgu") < 0)
 159 -               panic("Failed to request cgu memory\n");
 160 -
 161 -       ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
 162 -                               resource_size(&ltq_cgu_resource));
 163 -       if (!ltq_cgu_membase) {
 164 -               pr_err("Failed to remap cgu memory\n");
 165 -               unreachable();
 166 -       }
 167         clk = clk_get(0, "cpu");
 168         mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
 169         write_c0_compare(read_c0_count());
 170 +       pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
 171         clk_put(clk);
 172  }
 173 --- a/arch/mips/lantiq/devices.c
 174 +++ b/arch/mips/lantiq/devices.c
 175 @@ -27,12 +27,8 @@
 176  #include "devices.h"
 177
 178  /* nor flash */
 179 -static struct resource ltq_nor_resource = {
 180 -       .name   = "nor",
 181 -       .start  = LTQ_FLASH_START,
 182 -       .end    = LTQ_FLASH_START + LTQ_FLASH_MAX - 1,
 183 -       .flags  = IORESOURCE_MEM,
 184 -};
 185 +static struct resource ltq_nor_resource =
 186 +       MEM_RES("nor", LTQ_FLASH_START, LTQ_FLASH_MAX);
 187
 188  static struct platform_device ltq_nor = {
 189         .name           = "ltq_nor",
 190 @@ -47,12 +43,8 @@ void __init ltq_register_nor(struct phys
 191  }
 192
 193  /* watchdog */
 194 -static struct resource ltq_wdt_resource = {
 195 -       .name   = "watchdog",
 196 -       .start  = LTQ_WDT_BASE_ADDR,
 197 -       .end    = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1,
 198 -       .flags  = IORESOURCE_MEM,
 199 -};
 200 +static struct resource ltq_wdt_resource =
 201 +       MEM_RES("watchdog", LTQ_WDT_BASE_ADDR, LTQ_WDT_SIZE);
 202
 203  void __init ltq_register_wdt(void)
 204  {
 205 @@ -61,24 +53,14 @@ void __init ltq_register_wdt(void)
 206
 207  /* asc ports */
 208  static struct resource ltq_asc0_resources[] = {
 209 -       {
 210 -               .name   = "asc0",
 211 -               .start  = LTQ_ASC0_BASE_ADDR,
 212 -               .end    = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1,
 213 -               .flags  = IORESOURCE_MEM,
 214 -       },
 215 +       MEM_RES("asc0", LTQ_ASC0_BASE_ADDR, LTQ_ASC_SIZE),
 216         IRQ_RES(tx, LTQ_ASC_TIR(0)),
 217         IRQ_RES(rx, LTQ_ASC_RIR(0)),
 218         IRQ_RES(err, LTQ_ASC_EIR(0)),
 219  };
 220
 221  static struct resource ltq_asc1_resources[] = {
 222 -       {
 223 -               .name   = "asc1",
 224 -               .start  = LTQ_ASC1_BASE_ADDR,
 225 -               .end    = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
 226 -               .flags  = IORESOURCE_MEM,
 227 -       },
 228 +       MEM_RES("asc1", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
 229         IRQ_RES(tx, LTQ_ASC_TIR(1)),
 230         IRQ_RES(rx, LTQ_ASC_RIR(1)),
 231         IRQ_RES(err, LTQ_ASC_EIR(1)),
 232 --- a/arch/mips/lantiq/devices.h
 233 +++ b/arch/mips/lantiq/devices.h
 234 @@ -14,6 +14,10 @@
 235
 236  #define IRQ_RES(resname, irq) \
 237         {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ}
 238 +#define MEM_RES(resname, adr_start, adr_size) \
 239 +       { .name = resname, .flags = IORESOURCE_MEM, \
 240 +         .start = ((adr_start) & ~KSEG1), \
 241 +         .end = ((adr_start + adr_size - 1) & ~KSEG1) }
 242
 243  extern void ltq_register_nor(struct physmap_flash_data *data);
 244  extern void ltq_register_wdt(void);
 245 --- a/arch/mips/lantiq/prom.c
 246 +++ b/arch/mips/lantiq/prom.c
 247 @@ -16,6 +16,10 @@
 248  #include "prom.h"
 249  #include "clk.h"
 250
 251 +/* access to the ebu needs to be locked between different drivers */
 252 +DEFINE_SPINLOCK(ebu_lock);
 253 +EXPORT_SYMBOL_GPL(ebu_lock);
 254 +
 255  static struct ltq_soc_info soc_info;
 256
 257  unsigned int ltq_get_cpu_ver(void)
 258 @@ -57,16 +61,50 @@ static void __init prom_init_cmdline(voi
 259         }
 260  }
 261
 262 -void __init prom_init(void)
 263 +void __iomem *ltq_remap_resource(struct resource *res)
 264  {
 265 -       struct clk *clk;
 266 +       __iomem void *ret = NULL;
 267 +       struct resource *lookup = lookup_resource(&iomem_resource, res->start);
 268
 269 +       if (lookup && strcmp(lookup->name, res->name)) {
 270 +               panic("conflicting memory range %s\n", res->name);
 271 +               return NULL;
 272 +       }
 273 +       if (!lookup) {
 274 +               if (insert_resource(&iomem_resource, res) < 0) {
 275 +                       panic("Failed to insert %s memory\n", res->name);
 276 +                       return NULL;
 277 +               }
 278 +       }
 279 +       if (request_mem_region(res->start,
 280 +                       resource_size(res), res->name) < 0) {
 281 +               panic("Failed to request %s memory\n", res->name);
 282 +               goto err_res;
 283 +       }
 284 +
 285 +       ret = ioremap_nocache(res->start, resource_size(res));
 286 +       if (!ret)
 287 +               goto err_mem;
 288 +
 289 +       pr_debug("remap: 0x%08X-0x%08X : \"%s\"\n",
 290 +               res->start, res->end, res->name);
 291 +       return ret;
 292 +
 293 +err_mem:
 294 +       panic("Failed to remap %s memory\n", res->name);
 295 +       release_mem_region(res->start, resource_size(res));
 296 +
 297 +err_res:
 298 +       release_resource(res);
 299 +       return NULL;
 300 +}
 301 +
 302 +void __init prom_init(void)
 303 +{
 304         ltq_soc_detect(&soc_info);
 305         clk_init();
 306 -       clk = clk_get(0, "cpu");
 307 -       snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d",
 308 -               soc_info.name, soc_info.rev);
 309 -       clk_put(clk);
 310 +       snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
 311 +               soc_info.name, soc_info.rev_type);
 312         soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
 313         pr_info("SoC: %s\n", soc_info.sys_type);
 314         prom_init_cmdline();
 315 --- a/arch/mips/lantiq/prom.h
 316 +++ b/arch/mips/lantiq/prom.h
 317 @@ -9,17 +9,21 @@
 318  #ifndef _LTQ_PROM_H__
 319  #define _LTQ_PROM_H__
 320
 321 +#define LTQ_SYS_REV_LEN                0x10
 322  #define LTQ_SYS_TYPE_LEN       0x100
 323
 324  struct ltq_soc_info {
 325         unsigned char *name;
 326         unsigned int rev;
 327 +       unsigned char rev_type[LTQ_SYS_REV_LEN];
 328 +       unsigned int srev;
 329         unsigned int partnum;
 330         unsigned int type;
 331         unsigned char sys_type[LTQ_SYS_TYPE_LEN];
 332  };
 333
 334  extern void ltq_soc_detect(struct ltq_soc_info *i);
 335 +extern void ltq_soc_init(void);
 336  extern void ltq_soc_setup(void);
 337
 338  #endif
 339 --- a/arch/mips/lantiq/xway/Makefile
 340 +++ b/arch/mips/lantiq/xway/Makefile
 341 @@ -1,7 +1,7 @@
 342 -obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
 343 +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
 344
 345 -obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
 346 -obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
 347 +obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
 348 +obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
 349
 350  obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
 351  obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
 352 --- a/arch/mips/lantiq/xway/devices.c
 353 +++ b/arch/mips/lantiq/xway/devices.c
 354 @@ -31,22 +31,9 @@
 355
 356  /* gpio */
 357  static struct resource ltq_gpio_resource[] = {
 358 -       {
 359 -               .name   = "gpio0",
 360 -               .start  = LTQ_GPIO0_BASE_ADDR,
 361 -               .end    = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1,
 362 -               .flags  = IORESOURCE_MEM,
 363 -       }, {
 364 -               .name   = "gpio1",
 365 -               .start  = LTQ_GPIO1_BASE_ADDR,
 366 -               .end    = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1,
 367 -               .flags  = IORESOURCE_MEM,
 368 -       }, {
 369 -               .name   = "gpio2",
 370 -               .start  = LTQ_GPIO2_BASE_ADDR,
 371 -               .end    = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1,
 372 -               .flags  = IORESOURCE_MEM,
 373 -       }
 374 +       MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE),
 375 +       MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE),
 376 +       MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE),
 377  };
 378
 379  void __init ltq_register_gpio(void)
 380 @@ -64,12 +51,8 @@ void __init ltq_register_gpio(void)
 381  }
 382
 383  /* serial to parallel conversion */
 384 -static struct resource ltq_stp_resource = {
 385 -       .name   = "stp",
 386 -       .start  = LTQ_STP_BASE_ADDR,
 387 -       .end    = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1,
 388 -       .flags  = IORESOURCE_MEM,
 389 -};
 390 +static struct resource ltq_stp_resource =
 391 +       MEM_RES("stp", LTQ_STP_BASE_ADDR, LTQ_STP_SIZE);
 392
 393  void __init ltq_register_gpio_stp(void)
 394  {
 395 @@ -78,12 +61,7 @@ void __init ltq_register_gpio_stp(void)
 396
 397  /* asc ports - amazon se has its own serial mapping */
 398  static struct resource ltq_ase_asc_resources[] = {
 399 -       {
 400 -               .name   = "asc0",
 401 -               .start  = LTQ_ASC1_BASE_ADDR,
 402 -               .end    = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
 403 -               .flags  = IORESOURCE_MEM,
 404 -       },
 405 +       MEM_RES("asc0", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
 406         IRQ_RES(tx, LTQ_ASC_ASE_TIR),
 407         IRQ_RES(rx, LTQ_ASC_ASE_RIR),
 408         IRQ_RES(err, LTQ_ASC_ASE_EIR),
 409 @@ -96,12 +74,8 @@ void __init ltq_register_ase_asc(void)
 410  }
 411
 412  /* ethernet */
 413 -static struct resource ltq_etop_resources = {
 414 -       .name   = "etop",
 415 -       .start  = LTQ_ETOP_BASE_ADDR,
 416 -       .end    = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1,
 417 -       .flags  = IORESOURCE_MEM,
 418 -};
 419 +static struct resource ltq_etop_resources =
 420 +       MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE);
 421
 422  static struct platform_device ltq_etop = {
 423         .name           = "ltq_etop",
 424 --- a/arch/mips/lantiq/xway/dma.c
 425 +++ b/arch/mips/lantiq/xway/dma.c
 426 @@ -23,6 +23,8 @@
 427  #include <lantiq_soc.h>
 428  #include <xway_dma.h>
 429
 430 +#include "../devices.h"
 431 +
 432  #define LTQ_DMA_CTRL           0x10
 433  #define LTQ_DMA_CPOLL          0x14
 434  #define LTQ_DMA_CS             0x18
 435 @@ -54,12 +56,8 @@
 436  #define ltq_dma_w32_mask(x, y, z)      ltq_w32_mask(x, y, \
 437                                                 ltq_dma_membase + (z))
 438
 439 -static struct resource ltq_dma_resource = {
 440 -       .name   = "dma",
 441 -       .start  = LTQ_DMA_BASE_ADDR,
 442 -       .end    = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1,
 443 -       .flags  = IORESOURCE_MEM,
 444 -};
 445 +static struct resource ltq_dma_resource =
 446 +       MEM_RES("dma", LTQ_DMA_BASE_ADDR, LTQ_DMA_SIZE);
 447
 448  static void __iomem *ltq_dma_membase;
 449
 450 @@ -219,17 +217,8 @@ ltq_dma_init(void)
 451  {
 452         int i;
 453
 454 -       /* insert and request the memory region */
 455 -       if (insert_resource(&iomem_resource, &ltq_dma_resource) < 0)
 456 -               panic("Failed to insert dma memory\n");
 457 -
 458 -       if (request_mem_region(ltq_dma_resource.start,
 459 -                       resource_size(&ltq_dma_resource), "dma") < 0)
 460 -               panic("Failed to request dma memory\n");
 461 -
 462         /* remap dma register range */
 463 -       ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
 464 -                               resource_size(&ltq_dma_resource));
 465 +       ltq_dma_membase = ltq_remap_resource(&ltq_dma_resource);
 466         if (!ltq_dma_membase)
 467                 panic("Failed to remap dma memory\n");
 468
 469 --- a/arch/mips/lantiq/xway/ebu.c
 470 +++ /dev/null
 471 @@ -1,52 +0,0 @@
 472 -/*
 473 - *  This program is free software; you can redistribute it and/or modify it
 474 - *  under the terms of the GNU General Public License version 2 as published
 475 - *  by the Free Software Foundation.
 476 - *
 477 - *  EBU - the external bus unit attaches PCI, NOR and NAND
 478 - *
 479 - *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 480 - */
 481 -
 482 -#include <linux/kernel.h>
 483 -#include <linux/module.h>
 484 -#include <linux/ioport.h>
 485 -
 486 -#include <lantiq_soc.h>
 487 -
 488 -/* all access to the ebu must be locked */
 489 -DEFINE_SPINLOCK(ebu_lock);
 490 -EXPORT_SYMBOL_GPL(ebu_lock);
 491 -
 492 -static struct resource ltq_ebu_resource = {
 493 -       .name   = "ebu",
 494 -       .start  = LTQ_EBU_BASE_ADDR,
 495 -       .end    = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1,
 496 -       .flags  = IORESOURCE_MEM,
 497 -};
 498 -
 499 -/* remapped base addr of the clock unit and external bus unit */
 500 -void __iomem *ltq_ebu_membase;
 501 -
 502 -static int __init lantiq_ebu_init(void)
 503 -{
 504 -       /* insert and request the memory region */
 505 -       if (insert_resource(&iomem_resource, &ltq_ebu_resource) < 0)
 506 -               panic("Failed to insert ebu memory\n");
 507 -
 508 -       if (request_mem_region(ltq_ebu_resource.start,
 509 -                       resource_size(&ltq_ebu_resource), "ebu") < 0)
 510 -               panic("Failed to request ebu memory\n");
 511 -
 512 -       /* remap ebu register range */
 513 -       ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
 514 -                               resource_size(&ltq_ebu_resource));
 515 -       if (!ltq_ebu_membase)
 516 -               panic("Failed to remap ebu memory\n");
 517 -
 518 -       /* make sure to unprotect the memory region where flash is located */
 519 -       ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 520 -       return 0;
 521 -}
 522 -
 523 -postcore_initcall(lantiq_ebu_init);
 524 --- a/arch/mips/lantiq/xway/pmu.c
 525 +++ /dev/null
 526 @@ -1,69 +0,0 @@
 527 -/*
 528 - *  This program is free software; you can redistribute it and/or modify it
 529 - *  under the terms of the GNU General Public License version 2 as published
 530 - *  by the Free Software Foundation.
 531 - *
 532 - *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 533 - */
 534 -
 535 -#include <linux/kernel.h>
 536 -#include <linux/module.h>
 537 -#include <linux/ioport.h>
 538 -
 539 -#include <lantiq_soc.h>
 540 -
 541 -/* PMU - the power management unit allows us to turn part of the core
 542 - * on and off
 543 - */
 544 -
 545 -/* the enable / disable registers */
 546 -#define LTQ_PMU_PWDCR  0x1C
 547 -#define LTQ_PMU_PWDSR  0x20
 548 -
 549 -#define ltq_pmu_w32(x, y)      ltq_w32((x), ltq_pmu_membase + (y))
 550 -#define ltq_pmu_r32(x)         ltq_r32(ltq_pmu_membase + (x))
 551 -
 552 -static struct resource ltq_pmu_resource = {
 553 -       .name   = "pmu",
 554 -       .start  = LTQ_PMU_BASE_ADDR,
 555 -       .end    = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1,
 556 -       .flags  = IORESOURCE_MEM,
 557 -};
 558 -
 559 -static void __iomem *ltq_pmu_membase;
 560 -
 561 -void ltq_pmu_enable(unsigned int module)
 562 -{
 563 -       int err = 1000000;
 564 -
 565 -       ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
 566 -       do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
 567 -
 568 -       if (!err)
 569 -               panic("activating PMU module failed!\n");
 570 -}
 571 -EXPORT_SYMBOL(ltq_pmu_enable);
 572 -
 573 -void ltq_pmu_disable(unsigned int module)
 574 -{
 575 -       ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
 576 -}
 577 -EXPORT_SYMBOL(ltq_pmu_disable);
 578 -
 579 -int __init ltq_pmu_init(void)
 580 -{
 581 -       if (insert_resource(&iomem_resource, &ltq_pmu_resource) < 0)
 582 -               panic("Failed to insert pmu memory\n");
 583 -
 584 -       if (request_mem_region(ltq_pmu_resource.start,
 585 -                       resource_size(&ltq_pmu_resource), "pmu") < 0)
 586 -               panic("Failed to request pmu memory\n");
 587 -
 588 -       ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
 589 -                               resource_size(&ltq_pmu_resource));
 590 -       if (!ltq_pmu_membase)
 591 -               panic("Failed to remap pmu memory\n");
 592 -       return 0;
 593 -}
 594 -
 595 -core_initcall(ltq_pmu_init);
 596 --- a/arch/mips/lantiq/xway/prom-ase.c
 597 +++ b/arch/mips/lantiq/xway/prom-ase.c
 598 @@ -13,6 +13,7 @@
 599
 600  #include <lantiq_soc.h>
 601
 602 +#include "devices.h"
 603  #include "../prom.h"
 604
 605  #define SOC_AMAZON_SE  "Amazon_SE"
 606 @@ -26,6 +27,7 @@ void __init ltq_soc_detect(struct ltq_so
 607  {
 608         i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
 609         i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
 610 +       sprintf(i->rev_type, "1.%d", i->rev);
 611         switch (i->partnum) {
 612         case SOC_ID_AMAZON_SE:
 613                 i->name = SOC_AMAZON_SE;
 614 @@ -37,3 +39,10 @@ void __init ltq_soc_detect(struct ltq_so
 615                 break;
 616         }
 617  }
 618 +
 619 +void __init ltq_soc_setup(void)
 620 +{
 621 +       ltq_register_ase_asc();
 622 +       ltq_register_gpio();
 623 +       ltq_register_wdt();
 624 +}
 625 --- a/arch/mips/lantiq/xway/prom-xway.c
 626 +++ b/arch/mips/lantiq/xway/prom-xway.c
 627 @@ -13,6 +13,7 @@
 628
 629  #include <lantiq_soc.h>
 630
 631 +#include "devices.h"
 632  #include "../prom.h"
 633
 634  #define SOC_DANUBE     "Danube"
 635 @@ -28,6 +29,7 @@ void __init ltq_soc_detect(struct ltq_so
 636  {
 637         i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
 638         i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
 639 +       sprintf(i->rev_type, "1.%d", i->rev);
 640         switch (i->partnum) {
 641         case SOC_ID_DANUBE1:
 642         case SOC_ID_DANUBE2:
 643 @@ -52,3 +54,11 @@ void __init ltq_soc_detect(struct ltq_so
 644                 break;
 645         }
 646  }
 647 +
 648 +void __init ltq_soc_setup(void)
 649 +{
 650 +       ltq_register_asc(0);
 651 +       ltq_register_asc(1);
 652 +       ltq_register_gpio();
 653 +       ltq_register_wdt();
 654 +}
 655 --- a/arch/mips/lantiq/xway/reset.c
 656 +++ b/arch/mips/lantiq/xway/reset.c
 657 @@ -15,6 +15,8 @@
 658
 659  #include <lantiq_soc.h>
 660
 661 +#include "../devices.h"
 662 +
 663  #define ltq_rcu_w32(x, y)      ltq_w32((x), ltq_rcu_membase + (y))
 664  #define ltq_rcu_r32(x)         ltq_r32(ltq_rcu_membase + (x))
 665
 666 @@ -25,12 +27,8 @@
 667  #define LTQ_RCU_RST_STAT       0x0014
 668  #define LTQ_RCU_STAT_SHIFT     26
 669
 670 -static struct resource ltq_rcu_resource = {
 671 -       .name   = "rcu",
 672 -       .start  = LTQ_RCU_BASE_ADDR,
 673 -       .end    = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1,
 674 -       .flags  = IORESOURCE_MEM,
 675 -};
 676 +static struct resource ltq_rcu_resource =
 677 +       MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE);
 678
 679  /* remapped base addr of the reset control unit */
 680  static void __iomem *ltq_rcu_membase;
 681 @@ -67,17 +65,8 @@ static void ltq_machine_power_off(void)
 682
 683  static int __init mips_reboot_setup(void)
 684  {
 685 -       /* insert and request the memory region */
 686 -       if (insert_resource(&iomem_resource, &ltq_rcu_resource) < 0)
 687 -               panic("Failed to insert rcu memory\n");
 688 -
 689 -       if (request_mem_region(ltq_rcu_resource.start,
 690 -                       resource_size(&ltq_rcu_resource), "rcu") < 0)
 691 -               panic("Failed to request rcu memory\n");
 692 -
 693         /* remap rcu register range */
 694 -       ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
 695 -                               resource_size(&ltq_rcu_resource));
 696 +       ltq_rcu_membase = ltq_remap_resource(&ltq_rcu_resource);
 697         if (!ltq_rcu_membase)
 698                 panic("Failed to remap rcu memory\n");
 699
 700 --- a/arch/mips/lantiq/xway/setup-ase.c
 701 +++ /dev/null
 702 @@ -1,19 +0,0 @@
 703 -/*
 704 - *  This program is free software; you can redistribute it and/or modify it
 705 - *  under the terms of the GNU General Public License version 2 as published
 706 - *  by the Free Software Foundation.
 707 - *
 708 - *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 709 - */
 710 -
 711 -#include <lantiq_soc.h>
 712 -
 713 -#include "../prom.h"
 714 -#include "devices.h"
 715 -
 716 -void __init ltq_soc_setup(void)
 717 -{
 718 -       ltq_register_ase_asc();
 719 -       ltq_register_gpio();
 720 -       ltq_register_wdt();
 721 -}
 722 --- a/arch/mips/lantiq/xway/setup-xway.c
 723 +++ /dev/null
 724 @@ -1,20 +0,0 @@
 725 -/*
 726 - *  This program is free software; you can redistribute it and/or modify it
 727 - *  under the terms of the GNU General Public License version 2 as published
 728 - *  by the Free Software Foundation.
 729 - *
 730 - *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 731 - */
 732 -
 733 -#include <lantiq_soc.h>
 734 -
 735 -#include "../prom.h"
 736 -#include "devices.h"
 737 -
 738 -void __init ltq_soc_setup(void)
 739 -{
 740 -       ltq_register_asc(0);
 741 -       ltq_register_asc(1);
 742 -       ltq_register_gpio();
 743 -       ltq_register_wdt();
 744 -}
 745 --- /dev/null
 746 +++ b/arch/mips/lantiq/xway/sysctrl.c
 747 @@ -0,0 +1,77 @@
 748 +/*
 749 + *  This program is free software; you can redistribute it and/or modify it
 750 + *  under the terms of the GNU General Public License version 2 as published
 751 + *  by the Free Software Foundation.
 752 + *
 753 + *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
 754 + */
 755 +
 756 +#include <linux/ioport.h>
 757 +
 758 +#include <lantiq_soc.h>
 759 +
 760 +#include "../devices.h"
 761 +
 762 +/* clock control register */
 763 +#define LTQ_CGU_IFCCR  0x0018
 764 +
 765 +/* the enable / disable registers */
 766 +#define LTQ_PMU_PWDCR  0x1C
 767 +#define LTQ_PMU_PWDSR  0x20
 768 +
 769 +#define ltq_pmu_w32(x, y)      ltq_w32((x), ltq_pmu_membase + (y))
 770 +#define ltq_pmu_r32(x)         ltq_r32(ltq_pmu_membase + (x))
 771 +
 772 +static struct resource ltq_cgu_resource =
 773 +       MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE);
 774 +
 775 +static struct resource ltq_pmu_resource =
 776 +       MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE);
 777 +
 778 +static struct resource ltq_ebu_resource =
 779 +       MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
 780 +
 781 +void __iomem *ltq_cgu_membase;
 782 +void __iomem *ltq_ebu_membase;
 783 +static void __iomem *ltq_pmu_membase;
 784 +
 785 +void ltq_cgu_enable(unsigned int clk)
 786 +{
 787 +       ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR);
 788 +}
 789 +
 790 +void ltq_pmu_enable(unsigned int module)
 791 +{
 792 +       int err = 1000000;
 793 +
 794 +       ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
 795 +       do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
 796 +
 797 +       if (!err)
 798 +               panic("activating PMU module failed!\n");
 799 +}
 800 +EXPORT_SYMBOL(ltq_pmu_enable);
 801 +
 802 +void ltq_pmu_disable(unsigned int module)
 803 +{
 804 +       ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
 805 +}
 806 +EXPORT_SYMBOL(ltq_pmu_disable);
 807 +
 808 +void __init ltq_soc_init(void)
 809 +{
 810 +       ltq_pmu_membase = ltq_remap_resource(&ltq_pmu_resource);
 811 +       if (!ltq_pmu_membase)
 812 +               panic("Failed to remap pmu memory\n");
 813 +
 814 +       ltq_cgu_membase = ltq_remap_resource(&ltq_cgu_resource);
 815 +       if (!ltq_cgu_membase)
 816 +               panic("Failed to remap cgu memory\n");
 817 +
 818 +       ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_resource);
 819 +       if (!ltq_ebu_membase)
 820 +               panic("Failed to remap ebu memory\n");
 821 +
 822 +       /* make sure to unprotect the memory region where flash is located */
 823 +       ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 824 +}
 825 --- a/drivers/watchdog/lantiq_wdt.c
 826 +++ b/drivers/watchdog/lantiq_wdt.c
 827 @@ -16,7 +16,7 @@
 828  #include <linux/clk.h>
 829  #include <linux/io.h>
 830
 831 -#include <lantiq.h>
 832 +#include <lantiq_soc.h>
 833
 834  /* Section 3.4 of the datasheet
 835   * The password sequence protects the WDT control register from unintended