target/linux/ixp4xx/patches-2.6.25/210-npe_hss.patch

   1 Index: linux-2.6.25.4/drivers/net/wan/Kconfig
   2 ===================================================================
   3 --- linux-2.6.25.4.orig/drivers/net/wan/Kconfig
   4 +++ linux-2.6.25.4/drivers/net/wan/Kconfig
   5 @@ -338,6 +338,15 @@ config DSCC4_PCI_RST
   6
   7           Say Y if your card supports this feature.
   8
   9 +config IXP4XX_HSS
  10 +       tristate "IXP4xx HSS (synchronous serial port) support"
  11 +       depends on HDLC && ARM && ARCH_IXP4XX
  12 +       select IXP4XX_NPE
  13 +       select IXP4XX_QMGR
  14 +       help
  15 +         Say Y here if you want to use built-in HSS ports
  16 +         on IXP4xx processor.
  17 +
  18  config DLCI
  19         tristate "Frame Relay DLCI support"
  20         ---help---
  21 Index: linux-2.6.25.4/drivers/net/wan/Makefile
  22 ===================================================================
  23 --- linux-2.6.25.4.orig/drivers/net/wan/Makefile
  24 +++ linux-2.6.25.4/drivers/net/wan/Makefile
  25 @@ -42,6 +42,7 @@ obj-$(CONFIG_C101)            += c101.o
  26  obj-$(CONFIG_WANXL)            += wanxl.o
  27  obj-$(CONFIG_PCI200SYN)                += pci200syn.o
  28  obj-$(CONFIG_PC300TOO)         += pc300too.o
  29 +obj-$(CONFIG_IXP4XX_HSS)       += ixp4xx_hss.o
  30
  31  clean-files := wanxlfw.inc
  32  $(obj)/wanxl.o:        $(obj)/wanxlfw.inc
  33 Index: linux-2.6.25.4/drivers/net/wan/ixp4xx_hss.c
  34 ===================================================================
  35 --- /dev/null
  36 +++ linux-2.6.25.4/drivers/net/wan/ixp4xx_hss.c
  37 @@ -0,0 +1,2886 @@
  38 +/*
  39 + * Intel IXP4xx HSS (synchronous serial port) driver for Linux
  40 + *
  41 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
  42 + *
  43 + * This program is free software; you can redistribute it and/or modify it
  44 + * under the terms of version 2 of the GNU General Public License
  45 + * as published by the Free Software Foundation.
  46 + */
  47 +
  48 +#include <linux/bitops.h>
  49 +#include <linux/cdev.h>
  50 +#include <linux/dma-mapping.h>
  51 +#include <linux/dmapool.h>
  52 +#include <linux/fs.h>
  53 +#include <linux/io.h>
  54 +#include <linux/kernel.h>
  55 +#include <linux/hdlc.h>
  56 +#include <linux/platform_device.h>
  57 +#include <linux/poll.h>
  58 +#include <asm/arch/npe.h>
  59 +#include <asm/arch/qmgr.h>
  60 +
  61 +#define DEBUG_QUEUES           0
  62 +#define DEBUG_DESC             0
  63 +#define DEBUG_RX               0
  64 +#define DEBUG_TX               0
  65 +#define DEBUG_PKT_BYTES                0
  66 +#define DEBUG_CLOSE            0
  67 +#define DEBUG_FRAMER           0
  68 +
  69 +#define DRV_NAME               "ixp4xx_hss"
  70 +
  71 +#define PKT_EXTRA_FLAGS                0 /* orig 1 */
  72 +#define TX_FRAME_SYNC_OFFSET   0 /* channelized */
  73 +#define PKT_NUM_PIPES          1 /* 1, 2 or 4 */
  74 +#define PKT_PIPE_FIFO_SIZEW    4 /* total 4 dwords per HSS */
  75 +
  76 +#define RX_DESCS               16 /* also length of all RX queues */
  77 +#define TX_DESCS               16 /* also length of all TX queues */
  78 +
  79 +#define POOL_ALLOC_SIZE                (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
  80 +#define RX_SIZE                        (HDLC_MAX_MRU + 4) /* NPE needs more space */
  81 +#define MAX_CLOSE_WAIT         1000 /* microseconds */
  82 +#define HSS_COUNT              2
  83 +#define MIN_FRAME_SIZE         16   /* bits */
  84 +#define MAX_FRAME_SIZE         257  /* 256 bits + framing bit */
  85 +#define MAX_CHANNELS           (MAX_FRAME_SIZE / 8)
  86 +#define MAX_CHAN_DEVICES       32
  87 +#define CHANNEL_HDLC           0xFE
  88 +#define CHANNEL_UNUSED         0xFF
  89 +
  90 +#define NAPI_WEIGHT            16
  91 +#define CHAN_RX_TRIGGER                16 /* 8 RX frames = 1 ms @ E1 */
  92 +#define CHAN_RX_FRAMES         64
  93 +#define MAX_CHAN_RX_BAD_SYNC   (CHAN_RX_TRIGGER / 2 /* pairs */ - 3)
  94 +#define CHAN_TX_LIST_FRAMES    16 /* bytes/channel per list, 16 - 48 */
  95 +#define CHAN_TX_LISTS          8
  96 +#define CHAN_TX_FRAMES         (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS)
  97 +#define CHAN_QUEUE_LEN         16 /* minimum possible */
  98 +
  99 +
 100 +/* Queue IDs */
 101 +#define HSS0_CHL_RXTRIG_QUEUE  12      /* orig size = 32 dwords */
 102 +#define HSS0_PKT_RX_QUEUE      13      /* orig size = 32 dwords */
 103 +#define HSS0_PKT_TX0_QUEUE     14      /* orig size = 16 dwords */
 104 +#define HSS0_PKT_TX1_QUEUE     15
 105 +#define HSS0_PKT_TX2_QUEUE     16
 106 +#define HSS0_PKT_TX3_QUEUE     17
 107 +#define HSS0_PKT_RXFREE0_QUEUE 18      /* orig size = 16 dwords */
 108 +#define HSS0_PKT_RXFREE1_QUEUE 19
 109 +#define HSS0_PKT_RXFREE2_QUEUE 20
 110 +#define HSS0_PKT_RXFREE3_QUEUE 21
 111 +#define HSS0_PKT_TXDONE_QUEUE  22      /* orig size = 64 dwords */
 112 +
 113 +#define HSS1_CHL_RXTRIG_QUEUE  10
 114 +#define HSS1_PKT_RX_QUEUE      0
 115 +#define HSS1_PKT_TX0_QUEUE     5
 116 +#define HSS1_PKT_TX1_QUEUE     6
 117 +#define HSS1_PKT_TX2_QUEUE     7
 118 +#define HSS1_PKT_TX3_QUEUE     8
 119 +#define HSS1_PKT_RXFREE0_QUEUE 1
 120 +#define HSS1_PKT_RXFREE1_QUEUE 2
 121 +#define HSS1_PKT_RXFREE2_QUEUE 3
 122 +#define HSS1_PKT_RXFREE3_QUEUE 4
 123 +#define HSS1_PKT_TXDONE_QUEUE  9
 124 +
 125 +#define NPE_PKT_MODE_HDLC              0
 126 +#define NPE_PKT_MODE_RAW               1
 127 +#define NPE_PKT_MODE_56KMODE           2
 128 +#define NPE_PKT_MODE_56KENDIAN_MSB     4
 129 +
 130 +/* PKT_PIPE_HDLC_CFG_WRITE flags */
 131 +#define PKT_HDLC_IDLE_ONES             0x1 /* default = flags */
 132 +#define PKT_HDLC_CRC_32                        0x2 /* default = CRC-16 */
 133 +#define PKT_HDLC_MSB_ENDIAN            0x4 /* default = LE */
 134 +
 135 +
 136 +/* hss_config, PCRs */
 137 +/* Frame sync sampling, default = active low */
 138 +#define PCR_FRM_SYNC_ACTIVE_HIGH       0x40000000
 139 +#define PCR_FRM_SYNC_FALLINGEDGE       0x80000000
 140 +#define PCR_FRM_SYNC_RISINGEDGE                0xC0000000
 141 +
 142 +/* Frame sync pin: input (default) or output generated off a given clk edge */
 143 +#define PCR_FRM_SYNC_OUTPUT_FALLING    0x20000000
 144 +#define PCR_FRM_SYNC_OUTPUT_RISING     0x30000000
 145 +
 146 +/* Frame and data clock sampling on edge, default = falling */
 147 +#define PCR_FCLK_EDGE_RISING           0x08000000
 148 +#define PCR_DCLK_EDGE_RISING           0x04000000
 149 +
 150 +/* Clock direction, default = input */
 151 +#define PCR_SYNC_CLK_DIR_OUTPUT                0x02000000
 152 +
 153 +/* Generate/Receive frame pulses, default = enabled */
 154 +#define PCR_FRM_PULSE_DISABLED         0x01000000
 155 +
 156 + /* Data rate is full (default) or half the configured clk speed */
 157 +#define PCR_HALF_CLK_RATE              0x00200000
 158 +
 159 +/* Invert data between NPE and HSS FIFOs? (default = no) */
 160 +#define PCR_DATA_POLARITY_INVERT       0x00100000
 161 +
 162 +/* TX/RX endianness, default = LSB */
 163 +#define PCR_MSB_ENDIAN                 0x00080000
 164 +
 165 +/* Normal (default) / open drain mode (TX only) */
 166 +#define PCR_TX_PINS_OPEN_DRAIN         0x00040000
 167 +
 168 +/* No framing bit transmitted and expected on RX? (default = framing bit) */
 169 +#define PCR_SOF_NO_FBIT                        0x00020000
 170 +
 171 +/* Drive data pins? */
 172 +#define PCR_TX_DATA_ENABLE             0x00010000
 173 +
 174 +/* Voice 56k type: drive the data pins low (default), high, high Z */
 175 +#define PCR_TX_V56K_HIGH               0x00002000
 176 +#define PCR_TX_V56K_HIGH_IMP           0x00004000
 177 +
 178 +/* Unassigned type: drive the data pins low (default), high, high Z */
 179 +#define PCR_TX_UNASS_HIGH              0x00000800
 180 +#define PCR_TX_UNASS_HIGH_IMP          0x00001000
 181 +
 182 +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
 183 +#define PCR_TX_FB_HIGH_IMP             0x00000400
 184 +
 185 +/* 56k data endiannes - which bit unused: high (default) or low */
 186 +#define PCR_TX_56KE_BIT_0_UNUSED       0x00000200
 187 +
 188 +/* 56k data transmission type: 32/8 bit data (default) or 56K data */
 189 +#define PCR_TX_56KS_56K_DATA           0x00000100
 190 +
 191 +/* hss_config, cCR */
 192 +/* Number of packetized clients, default = 1 */
 193 +#define CCR_NPE_HFIFO_2_HDLC           0x04000000
 194 +#define CCR_NPE_HFIFO_3_OR_4HDLC       0x08000000
 195 +
 196 +/* default = no loopback */
 197 +#define CCR_LOOPBACK                   0x02000000
 198 +
 199 +/* HSS number, default = 0 (first) */
 200 +#define CCR_SECOND_HSS                 0x01000000
 201 +
 202 +
 203 +/* hss_config, clkCR: main:10, num:10, denom:12 */
 204 +#define CLK42X_SPEED_EXP       ((0x3FF << 22) | (  2 << 12) |   15) /*65 KHz*/
 205 +
 206 +#define CLK42X_SPEED_512KHZ    ((  130 << 22) | (  2 << 12) |   15)
 207 +#define CLK42X_SPEED_1536KHZ   ((   43 << 22) | ( 18 << 12) |   47)
 208 +#define CLK42X_SPEED_1544KHZ   ((   43 << 22) | ( 33 << 12) |  192)
 209 +#define CLK42X_SPEED_2048KHZ   ((   32 << 22) | ( 34 << 12) |   63)
 210 +#define CLK42X_SPEED_4096KHZ   ((   16 << 22) | ( 34 << 12) |  127)
 211 +#define CLK42X_SPEED_8192KHZ   ((    8 << 22) | ( 34 << 12) |  255)
 212 +
 213 +#define CLK46X_SPEED_512KHZ    ((  130 << 22) | ( 24 << 12) |  127)
 214 +#define CLK46X_SPEED_1536KHZ   ((   43 << 22) | (152 << 12) |  383)
 215 +#define CLK46X_SPEED_1544KHZ   ((   43 << 22) | ( 66 << 12) |  385)
 216 +#define CLK46X_SPEED_2048KHZ   ((   32 << 22) | (280 << 12) |  511)
 217 +#define CLK46X_SPEED_4096KHZ   ((   16 << 22) | (280 << 12) | 1023)
 218 +#define CLK46X_SPEED_8192KHZ   ((    8 << 22) | (280 << 12) | 2047)
 219 +
 220 +
 221 +/* hss_config, LUT entries */
 222 +#define TDMMAP_UNASSIGNED      0
 223 +#define TDMMAP_HDLC            1       /* HDLC - packetized */
 224 +#define TDMMAP_VOICE56K                2       /* Voice56K - 7-bit channelized */
 225 +#define TDMMAP_VOICE64K                3       /* Voice64K - 8-bit channelized */
 226 +
 227 +/* offsets into HSS config */
 228 +#define HSS_CONFIG_TX_PCR      0x00 /* port configuration registers */
 229 +#define HSS_CONFIG_RX_PCR      0x04
 230 +#define HSS_CONFIG_CORE_CR     0x08 /* loopback control, HSS# */
 231 +#define HSS_CONFIG_CLOCK_CR    0x0C /* clock generator control */
 232 +#define HSS_CONFIG_TX_FCR      0x10 /* frame configuration registers */
 233 +#define HSS_CONFIG_RX_FCR      0x14
 234 +#define HSS_CONFIG_TX_LUT      0x18 /* channel look-up tables */
 235 +#define HSS_CONFIG_RX_LUT      0x38
 236 +
 237 +
 238 +/* NPE command codes */
 239 +/* writes the ConfigWord value to the location specified by offset */
 240 +#define PORT_CONFIG_WRITE              0x40
 241 +
 242 +/* triggers the NPE to load the contents of the configuration table */
 243 +#define PORT_CONFIG_LOAD               0x41
 244 +
 245 +/* triggers the NPE to return an HssErrorReadResponse message */
 246 +#define PORT_ERROR_READ                        0x42
 247 +
 248 +/* reset NPE internal status and enable the HssChannelized operation */
 249 +#define CHAN_FLOW_ENABLE               0x43
 250 +#define CHAN_FLOW_DISABLE              0x44
 251 +#define CHAN_IDLE_PATTERN_WRITE                0x45
 252 +#define CHAN_NUM_CHANS_WRITE           0x46
 253 +#define CHAN_RX_BUF_ADDR_WRITE         0x47
 254 +#define CHAN_RX_BUF_CFG_WRITE          0x48
 255 +#define CHAN_TX_BLK_CFG_WRITE          0x49
 256 +#define CHAN_TX_BUF_ADDR_WRITE         0x4A
 257 +#define CHAN_TX_BUF_SIZE_WRITE         0x4B
 258 +#define CHAN_TSLOTSWITCH_ENABLE                0x4C
 259 +#define CHAN_TSLOTSWITCH_DISABLE       0x4D
 260 +
 261 +/* downloads the gainWord value for a timeslot switching channel associated
 262 +   with bypassNum */
 263 +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD  0x4E
 264 +
 265 +/* triggers the NPE to reset internal status and enable the HssPacketized
 266 +   operation for the flow specified by pPipe */
 267 +#define PKT_PIPE_FLOW_ENABLE           0x50
 268 +#define PKT_PIPE_FLOW_DISABLE          0x51
 269 +#define PKT_NUM_PIPES_WRITE            0x52
 270 +#define PKT_PIPE_FIFO_SIZEW_WRITE      0x53
 271 +#define PKT_PIPE_HDLC_CFG_WRITE                0x54
 272 +#define PKT_PIPE_IDLE_PATTERN_WRITE    0x55
 273 +#define PKT_PIPE_RX_SIZE_WRITE         0x56
 274 +#define PKT_PIPE_MODE_WRITE            0x57
 275 +
 276 +/* HDLC packet status values - desc->status */
 277 +#define ERR_SHUTDOWN           1 /* stop or shutdown occurrance */
 278 +#define ERR_HDLC_ALIGN         2 /* HDLC alignment error */
 279 +#define ERR_HDLC_FCS           3 /* HDLC Frame Check Sum error */
 280 +#define ERR_RXFREE_Q_EMPTY     4 /* RX-free queue became empty while receiving
 281 +                                    this packet (if buf_len < pkt_len) */
 282 +#define ERR_HDLC_TOO_LONG      5 /* HDLC frame size too long */
 283 +#define ERR_HDLC_ABORT         6 /* abort sequence received */
 284 +#define ERR_DISCONNECTING      7 /* disconnect is in progress */
 285 +
 286 +
 287 +enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704};
 288 +enum error_bit {TX_ERROR_BIT = 0, RX_ERROR_BIT = 1};
 289 +enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST };
 290 +
 291 +#ifdef __ARMEB__
 292 +typedef struct sk_buff buffer_t;
 293 +#define free_buffer dev_kfree_skb
 294 +#define free_buffer_irq dev_kfree_skb_irq
 295 +#else
 296 +typedef void buffer_t;
 297 +#define free_buffer kfree
 298 +#define free_buffer_irq kfree
 299 +#endif
 300 +
 301 +struct chan_device {
 302 +       struct cdev cdev;
 303 +       struct device *dev;
 304 +       struct port *port;
 305 +       unsigned int open_count, excl_open;
 306 +       unsigned int tx_first, tx_count, rx_first, rx_count; /* bytes */
 307 +       unsigned long errors_bitmap;
 308 +       u8 id, chan_count;
 309 +       u8 log_channels[MAX_CHANNELS];
 310 +};
 311 +
 312 +struct port {
 313 +       struct device *dev;
 314 +       struct npe *npe;
 315 +       struct net_device *netdev;
 316 +       struct napi_struct napi;
 317 +       struct hss_plat_info *plat;
 318 +       buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
 319 +       struct desc *desc_tab;  /* coherent */
 320 +       u32 desc_tab_phys;
 321 +       unsigned int id;
 322 +       atomic_t chan_tx_irq_number, chan_rx_irq_number;
 323 +       wait_queue_head_t chan_tx_waitq, chan_rx_waitq;
 324 +       u8 hdlc_cfg;
 325 +
 326 +       /* the following fields must be protected by npe_lock */
 327 +       enum mode mode;
 328 +       unsigned int clock_type, clock_rate, loopback;
 329 +       unsigned int frame_size, frame_sync_offset;
 330 +
 331 +       struct chan_device *chan_devices[MAX_CHAN_DEVICES];
 332 +       u8 *chan_buf;
 333 +       u32 chan_tx_buf_phys, chan_rx_buf_phys;
 334 +       unsigned int chan_open_count, hdlc_open;
 335 +       unsigned int chan_started, initialized, just_set_offset;
 336 +       enum alignment aligned, carrier;
 337 +       unsigned int chan_last_rx, chan_last_tx;
 338 +       /* assigned channels, may be invalid with given frame length or mode */
 339 +       u8 channels[MAX_CHANNELS];
 340 +       int msg_count;
 341 +};
 342 +
 343 +/* NPE message structure */
 344 +struct msg {
 345 +#ifdef __ARMEB__
 346 +       u8 cmd, unused, hss_port, index;
 347 +       union {
 348 +               struct { u8 data8a, data8b, data8c, data8d; };
 349 +               struct { u16 data16a, data16b; };
 350 +               struct { u32 data32; };
 351 +       };
 352 +#else
 353 +       u8 index, hss_port, unused, cmd;
 354 +       union {
 355 +               struct { u8 data8d, data8c, data8b, data8a; };
 356 +               struct { u16 data16b, data16a; };
 357 +               struct { u32 data32; };
 358 +       };
 359 +#endif
 360 +};
 361 +
 362 +/* HDLC packet descriptor */
 363 +struct desc {
 364 +       u32 next;               /* pointer to next buffer, unused */
 365 +
 366 +#ifdef __ARMEB__
 367 +       u16 buf_len;            /* buffer length */
 368 +       u16 pkt_len;            /* packet length */
 369 +       u32 data;               /* pointer to data buffer in RAM */
 370 +       u8 status;
 371 +       u8 error_count;
 372 +       u16 __reserved;
 373 +#else
 374 +       u16 pkt_len;            /* packet length */
 375 +       u16 buf_len;            /* buffer length */
 376 +       u32 data;               /* pointer to data buffer in RAM */
 377 +       u16 __reserved;
 378 +       u8 error_count;
 379 +       u8 status;
 380 +#endif
 381 +       u32 __reserved1[4];
 382 +};
 383 +
 384 +
 385 +#define rx_desc_phys(port, n)  ((port)->desc_tab_phys +                \
 386 +                                (n) * sizeof(struct desc))
 387 +#define rx_desc_ptr(port, n)   (&(port)->desc_tab[n])
 388 +
 389 +#define tx_desc_phys(port, n)  ((port)->desc_tab_phys +                \
 390 +                                ((n) + RX_DESCS) * sizeof(struct desc))
 391 +#define tx_desc_ptr(port, n)   (&(port)->desc_tab[(n) + RX_DESCS])
 392 +
 393 +#define chan_tx_buf_len(port)  (port->frame_size / 8 * CHAN_TX_FRAMES)
 394 +#define chan_tx_lists_len(port)        (port->frame_size / 8 * CHAN_TX_LISTS * \
 395 +                                sizeof(u32))
 396 +#define chan_rx_buf_len(port)  (port->frame_size / 8 * CHAN_RX_FRAMES)
 397 +
 398 +#define chan_tx_buf(port)      ((port)->chan_buf)
 399 +#define chan_tx_lists(port)    (chan_tx_buf(port) + chan_tx_buf_len(port))
 400 +#define chan_rx_buf(port)      (chan_tx_lists(port) + chan_tx_lists_len(port))
 401 +
 402 +#define chan_tx_lists_phys(port) ((port)->chan_tx_buf_phys +   \
 403 +                                 chan_tx_buf_len(port))
 404 +
 405 +static int hss_prepare_chan(struct port *port);
 406 +void hss_chan_stop(struct port *port);
 407 +
 408 +/*****************************************************************************
 409 + * global variables
 410 + ****************************************************************************/
 411 +
 412 +static struct class *hss_class;
 413 +static int chan_major;
 414 +static int ports_open;
 415 +static struct dma_pool *dma_pool;
 416 +static spinlock_t npe_lock;
 417 +
 418 +static const struct {
 419 +       int tx, txdone, rx, rxfree, chan;
 420 +}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
 421 +                 HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE},
 422 +                {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
 423 +                 HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE},
 424 +};
 425 +
 426 +/*****************************************************************************
 427 + * utility functions
 428 + ****************************************************************************/
 429 +
 430 +static inline struct port* dev_to_port(struct net_device *dev)
 431 +{
 432 +       return dev_to_hdlc(dev)->priv;
 433 +}
 434 +
 435 +static inline struct chan_device* inode_to_chan_dev(struct inode *inode)
 436 +{
 437 +       return container_of(inode->i_cdev, struct chan_device, cdev);
 438 +}
 439 +
 440 +#ifndef __ARMEB__
 441 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
 442 +{
 443 +       int i;
 444 +       for (i = 0; i < cnt; i++)
 445 +               dest[i] = swab32(src[i]);
 446 +}
 447 +#endif
 448 +
 449 +static int get_number(const char **buf, size_t *len, unsigned int *ptr,
 450 +                     unsigned int min, unsigned int max)
 451 +{
 452 +       char *endp;
 453 +       unsigned long val = simple_strtoul(*buf, &endp, 10);
 454 +
 455 +       if (endp == *buf || endp - *buf > *len || val < min || val > max)
 456 +               return -EINVAL;
 457 +       *len -= endp - *buf;
 458 +       *buf = endp;
 459 +       *ptr = val;
 460 +       return 0;
 461 +}
 462 +
 463 +static int parse_channels(const char **buf, size_t *len, u8 *channels)
 464 +{
 465 +       unsigned int ch, next = 0;
 466 +
 467 +       if (*len && (*buf)[*len - 1] == '\n')
 468 +               (*len)--;
 469 +
 470 +       memset(channels, 0, MAX_CHANNELS);
 471 +
 472 +       if (!*len)
 473 +               return 0;
 474 +
 475 +       /* Format: "A,B-C,...", A > B > C */
 476 +       while (1) {
 477 +               if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
 478 +                       return -EINVAL;
 479 +               channels[ch] = 1;
 480 +               next = ch + 1;
 481 +               if (!*len)
 482 +                       break;
 483 +               if (**buf == ',') {
 484 +                       (*buf)++;
 485 +                       (*len)--;
 486 +                       continue;
 487 +               }
 488 +               if (**buf != '-')
 489 +                       return -EINVAL;
 490 +               (*buf)++;
 491 +               (*len)--;
 492 +               if (get_number(buf, len, &ch, next, MAX_CHANNELS - 1))
 493 +                       return -EINVAL;
 494 +               while (next <= ch)
 495 +                       channels[next++] = 1;
 496 +               if (!*len)
 497 +                       break;
 498 +               if (**buf != ',')
 499 +                       return -EINVAL;
 500 +               (*buf)++;
 501 +               (*len)--;
 502 +       }
 503 +       return 1;
 504 +}
 505 +
 506 +static size_t print_channels(struct port *port, char *buf, u8 id)
 507 +{
 508 +       unsigned int ch, cnt = 0;
 509 +       size_t len = 0;
 510 +
 511 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
 512 +               if (port->channels[ch] == id) {
 513 +                       if (cnt == 0) {
 514 +                               sprintf(buf + len, "%s%u", len ? "," : "", ch);
 515 +                               len += strlen(buf + len);
 516 +                       }
 517 +                       cnt++;
 518 +               } else {
 519 +                       if (cnt > 1) {
 520 +                               sprintf(buf + len, "-%u", ch - 1);
 521 +                               len += strlen(buf + len);
 522 +                       }
 523 +                       cnt = 0;
 524 +               }
 525 +       if (cnt > 1) {
 526 +               sprintf(buf + len, "-%u", ch - 1);
 527 +               len += strlen(buf + len);
 528 +       }
 529 +
 530 +       buf[len++] = '\n';
 531 +       return len;
 532 +}
 533 +
 534 +static inline unsigned int sub_offset(unsigned int a, unsigned int b,
 535 +                                     unsigned int modulo)
 536 +{
 537 +       return (modulo /* make sure the result >= 0 */ + a - b) % modulo;
 538 +}
 539 +
 540 +/*****************************************************************************
 541 + * HSS access
 542 + ****************************************************************************/
 543 +
 544 +static void hss_config_load(struct port *port)
 545 +{
 546 +       struct msg msg;
 547 +
 548 +       do {
 549 +               memset(&msg, 0, sizeof(msg));
 550 +               msg.cmd = PORT_CONFIG_LOAD;
 551 +               msg.hss_port = port->id;
 552 +               if (npe_send_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
 553 +                       break;
 554 +               if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG"))
 555 +                       break;
 556 +
 557 +               /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
 558 +               if (msg.cmd != PORT_CONFIG_LOAD || msg.data32)
 559 +                       break;
 560 +
 561 +               /* HDLC may stop working without this */
 562 +               npe_recv_message(port->npe, &msg, "FLUSH_IT");
 563 +               return;
 564 +       } while (0);
 565 +
 566 +       printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n",
 567 +              port->id);
 568 +       BUG();
 569 +}
 570 +
 571 +static void hss_config_set_pcr(struct port *port)
 572 +{
 573 +       struct msg msg;
 574 +
 575 +       do {
 576 +               memset(&msg, 0, sizeof(msg));
 577 +               msg.cmd = PORT_CONFIG_WRITE;
 578 +               msg.hss_port = port->id;
 579 +               msg.index = HSS_CONFIG_TX_PCR;
 580 +               msg.data32 = PCR_FRM_SYNC_OUTPUT_RISING | PCR_MSB_ENDIAN |
 581 +                       PCR_TX_DATA_ENABLE;
 582 +               if (port->frame_size % 8 == 0)
 583 +                       msg.data32 |= PCR_SOF_NO_FBIT;
 584 +               if (port->clock_type == CLOCK_INT)
 585 +                       msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
 586 +               if (npe_send_message(port->npe, &msg, "HSS_SET_TX_PCR"))
 587 +                       break;
 588 +
 589 +               msg.index = HSS_CONFIG_RX_PCR;
 590 +               msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
 591 +               if (npe_send_message(port->npe, &msg, "HSS_SET_RX_PCR"))
 592 +                       break;
 593 +               return;
 594 +       } while (0);
 595 +
 596 +       printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id);
 597 +       BUG();
 598 +}
 599 +
 600 +static void hss_config_set_hdlc_cfg(struct port *port)
 601 +{
 602 +       struct msg msg;
 603 +
 604 +       memset(&msg, 0, sizeof(msg));
 605 +       msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
 606 +       msg.hss_port = port->id;
 607 +       msg.data8a = port->hdlc_cfg; /* rx_cfg */
 608 +       msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
 609 +       if (npe_send_message(port->npe, &msg, "HSS_SET_HDLC_CFG")) {
 610 +               printk(KERN_CRIT "HSS-%i: unable to set HSS HDLC"
 611 +                      " configuration\n", port->id);
 612 +               BUG();
 613 +       }
 614 +}
 615 +
 616 +static void hss_config_set_core(struct port *port)
 617 +{
 618 +       struct msg msg;
 619 +
 620 +       memset(&msg, 0, sizeof(msg));
 621 +       msg.cmd = PORT_CONFIG_WRITE;
 622 +       msg.hss_port = port->id;
 623 +       msg.index = HSS_CONFIG_CORE_CR;
 624 +       msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
 625 +               (port->id ? CCR_SECOND_HSS : 0);
 626 +       if (npe_send_message(port->npe, &msg, "HSS_SET_CORE_CR")) {
 627 +               printk(KERN_CRIT "HSS-%i: unable to set HSS core control"
 628 +                      " register\n", port->id);
 629 +               BUG();
 630 +       }
 631 +}
 632 +
 633 +static void hss_config_set_line(struct port *port)
 634 +{
 635 +       struct msg msg;
 636 +
 637 +       hss_config_set_pcr(port);
 638 +       hss_config_set_core(port);
 639 +
 640 +       memset(&msg, 0, sizeof(msg));
 641 +       msg.cmd = PORT_CONFIG_WRITE;
 642 +       msg.hss_port = port->id;
 643 +       msg.index = HSS_CONFIG_CLOCK_CR;
 644 +       msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
 645 +       if (npe_send_message(port->npe, &msg, "HSS_SET_CLOCK_CR")) {
 646 +               printk(KERN_CRIT "HSS-%i: unable to set HSS clock control"
 647 +                      " register\n", port->id);
 648 +               BUG();
 649 +       }
 650 +}
 651 +
 652 +static void hss_config_set_rx_frame(struct port *port)
 653 +{
 654 +       struct msg msg;
 655 +
 656 +       memset(&msg, 0, sizeof(msg));
 657 +       msg.cmd = PORT_CONFIG_WRITE;
 658 +       msg.hss_port = port->id;
 659 +       msg.index = HSS_CONFIG_RX_FCR;
 660 +       msg.data16a = port->frame_sync_offset;
 661 +       msg.data16b = port->frame_size - 1;
 662 +       if (npe_send_message(port->npe, &msg, "HSS_SET_RX_FCR")) {
 663 +               printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size"
 664 +                      " and offset\n", port->id);
 665 +               BUG();
 666 +       }
 667 +}
 668 +
 669 +static void hss_config_set_frame(struct port *port)
 670 +{
 671 +       struct msg msg;
 672 +
 673 +       memset(&msg, 0, sizeof(msg));
 674 +       msg.cmd = PORT_CONFIG_WRITE;
 675 +       msg.hss_port = port->id;
 676 +       msg.index = HSS_CONFIG_TX_FCR;
 677 +       msg.data16a = TX_FRAME_SYNC_OFFSET;
 678 +       msg.data16b = port->frame_size - 1;
 679 +       if (npe_send_message(port->npe, &msg, "HSS_SET_TX_FCR")) {
 680 +               printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size"
 681 +                      " and offset\n", port->id);
 682 +               BUG();
 683 +       }
 684 +       hss_config_set_rx_frame(port);
 685 +}
 686 +
 687 +static void hss_config_set_lut(struct port *port)
 688 +{
 689 +       struct msg msg;
 690 +       int chan_count = 0, log_chan = 0, i, ch;
 691 +       u32 lut[MAX_CHANNELS / 4];
 692 +
 693 +       memset(lut, 0, sizeof(lut));
 694 +       for (i = 0; i < MAX_CHAN_DEVICES; i++)
 695 +               if (port->chan_devices[i])
 696 +                       port->chan_devices[i]->chan_count = 0;
 697 +
 698 +       memset(&msg, 0, sizeof(msg));
 699 +       msg.cmd = PORT_CONFIG_WRITE;
 700 +       msg.hss_port = port->id;
 701 +
 702 +       for (ch = 0; ch < MAX_CHANNELS; ch++) {
 703 +               struct chan_device *chdev = NULL;
 704 +               unsigned int entry;
 705 +
 706 +               if (port->channels[ch] < MAX_CHAN_DEVICES /* assigned */)
 707 +                       chdev = port->chan_devices[port->channels[ch]];
 708 +
 709 +               if (port->mode == MODE_G704 && ch == 0)
 710 +                       entry = TDMMAP_VOICE64K; /* PCM-31 pattern */
 711 +               else if (port->mode == MODE_HDLC ||
 712 +                        port->channels[ch] == CHANNEL_HDLC)
 713 +                       entry = TDMMAP_HDLC;
 714 +               else if (chdev && chdev->open_count) {
 715 +                       entry = TDMMAP_VOICE64K;
 716 +                       chdev->log_channels[chdev->chan_count++] = log_chan;
 717 +               } else
 718 +                       entry = TDMMAP_UNASSIGNED;
 719 +               if (entry == TDMMAP_VOICE64K) {
 720 +                       chan_count++;
 721 +                       log_chan++;
 722 +               }
 723 +
 724 +               msg.data32 >>= 2;
 725 +               msg.data32 |= entry << 30;
 726 +
 727 +               if (ch % 16 == 15) {
 728 +                       msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
 729 +                       if (npe_send_message(port->npe, &msg, "HSS_SET_TX_LUT"))
 730 +                               break;
 731 +
 732 +                       msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
 733 +                       if (npe_send_message(port->npe, &msg, "HSS_SET_RX_LUT"))
 734 +                               break;
 735 +               }
 736 +       }
 737 +       if (ch != MAX_CHANNELS) {
 738 +               printk(KERN_CRIT "HSS-%i: unable to set HSS channel look-up"
 739 +                      " table\n", port->id);
 740 +               BUG();
 741 +       }
 742 +
 743 +       hss_config_set_frame(port);
 744 +
 745 +       if (!chan_count)
 746 +               return;
 747 +
 748 +       memset(&msg, 0, sizeof(msg));
 749 +       msg.cmd = CHAN_NUM_CHANS_WRITE;
 750 +       msg.hss_port = port->id;
 751 +       msg.data8a = chan_count;
 752 +       if (npe_send_message(port->npe, &msg, "CHAN_NUM_CHANS_WRITE")) {
 753 +               printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n",
 754 +                      port->id);
 755 +               BUG();
 756 +       }
 757 +
 758 +       /* don't leak data */
 759 +       // FIXME memset(chan_tx_buf(port), 0, CHAN_TX_FRAMES * chan_count);
 760 +       if (port->mode == MODE_G704) /* G.704 PCM-31 sync pattern */
 761 +               for (i = 0; i < CHAN_TX_FRAMES; i += 4)
 762 +                       *(u32*)(chan_tx_buf(port) + i) = 0x9BDF9BDF;
 763 +
 764 +       for (i = 0; i < CHAN_TX_LISTS; i++) {
 765 +               u32 phys = port->chan_tx_buf_phys + i * CHAN_TX_LIST_FRAMES;
 766 +               u32 *list = ((u32 *)chan_tx_lists(port)) + i * chan_count;
 767 +               for (ch = 0; ch < chan_count; ch++)
 768 +                       list[ch] = phys + ch * CHAN_TX_FRAMES;
 769 +       }
 770 +       dma_sync_single(port->dev, port->chan_tx_buf_phys,
 771 +                       chan_tx_buf_len(port) + chan_tx_lists_len(port),
 772 +                       DMA_TO_DEVICE);
 773 +}
 774 +
 775 +static u32 hss_config_get_status(struct port *port)
 776 +{
 777 +       struct msg msg;
 778 +
 779 +       do {
 780 +               memset(&msg, 0, sizeof(msg));
 781 +               msg.cmd = PORT_ERROR_READ;
 782 +               msg.hss_port = port->id;
 783 +               if (npe_send_message(port->npe, &msg, "PORT_ERROR_READ"))
 784 +                       break;
 785 +               if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ"))
 786 +                       break;
 787 +
 788 +               return msg.data32;
 789 +       } while (0);
 790 +
 791 +       printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id);
 792 +       BUG();
 793 +}
 794 +
 795 +static void hss_config_start_chan(struct port *port)
 796 +{
 797 +       struct msg msg;
 798 +
 799 +       port->chan_last_tx = 0;
 800 +       port->chan_last_rx = 0;
 801 +
 802 +       do {
 803 +               memset(&msg, 0, sizeof(msg));
 804 +               msg.cmd = CHAN_RX_BUF_ADDR_WRITE;
 805 +               msg.hss_port = port->id;
 806 +               msg.data32 = port->chan_rx_buf_phys;
 807 +               if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_ADDR_WRITE"))
 808 +                       break;
 809 +
 810 +               memset(&msg, 0, sizeof(msg));
 811 +               msg.cmd = CHAN_TX_BUF_ADDR_WRITE;
 812 +               msg.hss_port = port->id;
 813 +               msg.data32 = chan_tx_lists_phys(port);
 814 +               if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_ADDR_WRITE"))
 815 +                       break;
 816 +
 817 +               memset(&msg, 0, sizeof(msg));
 818 +               msg.cmd = CHAN_FLOW_ENABLE;
 819 +               msg.hss_port = port->id;
 820 +               if (npe_send_message(port->npe, &msg, "CHAN_FLOW_ENABLE"))
 821 +                       break;
 822 +               port->chan_started = 1;
 823 +               return;
 824 +       } while (0);
 825 +
 826 +       printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n",
 827 +              port->id);
 828 +       BUG();
 829 +}
 830 +
 831 +static void hss_config_stop_chan(struct port *port)
 832 +{
 833 +       struct msg msg;
 834 +
 835 +       if (!port->chan_started)
 836 +               return;
 837 +
 838 +       memset(&msg, 0, sizeof(msg));
 839 +       msg.cmd = CHAN_FLOW_DISABLE;
 840 +       msg.hss_port = port->id;
 841 +       if (npe_send_message(port->npe, &msg, "CHAN_FLOW_DISABLE")) {
 842 +               printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n",
 843 +                      port->id);
 844 +               BUG();
 845 +       }
 846 +       hss_config_get_status(port); /* make sure it's halted */
 847 +}
 848 +
 849 +static void hss_config_start_hdlc(struct port *port)
 850 +{
 851 +       struct msg msg;
 852 +
 853 +       memset(&msg, 0, sizeof(msg));
 854 +       msg.cmd = PKT_PIPE_FLOW_ENABLE;
 855 +       msg.hss_port = port->id;
 856 +       msg.data32 = 0;
 857 +       if (npe_send_message(port->npe, &msg, "HSS_ENABLE_PKT_PIPE")) {
 858 +               printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
 859 +                      port->id);
 860 +               BUG();
 861 +       }
 862 +}
 863 +
 864 +static void hss_config_stop_hdlc(struct port *port)
 865 +{
 866 +       struct msg msg;
 867 +
 868 +       memset(&msg, 0, sizeof(msg));
 869 +       msg.cmd = PKT_PIPE_FLOW_DISABLE;
 870 +       msg.hss_port = port->id;
 871 +       if (npe_send_message(port->npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
 872 +               printk(KERN_CRIT "HSS-%i: unable to stop packetized flow\n",
 873 +                      port->id);
 874 +               BUG();
 875 +       }
 876 +       hss_config_get_status(port); /* make sure it's halted */
 877 +}
 878 +
 879 +static int hss_config_load_firmware(struct port *port)
 880 +{
 881 +       struct msg msg;
 882 +
 883 +       if (port->initialized)
 884 +               return 0;
 885 +
 886 +       if (!npe_running(port->npe)) {
 887 +               int err;
 888 +               if ((err = npe_load_firmware(port->npe, npe_name(port->npe),
 889 +                                            port->dev)))
 890 +                       return err;
 891 +       }
 892 +
 893 +       do {
 894 +               /* HSS main configuration */
 895 +               hss_config_set_line(port);
 896 +
 897 +               hss_config_set_frame(port);
 898 +
 899 +               /* HDLC mode configuration */
 900 +               memset(&msg, 0, sizeof(msg));
 901 +               msg.cmd = PKT_NUM_PIPES_WRITE;
 902 +               msg.hss_port = port->id;
 903 +               msg.data8a = PKT_NUM_PIPES;
 904 +               if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_PIPES"))
 905 +                       break;
 906 +
 907 +               msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
 908 +               msg.data8a = PKT_PIPE_FIFO_SIZEW;
 909 +               if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_FIFO"))
 910 +                       break;
 911 +
 912 +               msg.cmd = PKT_PIPE_MODE_WRITE;
 913 +               msg.data8a = NPE_PKT_MODE_HDLC;
 914 +               /* msg.data8b = inv_mask */
 915 +               /* msg.data8c = or_mask */
 916 +               if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_MODE"))
 917 +                       break;
 918 +
 919 +               msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
 920 +               msg.data16a = HDLC_MAX_MRU; /* including CRC */
 921 +               if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_RX_SIZE"))
 922 +                       break;
 923 +
 924 +               msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
 925 +               msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
 926 +               if (npe_send_message(port->npe, &msg, "HSS_SET_PKT_IDLE"))
 927 +                       break;
 928 +
 929 +               /* Channelized operation settings */
 930 +               memset(&msg, 0, sizeof(msg));
 931 +               msg.cmd = CHAN_TX_BLK_CFG_WRITE;
 932 +               msg.hss_port = port->id;
 933 +               msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2;
 934 +               msg.data8a = msg.data8b / 4;
 935 +               msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b;
 936 +               msg.data8c = msg.data8d / 4;
 937 +               if (npe_send_message(port->npe, &msg, "CHAN_TX_BLK_CFG_WRITE"))
 938 +                       break;
 939 +
 940 +               memset(&msg, 0, sizeof(msg));
 941 +               msg.cmd = CHAN_RX_BUF_CFG_WRITE;
 942 +               msg.hss_port = port->id;
 943 +               msg.data8a = CHAN_RX_TRIGGER / 8;
 944 +               msg.data8b = CHAN_RX_FRAMES;
 945 +               if (npe_send_message(port->npe, &msg, "CHAN_RX_BUF_CFG_WRITE"))
 946 +                       break;
 947 +
 948 +               memset(&msg, 0, sizeof(msg));
 949 +               msg.cmd = CHAN_TX_BUF_SIZE_WRITE;
 950 +               msg.hss_port = port->id;
 951 +               msg.data8a = CHAN_TX_LISTS;
 952 +               if (npe_send_message(port->npe, &msg, "CHAN_TX_BUF_SIZE_WRITE"))
 953 +                       break;
 954 +
 955 +               port->initialized = 1;
 956 +               return 0;
 957 +       } while (0);
 958 +
 959 +       printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id);
 960 +       BUG();
 961 +}
 962 +
 963 +/*****************************************************************************
 964 + * packetized (HDLC) operation
 965 + ****************************************************************************/
 966 +
 967 +static inline void debug_pkt(struct net_device *dev, const char *func,
 968 +                            u8 *data, int len)
 969 +{
 970 +#if DEBUG_PKT_BYTES
 971 +       int i;
 972 +
 973 +       printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
 974 +       for (i = 0; i < len; i++) {
 975 +               if (i >= DEBUG_PKT_BYTES)
 976 +                       break;
 977 +               printk(KERN_DEBUG "%s%02X", !(i % 4) ? " " : "", data[i]);
 978 +       }
 979 +       printk(KERN_DEBUG "\n");
 980 +#endif
 981 +}
 982 +
 983 +
 984 +static inline void debug_desc(u32 phys, struct desc *desc)
 985 +{
 986 +#if DEBUG_DESC
 987 +       printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
 988 +              phys, desc->next, desc->buf_len, desc->pkt_len,
 989 +              desc->data, desc->status, desc->error_count);
 990 +#endif
 991 +}
 992 +
 993 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
 994 +{
 995 +#if DEBUG_QUEUES
 996 +       static struct {
 997 +               int queue;
 998 +               char *name;
 999 +       } names[] = {
1000 +               { HSS0_PKT_TX0_QUEUE, "TX#0 " },
1001 +               { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
1002 +               { HSS0_PKT_RX_QUEUE, "RX#0 " },
1003 +               { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
1004 +               { HSS1_PKT_TX0_QUEUE, "TX#1 " },
1005 +               { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
1006 +               { HSS1_PKT_RX_QUEUE, "RX#1 " },
1007 +               { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
1008 +       };
1009 +       int i;
1010 +
1011 +       for (i = 0; i < ARRAY_SIZE(names); i++)
1012 +               if (names[i].queue == queue)
1013 +                       break;
1014 +
1015 +       printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
1016 +              i < ARRAY_SIZE(names) ? names[i].name : "",
1017 +              is_get ? "->" : "<-", phys);
1018 +#endif
1019 +}
1020 +
1021 +static inline u32 queue_get_entry(unsigned int queue)
1022 +{
1023 +       u32 phys = qmgr_get_entry(queue);
1024 +       debug_queue(queue, 1, phys);
1025 +       return phys;
1026 +}
1027 +
1028 +static inline int queue_get_desc(unsigned int queue, struct port *port,
1029 +                                int is_tx)
1030 +{
1031 +       u32 phys, tab_phys, n_desc;
1032 +       struct desc *tab;
1033 +
1034 +       if (!(phys = queue_get_entry(queue)))
1035 +               return -1;
1036 +
1037 +       BUG_ON(phys & 0x1F);
1038 +       tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
1039 +       tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
1040 +       n_desc = (phys - tab_phys) / sizeof(struct desc);
1041 +       BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
1042 +       debug_desc(phys, &tab[n_desc]);
1043 +       BUG_ON(tab[n_desc].next);
1044 +       return n_desc;
1045 +}
1046 +
1047 +static inline void queue_put_desc(unsigned int queue, u32 phys,
1048 +                                 struct desc *desc)
1049 +{
1050 +       debug_queue(queue, 0, phys);
1051 +       debug_desc(phys, desc);
1052 +       BUG_ON(phys & 0x1F);
1053 +       qmgr_put_entry(queue, phys);
1054 +       BUG_ON(qmgr_stat_overflow(queue));
1055 +}
1056 +
1057 +
1058 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
1059 +{
1060 +#ifdef __ARMEB__
1061 +       dma_unmap_single(&port->netdev->dev, desc->data,
1062 +                        desc->buf_len, DMA_TO_DEVICE);
1063 +#else
1064 +       dma_unmap_single(&port->netdev->dev, desc->data & ~3,
1065 +                        ALIGN((desc->data & 3) + desc->buf_len, 4),
1066 +                        DMA_TO_DEVICE);
1067 +#endif
1068 +}
1069 +
1070 +
1071 +static void hss_hdlc_set_carrier(void *pdev, int carrier)
1072 +{
1073 +       struct net_device *netdev = pdev;
1074 +       struct port *port = dev_to_port(netdev);
1075 +       unsigned long flags;
1076 +
1077 +       spin_lock_irqsave(&npe_lock, flags);
1078 +       port->carrier = carrier;
1079 +       if (!port->loopback) {
1080 +               if (carrier)
1081 +                       netif_carrier_on(netdev);
1082 +               else
1083 +                       netif_carrier_off(netdev);
1084 +       }
1085 +       spin_unlock_irqrestore(&npe_lock, flags);
1086 +}
1087 +
1088 +static void hss_hdlc_rx_irq(void *pdev)
1089 +{
1090 +       struct net_device *dev = pdev;
1091 +       struct port *port = dev_to_port(dev);
1092 +
1093 +#if DEBUG_RX
1094 +       printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
1095 +#endif
1096 +       qmgr_disable_irq(queue_ids[port->id].rx);
1097 +       netif_rx_schedule(dev, &port->napi);
1098 +}
1099 +
1100 +static int hss_hdlc_poll(struct napi_struct *napi, int budget)
1101 +{
1102 +       struct port *port = container_of(napi, struct port, napi);
1103 +       struct net_device *dev = port->netdev;
1104 +       unsigned int rxq = queue_ids[port->id].rx;
1105 +       unsigned int rxfreeq = queue_ids[port->id].rxfree;
1106 +       struct net_device_stats *stats = hdlc_stats(dev);
1107 +       int received = 0;
1108 +
1109 +#if DEBUG_RX
1110 +       printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
1111 +#endif
1112 +
1113 +       while (received < budget) {
1114 +               struct sk_buff *skb;
1115 +               struct desc *desc;
1116 +               int n;
1117 +#ifdef __ARMEB__
1118 +               struct sk_buff *temp;
1119 +               u32 phys;
1120 +#endif
1121 +
1122 +               if ((n = queue_get_desc(rxq, port, 0)) < 0) {
1123 +                       received = 0; /* No packet received */
1124 +#if DEBUG_RX
1125 +                       printk(KERN_DEBUG "%s: hss_hdlc_poll"
1126 +                              " netif_rx_complete\n", dev->name);
1127 +#endif
1128 +                       netif_rx_complete(dev, napi);
1129 +                       qmgr_enable_irq(rxq);
1130 +                       if (!qmgr_stat_empty(rxq) &&
1131 +                           netif_rx_reschedule(dev, napi)) {
1132 +#if DEBUG_RX
1133 +                               printk(KERN_DEBUG "%s: hss_hdlc_poll"
1134 +                                      " netif_rx_reschedule succeeded\n",
1135 +                                      dev->name);
1136 +#endif
1137 +                               qmgr_disable_irq(rxq);
1138 +                               continue;
1139 +                       }
1140 +#if DEBUG_RX
1141 +                       printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
1142 +                              dev->name);
1143 +#endif
1144 +                       return 0; /* all work done */
1145 +               }
1146 +
1147 +               desc = rx_desc_ptr(port, n);
1148 +#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
1149 +               if (desc->error_count)
1150 +                       printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
1151 +                              " errors %u\n", dev->name, desc->status,
1152 +                              desc->error_count);
1153 +#endif
1154 +               skb = NULL;
1155 +               switch (desc->status) {
1156 +               case 0:
1157 +#ifdef __ARMEB__
1158 +                       if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
1159 +                               phys = dma_map_single(&dev->dev, skb->data,
1160 +                                                     RX_SIZE,
1161 +                                                     DMA_FROM_DEVICE);
1162 +                               if (dma_mapping_error(phys)) {
1163 +                                       dev_kfree_skb(skb);
1164 +                                       skb = NULL;
1165 +                               }
1166 +                       }
1167 +#else
1168 +                       skb = netdev_alloc_skb(dev, desc->pkt_len);
1169 +#endif
1170 +                       if (!skb)
1171 +                               stats->rx_dropped++;
1172 +                       break;
1173 +               case ERR_HDLC_ALIGN:
1174 +               case ERR_HDLC_ABORT:
1175 +                       stats->rx_frame_errors++;
1176 +                       stats->rx_errors++;
1177 +                       break;
1178 +               case ERR_HDLC_FCS:
1179 +                       stats->rx_crc_errors++;
1180 +                       stats->rx_errors++;
1181 +                       break;
1182 +               case ERR_HDLC_TOO_LONG:
1183 +                       stats->rx_length_errors++;
1184 +                       stats->rx_errors++;
1185 +                       break;
1186 +               default:        /* FIXME - remove printk */
1187 +                       printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
1188 +                              " errors %u\n", dev->name, desc->status,
1189 +                              desc->error_count);
1190 +                       stats->rx_errors++;
1191 +               }
1192 +
1193 +               if (!skb) {
1194 +                       /* put the desc back on RX-ready queue */
1195 +                       desc->buf_len = RX_SIZE;
1196 +                       desc->pkt_len = desc->status = 0;
1197 +                       queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1198 +                       continue;
1199 +               }
1200 +
1201 +               /* process received frame */
1202 +#ifdef __ARMEB__
1203 +               temp = skb;
1204 +               skb = port->rx_buff_tab[n];
1205 +               dma_unmap_single(&dev->dev, desc->data,
1206 +                                RX_SIZE, DMA_FROM_DEVICE);
1207 +#else
1208 +               dma_sync_single(&dev->dev, desc->data,
1209 +                               RX_SIZE, DMA_FROM_DEVICE);
1210 +               memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
1211 +                             ALIGN(desc->pkt_len, 4) / 4);
1212 +#endif
1213 +               skb_put(skb, desc->pkt_len);
1214 +
1215 +               debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
1216 +
1217 +               skb->protocol = hdlc_type_trans(skb, dev);
1218 +               dev->last_rx = jiffies;
1219 +               stats->rx_packets++;
1220 +               stats->rx_bytes += skb->len;
1221 +               netif_receive_skb(skb);
1222 +
1223 +               /* put the new buffer on RX-free queue */
1224 +#ifdef __ARMEB__
1225 +               port->rx_buff_tab[n] = temp;
1226 +               desc->data = phys;
1227 +#endif
1228 +               desc->buf_len = RX_SIZE;
1229 +               desc->pkt_len = 0;
1230 +               queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1231 +               received++;
1232 +       }
1233 +#if DEBUG_RX
1234 +       printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
1235 +#endif
1236 +       return received;        /* not all work done */
1237 +}
1238 +
1239 +
1240 +static void hss_hdlc_txdone_irq(void *pdev)
1241 +{
1242 +       struct net_device *dev = pdev;
1243 +       struct port *port = dev_to_port(dev);
1244 +       struct net_device_stats *stats = hdlc_stats(dev);
1245 +       int n_desc;
1246 +
1247 +#if DEBUG_TX
1248 +       printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
1249 +#endif
1250 +       while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
1251 +                                       port, 1)) >= 0) {
1252 +               struct desc *desc;
1253 +               int start;
1254 +
1255 +               desc = tx_desc_ptr(port, n_desc);
1256 +
1257 +               stats->tx_packets++;
1258 +               stats->tx_bytes += desc->pkt_len;
1259 +
1260 +               dma_unmap_tx(port, desc);
1261 +#if DEBUG_TX
1262 +               printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
1263 +                      dev->name, port->tx_buff_tab[n_desc]);
1264 +#endif
1265 +               free_buffer_irq(port->tx_buff_tab[n_desc]);
1266 +               port->tx_buff_tab[n_desc] = NULL;
1267 +
1268 +               start = qmgr_stat_empty(port->plat->txreadyq);
1269 +               queue_put_desc(port->plat->txreadyq,
1270 +                              tx_desc_phys(port, n_desc), desc);
1271 +               if (start) {
1272 +#if DEBUG_TX
1273 +                       printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
1274 +                              " ready\n", dev->name);
1275 +#endif
1276 +                       netif_wake_queue(dev);
1277 +               }
1278 +       }
1279 +}
1280 +
1281 +static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
1282 +{
1283 +       struct port *port = dev_to_port(dev);
1284 +       struct net_device_stats *stats = hdlc_stats(dev);
1285 +       unsigned int txreadyq = port->plat->txreadyq;
1286 +       int len, offset, bytes, n;
1287 +       void *mem;
1288 +       u32 phys;
1289 +       struct desc *desc;
1290 +
1291 +#if DEBUG_TX
1292 +       printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
1293 +#endif
1294 +
1295 +       if (unlikely(skb->len > HDLC_MAX_MRU)) {
1296 +               dev_kfree_skb(skb);
1297 +               stats->tx_errors++;
1298 +               return NETDEV_TX_OK;
1299 +       }
1300 +
1301 +       debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
1302 +
1303 +       len = skb->len;
1304 +#ifdef __ARMEB__
1305 +       offset = 0; /* no need to keep alignment */
1306 +       bytes = len;
1307 +       mem = skb->data;
1308 +#else
1309 +       offset = (int)skb->data & 3; /* keep 32-bit alignment */
1310 +       bytes = ALIGN(offset + len, 4);
1311 +       if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
1312 +               dev_kfree_skb(skb);
1313 +               stats->tx_dropped++;
1314 +               return NETDEV_TX_OK;
1315 +       }
1316 +       memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
1317 +       dev_kfree_skb(skb);
1318 +#endif
1319 +
1320 +       phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
1321 +       if (dma_mapping_error(phys)) {
1322 +#ifdef __ARMEB__
1323 +               dev_kfree_skb(skb);
1324 +#else
1325 +               kfree(mem);
1326 +#endif
1327 +               stats->tx_dropped++;
1328 +               return NETDEV_TX_OK;
1329 +       }
1330 +
1331 +       n = queue_get_desc(txreadyq, port, 1);
1332 +       BUG_ON(n < 0);
1333 +       desc = tx_desc_ptr(port, n);
1334 +
1335 +#ifdef __ARMEB__
1336 +       port->tx_buff_tab[n] = skb;
1337 +#else
1338 +       port->tx_buff_tab[n] = mem;
1339 +#endif
1340 +       desc->data = phys + offset;
1341 +       desc->buf_len = desc->pkt_len = len;
1342 +
1343 +       wmb();
1344 +       queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
1345 +       dev->trans_start = jiffies;
1346 +
1347 +       if (qmgr_stat_empty(txreadyq)) {
1348 +#if DEBUG_TX
1349 +               printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
1350 +#endif
1351 +               netif_stop_queue(dev);
1352 +               /* we could miss TX ready interrupt */
1353 +               if (!qmgr_stat_empty(txreadyq)) {
1354 +#if DEBUG_TX
1355 +                       printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
1356 +                              dev->name);
1357 +#endif
1358 +                       netif_wake_queue(dev);
1359 +               }
1360 +       }
1361 +
1362 +#if DEBUG_TX
1363 +       printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
1364 +#endif
1365 +       return NETDEV_TX_OK;
1366 +}
1367 +
1368 +
1369 +static int request_hdlc_queues(struct port *port)
1370 +{
1371 +       int err;
1372 +
1373 +       err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
1374 +       if (err)
1375 +               return err;
1376 +
1377 +       err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
1378 +       if (err)
1379 +               goto rel_rxfree;
1380 +
1381 +       err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
1382 +       if (err)
1383 +               goto rel_rx;
1384 +
1385 +       err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
1386 +       if (err)
1387 +               goto rel_tx;
1388 +
1389 +       err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
1390 +       if (err)
1391 +               goto rel_txready;
1392 +       return 0;
1393 +
1394 +rel_txready:
1395 +       qmgr_release_queue(port->plat->txreadyq);
1396 +rel_tx:
1397 +       qmgr_release_queue(queue_ids[port->id].tx);
1398 +rel_rx:
1399 +       qmgr_release_queue(queue_ids[port->id].rx);
1400 +rel_rxfree:
1401 +       qmgr_release_queue(queue_ids[port->id].rxfree);
1402 +       printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1403 +              port->netdev->name);
1404 +       return err;
1405 +}
1406 +
1407 +static void release_hdlc_queues(struct port *port)
1408 +{
1409 +       qmgr_release_queue(queue_ids[port->id].rxfree);
1410 +       qmgr_release_queue(queue_ids[port->id].rx);
1411 +       qmgr_release_queue(queue_ids[port->id].txdone);
1412 +       qmgr_release_queue(queue_ids[port->id].tx);
1413 +       qmgr_release_queue(port->plat->txreadyq);
1414 +}
1415 +
1416 +static int init_hdlc_queues(struct port *port)
1417 +{
1418 +       int i;
1419 +
1420 +       if (!ports_open)
1421 +               if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
1422 +                                                POOL_ALLOC_SIZE, 32, 0)))
1423 +                       return -ENOMEM;
1424 +
1425 +       if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1426 +                                             &port->desc_tab_phys)))
1427 +               return -ENOMEM;
1428 +       memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1429 +       memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1430 +       memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1431 +
1432 +       /* Setup RX buffers */
1433 +       for (i = 0; i < RX_DESCS; i++) {
1434 +               struct desc *desc = rx_desc_ptr(port, i);
1435 +               buffer_t *buff;
1436 +               void *data;
1437 +#ifdef __ARMEB__
1438 +               if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
1439 +                       return -ENOMEM;
1440 +               data = buff->data;
1441 +#else
1442 +               if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
1443 +                       return -ENOMEM;
1444 +               data = buff;
1445 +#endif
1446 +               desc->buf_len = RX_SIZE;
1447 +               desc->data = dma_map_single(&port->netdev->dev, data,
1448 +                                           RX_SIZE, DMA_FROM_DEVICE);
1449 +               if (dma_mapping_error(desc->data)) {
1450 +                       free_buffer(buff);
1451 +                       return -EIO;
1452 +               }
1453 +               port->rx_buff_tab[i] = buff;
1454 +       }
1455 +
1456 +       return 0;
1457 +}
1458 +
1459 +static void destroy_hdlc_queues(struct port *port)
1460 +{
1461 +       int i;
1462 +
1463 +       if (port->desc_tab) {
1464 +               for (i = 0; i < RX_DESCS; i++) {
1465 +                       struct desc *desc = rx_desc_ptr(port, i);
1466 +                       buffer_t *buff = port->rx_buff_tab[i];
1467 +                       if (buff) {
1468 +                               dma_unmap_single(&port->netdev->dev,
1469 +                                                desc->data, RX_SIZE,
1470 +                                                DMA_FROM_DEVICE);
1471 +                               free_buffer(buff);
1472 +                       }
1473 +               }
1474 +               for (i = 0; i < TX_DESCS; i++) {
1475 +                       struct desc *desc = tx_desc_ptr(port, i);
1476 +                       buffer_t *buff = port->tx_buff_tab[i];
1477 +                       if (buff) {
1478 +                               dma_unmap_tx(port, desc);
1479 +                               free_buffer(buff);
1480 +                       }
1481 +               }
1482 +               dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1483 +               port->desc_tab = NULL;
1484 +       }
1485 +
1486 +       if (!ports_open && dma_pool) {
1487 +               dma_pool_destroy(dma_pool);
1488 +               dma_pool = NULL;
1489 +       }
1490 +}
1491 +
1492 +static int hss_hdlc_open(struct net_device *dev)
1493 +{
1494 +       struct port *port = dev_to_port(dev);
1495 +       unsigned long flags;
1496 +       int i, err = 0;
1497 +
1498 +       if ((err = hdlc_open(dev)))
1499 +               return err;
1500 +
1501 +       if ((err = request_hdlc_queues(port)))
1502 +               goto err_hdlc_close;
1503 +
1504 +       if ((err = init_hdlc_queues(port)))
1505 +               goto err_destroy_queues;
1506 +
1507 +       spin_lock_irqsave(&npe_lock, flags);
1508 +
1509 +       if (port->mode == MODE_G704 && port->channels[0] == CHANNEL_HDLC) {
1510 +               err = -EBUSY; /* channel #0 is used for G.704 framing */
1511 +               goto err_unlock;
1512 +       }
1513 +       if (port->mode != MODE_HDLC)
1514 +               for (i = port->frame_size / 8; i < MAX_CHANNELS; i++)
1515 +                       if (port->channels[i] == CHANNEL_HDLC) {
1516 +                               err = -ECHRNG; /* frame too short */
1517 +                               goto err_unlock;
1518 +                       }
1519 +
1520 +       if ((err = hss_config_load_firmware(port)))
1521 +               goto err_unlock;
1522 +
1523 +       if (!port->chan_open_count && port->plat->open)
1524 +               if ((err = port->plat->open(port->id, dev,
1525 +                                           hss_hdlc_set_carrier)))
1526 +                       goto err_unlock;
1527 +
1528 +       if (port->mode == MODE_G704 && !port->chan_open_count)
1529 +               if ((err = hss_prepare_chan(port)))
1530 +                       goto err_plat_close;
1531 +
1532 +       spin_unlock_irqrestore(&npe_lock, flags);
1533 +
1534 +       /* Populate queues with buffers, no failure after this point */
1535 +       for (i = 0; i < TX_DESCS; i++)
1536 +               queue_put_desc(port->plat->txreadyq,
1537 +                              tx_desc_phys(port, i), tx_desc_ptr(port, i));
1538 +
1539 +       for (i = 0; i < RX_DESCS; i++)
1540 +               queue_put_desc(queue_ids[port->id].rxfree,
1541 +                              rx_desc_phys(port, i), rx_desc_ptr(port, i));
1542 +
1543 +       napi_enable(&port->napi);
1544 +       netif_start_queue(dev);
1545 +
1546 +       qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1547 +                    hss_hdlc_rx_irq, dev);
1548 +
1549 +       qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1550 +                    hss_hdlc_txdone_irq, dev);
1551 +       qmgr_enable_irq(queue_ids[port->id].txdone);
1552 +
1553 +       ports_open++;
1554 +       port->hdlc_open = 1;
1555 +
1556 +       hss_config_set_hdlc_cfg(port);
1557 +       hss_config_set_lut(port);
1558 +       hss_config_load(port);
1559 +
1560 +       if (port->mode == MODE_G704 && !port->chan_open_count)
1561 +               hss_config_start_chan(port);
1562 +
1563 +       hss_config_start_hdlc(port);
1564 +
1565 +       /* we may already have RX data, enables IRQ */
1566 +       netif_rx_schedule(dev, &port->napi);
1567 +       return 0;
1568 +
1569 +err_plat_close:
1570 +       if (!port->chan_open_count && port->plat->close)
1571 +               port->plat->close(port->id, dev);
1572 +err_unlock:
1573 +       spin_unlock_irqrestore(&npe_lock, flags);
1574 +err_destroy_queues:
1575 +       destroy_hdlc_queues(port);
1576 +       release_hdlc_queues(port);
1577 +err_hdlc_close:
1578 +       hdlc_close(dev);
1579 +       return err;
1580 +}
1581 +
1582 +static int hss_hdlc_close(struct net_device *dev)
1583 +{
1584 +       struct port *port = dev_to_port(dev);
1585 +       unsigned long flags;
1586 +       int i, buffs = RX_DESCS; /* allocated RX buffers */
1587 +
1588 +       spin_lock_irqsave(&npe_lock, flags);
1589 +       ports_open--;
1590 +       port->hdlc_open = 0;
1591 +       qmgr_disable_irq(queue_ids[port->id].rx);
1592 +       netif_stop_queue(dev);
1593 +       napi_disable(&port->napi);
1594 +
1595 +       hss_config_stop_hdlc(port);
1596 +
1597 +       if (port->mode == MODE_G704 && !port->chan_open_count)
1598 +               hss_chan_stop(port);
1599 +
1600 +       while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1601 +               buffs--;
1602 +       while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1603 +               buffs--;
1604 +
1605 +       if (buffs)
1606 +               printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1607 +                      " left in NPE\n", dev->name, buffs);
1608 +
1609 +       buffs = TX_DESCS;
1610 +       while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1611 +               buffs--; /* cancel TX */
1612 +
1613 +       i = 0;
1614 +       do {
1615 +               while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1616 +                       buffs--;
1617 +               if (!buffs)
1618 +                       break;
1619 +       } while (++i < MAX_CLOSE_WAIT);
1620 +
1621 +       if (buffs)
1622 +               printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1623 +                      "left in NPE\n", dev->name, buffs);
1624 +#if DEBUG_CLOSE
1625 +       if (!buffs)
1626 +               printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1627 +#endif
1628 +       qmgr_disable_irq(queue_ids[port->id].txdone);
1629 +
1630 +       if (!port->chan_open_count && port->plat->close)
1631 +               port->plat->close(port->id, dev);
1632 +       spin_unlock_irqrestore(&npe_lock, flags);
1633 +
1634 +       destroy_hdlc_queues(port);
1635 +       release_hdlc_queues(port);
1636 +       hdlc_close(dev);
1637 +       return 0;
1638 +}
1639 +
1640 +
1641 +static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1642 +                          unsigned short parity)
1643 +{
1644 +       struct port *port = dev_to_port(dev);
1645 +
1646 +       if (encoding != ENCODING_NRZ)
1647 +               return -EINVAL;
1648 +
1649 +       switch(parity) {
1650 +       case PARITY_CRC16_PR1_CCITT:
1651 +               port->hdlc_cfg = 0;
1652 +               return 0;
1653 +
1654 +       case PARITY_CRC32_PR1_CCITT:
1655 +               port->hdlc_cfg = PKT_HDLC_CRC_32;
1656 +               return 0;
1657 +
1658 +       default:
1659 +               return -EINVAL;
1660 +       }
1661 +}
1662 +
1663 +
1664 +static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1665 +{
1666 +       const size_t size = sizeof(sync_serial_settings);
1667 +       sync_serial_settings new_line;
1668 +       sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1669 +       struct port *port = dev_to_port(dev);
1670 +       unsigned long flags;
1671 +       int i, clk;
1672 +
1673 +       if (cmd != SIOCWANDEV)
1674 +               return hdlc_ioctl(dev, ifr, cmd);
1675 +
1676 +       switch(ifr->ifr_settings.type) {
1677 +       case IF_GET_IFACE:
1678 +               ifr->ifr_settings.type = IF_IFACE_V35;
1679 +               if (ifr->ifr_settings.size < size) {
1680 +                       ifr->ifr_settings.size = size; /* data size wanted */
1681 +                       return -ENOBUFS;
1682 +               }
1683 +               memset(&new_line, 0, sizeof(new_line));
1684 +               new_line.clock_type = port->clock_type;
1685 +               new_line.clock_rate = port->clock_rate;
1686 +               new_line.loopback = port->loopback;
1687 +               if (copy_to_user(line, &new_line, size))
1688 +                       return -EFAULT;
1689 +
1690 +               if (!port->chan_buf)
1691 +                       return 0;
1692 +
1693 +               dma_sync_single(&dev->dev, port->chan_rx_buf_phys,
1694 +                               chan_rx_buf_len(port), DMA_FROM_DEVICE);
1695 +               printk(KERN_DEBUG "RX:\n");
1696 +               for (i = 0; i < chan_rx_buf_len(port); i++) {
1697 +                       if (i % 32 == 0)
1698 +                               printk(KERN_DEBUG "%03X ", i);
1699 +                       printk("%02X%c", chan_rx_buf(port)[i],
1700 +                              (i + 1) % 32 ? ' ' : '\n');
1701 +               }
1702 +
1703 +#if 0
1704 +               printk(KERN_DEBUG "TX:\n");
1705 +               for (i = 0; i < /*CHAN_TX_FRAMES * 2*/ chan_tx_buf_len(port)
1706 +                            + chan_tx_lists_len(port); i++) {
1707 +                       if (i % 32 == 0)
1708 +                               printk(KERN_DEBUG "%03X ", i);
1709 +                       printk("%02X%c", chan_tx_buf(port)[i],
1710 +                              (i + 1) % 32 ? ' ' : '\n');
1711 +               }
1712 +#endif
1713 +               port->msg_count = 10;
1714 +               return 0;
1715 +
1716 +       case IF_IFACE_SYNC_SERIAL:
1717 +       case IF_IFACE_V35:
1718 +               if(!capable(CAP_NET_ADMIN))
1719 +                       return -EPERM;
1720 +               if (copy_from_user(&new_line, line, size))
1721 +                       return -EFAULT;
1722 +
1723 +               clk = new_line.clock_type;
1724 +               if (port->plat->set_clock)
1725 +                       clk = port->plat->set_clock(port->id, clk);
1726 +
1727 +               if (clk != CLOCK_EXT && clk != CLOCK_INT)
1728 +                       return -EINVAL; /* No such clock setting */
1729 +
1730 +               if (new_line.loopback != 0 && new_line.loopback != 1)
1731 +                       return -EINVAL;
1732 +
1733 +               port->clock_type = clk; /* Update settings */
1734 +               /* FIXME port->clock_rate = new_line.clock_rate */;
1735 +               port->loopback = new_line.loopback;
1736 +
1737 +               spin_lock_irqsave(&npe_lock, flags);
1738 +
1739 +               if (port->chan_open_count || port->hdlc_open) {
1740 +                       hss_config_set_line(port);
1741 +                       hss_config_load(port);
1742 +               }
1743 +               if (port->loopback || port->carrier)
1744 +                       netif_carrier_on(port->netdev);
1745 +               else
1746 +                       netif_carrier_off(port->netdev);
1747 +               spin_unlock_irqrestore(&npe_lock, flags);
1748 +
1749 +               return 0;
1750 +
1751 +       default:
1752 +               return hdlc_ioctl(dev, ifr, cmd);
1753 +       }
1754 +}
1755 +
1756 +/*****************************************************************************
1757 + * channelized (G.704) operation
1758 + ****************************************************************************/
1759 +
1760 +static void g704_rx_framer(struct port *port, unsigned int offset)
1761 +{
1762 +       u8 *data = chan_rx_buf(port) + sub_offset(offset, CHAN_RX_TRIGGER,
1763 +                                                 CHAN_RX_FRAMES);
1764 +       unsigned int bit, frame, bad_even = 0, bad_odd = 0, cnt;
1765 +       unsigned int is_first = port->just_set_offset;
1766 +       u8 zeros_even, zeros_odd, ones_even, ones_odd;
1767 +       enum alignment aligned;
1768 +
1769 +       port->just_set_offset = 0;
1770 +       dma_sync_single(port->dev, port->chan_rx_buf_phys, CHAN_RX_FRAMES,
1771 +                       DMA_FROM_DEVICE);
1772 +
1773 +       /* check if aligned first */
1774 +       for (frame = 0; frame < CHAN_RX_TRIGGER &&
1775 +                    (bad_even <= MAX_CHAN_RX_BAD_SYNC ||
1776 +                     bad_odd <= MAX_CHAN_RX_BAD_SYNC); frame += 2) {
1777 +               u8 ve = data[frame];
1778 +               u8 vo = data[frame + 1];
1779 +
1780 +               if ((ve & 0x7F) != 0x1B || !(vo & 0x40))
1781 +                       bad_even++;
1782 +
1783 +               if ((vo & 0x7F) != 0x1B || !(ve & 0x40))
1784 +                       bad_odd++;
1785 +       }
1786 +
1787 +       if (bad_even <= MAX_CHAN_RX_BAD_SYNC)
1788 +               aligned = EVEN_FIRST;
1789 +       else if (bad_odd <= MAX_CHAN_RX_BAD_SYNC)
1790 +               aligned = ODD_FIRST;
1791 +       else
1792 +               aligned = NOT_ALIGNED;
1793 +
1794 +       if (aligned != NOT_ALIGNED) {
1795 +               if (aligned == port->aligned)
1796 +                       return; /* no change */
1797 +               if (printk_ratelimit())
1798 +                       printk(KERN_INFO "HSS-%i: synchronized at %u (%s frame"
1799 +                              " first)\n", port->id, port->frame_sync_offset,
1800 +                              aligned == EVEN_FIRST ? "even" : "odd");
1801 +               port->aligned = aligned;
1802 +
1803 +               atomic_inc(&port->chan_tx_irq_number);
1804 +               wake_up_interruptible(&port->chan_tx_waitq);
1805 +               atomic_inc(&port->chan_rx_irq_number);
1806 +               wake_up_interruptible(&port->chan_rx_waitq);
1807 +               return;
1808 +       }
1809 +
1810 +       /* not aligned */
1811 +       if (port->aligned != NOT_ALIGNED && printk_ratelimit()) {
1812 +               printk(KERN_INFO "HSS-%i: lost alignment\n", port->id);
1813 +               port->aligned = NOT_ALIGNED;
1814 +#if DEBUG_FRAMER
1815 +               for (cnt = 0; cnt < CHAN_RX_FRAMES; cnt++)
1816 +                       printk("%c%02X%s", cnt == offset ? '>' : ' ',
1817 +                              chan_rx_buf(port)[cnt],
1818 +                              (cnt + 1) % 32 ? "" : "\n");
1819 +#endif
1820 +
1821 +               for (cnt = 0; cnt < MAX_CHAN_DEVICES; cnt++)
1822 +                       if (port->chan_devices[cnt]) {
1823 +                               set_bit(TX_ERROR_BIT, &port->chan_devices[cnt]
1824 +                                       ->errors_bitmap);
1825 +                               set_bit(RX_ERROR_BIT, &port->chan_devices[cnt]
1826 +                                       ->errors_bitmap);
1827 +                       }
1828 +               atomic_inc(&port->chan_tx_irq_number);
1829 +               wake_up_interruptible(&port->chan_tx_waitq);
1830 +               atomic_inc(&port->chan_rx_irq_number);
1831 +               wake_up_interruptible(&port->chan_rx_waitq);
1832 +       }
1833 +
1834 +       if (is_first)
1835 +               return;
1836 +
1837 +       zeros_even = zeros_odd = 0;
1838 +       ones_even = ones_odd = 0xFF;
1839 +       for (frame = 0; frame < CHAN_RX_TRIGGER; frame += 2) {
1840 +               zeros_even |= data[frame];
1841 +               zeros_odd |= data[frame + 1];
1842 +               ones_even &= data[frame];
1843 +               ones_odd &= data[frame + 1];
1844 +       }
1845 +
1846 +       for (bit = 0; bit < 7; bit++) {
1847 +               if ((zeros_even & ~0x9B) == 0 && (ones_even & 0x1B) == 0x1B &&
1848 +                   (ones_odd & 0x40) == 0x40) {
1849 +                       aligned = EVEN_FIRST; /* maybe */
1850 +                       break;
1851 +               }
1852 +               if ((zeros_odd & ~0x9B) == 0 && (ones_odd & 0x1B) == 0x1B &&
1853 +                   (ones_even & 0x40) == 0x40) {
1854 +                       aligned = ODD_FIRST; /* maybe */
1855 +                       break;
1856 +               }
1857 +               zeros_even <<= 1;
1858 +               ones_even = ones_even << 1 | 1;
1859 +               zeros_odd <<= 1;
1860 +               ones_odd = ones_odd << 1 | 1;
1861 +       }
1862 +
1863 +       port->frame_sync_offset += port->frame_size - bit;
1864 +       port->frame_sync_offset %= port->frame_size;
1865 +       port->just_set_offset = 1;
1866 +
1867 +#if DEBUG_FRAMER
1868 +       if (bit == 7)
1869 +               printk(KERN_DEBUG "HSS-%i: trying frame sync at %u\n",
1870 +                      port->id, port->frame_sync_offset);
1871 +       else
1872 +               printk(KERN_DEBUG "HSS-%i: found possible frame sync pattern at"
1873 +                      " %u (%s frame first)\n", port->id,
1874 +                      port->frame_sync_offset,
1875 +                      aligned == EVEN_FIRST ? "even" : "odd");
1876 +#endif
1877 +
1878 +       hss_config_set_rx_frame(port);
1879 +       hss_config_load(port);
1880 +}
1881 +
1882 +static void chan_process_tx_irq(struct chan_device *chan_dev, int offset)
1883 +{
1884 +       /* in bytes */
1885 +       unsigned int buff_len = CHAN_TX_FRAMES * chan_dev->chan_count;
1886 +       unsigned int list_len = CHAN_TX_LIST_FRAMES * chan_dev->chan_count;
1887 +       int eaten, last_offset = chan_dev->port->chan_last_tx * list_len;
1888 +
1889 +       offset *= list_len;
1890 +       eaten = sub_offset(offset, last_offset, buff_len);
1891 +
1892 +       if (chan_dev->tx_count > eaten + 2 * list_len) {
1893 +               /* two pages must be reserved for the transmitter */
1894 +               chan_dev->tx_first += eaten;
1895 +               chan_dev->tx_first %= buff_len;
1896 +               chan_dev->tx_count -= eaten;
1897 +       } else {
1898 +               /* FIXME check
1899 +                  0
1900 +                  1 tx_first (may still be transmited)
1901 +                  2 tx_offset (currently reported by the NPE)
1902 +                  3 tx_first + 2 * list_len (free to write here)
1903 +                  4
1904 +                  5
1905 +               */
1906 +
1907 +               /* printk(KERN_DEBUG "TX buffer underflow\n"); */
1908 +               chan_dev->tx_first = sub_offset(offset, list_len, buff_len);
1909 +               chan_dev->tx_count = 2 * list_len; /* reserve */
1910 +               set_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
1911 +       }
1912 +}
1913 +
1914 +static void chan_process_rx_irq(struct chan_device *chan_dev, int offset)
1915 +{
1916 +       /* in bytes */
1917 +       unsigned int buff_len = CHAN_RX_FRAMES * chan_dev->chan_count;
1918 +       unsigned int trig_len = CHAN_RX_TRIGGER * chan_dev->chan_count;
1919 +       int last_offset = chan_dev->port->chan_last_rx * chan_dev->chan_count;
1920 +
1921 +       offset *= chan_dev->chan_count;
1922 +       chan_dev->rx_count += sub_offset(offset, last_offset + trig_len,
1923 +                                        buff_len) + trig_len;
1924 +       if (chan_dev->rx_count > buff_len - 2 * trig_len) {
1925 +               /* two pages - offset[0] and offset[1] are lost - FIXME check */
1926 +               /* printk(KERN_DEBUG "RX buffer overflow\n"); */
1927 +               chan_dev->rx_first = (offset + 2 * trig_len) % buff_len;
1928 +               chan_dev->rx_count = buff_len - 2 * trig_len;
1929 +               set_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
1930 +       }
1931 +}
1932 +
1933 +static void hss_chan_irq(void *pdev)
1934 +{
1935 +       struct port *port = pdev;
1936 +       u32 v;
1937 +
1938 +#if DEBUG_RX
1939 +       printk(KERN_DEBUG DRV_NAME ": hss_chan_irq\n");
1940 +#endif
1941 +       spin_lock(&npe_lock);
1942 +       while ((v = qmgr_get_entry(queue_ids[port->id].chan))) {
1943 +               unsigned int first, errors, tx_list, rx_frame;
1944 +               int i, bad;
1945 +
1946 +               first = v >> 24;
1947 +               errors = (v >> 16) & 0xFF;
1948 +               tx_list = (v >> 8) & 0xFF;
1949 +               rx_frame = v & 0xFF;
1950 +
1951 +               if (port->msg_count) {
1952 +                       printk(KERN_DEBUG "chan_irq hss %i jiffies %lu first"
1953 +                              " 0x%02X errors 0x%02X tx_list 0x%02X rx_frame"
1954 +                              " 0x%02X\n", port->id, jiffies, first, errors,
1955 +                              tx_list, rx_frame);
1956 +                       port->msg_count--;
1957 +               }
1958 +
1959 +               BUG_ON(rx_frame % CHAN_RX_TRIGGER);
1960 +               BUG_ON(rx_frame >= CHAN_RX_FRAMES);
1961 +               BUG_ON(tx_list >= CHAN_TX_LISTS);
1962 +
1963 +               bad = port->mode == MODE_G704 && port->aligned == NOT_ALIGNED;
1964 +               if (!bad && tx_list != port->chan_last_tx) {
1965 +                       if (tx_list != (port->chan_last_tx + 1) % CHAN_TX_LISTS)
1966 +                               printk(KERN_DEBUG "Skipped an IRQ? Tx last %i"
1967 +                                      " current %i\n", port->chan_last_tx,
1968 +                                      tx_list);
1969 +                       for (i = 0; i < MAX_CHAN_DEVICES; i++) {
1970 +                               if (!port->chan_devices[i] ||
1971 +                                   !port->chan_devices[i]->open_count)
1972 +                                       continue;
1973 +                               chan_process_tx_irq(port->chan_devices[i],
1974 +                                                   tx_list);
1975 +                       }
1976 +                       atomic_inc(&port->chan_tx_irq_number);
1977 +#if 0
1978 +                       printk(KERN_DEBUG "wakeing up TX jiff %lu\n",
1979 +                              jiffies, errors);
1980 +#endif
1981 +                       wake_up_interruptible(&port->chan_tx_waitq);
1982 +               }
1983 +
1984 +               if (rx_frame != (port->chan_last_rx + CHAN_RX_TRIGGER) %
1985 +                   CHAN_RX_FRAMES)
1986 +                       printk(KERN_DEBUG "Skipped an IRQ? Rx last %i"
1987 +                              " current %i\n", port->chan_last_rx, rx_frame);
1988 +
1989 +               if (port->mode == MODE_G704)
1990 +                       g704_rx_framer(port, rx_frame);
1991 +
1992 +               if (!bad &&
1993 +                   (port->mode != MODE_G704 || port->aligned != NOT_ALIGNED)) {
1994 +                       for (i = 0; i < MAX_CHAN_DEVICES; i++) {
1995 +                               if (!port->chan_devices[i] ||
1996 +                                   !port->chan_devices[i]->open_count)
1997 +                                       continue;
1998 +                               chan_process_rx_irq(port->chan_devices[i],
1999 +                                                   rx_frame);
2000 +                       }
2001 +                       atomic_inc(&port->chan_rx_irq_number);
2002 +                       wake_up_interruptible(&port->chan_rx_waitq);
2003 +               }
2004 +               port->chan_last_tx = tx_list;
2005 +               port->chan_last_rx = rx_frame;
2006 +       }
2007 +       spin_unlock(&npe_lock);
2008 +}
2009 +
2010 +
2011 +static int hss_prepare_chan(struct port *port)
2012 +{
2013 +       int err;
2014 +
2015 +       if ((err = hss_config_load_firmware(port)))
2016 +               return err;
2017 +
2018 +       if ((err = qmgr_request_queue(queue_ids[port->id].chan,
2019 +                                     CHAN_QUEUE_LEN, 0, 0)))
2020 +               return err;
2021 +
2022 +       if (!(port->chan_buf = kmalloc(chan_tx_buf_len(port) +
2023 +                                      chan_tx_lists_len(port) +
2024 +                                      chan_rx_buf_len(port), GFP_KERNEL))) {
2025 +               goto release_queue;
2026 +               err = -ENOBUFS;
2027 +       }
2028 +
2029 +       port->chan_tx_buf_phys = dma_map_single(port->dev, chan_tx_buf(port),
2030 +                                               chan_tx_buf_len(port) +
2031 +                                               chan_tx_lists_len(port),
2032 +                                               DMA_TO_DEVICE);
2033 +       if (dma_mapping_error(port->chan_tx_buf_phys)) {
2034 +               err = -EIO;
2035 +               goto free;
2036 +       }
2037 +
2038 +       port->chan_rx_buf_phys = dma_map_single(port->dev, chan_rx_buf(port),
2039 +                                               chan_rx_buf_len(port),
2040 +                                               DMA_FROM_DEVICE);
2041 +       if (dma_mapping_error(port->chan_rx_buf_phys)) {
2042 +               err = -EIO;
2043 +               goto unmap_tx;
2044 +       }
2045 +
2046 +       qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY,
2047 +                    hss_chan_irq, port);
2048 +       qmgr_enable_irq(queue_ids[port->id].chan);
2049 +       hss_chan_irq(port);
2050 +       return 0;
2051 +
2052 +unmap_tx:
2053 +       dma_unmap_single(port->dev, port->chan_tx_buf_phys,
2054 +                        chan_tx_buf_len(port) + chan_tx_lists_len(port),
2055 +                        DMA_TO_DEVICE);
2056 +free:
2057 +       kfree(port->chan_buf);
2058 +       port->chan_buf = NULL;
2059 +release_queue:
2060 +       qmgr_release_queue(queue_ids[port->id].chan);
2061 +       return err;
2062 +}
2063 +
2064 +void hss_chan_stop(struct port *port)
2065 +{
2066 +       if (!port->chan_open_count && !port->hdlc_open)
2067 +               qmgr_disable_irq(queue_ids[port->id].chan);
2068 +
2069 +       hss_config_stop_chan(port);
2070 +       hss_config_set_lut(port);
2071 +       hss_config_load(port);
2072 +
2073 +       if (!port->chan_open_count && !port->hdlc_open) {
2074 +               dma_unmap_single(port->dev, port->chan_tx_buf_phys,
2075 +                                chan_tx_buf_len(port) +
2076 +                                chan_tx_lists_len(port), DMA_TO_DEVICE);
2077 +               dma_unmap_single(port->dev, port->chan_rx_buf_phys,
2078 +                                chan_rx_buf_len(port), DMA_FROM_DEVICE);
2079 +               kfree(port->chan_buf);
2080 +               port->chan_buf = NULL;
2081 +               qmgr_release_queue(queue_ids[port->id].chan);
2082 +       }
2083 +}
2084 +
2085 +static int hss_chan_open(struct inode *inode, struct file *file)
2086 +{
2087 +       struct chan_device *chan_dev = inode_to_chan_dev(inode);
2088 +       struct port *port = chan_dev->port;
2089 +       unsigned long flags;
2090 +       int i, err = 0;
2091 +
2092 +       spin_lock_irqsave(&npe_lock, flags);
2093 +
2094 +       if (chan_dev->open_count) {
2095 +               if (chan_dev->excl_open || (file->f_flags & O_EXCL))
2096 +                       err = -EBUSY;
2097 +               else
2098 +                       chan_dev->open_count++;
2099 +               goto out;
2100 +       }
2101 +
2102 +       if (port->mode == MODE_HDLC) {
2103 +               err = -ENOSYS;
2104 +               goto out;
2105 +       }
2106 +
2107 +       if (port->mode == MODE_G704 && port->channels[0] == chan_dev->id) {
2108 +               err = -EBUSY; /* channel #0 is used for G.704 signaling */
2109 +               goto out;
2110 +       }
2111 +       for (i = MAX_CHANNELS; i > port->frame_size / 8; i--)
2112 +               if (port->channels[i - 1] == chan_dev->id) {
2113 +                       err = -ECHRNG; /* frame too short */
2114 +                       goto out;
2115 +               }
2116 +
2117 +       chan_dev->rx_first = chan_dev->tx_first = 0;
2118 +       chan_dev->rx_count = chan_dev->tx_count = 0;
2119 +       clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap);
2120 +       clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap);
2121 +
2122 +       if (!port->chan_open_count && !port->hdlc_open) {
2123 +               if (port->plat->open)
2124 +                       if ((err = port->plat->open(port->id, port->netdev,
2125 +                                                   hss_hdlc_set_carrier)))
2126 +                               goto out;
2127 +               if ((err = hss_prepare_chan(port))) {
2128 +                       if (port->plat->close)
2129 +                               port->plat->close(port->id, port->netdev);
2130 +                       goto out;
2131 +               }
2132 +       }
2133 +
2134 +       hss_config_stop_chan(port);
2135 +       chan_dev->open_count++;
2136 +       port->chan_open_count++;
2137 +       chan_dev->excl_open = !!file->f_flags & O_EXCL;
2138 +
2139 +       hss_config_set_lut(port);
2140 +       hss_config_load(port);
2141 +       hss_config_start_chan(port);
2142 +out:
2143 +       spin_unlock_irqrestore(&npe_lock, flags);
2144 +       return err;
2145 +}
2146 +
2147 +static int hss_chan_release(struct inode *inode, struct file *file)
2148 +{
2149 +       struct chan_device *chan_dev = inode_to_chan_dev(inode);
2150 +       struct port *port = chan_dev->port;
2151 +       unsigned long flags;
2152 +
2153 +       spin_lock_irqsave(&npe_lock, flags);
2154 +
2155 +       if (!--chan_dev->open_count) {
2156 +               if (!--port->chan_open_count && !port->hdlc_open) {
2157 +                       hss_chan_stop(port);
2158 +                       if (port->plat->close)
2159 +                               port->plat->close(port->id, port->netdev);
2160 +               } else {
2161 +                       hss_config_stop_chan(port);
2162 +                       hss_config_set_lut(port);
2163 +                       hss_config_set_line(port); //
2164 +                       hss_config_start_chan(port);
2165 +               }
2166 +       }
2167 +
2168 +       spin_unlock_irqrestore(&npe_lock, flags);
2169 +       return 0;
2170 +}
2171 +
2172 +static ssize_t hss_chan_read(struct file *file, char __user *buf, size_t count,
2173 +                            loff_t *f_pos)
2174 +{
2175 +       struct chan_device *chan_dev = inode_to_chan_dev
2176 +               (file->f_path.dentry->d_inode);
2177 +       struct port *port = chan_dev->port;
2178 +       unsigned long flags;
2179 +       u8 *rx_buf;
2180 +       int res = 0, loops = 0;
2181 +
2182 +       spin_lock_irqsave(&npe_lock, flags);
2183 +
2184 +       while (1) {
2185 +               int prev_irq = atomic_read(&port->chan_rx_irq_number);
2186 +#if 0
2187 +               if (test_and_clear_bit(RX_ERROR_BIT, &chan_dev->errors_bitmap)
2188 +                   || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
2189 +                       res = -EIO;
2190 +                       goto out;
2191 +               }
2192 +#endif
2193 +               if (count == 0)
2194 +                       goto out;       /* no need to wait */
2195 +
2196 +               if (chan_dev->rx_count)
2197 +                       break;
2198 +
2199 +               spin_unlock_irqrestore(&npe_lock, flags);
2200 +               loops++;
2201 +               if ((res = wait_event_interruptible
2202 +                    (port->chan_rx_waitq,
2203 +                     atomic_read(&port->chan_rx_irq_number) != prev_irq)))
2204 +                       goto out;
2205 +               spin_lock_irqsave(&npe_lock, flags);
2206 +               continue;
2207 +       }
2208 +
2209 +       dma_sync_single(port->dev, port->chan_rx_buf_phys,
2210 +                       chan_rx_buf_len(port), DMA_FROM_DEVICE);
2211 +
2212 +#if 0
2213 +       if (loops > 1)
2214 +               printk(KERN_DEBUG "ENTRY rx_first %u rx_count %u count %i"
2215 +                      " last_rx %u loops %i\n", chan_dev->rx_first,
2216 +                      chan_dev->rx_count, count, port->chan_last_rx, loops);
2217 +#endif
2218 +       rx_buf = chan_rx_buf(port);
2219 +       while (chan_dev->rx_count > 0 && res < count) {
2220 +               unsigned int chan = chan_dev->rx_first % chan_dev->chan_count;
2221 +               unsigned int frame = chan_dev->rx_first / chan_dev->chan_count;
2222 +
2223 +               chan = chan_dev->log_channels[chan];
2224 +               if (put_user(rx_buf[chan * CHAN_RX_FRAMES + frame], buf++)) {
2225 +                       res = -EFAULT;
2226 +                       goto out;
2227 +               }
2228 +               chan_dev->rx_first++;
2229 +               chan_dev->rx_first %= CHAN_RX_FRAMES * chan_dev->chan_count;
2230 +               chan_dev->rx_count--;
2231 +               res++;
2232 +       }
2233 +out:
2234 +#if 0
2235 +       printk(KERN_DEBUG "EXIT  rx_first %u rx_count %u res %i\n",
2236 +              chan_dev->rx_first, chan_dev->rx_count, res);
2237 +#endif
2238 +       spin_unlock_irqrestore(&npe_lock, flags);
2239 +       return res;
2240 +}
2241 +
2242 +static ssize_t hss_chan_write(struct file *file, const char __user *buf,
2243 +                             size_t count, loff_t *f_pos)
2244 +{
2245 +       struct chan_device *chan_dev = inode_to_chan_dev
2246 +               (file->f_path.dentry->d_inode);
2247 +       struct port *port = chan_dev->port;
2248 +       unsigned long flags;
2249 +       u8 *tx_buf;
2250 +       int res = 0, loops = 0;
2251 +
2252 +       spin_lock_irqsave(&npe_lock, flags);
2253 +       while (1) {
2254 +               int prev_irq = atomic_read(&port->chan_tx_irq_number);
2255 +#if 0
2256 +               if (test_and_clear_bit(TX_ERROR_BIT, &chan_dev->errors_bitmap)
2257 +                   || (port->mode == G704 && port->aligned == NOT_ALIGNED)) {
2258 +                       res = -EIO;
2259 +                       goto out;
2260 +               }
2261 +#endif
2262 +               if (count == 0)
2263 +                       goto out;       /* no need to wait */
2264 +
2265 +               if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
2266 +                       break;
2267 +
2268 +               spin_unlock_irqrestore(&npe_lock, flags);
2269 +               loops++;
2270 +               if ((res = wait_event_interruptible
2271 +                    (port->chan_tx_waitq,
2272 +                     atomic_read (&port->chan_tx_irq_number) != prev_irq)))
2273 +                       goto out;
2274 +               spin_lock_irqsave(&npe_lock, flags);
2275 +               continue;
2276 +       }
2277 +
2278 +#if 0
2279 +       if (loops > 1)
2280 +               printk(KERN_DEBUG "ENTRY TX_first %u tx_count %u count %i"
2281 +                      " last_tx %u loops %i\n", chan_dev->tx_first,
2282 +                      chan_dev->tx_count, count, port->chan_last_tx, loops);
2283 +#endif
2284 +       tx_buf = chan_tx_buf(port);
2285 +       while (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count &&
2286 +              res < count) {
2287 +               unsigned int tail, chan, frame;
2288 +
2289 +               tail = (chan_dev->tx_first + chan_dev->tx_count) %
2290 +                       (CHAN_TX_FRAMES * chan_dev->chan_count);
2291 +               chan = tail % chan_dev->chan_count;
2292 +               frame = tail / chan_dev->chan_count;
2293 +               chan = chan_dev->log_channels[chan];
2294 +
2295 +               if (get_user(tx_buf[chan * CHAN_TX_FRAMES + frame], buf++)) {
2296 +                       printk(KERN_DEBUG "BUG? TX %u %u %u\n",
2297 +                              tail, chan, frame);
2298 +                       res = -EFAULT;
2299 +                       goto out_sync;
2300 +               }
2301 +               chan_dev->tx_count++;
2302 +               res++;
2303 +       }
2304 +out_sync:
2305 +       dma_sync_single(port->dev, port->chan_tx_buf_phys,
2306 +                       chan_tx_buf_len(port), DMA_TO_DEVICE);
2307 +out:
2308 +#if 0
2309 +       printk(KERN_DEBUG "EXIT  TX_first %u tx_count %u res %i\n",
2310 +              chan_dev->tx_first, chan_dev->tx_count, res);
2311 +#endif
2312 +       spin_unlock_irqrestore(&npe_lock, flags);
2313 +       return res;
2314 +}
2315 +
2316 +
2317 +static unsigned int hss_chan_poll(struct file *file, poll_table *wait)
2318 +{
2319 +       struct chan_device *chan_dev = inode_to_chan_dev
2320 +               (file->f_path.dentry->d_inode);
2321 +       struct port *port = chan_dev->port;
2322 +       unsigned long flags;
2323 +       unsigned int mask = 0;
2324 +
2325 +       spin_lock_irqsave(&npe_lock, flags);
2326 +       poll_wait(file, &port->chan_tx_waitq, wait);
2327 +       poll_wait(file, &port->chan_rx_waitq, wait);
2328 +
2329 +       if (chan_dev->tx_count < CHAN_TX_FRAMES * chan_dev->chan_count)
2330 +               mask |= POLLOUT | POLLWRNORM;
2331 +       if (chan_dev->rx_count)
2332 +               mask |= POLLIN | POLLRDNORM;
2333 +       spin_unlock_irqrestore(&npe_lock, flags);
2334 +       return mask;
2335 +}
2336 +
2337 +/*****************************************************************************
2338 + * channelized device sysfs attributes
2339 + ****************************************************************************/
2340 +
2341 +static ssize_t chan_show_chan(struct device *dev, struct device_attribute *attr,
2342 +                             char *buf)
2343 +{
2344 +       struct chan_device *chan_dev = dev_get_drvdata(dev);
2345 +
2346 +       return print_channels(chan_dev->port, buf, chan_dev->id);
2347 +}
2348 +
2349 +static ssize_t chan_set_chan(struct device *dev, struct device_attribute *attr,
2350 +                            const char *buf, size_t len)
2351 +{
2352 +       struct chan_device *chan_dev = dev_get_drvdata(dev);
2353 +       struct port *port = chan_dev->port;
2354 +       unsigned long flags;
2355 +       unsigned int ch;
2356 +       size_t orig_len = len;
2357 +       int err;
2358 +
2359 +       if (len && buf[len - 1] == '\n')
2360 +               len--;
2361 +
2362 +       if (len != 7 || memcmp(buf, "destroy", 7))
2363 +               return -EINVAL;
2364 +
2365 +       spin_lock_irqsave(&npe_lock, flags);
2366 +       cdev_del(&chan_dev->cdev);
2367 +
2368 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2369 +               if (port->channels[ch] == chan_dev->id)
2370 +                       port->channels[ch] = CHANNEL_UNUSED;
2371 +       port->chan_devices[chan_dev->id] = NULL;
2372 +       kfree(chan_dev);
2373 +       spin_unlock_irqrestore(&npe_lock, flags);
2374 +
2375 +       if ((err = device_schedule_callback(dev, device_unregister)))
2376 +               return err;
2377 +       return orig_len;
2378 +}
2379 +
2380 +static struct device_attribute chan_attr =
2381 +       __ATTR(channels, 0644, chan_show_chan, chan_set_chan);
2382 +
2383 +/*****************************************************************************
2384 + * main sysfs attributes
2385 + ****************************************************************************/
2386 +
2387 +static const struct file_operations chan_fops = {
2388 +       .owner   = THIS_MODULE,
2389 +       .llseek  = no_llseek,
2390 +       .read    = hss_chan_read,
2391 +       .write   = hss_chan_write,
2392 +       .poll    = hss_chan_poll,
2393 +       .open    = hss_chan_open,
2394 +       .release = hss_chan_release,
2395 +};
2396 +
2397 +static ssize_t create_chan(struct device *dev, struct device_attribute *attr,
2398 +                          const char *buf, size_t len)
2399 +{
2400 +       struct port *port = dev_get_drvdata(dev);
2401 +       struct chan_device *chan_dev;
2402 +       u8 channels[MAX_CHANNELS];
2403 +       size_t orig_len = len;
2404 +       unsigned long flags;
2405 +       unsigned int ch, id;
2406 +       int minor, err;
2407 +
2408 +       if ((err = parse_channels(&buf, &len, channels)) < 1)
2409 +               return err;
2410 +
2411 +       if (!(chan_dev = kzalloc(sizeof(struct chan_device), GFP_KERNEL)))
2412 +               return -ENOBUFS;
2413 +
2414 +       spin_lock_irqsave(&npe_lock, flags);
2415 +
2416 +       if (port->mode != MODE_RAW && port->mode != MODE_G704) {
2417 +               err = -EINVAL;
2418 +               goto free;
2419 +       }
2420 +
2421 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2422 +               if (channels[ch] && port->channels[ch] != CHANNEL_UNUSED) {
2423 +                       printk(KERN_DEBUG "Channel #%i already in use\n", ch);
2424 +                       err = -EBUSY;
2425 +                       goto free;
2426 +               }
2427 +
2428 +       for (id = 0; id < MAX_CHAN_DEVICES; id++)
2429 +               if (port->chan_devices[id] == NULL)
2430 +                       break;
2431 +
2432 +       if (id == MAX_CHAN_DEVICES) {
2433 +               err = -EBUSY;
2434 +               goto free;
2435 +       }
2436 +
2437 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2438 +               if (channels[ch])
2439 +                       break;
2440 +
2441 +       minor = port->id * MAX_CHAN_DEVICES + ch;
2442 +       chan_dev->id = id;
2443 +       chan_dev->port = port;
2444 +       chan_dev->dev = device_create(hss_class, dev, MKDEV(chan_major, minor),
2445 +                                     "hss%uch%u", port->id, ch);
2446 +       if (IS_ERR(chan_dev->dev)) {
2447 +               err = PTR_ERR(chan_dev->dev);
2448 +               goto free;
2449 +       }
2450 +
2451 +       cdev_init(&chan_dev->cdev, &chan_fops);
2452 +       chan_dev->cdev.owner = THIS_MODULE;
2453 +       if ((err = cdev_add(&chan_dev->cdev, MKDEV(chan_major, minor), 1)))
2454 +               goto destroy_device;
2455 +
2456 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2457 +               if (channels[ch])
2458 +                       port->channels[ch] = id;
2459 +       port->chan_devices[id] = chan_dev;
2460 +       dev_set_drvdata(chan_dev->dev, chan_dev);
2461 +       BUG_ON(device_create_file(chan_dev->dev, &chan_attr));
2462 +
2463 +       spin_unlock_irqrestore(&npe_lock, flags);
2464 +       return orig_len;
2465 +
2466 +destroy_device:
2467 +       device_unregister(chan_dev->dev);
2468 +free:
2469 +       kfree(chan_dev);
2470 +       spin_unlock_irqrestore(&npe_lock, flags);
2471 +       return err;
2472 +}
2473 +
2474 +static ssize_t show_hdlc_chan(struct device *dev, struct device_attribute *attr,
2475 +                             char *buf)
2476 +{
2477 +       return print_channels(dev_get_drvdata(dev), buf, CHANNEL_HDLC);
2478 +}
2479 +
2480 +static ssize_t set_hdlc_chan(struct device *dev, struct device_attribute *attr,
2481 +                            const char *buf, size_t len)
2482 +{
2483 +       struct port *port = dev_get_drvdata(dev);
2484 +       u8 channels[MAX_CHANNELS];
2485 +       size_t orig_len = len;
2486 +       unsigned long flags;
2487 +       unsigned int ch;
2488 +       int err;
2489 +
2490 +       if ((err = parse_channels(&buf, &len, channels)) < 0)
2491 +               return err;
2492 +
2493 +       spin_lock_irqsave(&npe_lock, flags);
2494 +
2495 +       if (port->mode != MODE_RAW && port->mode != MODE_G704) {
2496 +               err = -EINVAL;
2497 +               goto err;
2498 +       }
2499 +
2500 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2501 +               if (channels[ch] &&
2502 +                   port->channels[ch] != CHANNEL_UNUSED &&
2503 +                   port->channels[ch] != CHANNEL_HDLC) {
2504 +                       printk(KERN_DEBUG "Channel #%i already in use\n", ch);
2505 +                       err = -EBUSY;
2506 +                       goto err;
2507 +               }
2508 +
2509 +       for (ch = 0; ch < MAX_CHANNELS; ch++)
2510 +               if (channels[ch])
2511 +                       port->channels[ch] = CHANNEL_HDLC;
2512 +               else if (port->channels[ch] == CHANNEL_HDLC)
2513 +                       port->channels[ch] = CHANNEL_UNUSED;
2514 +
2515 +       if (port->chan_open_count || port->hdlc_open) {
2516 +               hss_config_set_lut(port);
2517 +               hss_config_load(port);
2518 +       }
2519 +
2520 +       spin_unlock_irqrestore(&npe_lock, flags);
2521 +       return orig_len;
2522 +
2523 +err:
2524 +       spin_unlock_irqrestore(&npe_lock, flags);
2525 +       return err;
2526 +}
2527 +
2528 +static ssize_t show_clock_type(struct device *dev,
2529 +                              struct device_attribute *attr, char *buf)
2530 +{
2531 +       struct port *port = dev_get_drvdata(dev);
2532 +
2533 +       strcpy(buf, port->clock_type == CLOCK_INT ? "int\n" : "ext\n");
2534 +       return 5;
2535 +}
2536 +
2537 +static ssize_t set_clock_type(struct device *dev, struct device_attribute *attr,
2538 +                             const char *buf, size_t len)
2539 +{
2540 +       struct port *port = dev_get_drvdata(dev);
2541 +       size_t orig_len = len;
2542 +       unsigned long flags;
2543 +       unsigned int clk, err;
2544 +
2545 +       if (len && buf[len - 1] == '\n')
2546 +               len--;
2547 +
2548 +       if (len != 3)
2549 +               return -EINVAL;
2550 +       if (!memcmp(buf, "ext", 3))
2551 +               clk = CLOCK_EXT;
2552 +       else if (!memcmp(buf, "int", 3))
2553 +               clk = CLOCK_INT;
2554 +       else
2555 +               return -EINVAL;
2556 +
2557 +       spin_lock_irqsave(&npe_lock, flags);
2558 +       if (port->plat->set_clock)
2559 +               clk = port->plat->set_clock(port->id, clk);
2560 +       if (clk != CLOCK_EXT && clk != CLOCK_INT) {
2561 +               err = -EINVAL; /* plat->set_clock shouldn't change the state */
2562 +               goto err;
2563 +       }
2564 +       port->clock_type = clk;
2565 +       if (port->chan_open_count || port->hdlc_open) {
2566 +               hss_config_set_line(port);
2567 +               hss_config_load(port);
2568 +       }
2569 +       spin_unlock_irqrestore(&npe_lock, flags);
2570 +
2571 +       return orig_len;
2572 +err:
2573 +       spin_unlock_irqrestore(&npe_lock, flags);
2574 +       return err;
2575 +}
2576 +
2577 +static ssize_t show_clock_rate(struct device *dev,
2578 +                              struct device_attribute *attr, char *buf)
2579 +{
2580 +       struct port *port = dev_get_drvdata(dev);
2581 +
2582 +       sprintf(buf, "%u\n", port->clock_rate);
2583 +       return strlen(buf) + 1;
2584 +}
2585 +
2586 +static ssize_t set_clock_rate(struct device *dev, struct device_attribute *attr,
2587 +                             const char *buf, size_t len)
2588 +{
2589 +#if 0
2590 +       struct port *port = dev_get_drvdata(dev);
2591 +       size_t orig_len = len;
2592 +       unsigned long flags;
2593 +       unsigned int rate;
2594 +
2595 +       if (len && buf[len - 1] == '\n')
2596 +               len--;
2597 +
2598 +       if (get_number(&buf, &len, &rate, 1, 0xFFFFFFFFu))
2599 +               return -EINVAL;
2600 +       if (len)
2601 +               return -EINVAL;
2602 +
2603 +       spin_lock_irqsave(&npe_lock, flags);
2604 +       port->clock_rate = rate;
2605 +       spin_unlock_irqrestore(&npe_lock, flags);
2606 +       return orig_len;
2607 +#endif
2608 +       return -EINVAL; /* FIXME not yet supported */
2609 +}
2610 +
2611 +static ssize_t show_frame_size(struct device *dev,
2612 +                              struct device_attribute *attr, char *buf)
2613 +{
2614 +       struct port *port = dev_get_drvdata(dev);
2615 +
2616 +       if (port->mode != MODE_RAW && port->mode != MODE_G704)
2617 +               return -EINVAL;
2618 +
2619 +       sprintf(buf, "%u\n", port->frame_size);
2620 +       return strlen(buf) + 1;
2621 +}
2622 +
2623 +static ssize_t set_frame_size(struct device *dev, struct device_attribute *attr,
2624 +                             const char *buf, size_t len)
2625 +{
2626 +       struct port *port = dev_get_drvdata(dev);
2627 +       size_t ret = len;
2628 +       unsigned long flags;
2629 +       unsigned int size;
2630 +
2631 +       if (len && buf[len - 1] == '\n')
2632 +               len--;
2633 +
2634 +       if (get_number(&buf, &len, &size, MIN_FRAME_SIZE, MAX_FRAME_SIZE))
2635 +               return -EINVAL;
2636 +       if (len || size % 8 > 1)
2637 +               return -EINVAL;
2638 +
2639 +       spin_lock_irqsave(&npe_lock, flags);
2640 +       if (port->mode != MODE_RAW && port->mode != MODE_G704)
2641 +               ret = -EINVAL;
2642 +       else if (!port->chan_open_count && !port->hdlc_open)
2643 +               ret = -EBUSY;
2644 +       else {
2645 +               port->frame_size = size;
2646 +               port->frame_sync_offset = 0;
2647 +       }
2648 +       spin_unlock_irqrestore(&npe_lock, flags);
2649 +       return ret;
2650 +}
2651 +
2652 +static ssize_t show_frame_offset(struct device *dev,
2653 +                                struct device_attribute *attr, char *buf)
2654 +{
2655 +       struct port *port = dev_get_drvdata(dev);
2656 +
2657 +       sprintf(buf, "%u\n", port->frame_sync_offset);
2658 +       return strlen(buf) + 1;
2659 +}
2660 +
2661 +static ssize_t set_frame_offset(struct device *dev,
2662 +                               struct device_attribute *attr,
2663 +                               const char *buf, size_t len)
2664 +{
2665 +       struct port *port = dev_get_drvdata(dev);
2666 +       size_t orig_len = len;
2667 +       unsigned long flags;
2668 +       unsigned int offset;
2669 +
2670 +       if (len && buf[len - 1] == '\n')
2671 +               len--;
2672 +
2673 +       if (get_number(&buf, &len, &offset, 0, port->frame_size - 1))
2674 +               return -EINVAL;
2675 +       if (len)
2676 +               return -EINVAL;
2677 +
2678 +       spin_lock_irqsave(&npe_lock, flags);
2679 +
2680 +       port->frame_sync_offset = offset;
2681 +       if (port->chan_open_count || port->hdlc_open) {
2682 +               hss_config_set_rx_frame(port);
2683 +               hss_config_load(port);
2684 +       }
2685 +
2686 +       spin_unlock_irqrestore(&npe_lock, flags);
2687 +       return orig_len;
2688 +}
2689 +
2690 +static ssize_t show_loopback(struct device *dev, struct device_attribute *attr,
2691 +                            char *buf)
2692 +{
2693 +       struct port *port = dev_get_drvdata(dev);
2694 +
2695 +       sprintf(buf, "%u\n", port->loopback);
2696 +       return strlen(buf) + 1;
2697 +}
2698 +
2699 +static ssize_t set_loopback(struct device *dev, struct device_attribute *attr,
2700 +                           const char *buf, size_t len)
2701 +{
2702 +       struct port *port = dev_get_drvdata(dev);
2703 +       size_t orig_len = len;
2704 +       unsigned long flags;
2705 +       unsigned int lb;
2706 +
2707 +       if (len && buf[len - 1] == '\n')
2708 +               len--;
2709 +
2710 +       if (get_number(&buf, &len, &lb, 0, 1))
2711 +               return -EINVAL;
2712 +       if (len)
2713 +               return -EINVAL;
2714 +
2715 +       spin_lock_irqsave(&npe_lock, flags);
2716 +
2717 +       if (port->loopback != lb) {
2718 +               port->loopback = lb;
2719 +               if (port->chan_open_count || port->hdlc_open) {
2720 +                       hss_config_set_core(port);
2721 +                       hss_config_load(port);
2722 +               }
2723 +               if (port->loopback || port->carrier)
2724 +                       netif_carrier_on(port->netdev);
2725 +               else
2726 +                       netif_carrier_off(port->netdev);
2727 +       }
2728 +
2729 +       spin_unlock_irqrestore(&npe_lock, flags);
2730 +       return orig_len;
2731 +}
2732 +
2733 +static ssize_t show_mode(struct device *dev, struct device_attribute *attr,
2734 +                        char *buf)
2735 +{
2736 +       struct port *port = dev_get_drvdata(dev);
2737 +
2738 +       switch(port->mode) {
2739 +       case MODE_RAW:
2740 +               strcpy(buf, "raw\n");
2741 +               break;
2742 +       case MODE_G704:
2743 +               strcpy(buf, "g704\n");
2744 +               break;
2745 +       default:
2746 +               strcpy(buf, "hdlc\n");
2747 +               break;
2748 +       }
2749 +       return strlen(buf) + 1;
2750 +}
2751 +
2752 +static ssize_t set_mode(struct device *dev, struct device_attribute *attr,
2753 +                       const char *buf, size_t len)
2754 +{
2755 +       struct port *port = dev_get_drvdata(dev);
2756 +       size_t ret = len;
2757 +       unsigned long flags;
2758 +
2759 +       if (len && buf[len - 1] == '\n')
2760 +               len--;
2761 +
2762 +       spin_lock_irqsave(&npe_lock, flags);
2763 +
2764 +       if (port->chan_open_count || port->hdlc_open) {
2765 +               ret = -EBUSY;
2766 +       } else if (len == 4 && !memcmp(buf, "hdlc", 4))
2767 +               port->mode = MODE_HDLC;
2768 +       else if (len == 3 && !memcmp(buf, "raw", 3))
2769 +               port->mode = MODE_RAW;
2770 +       else if (len == 4 && !memcmp(buf, "g704", 4))
2771 +               port->mode = MODE_G704;
2772 +       else
2773 +               ret = -EINVAL;
2774 +
2775 +       spin_unlock_irqrestore(&npe_lock, flags);
2776 +       return ret;
2777 +}
2778 +
2779 +static struct device_attribute hss_attrs[] = {
2780 +       __ATTR(create_chan, 0200, NULL, create_chan),
2781 +       __ATTR(hdlc_chan, 0644, show_hdlc_chan, set_hdlc_chan),
2782 +       __ATTR(clock_type, 0644, show_clock_type, set_clock_type),
2783 +       __ATTR(clock_rate, 0644, show_clock_rate, set_clock_rate),
2784 +       __ATTR(frame_size, 0644, show_frame_size, set_frame_size),
2785 +       __ATTR(frame_offset, 0644, show_frame_offset, set_frame_offset),
2786 +       __ATTR(loopback, 0644, show_loopback, set_loopback),
2787 +       __ATTR(mode, 0644, show_mode, set_mode),
2788 +};
2789 +
2790 +/*****************************************************************************
2791 + * initialization
2792 + ****************************************************************************/
2793 +
2794 +static int __devinit hss_init_one(struct platform_device *pdev)
2795 +{
2796 +       struct port *port;
2797 +       struct net_device *dev;
2798 +       hdlc_device *hdlc;
2799 +       int i, err;
2800 +
2801 +       if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
2802 +               return -ENOMEM;
2803 +       platform_set_drvdata(pdev, port);
2804 +       port->id = pdev->id;
2805 +
2806 +       if ((port->npe = npe_request(0)) == NULL) {
2807 +               err = -ENOSYS;
2808 +               goto err_free;
2809 +       }
2810 +
2811 +       port->dev = &pdev->dev;
2812 +       port->plat = pdev->dev.platform_data;
2813 +       if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
2814 +               err = -ENOMEM;
2815 +               goto err_plat;
2816 +       }
2817 +
2818 +       SET_NETDEV_DEV(dev, &pdev->dev);
2819 +       hdlc = dev_to_hdlc(dev);
2820 +       hdlc->attach = hss_hdlc_attach;
2821 +       hdlc->xmit = hss_hdlc_xmit;
2822 +       dev->open = hss_hdlc_open;
2823 +       dev->stop = hss_hdlc_close;
2824 +       dev->do_ioctl = hss_hdlc_ioctl;
2825 +       dev->tx_queue_len = 100;
2826 +       port->clock_type = CLOCK_EXT;
2827 +       port->clock_rate = 2048000;
2828 +       port->frame_size = 256; /* E1 */
2829 +       memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels));
2830 +       init_waitqueue_head(&port->chan_tx_waitq);
2831 +       init_waitqueue_head(&port->chan_rx_waitq);
2832 +       netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
2833 +
2834 +       if ((err = register_hdlc_device(dev))) /* HDLC mode by default */
2835 +               goto err_free_netdev;
2836 +
2837 +       for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
2838 +               BUG_ON(device_create_file(port->dev, &hss_attrs[i]));
2839 +
2840 +       printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
2841 +       return 0;
2842 +
2843 +err_free_netdev:
2844 +       free_netdev(dev);
2845 +err_plat:
2846 +       npe_release(port->npe);
2847 +       platform_set_drvdata(pdev, NULL);
2848 +err_free:
2849 +       kfree(port);
2850 +       return err;
2851 +}
2852 +
2853 +static int __devexit hss_remove_one(struct platform_device *pdev)
2854 +{
2855 +       struct port *port = platform_get_drvdata(pdev);
2856 +       int i;
2857 +
2858 +       for (i = 0; i < ARRAY_SIZE(hss_attrs); i++)
2859 +               device_remove_file(port->dev, &hss_attrs[i]);
2860 +
2861 +       unregister_hdlc_device(port->netdev);
2862 +       free_netdev(port->netdev);
2863 +       npe_release(port->npe);
2864 +       platform_set_drvdata(pdev, NULL);
2865 +       kfree(port);
2866 +       return 0;
2867 +}
2868 +
2869 +static struct platform_driver drv = {
2870 +       .driver.name    = DRV_NAME,
2871 +       .probe          = hss_init_one,
2872 +       .remove         = hss_remove_one,
2873 +};
2874 +
2875 +static int __init hss_init_module(void)
2876 +{
2877 +       int err;
2878 +       dev_t rdev;
2879 +
2880 +       if ((ixp4xx_read_feature_bits() &
2881 +            (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
2882 +           (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
2883 +               return -ENOSYS;
2884 +
2885 +       if ((err = alloc_chrdev_region(&rdev, 0, HSS_COUNT * MAX_CHAN_DEVICES,
2886 +                                      "hss")))
2887 +               return err;
2888 +
2889 +       spin_lock_init(&npe_lock);
2890 +
2891 +       if (IS_ERR(hss_class = class_create(THIS_MODULE, "hss"))) {
2892 +               printk(KERN_ERR "Can't register device class 'hss'\n");
2893 +               err = PTR_ERR(hss_class);
2894 +               goto free_chrdev;
2895 +       }
2896 +       if ((err = platform_driver_register(&drv)))
2897 +               goto destroy_class;
2898 +
2899 +       chan_major = MAJOR(rdev);
2900 +       return 0;
2901 +
2902 +destroy_class:
2903 +       class_destroy(hss_class);
2904 +free_chrdev:
2905 +       unregister_chrdev_region(MKDEV(chan_major, 0),
2906 +                                HSS_COUNT * MAX_CHAN_DEVICES);
2907 +       return err;
2908 +}
2909 +
2910 +static void __exit hss_cleanup_module(void)
2911 +{
2912 +       platform_driver_unregister(&drv);
2913 +       class_destroy(hss_class);
2914 +       unregister_chrdev_region(MKDEV(chan_major, 0),
2915 +                                HSS_COUNT * MAX_CHAN_DEVICES);
2916 +}
2917 +
2918 +MODULE_AUTHOR("Krzysztof Halasa");
2919 +MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
2920 +MODULE_LICENSE("GPL v2");
2921 +MODULE_ALIAS("platform:ixp4xx_hss");
2922 +module_init(hss_init_module);
2923 +module_exit(hss_cleanup_module);