sync ixp4xx related patches with 2.6.24 and upgrade to 2.6.25
[openwrt.git] / target / linux / ixp4xx / patches-2.6.25 / 190-cambria_support.patch
1 diff -Nur linux-2.6.24.5/arch/arm/mach-ixp4xx/Kconfig linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/Kconfig
2 --- linux-2.6.24.5/arch/arm/mach-ixp4xx/Kconfig 2008-04-28 20:22:27.000000000 +0200
3 +++ linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/Kconfig    2008-04-28 20:26:44.000000000 +0200
4 @@ -25,6 +25,14 @@
5           Avila Network Platform. For more information on this platform,
6           see <file:Documentation/arm/IXP4xx>.
7  
8 +config MACH_CAMBRIA
9 +       bool "Cambria"
10 +       select PCI
11 +       help
12 +         Say 'Y' here if you want your kernel to support the Gateworks
13 +         Cambria series. For more information on this platform,
14 +         see <file:Documentation/arm/IXP4xx>.
15 +
16  config MACH_LOFT
17      bool "Loft"
18      depends on MACH_AVILA
19 @@ -200,7 +208,7 @@
20  
21  config CPU_IXP43X
22         bool
23 -       depends on MACH_KIXRP435
24 +       depends on MACH_KIXRP435 || MACH_CAMBRIA
25         default y
26  
27  config MACH_GTWX5715
28 diff -Nur linux-2.6.24.5/arch/arm/mach-ixp4xx/Makefile linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/Makefile
29 --- linux-2.6.24.5/arch/arm/mach-ixp4xx/Makefile        2008-04-28 20:22:27.000000000 +0200
30 +++ linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/Makefile   2008-04-28 20:26:44.000000000 +0200
31 @@ -7,6 +7,7 @@
32  
33  obj-pci-$(CONFIG_ARCH_IXDP4XX)         += ixdp425-pci.o
34  obj-pci-$(CONFIG_MACH_AVILA)           += avila-pci.o
35 +obj-pci-$(CONFIG_MACH_CAMBRIA)         += cambria-pci.o
36  obj-pci-$(CONFIG_MACH_IXDPG425)                += ixdpg425-pci.o
37  obj-pci-$(CONFIG_ARCH_ADI_COYOTE)      += coyote-pci.o
38  obj-pci-$(CONFIG_MACH_GTWX5715)                += gtwx5715-pci.o
39 @@ -28,6 +29,7 @@
40  
41  obj-$(CONFIG_ARCH_IXDP4XX)     += ixdp425-setup.o
42  obj-$(CONFIG_MACH_AVILA)       += avila-setup.o
43 +obj-$(CONFIG_MACH_CAMBRIA)     += cambria-setup.o
44  obj-$(CONFIG_MACH_IXDPG425)    += coyote-setup.o
45  obj-$(CONFIG_ARCH_ADI_COYOTE)  += coyote-setup.o
46  obj-$(CONFIG_MACH_GTWX5715)    += gtwx5715-setup.o
47 diff -Nur linux-2.6.24.5/arch/arm/mach-ixp4xx/cambria-pci.c linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/cambria-pci.c
48 --- linux-2.6.24.5/arch/arm/mach-ixp4xx/cambria-pci.c   1970-01-01 01:00:00.000000000 +0100
49 +++ linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/cambria-pci.c      2008-04-28 20:30:35.000000000 +0200
50 @@ -0,0 +1,74 @@
51 +/*
52 + * arch/arch/mach-ixp4xx/cambria-pci.c
53 + *
54 + * PCI setup routines for Gateworks Cambria series
55 + *
56 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
57 + *
58 + * based on coyote-pci.c:
59 + *     Copyright (C) 2002 Jungo Software Technologies.
60 + *     Copyright (C) 2003 MontaVista Softwrae, Inc.
61 + *
62 + * Maintainer: Imre Kaloz <kaloz@openwrt.org>
63 + *
64 + * This program is free software; you can redistribute it and/or modify
65 + * it under the terms of the GNU General Public License version 2 as
66 + * published by the Free Software Foundation.
67 + *
68 + */
69 +
70 +#include <linux/kernel.h>
71 +#include <linux/pci.h>
72 +#include <linux/init.h>
73 +#include <linux/irq.h>
74 +
75 +#include <asm/mach-types.h>
76 +#include <asm/hardware.h>
77 +#include <asm/irq.h>
78 +
79 +#include <asm/mach/pci.h>
80 +
81 +extern void ixp4xx_pci_preinit(void);
82 +extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
83 +extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
84 +
85 +void __init cambria_pci_preinit(void)
86 +{
87 +       set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW);
88 +       set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW);
89 +       set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW);
90 +       set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW);
91 +
92 +       ixp4xx_pci_preinit();
93 +}
94 +
95 +static int __init cambria_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
96 +{
97 +       if (slot == 1)
98 +               return IRQ_IXP4XX_GPIO11;
99 +       else if (slot == 2)
100 +               return IRQ_IXP4XX_GPIO10;
101 +       else if (slot == 3)
102 +               return IRQ_IXP4XX_GPIO9;
103 +       else if (slot == 4)
104 +               return IRQ_IXP4XX_GPIO8;
105 +       else return -1;
106 +}
107 +
108 +struct hw_pci cambria_pci __initdata = {
109 +       .nr_controllers = 1,
110 +       .preinit =        cambria_pci_preinit,
111 +       .swizzle =        pci_std_swizzle,
112 +       .setup =          ixp4xx_setup,
113 +       .scan =           ixp4xx_scan_bus,
114 +       .map_irq =        cambria_map_irq,
115 +};
116 +
117 +int __init cambria_pci_init(void)
118 +{
119 +       if (machine_is_cambria())
120 +               pci_common_init(&cambria_pci);
121 +       return 0;
122 +}
123 +
124 +subsys_initcall(cambria_pci_init);
125 diff -Nur linux-2.6.24.5/arch/arm/mach-ixp4xx/cambria-setup.c linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/cambria-setup.c
126 --- linux-2.6.24.5/arch/arm/mach-ixp4xx/cambria-setup.c 1970-01-01 01:00:00.000000000 +0100
127 +++ linux-2.6.24.5-owrt/arch/arm/mach-ixp4xx/cambria-setup.c    2008-04-28 21:07:16.000000000 +0200
128 @@ -0,0 +1,250 @@
129 +/*
130 + * arch/arm/mach-ixp4xx/cambria-setup.c
131 + *
132 + * Board setup for the Gateworks Cambria series
133 + *
134 + * Copyright (C) 2008 Imre Kaloz <Kaloz@openwrt.org>
135 + *
136 + * based on coyote-setup.c:
137 + *      Copyright (C) 2003-2005 MontaVista Software, Inc.
138 + *
139 + * Author: Imre Kaloz <Kaloz@openwrt.org>
140 + */
141 +
142 +#include <linux/kernel.h>
143 +#include <linux/init.h>
144 +#include <linux/device.h>
145 +#include <linux/if_ether.h>
146 +#include <linux/socket.h>
147 +#include <linux/netdevice.h>
148 +#include <linux/serial.h>
149 +#include <linux/tty.h>
150 +#include <linux/serial_8250.h>
151 +#include <linux/slab.h>
152 +#ifdef CONFIG_SENSORS_EEPROM
153 +# include <linux/i2c.h>
154 +# include <linux/eeprom.h>
155 +#endif
156 +                                                                                
157 +#include <linux/i2c-gpio.h>
158 +#include <asm/types.h>
159 +#include <asm/setup.h>
160 +#include <asm/memory.h>
161 +#include <asm/hardware.h>
162 +#include <asm/irq.h>
163 +#include <asm/mach-types.h>
164 +#include <asm/mach/arch.h>
165 +#include <asm/mach/flash.h>
166 +
167 +static struct flash_platform_data cambria_flash_data = {
168 +       .map_name       = "cfi_probe",
169 +       .width          = 2,
170 +};
171 +
172 +static struct resource cambria_flash_resource = {
173 +       .flags          = IORESOURCE_MEM,
174 +};
175 +
176 +static struct platform_device cambria_flash = {
177 +       .name           = "IXP4XX-Flash",
178 +       .id             = 0,
179 +       .dev            = {
180 +               .platform_data = &cambria_flash_data,
181 +       },
182 +       .num_resources  = 1,
183 +       .resource       = &cambria_flash_resource,
184 +};
185 +
186 +static struct i2c_gpio_platform_data cambria_i2c_gpio_data = {
187 +       .sda_pin        = 7,
188 +       .scl_pin        = 6,
189 +};
190 +
191 +static struct platform_device cambria_i2c_gpio = {
192 +       .name           = "i2c-gpio",
193 +       .id             = 0,
194 +       .dev            = {
195 +               .platform_data  = &cambria_i2c_gpio_data,
196 +       },
197 +};
198 +
199 +static struct resource cambria_uart_resource = {
200 +       .start  = IXP4XX_UART1_BASE_PHYS,
201 +       .end    = IXP4XX_UART1_BASE_PHYS + 0x0fff,
202 +       .flags  = IORESOURCE_MEM,
203 +};
204 +
205 +static struct plat_serial8250_port cambria_uart_data[] = {
206 +       {
207 +               .mapbase        = IXP4XX_UART1_BASE_PHYS,
208 +               .membase        = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
209 +               .irq            = IRQ_IXP4XX_UART1,
210 +               .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
211 +               .iotype         = UPIO_MEM,
212 +               .regshift       = 2,
213 +               .uartclk        = IXP4XX_UART_XTAL,
214 +       },
215 +       { },
216 +};
217 +
218 +static struct platform_device cambria_uart = {
219 +       .name           = "serial8250",
220 +       .id             = PLAT8250_DEV_PLATFORM,
221 +       .dev                    = {
222 +               .platform_data  = cambria_uart_data,
223 +       },
224 +       .num_resources  = 1,
225 +       .resource       = &cambria_uart_resource,
226 +};
227 +
228 +static struct resource cambria_pata_resources[] = {
229 +       {
230 +               .flags  = IORESOURCE_MEM
231 +       },
232 +       {
233 +               .flags  = IORESOURCE_MEM,
234 +       },
235 +       {
236 +               .name   = "intrq",
237 +               .start  = IRQ_IXP4XX_GPIO12,
238 +               .end    = IRQ_IXP4XX_GPIO12,
239 +               .flags  = IORESOURCE_IRQ,
240 +       },
241 +};
242 +
243 +static struct ixp4xx_pata_data cambria_pata_data = {
244 +       .cs0_bits       = 0xbfff3c03,
245 +       .cs1_bits       = 0xbfff3c03,
246 +};
247 +
248 +static struct platform_device cambria_pata = {
249 +       .name                   = "pata_ixp4xx_cf",
250 +       .id                     = 0,
251 +       .dev.platform_data      = &cambria_pata_data,
252 +       .num_resources          = ARRAY_SIZE(cambria_pata_resources),
253 +       .resource               = cambria_pata_resources,
254 +};
255 +
256 +static struct eth_plat_info cambria_plat_eth[] = {
257 +        {
258 +               .phy            = 2,
259 +               .rxq            = 4,
260 +               .txreadyq       = 21,
261 +        }, {
262 +               .phy            = 1,
263 +               .rxq            = 2,
264 +               .txreadyq       = 19,
265 +       }
266 +};
267 +
268 +static struct platform_device cambria_eth[] = {
269 +        {
270 +                .name                   = "ixp4xx_eth",
271 +                .id                     = IXP4XX_ETH_NPEC,
272 +                .dev.platform_data      = cambria_plat_eth,
273 +        }, {
274 +                .name                   = "ixp4xx_eth",
275 +                .id                     = IXP4XX_ETH_NPEA,
276 +                .dev.platform_data      = cambria_plat_eth + 1,
277 +       }
278 +};
279 +
280 +#ifdef CONFIG_LEDS_IXP4XX
281 +static struct platform_device cambria_leds_pld = {
282 +       .name           = "IXP4XX-PLD-LED",
283 +       .id             = -1,
284 +       .num_resources  = 0,
285 +};
286 +
287 +static struct platform_device cambria_leds_mem = {
288 +       .name           = "IXP4XX-MEM-LED",
289 +       .id             = -1,
290 +       .num_resources  = 0,
291 +};
292 +#endif
293 +
294 +static struct platform_device *cambria_devices[] __initdata = {
295 +       &cambria_i2c_gpio,
296 +       &cambria_flash,
297 +       &cambria_uart,
298 +#ifdef CONFIG_LEDS_IXP4XX
299 +       &cambria_leds_pld,
300 +       &cambria_leds_mem,
301 +#endif
302 +       &cambria_eth[0],
303 +       &cambria_eth[1],
304 +};
305 +
306 +#ifdef CONFIG_SENSORS_EEPROM
307 +static int cambria_eeprom_do(struct notifier_block *self, unsigned long event, void *t)
308 +{
309 +       struct eeprom_data *data = t;
310 +       struct sockaddr address;
311 +       struct net_device * netdev;
312 +
313 +       char macs[12];
314 +
315 +       /* The MACs are the first 12 bytes in the eeprom at address 0x51 */
316 +       if (event == EEPROM_REGISTER && data->client.addr == 0x51) {
317 +               data->attr->read(&data->client.dev.kobj, data->attr, macs, 0, 12);
318 +               /* eth0 */
319 +               memcpy(address.sa_data, macs, ETH_ALEN);
320 +               memcpy(&cambria_plat_eth[0].hwaddr, macs, ETH_ALEN);
321 +               if ( (netdev = dev_get_by_name(&init_net, "eth0")) )
322 +                       netdev->set_mac_address(netdev, &address);
323 +
324 +               /* eth1 */
325 +               memcpy(address.sa_data, macs + ETH_ALEN, ETH_ALEN);
326 +               memcpy(&cambria_plat_eth[1].hwaddr, macs + ETH_ALEN, ETH_ALEN);
327 +               if ( (netdev = dev_get_by_name(&init_net, "eth1")) )
328 +                       netdev->set_mac_address(netdev, &address);
329 +       }
330 +
331 +       return NOTIFY_DONE;
332 +}
333 +
334 +static struct notifier_block cambria_eeprom_notifier = {
335 +       .notifier_call = cambria_eeprom_do
336 +};
337 +#endif
338 +
339 +static void __init cambria_init(void)
340 +{
341 +       ixp4xx_sys_init();
342 +
343 +#ifdef CONFIG_SENSORS_EEPROM
344 +       register_eeprom_notifier(&cambria_eeprom_notifier);
345 +#endif
346 +
347 +       cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
348 +       cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
349 +
350 +       *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
351 +       *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
352 +
353 +       platform_add_devices(cambria_devices, ARRAY_SIZE(cambria_devices));
354 +
355 +       cambria_pata_resources[0].start = 0x53e00000;
356 +       cambria_pata_resources[0].end = 0x53e3ffff;
357 +
358 +       cambria_pata_resources[1].start = 0x53e40000;
359 +       cambria_pata_resources[1].end = 0x53e7ffff;
360 +
361 +       cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
362 +       cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
363 +
364 +       platform_device_register(&cambria_pata);
365 +}
366 +
367 +#ifdef CONFIG_MACH_CAMBRIA
368 +MACHINE_START(CAMBRIA, "Gateworks Cambria series")
369 +       /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
370 +       .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
371 +       .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
372 +       .map_io         = ixp4xx_map_io,
373 +       .init_irq       = ixp4xx_init_irq,
374 +       .timer          = &ixp4xx_timer,
375 +       .boot_params    = 0x0100,
376 +       .init_machine   = cambria_init,
377 +MACHINE_END
378 +#endif
379 diff -Nur linux-2.6.24.5/include/asm-arm/arch-ixp4xx/hardware.h linux-2.6.24.5-owrt/include/asm-arm/arch-ixp4xx/hardware.h
380 --- linux-2.6.24.5/include/asm-arm/arch-ixp4xx/hardware.h       1970-01-01 01:00:00.000000000 +0100
381 +++ linux-2.6.24.5-owrt/include/asm-arm/arch-ixp4xx/hardware.h  2008-04-28 21:07:16.000000000 +0200
382 @@ -18,7 +18,7 @@
383  #define __ASM_ARCH_HARDWARE_H__
384  
385  #define PCIBIOS_MIN_IO         0x00001000
386 -#define PCIBIOS_MIN_MEM                (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
387 +#define PCIBIOS_MIN_MEM                (cpu_is_ixp43x() ? 0x48000000 : 0x48000000)
388  
389  /*
390   * We override the standard dma-mask routines for bouncing.