target/linux/imx6/patches-3.10/0010-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch

   1 Subject: [v6,1/3] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q
   2 From: Sean Cross <xobs@kosagi.com>
   3
   4 The i.MX6 has two general-purpose LVDS clocks that can be driven
   5 from a variety of sources.  This patch adds a mux and a gate for
   6 both of these clocks.
   7
   8 Signed-off-by: Sean Cross <xobs@kosagi.com>
   9 ---
  10  arch/arm/mach-imx/clk-imx6q.c                      |   20 +++++++++++++++++++-
  11  2 files changed, 23 insertions(+), 1 deletion(-)
  12
  13 --- a/arch/arm/mach-imx/clk-imx6q.c
  14 +++ b/arch/arm/mach-imx/clk-imx6q.c
  15 @@ -205,6 +205,11 @@ static const char *vpu_axi_sels[]  = { "a
  16  static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
  17                                     "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
  18                                     "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
  19 +static const char *lvds_sels[] = {
  20 +       "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
  21 +       "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
  22 +       "pcie_ref", "sata_ref",
  23 +};
  24
  25  enum mx6q_clks {
  26         dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
  27 @@ -238,7 +243,8 @@ enum mx6q_clks {
  28         pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
  29         ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
  30         sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
  31 -       usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
  32 +       usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div,
  33 +       lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
  34  };
  35
  36  static struct clk *clk[clk_max];
  37 @@ -340,6 +346,18 @@ int __init mx6q_clocks_init(void)
  38                         base + 0xe0, 0, 2, 0, clk_enet_ref_table,
  39                         &imx_ccm_lock);
  40
  41 +       clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
  42 +       clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
  43 +
  44 +       /*
  45 +        * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be
  46 +        * independently configured as clock inputs or outputs.  We treat
  47 +        * the "output_enable" bit as a gate, even though it's really just
  48 +        * enabling clock output.
  49 +        */
  50 +       clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
  51 +       clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
  52 +
  53         /*                                name              parent_name        reg       idx */
  54         clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
  55         clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);