2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/phy.h>
20 #include <linux/rtl8366s.h>
22 #include "rtl8366_smi.h"
24 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
25 #include <linux/debugfs.h>
28 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
29 #define RTL8366S_DRIVER_VER "0.2.1"
31 #define RTL8366S_PHY_NO_MAX 4
32 #define RTL8366S_PHY_PAGE_MAX 7
33 #define RTL8366S_PHY_ADDR_MAX 31
35 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
36 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
38 #define RTL8366_RESET_CTRL_REG 0x0100
39 #define RTL8366_CHIP_CTRL_RESET_HW 1
40 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
42 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
43 #define RTL8366S_CHIP_VERSION_MASK 0xf
44 #define RTL8366S_CHIP_ID_REG 0x0105
45 #define RTL8366S_CHIP_ID_8366 0x8366
47 /* PHY registers control */
48 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
49 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
51 #define RTL8366S_PHY_CTRL_READ 1
52 #define RTL8366S_PHY_CTRL_WRITE 0
54 #define RTL8366S_PHY_REG_MASK 0x1f
55 #define RTL8366S_PHY_PAGE_OFFSET 5
56 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
57 #define RTL8366S_PHY_NO_OFFSET 9
58 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
60 /* LED control registers */
61 #define RTL8366_LED_BLINKRATE_REG 0x0420
62 #define RTL8366_LED_BLINKRATE_BIT 0
63 #define RTL8366_LED_BLINKRATE_MASK 0x0007
65 #define RTL8366_LED_CTRL_REG 0x0421
66 #define RTL8366_LED_0_1_CTRL_REG 0x0422
67 #define RTL8366_LED_2_3_CTRL_REG 0x0423
69 #define RTL8366S_MIB_COUNT 33
70 #define RTL8366S_GLOBAL_MIB_COUNT 1
71 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
72 #define RTL8366S_MIB_COUNTER_BASE 0x1000
73 #define RTL8366S_MIB_CTRL_REG 0x11F0
74 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
75 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
76 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
78 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
79 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
80 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
83 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
84 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
85 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
86 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
87 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
132 RTL8366_PORT_UNKNOWN | \
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
139 RTL8366_PORT_UNKNOWN)
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
150 struct device *parent;
151 struct rtl8366_smi smi;
152 struct mii_bus *mii_bus;
153 int mii_irq[PHY_MAX_ADDR];
154 struct switch_dev dev;
156 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
157 struct dentry *debugfs_root;
161 struct rtl8366s_vlanconfig {
172 struct rtl8366s_vlan4kentry {
182 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
192 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
193 { 0, 4, "IfInOctets " },
194 { 4, 4, "EtherStatsOctets " },
195 { 8, 2, "EtherStatsUnderSizePkts " },
196 { 10, 2, "EtherFregament " },
197 { 12, 2, "EtherStatsPkts64Octets " },
198 { 14, 2, "EtherStatsPkts65to127Octets " },
199 { 16, 2, "EtherStatsPkts128to255Octets " },
200 { 18, 2, "EtherStatsPkts256to511Octets " },
201 { 20, 2, "EtherStatsPkts512to1023Octets " },
202 { 22, 2, "EtherStatsPkts1024to1518Octets " },
203 { 24, 2, "EtherOversizeStats " },
204 { 26, 2, "EtherStatsJabbers " },
205 { 28, 2, "IfInUcastPkts " },
206 { 30, 2, "EtherStatsMulticastPkts " },
207 { 32, 2, "EtherStatsBroadcastPkts " },
208 { 34, 2, "EtherStatsDropEvents " },
209 { 36, 2, "Dot3StatsFCSErrors " },
210 { 38, 2, "Dot3StatsSymbolErrors " },
211 { 40, 2, "Dot3InPauseFrames " },
212 { 42, 2, "Dot3ControlInUnknownOpcodes " },
213 { 44, 4, "IfOutOctets " },
214 { 48, 2, "Dot3StatsSingleCollisionFrames " },
215 { 50, 2, "Dot3StatMultipleCollisionFrames " },
216 { 52, 2, "Dot3sDeferredTransmissions " },
217 { 54, 2, "Dot3StatsLateCollisions " },
218 { 56, 2, "EtherStatsCollisions " },
219 { 58, 2, "Dot3StatsExcessiveCollisions " },
220 { 60, 2, "Dot3OutPauseFrames " },
221 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
222 { 64, 2, "Dot1dTpPortInDiscards " },
223 { 66, 2, "IfOutUcastPkts " },
224 { 68, 2, "IfOutMulticastPkts " },
225 { 70, 2, "IfOutBroadcastPkts " },
228 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
230 return container_of(sw, struct rtl8366s, dev);
233 static int rtl8366s_reset_chip(struct rtl8366s *rtl)
235 struct rtl8366_smi *smi = &rtl->smi;
239 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
240 RTL8366_CHIP_CTRL_RESET_HW);
243 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
246 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
251 printk("Timeout waiting for the switch to reset\n");
258 static int rtl8366s_read_phy_reg(struct rtl8366s *rtl,
259 u32 phy_no, u32 page, u32 addr, u32 *data)
261 struct rtl8366_smi *smi = &rtl->smi;
265 if (phy_no > RTL8366S_PHY_NO_MAX)
268 if (page > RTL8366S_PHY_PAGE_MAX)
271 if (addr > RTL8366S_PHY_ADDR_MAX)
274 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
275 RTL8366S_PHY_CTRL_READ);
279 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
280 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
281 (addr & RTL8366S_PHY_REG_MASK);
283 ret = rtl8366_smi_write_reg(smi, reg, 0);
287 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
294 static int rtl8366s_write_phy_reg(struct rtl8366s *rtl,
295 u32 phy_no, u32 page, u32 addr, u32 data)
297 struct rtl8366_smi *smi = &rtl->smi;
301 if (phy_no > RTL8366S_PHY_NO_MAX)
304 if (page > RTL8366S_PHY_PAGE_MAX)
307 if (addr > RTL8366S_PHY_ADDR_MAX)
310 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
311 RTL8366S_PHY_CTRL_WRITE);
315 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
316 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
317 (addr & RTL8366S_PHY_REG_MASK);
319 ret = rtl8366_smi_write_reg(smi, reg, data);
326 static int rtl8366_get_mib_counter(struct rtl8366s *rtl, int counter,
327 int port, unsigned long long *val)
329 struct rtl8366_smi *smi = &rtl->smi;
335 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
338 addr = RTL8366S_MIB_COUNTER_BASE +
339 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
340 rtl8366s_mib_counters[counter].offset;
343 * Writing access counter address first
344 * then ASIC will prepare 64bits counter wait for being retrived
346 data = 0; /* writing data will be discard by ASIC */
347 err = rtl8366_smi_write_reg(smi, addr, data);
351 /* read MIB control register */
352 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
356 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
359 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
363 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
364 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
368 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
375 static int rtl8366s_get_vlan_4k_entry(struct rtl8366s *rtl, u32 vid,
376 struct rtl8366s_vlan4kentry *vlan4k)
378 struct rtl8366_smi *smi = &rtl->smi;
383 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
386 if (vid >= RTL8366_NUM_VIDS)
389 tableaddr = (u16 *)vlan4k;
393 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
397 /* write table access control word */
398 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
399 RTL8366S_TABLE_VLAN_READ_CTRL);
403 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
410 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
421 static int rtl8366s_set_vlan_4k_entry(struct rtl8366s *rtl,
422 const struct rtl8366s_vlan4kentry *vlan4k)
424 struct rtl8366_smi *smi = &rtl->smi;
429 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
430 vlan4k->member > RTL8366_PORT_ALL ||
431 vlan4k->untag > RTL8366_PORT_ALL ||
432 vlan4k->fid > RTL8366S_FIDMAX)
435 tableaddr = (u16 *)vlan4k;
439 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
447 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
452 /* write table access control word */
453 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
454 RTL8366S_TABLE_VLAN_WRITE_CTRL);
459 static int rtl8366s_get_vlan_member_config(struct rtl8366s *rtl, u32 index,
460 struct rtl8366s_vlanconfig *vlanmc)
462 struct rtl8366_smi *smi = &rtl->smi;
468 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
470 if (index >= RTL8366_NUM_VLANS)
473 tableaddr = (u16 *)vlanmc;
475 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
476 err = rtl8366_smi_read_reg(smi, addr, &data);
483 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
484 err = rtl8366_smi_read_reg(smi, addr, &data);
493 static int rtl8366s_set_vlan_member_config(struct rtl8366s *rtl, u32 index,
494 const struct rtl8366s_vlanconfig
497 struct rtl8366_smi *smi = &rtl->smi;
503 if (index >= RTL8366_NUM_VLANS ||
504 vlanmc->vid >= RTL8366_NUM_VIDS ||
505 vlanmc->priority > RTL8366S_PRIORITYMAX ||
506 vlanmc->member > RTL8366_PORT_ALL ||
507 vlanmc->untag > RTL8366_PORT_ALL ||
508 vlanmc->fid > RTL8366S_FIDMAX)
511 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
513 tableaddr = (u16 *)vlanmc;
516 err = rtl8366_smi_write_reg(smi, addr, data);
520 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
525 err = rtl8366_smi_write_reg(smi, addr, data);
532 static int rtl8366s_get_port_vlan_index(struct rtl8366s *rtl, int port,
535 struct rtl8366_smi *smi = &rtl->smi;
539 if (port >= RTL8366_NUM_PORTS)
542 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
547 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
548 RTL8366S_PORT_VLAN_CTRL_MASK;
554 static int rtl8366s_get_vlan_port_pvid(struct rtl8366s *rtl, int port,
557 struct rtl8366s_vlanconfig vlanmc;
561 err = rtl8366s_get_port_vlan_index(rtl, port, &index);
565 err = rtl8366s_get_vlan_member_config(rtl, index, &vlanmc);
573 static int rtl8366s_set_port_vlan_index(struct rtl8366s *rtl, int port,
576 struct rtl8366_smi *smi = &rtl->smi;
580 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
583 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
588 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
589 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
590 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
591 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
593 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
598 static int rtl8366s_set_vlan_port_pvid(struct rtl8366s *rtl, int port, int val)
601 struct rtl8366s_vlanconfig vlanmc;
602 struct rtl8366s_vlan4kentry vlan4k;
604 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
607 /* Updating the 4K entry; lookup it and change the port member set */
608 rtl8366s_get_vlan_4k_entry(rtl, val, &vlan4k);
609 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
610 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
611 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
614 * For the 16 entries more work needs to be done. First see if such
615 * VID is already there and change it
617 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
618 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
620 /* Try to find an existing vid and update port member set */
621 if (val == vlanmc.vid) {
622 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
623 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
625 /* Now update PVID register settings */
626 rtl8366s_set_port_vlan_index(rtl, port, i);
633 * PVID could not be found from vlan table. Replace unused (one that
634 * has no member ports) with new one
636 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
637 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
640 * See if this vlan member configuration is unused. It is
641 * unused if member set contains no ports or CPU port only
643 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
646 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
647 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
650 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
652 /* Now update PVID register settings */
653 rtl8366s_set_port_vlan_index(rtl, port, i);
660 "All 16 vlan member configurations are in use\n");
666 static int rtl8366s_vlan_set_vlan(struct rtl8366s *rtl, int enable)
668 struct rtl8366_smi *smi = &rtl->smi;
671 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
674 data |= RTL8366_CHIP_CTRL_VLAN;
676 data &= ~RTL8366_CHIP_CTRL_VLAN;
678 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
681 static int rtl8366s_vlan_set_4ktable(struct rtl8366s *rtl, int enable)
683 struct rtl8366_smi *smi = &rtl->smi;
686 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
693 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
696 static int rtl8366s_reset_vlan(struct rtl8366s *rtl)
698 struct rtl8366s_vlan4kentry vlan4k;
699 struct rtl8366s_vlanconfig vlanmc;
703 /* clear 16 VLAN member configuration */
709 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
710 err = rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
715 /* Set a default VLAN with vid 1 to 4K table for all ports */
717 vlan4k.member = RTL8366_PORT_ALL;
718 vlan4k.untag = RTL8366_PORT_ALL;
720 err = rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
724 /* Set all ports PVID to default VLAN */
725 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
726 err = rtl8366s_set_vlan_port_pvid(rtl, i, 0);
734 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
735 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
737 file->private_data = inode->i_private;
741 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
742 char __user *user_buf,
743 size_t count, loff_t *ppos)
745 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
747 char *buf = rtl->buf;
749 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
750 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
752 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
755 for (i = 0; i < 33; ++i) {
756 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
757 i, rtl8366s_mib_counters[i].name);
758 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
759 unsigned long long counter = 0;
761 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
762 len += snprintf(buf + len,
763 sizeof(rtl->buf) - len,
766 len += snprintf(buf + len,
767 sizeof(rtl->buf) - len,
770 if (j != RTL8366_NUM_PORTS - 1) {
771 if (counter < 100000)
772 len += snprintf(buf + len,
773 sizeof(rtl->buf) - len,
776 len += snprintf(buf + len,
777 sizeof(rtl->buf) - len,
781 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
784 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
786 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
789 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
790 char __user *user_buf,
791 size_t count, loff_t *ppos)
793 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
795 char *buf = rtl->buf;
797 len += snprintf(buf + len, sizeof(rtl->buf) - len,
798 "VLAN Member Config:\n");
799 len += snprintf(buf + len, sizeof(rtl->buf) - len,
800 "\t id \t vid \t prio \t member \t untag \t fid "
803 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
804 struct rtl8366s_vlanconfig vlanmc;
806 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
808 len += snprintf(buf + len, sizeof(rtl->buf) - len,
809 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
810 "\t", i, vlanmc.vid, vlanmc.priority,
811 vlanmc.member, vlanmc.untag, vlanmc.fid);
813 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
815 if (!rtl8366s_get_port_vlan_index(rtl, j, &index)) {
817 len += snprintf(buf + len,
818 sizeof(rtl->buf) - len,
822 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
825 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
828 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
829 char __user *user_buf,
830 size_t count, loff_t *ppos)
832 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
833 struct rtl8366_smi *smi = &rtl->smi;
834 u32 t, reg = g_dbg_reg;
836 char *buf = rtl->buf;
838 memset(buf, '\0', sizeof(rtl->buf));
840 err = rtl8366_smi_read_reg(smi, reg, &t);
842 len += snprintf(buf, sizeof(rtl->buf),
843 "Read failed (reg: 0x%04x)\n", reg);
844 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
847 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
850 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
853 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
854 const char __user *user_buf,
855 size_t count, loff_t *ppos)
857 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
858 struct rtl8366_smi *smi = &rtl->smi;
863 char *buf = rtl->buf;
865 len = min(count, sizeof(rtl->buf) - 1);
866 if (copy_from_user(buf, user_buf, len)) {
867 dev_err(rtl->parent, "copy from user failed\n");
872 if (len > 0 && buf[len - 1] == '\n')
876 if (strict_strtoul(buf, 16, &data)) {
877 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
879 err = rtl8366_smi_write_reg(smi, reg, data);
882 "writing reg 0x%04x val 0x%04lx failed\n",
890 static const struct file_operations fops_rtl8366s_regs = {
891 .read = rtl8366s_read_debugfs_reg,
892 .write = rtl8366s_write_debugfs_reg,
893 .open = rtl8366s_debugfs_open,
897 static const struct file_operations fops_rtl8366s_vlan = {
898 .read = rtl8366s_read_debugfs_vlan,
899 .open = rtl8366s_debugfs_open,
903 static const struct file_operations fops_rtl8366s_mibs = {
904 .read = rtl8366s_read_debugfs_mibs,
905 .open = rtl8366s_debugfs_open,
909 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
914 if (!rtl->debugfs_root)
915 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
917 if (!rtl->debugfs_root) {
918 dev_err(rtl->parent, "Unable to create debugfs dir\n");
921 root = rtl->debugfs_root;
923 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
925 dev_err(rtl->parent, "Creating debugfs file reg failed\n");
929 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
930 &fops_rtl8366s_regs);
932 dev_err(rtl->parent, "Creating debugfs file val failed\n");
936 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
937 &fops_rtl8366s_vlan);
940 "Creating debugfs file vlan failed\n");
944 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
945 &fops_rtl8366s_mibs);
948 "Creating debugfs file mibs failed\n");
953 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
955 if (rtl->debugfs_root) {
956 debugfs_remove_recursive(rtl->debugfs_root);
957 rtl->debugfs_root = NULL;
962 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
963 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
964 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
966 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
967 const struct switch_attr *attr,
968 struct switch_val *val)
970 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
971 struct rtl8366_smi *smi = &rtl->smi;
974 if (val->value.i == 1) {
975 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
977 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
983 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
984 const struct switch_attr *attr,
985 struct switch_val *val)
987 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
988 struct rtl8366_smi *smi = &rtl->smi;
991 if (attr->ofs == 1) {
992 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
994 if (data & RTL8366_CHIP_CTRL_VLAN)
998 } else if (attr->ofs == 2) {
999 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1010 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
1011 const struct switch_attr *attr,
1012 struct switch_val *val)
1014 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1015 struct rtl8366_smi *smi = &rtl->smi;
1018 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1020 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1025 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1026 const struct switch_attr *attr,
1027 struct switch_val *val)
1029 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1030 struct rtl8366_smi *smi = &rtl->smi;
1033 if (val->value.i >= 6)
1036 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1038 data &= ~RTL8366_LED_BLINKRATE_MASK;
1039 data |= val->value.i;
1041 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1046 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1047 const struct switch_attr *attr,
1048 struct switch_val *val)
1050 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1053 return rtl8366s_vlan_set_vlan(rtl, val->value.i);
1055 return rtl8366s_vlan_set_4ktable(rtl, val->value.i);
1058 static const char *rtl8366s_speed_str(unsigned speed)
1072 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1073 const struct switch_attr *attr,
1074 struct switch_val *val)
1076 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1077 struct rtl8366_smi *smi = &rtl->smi;
1078 u32 len = 0, data = 0;
1080 if (val->port_vlan >= RTL8366_NUM_PORTS)
1083 memset(rtl->buf, '\0', sizeof(rtl->buf));
1084 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1085 (val->port_vlan / 2), &data);
1087 if (val->port_vlan % 2)
1090 len = snprintf(rtl->buf, sizeof(rtl->buf),
1091 "port:%d link:%s speed:%s %s-duplex %s%s%s",
1093 (data & RTL8366S_PORT_STATUS_LINK_MASK) ? "up" : "down",
1094 rtl8366s_speed_str(data &
1095 RTL8366S_PORT_STATUS_SPEED_MASK),
1096 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1098 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1100 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1102 (data & RTL8366S_PORT_STATUS_AN_MASK) ? "nway ": "");
1104 val->value.s = rtl->buf;
1110 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1111 const struct switch_attr *attr,
1112 struct switch_val *val)
1116 struct rtl8366s_vlanconfig vlanmc;
1117 struct rtl8366s_vlan4kentry vlan4k;
1118 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1119 char *buf = rtl->buf;
1121 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1124 memset(buf, '\0', sizeof(rtl->buf));
1126 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1127 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1129 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1132 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1134 if (!rtl8366s_get_port_vlan_index(rtl, i, &index) &&
1135 index == val->port_vlan)
1136 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1139 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1141 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1142 "\t\t vid \t prio \t member \t untag \t fid\n");
1143 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1144 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1145 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1146 vlanmc.vid, vlanmc.priority, vlanmc.member,
1147 vlanmc.untag, vlanmc.fid);
1148 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1149 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1150 "%d \t \t 0x%04x \t 0x%04x \t %d",
1151 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1159 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1160 const struct switch_attr *attr,
1161 struct switch_val *val)
1163 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1164 struct rtl8366_smi *smi = &rtl->smi;
1167 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1168 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1171 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1172 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1173 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1174 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1176 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1177 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1178 (val->value.i << (val->port_vlan * 4));
1179 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1185 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1186 const struct switch_attr *attr,
1187 struct switch_val *val)
1189 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1190 struct rtl8366_smi *smi = &rtl->smi;
1193 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1196 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1197 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1202 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1203 const struct switch_attr *attr,
1204 struct switch_val *val)
1206 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1207 struct rtl8366_smi *smi = &rtl->smi;
1210 if (val->port_vlan >= RTL8366_NUM_PORTS)
1213 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1214 data |= (1 << (val->port_vlan + 3));
1215 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1220 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1221 const struct switch_attr *attr,
1222 struct switch_val *val)
1224 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1226 unsigned long long counter = 0;
1227 char *buf = rtl->buf;
1229 if (val->port_vlan >= RTL8366_NUM_PORTS)
1232 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1233 "Port %d MIB counters\n",
1236 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1237 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1238 "%d:%s\t", i, rtl8366s_mib_counters[i].name);
1239 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1240 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1241 "[%llu]\n", counter);
1243 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1252 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1253 struct switch_val *val)
1255 struct rtl8366s_vlanconfig vlanmc;
1256 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1257 struct switch_port *port;
1260 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1263 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1265 port = &val->value.ports[0];
1267 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1268 if (!(vlanmc.member & BIT(i)))
1272 port->flags = (vlanmc.untag & BIT(i)) ?
1273 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1280 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1281 struct switch_val *val)
1283 struct rtl8366s_vlanconfig vlanmc;
1284 struct rtl8366s_vlan4kentry vlan4k;
1285 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1286 struct switch_port *port;
1289 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1292 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1293 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1298 port = &val->value.ports[0];
1299 for (i = 0; i < val->len; i++, port++) {
1300 vlanmc.member |= BIT(port->id);
1302 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1303 vlanmc.untag |= BIT(port->id);
1306 vlan4k.member = vlanmc.member;
1307 vlan4k.untag = vlanmc.untag;
1309 rtl8366s_set_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1310 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
1314 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1316 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1317 return rtl8366s_get_vlan_port_pvid(rtl, port, val);
1320 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1322 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1323 return rtl8366s_set_vlan_port_pvid(rtl, port, val);
1326 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1328 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1331 err = rtl8366s_reset_chip(rtl);
1335 return rtl8366s_reset_vlan(rtl);
1338 static struct switch_attr rtl8366s_globals[] = {
1340 .type = SWITCH_TYPE_INT,
1341 .name = "enable_vlan",
1342 .description = "Enable VLAN mode",
1343 .set = rtl8366s_sw_set_vlan_enable,
1344 .get = rtl8366s_sw_get_vlan_enable,
1348 .type = SWITCH_TYPE_INT,
1349 .name = "enable_vlan4k",
1350 .description = "Enable VLAN 4K mode",
1351 .set = rtl8366s_sw_set_vlan_enable,
1352 .get = rtl8366s_sw_get_vlan_enable,
1356 .type = SWITCH_TYPE_INT,
1357 .name = "reset_mibs",
1358 .description = "Reset all MIB counters",
1359 .set = rtl8366s_sw_reset_mibs,
1363 .type = SWITCH_TYPE_INT,
1364 .name = "blinkrate",
1365 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1366 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1367 .set = rtl8366s_sw_set_blinkrate,
1368 .get = rtl8366s_sw_get_blinkrate,
1373 static struct switch_attr rtl8366s_port[] = {
1375 .type = SWITCH_TYPE_STRING,
1377 .description = "Get port link information",
1380 .get = rtl8366s_sw_get_port_link,
1382 .type = SWITCH_TYPE_INT,
1383 .name = "reset_mib",
1384 .description = "Reset single port MIB counters",
1386 .set = rtl8366s_sw_reset_port_mibs,
1389 .type = SWITCH_TYPE_STRING,
1391 .description = "Get MIB counters for port",
1394 .get = rtl8366s_sw_get_port_mib,
1396 .type = SWITCH_TYPE_INT,
1398 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1400 .set = rtl8366s_sw_set_port_led,
1401 .get = rtl8366s_sw_get_port_led,
1405 static struct switch_attr rtl8366s_vlan[] = {
1407 .type = SWITCH_TYPE_STRING,
1409 .description = "Get vlan information",
1412 .get = rtl8366s_sw_get_vlan_info,
1417 static struct switch_dev rtl8366_switch_dev = {
1419 .cpu_port = RTL8366_PORT_NUM_CPU,
1420 .ports = RTL8366_NUM_PORTS,
1421 .vlans = RTL8366_NUM_VLANS,
1423 .attr = rtl8366s_globals,
1424 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1427 .attr = rtl8366s_port,
1428 .n_attr = ARRAY_SIZE(rtl8366s_port),
1431 .attr = rtl8366s_vlan,
1432 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1435 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1436 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1437 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1438 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1439 .reset_switch = rtl8366s_sw_reset_switch,
1442 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1444 struct switch_dev *dev = &rtl->dev;
1447 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1449 dev->devname = dev_name(rtl->parent);
1451 err = register_switch(dev, NULL);
1453 dev_err(rtl->parent, "switch registration failed\n");
1458 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1460 unregister_switch(&rtl->dev);
1463 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1465 struct rtl8366s *rtl = bus->priv;
1469 err = rtl8366s_read_phy_reg(rtl, addr, 0, reg, &val);
1476 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1478 struct rtl8366s *rtl = bus->priv;
1482 err = rtl8366s_write_phy_reg(rtl, addr, 0, reg, val);
1484 (void) rtl8366s_read_phy_reg(rtl, addr, 0, reg, &t);
1489 static int rtl8366s_mii_init(struct rtl8366s *rtl)
1494 rtl->mii_bus = mdiobus_alloc();
1495 if (rtl->mii_bus == NULL) {
1500 rtl->mii_bus->priv = (void *) rtl;
1501 rtl->mii_bus->name = "rtl8366-rtl";
1502 rtl->mii_bus->read = rtl8366s_mii_read;
1503 rtl->mii_bus->write = rtl8366s_mii_write;
1504 snprintf(rtl->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1505 dev_name(rtl->parent));
1506 rtl->mii_bus->parent = rtl->parent;
1507 rtl->mii_bus->phy_mask = ~(0x1f);
1508 rtl->mii_bus->irq = rtl->mii_irq;
1509 for (i = 0; i < PHY_MAX_ADDR; i++)
1510 rtl->mii_irq[i] = PHY_POLL;
1512 ret = mdiobus_register(rtl->mii_bus);
1519 mdiobus_free(rtl->mii_bus);
1524 static void rtl8366s_mii_cleanup(struct rtl8366s *rtl)
1526 mdiobus_unregister(rtl->mii_bus);
1527 mdiobus_free(rtl->mii_bus);
1530 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1532 return (bus->read == rtl8366s_mii_read &&
1533 bus->write == rtl8366s_mii_write);
1536 static int rtl8366s_setup(struct rtl8366s *rtl)
1538 struct rtl8366_smi *smi = &rtl->smi;
1543 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1545 dev_err(rtl->parent, "unable to read chip id\n");
1550 case RTL8366S_CHIP_ID_8366:
1553 dev_err(rtl->parent, "unknown chip id (%04x)\n", chip_id);
1557 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1560 dev_err(rtl->parent, "unable to read chip version\n");
1564 dev_info(rtl->parent, "RTL%04x ver. %u chip found\n",
1565 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1567 ret = rtl8366s_reset_chip(rtl);
1571 rtl8366s_debugfs_init(rtl);
1575 static int __init rtl8366s_probe(struct platform_device *pdev)
1577 static int rtl8366_smi_version_printed;
1578 struct rtl8366s_platform_data *pdata;
1579 struct rtl8366s *rtl;
1580 struct rtl8366_smi *smi;
1583 if (!rtl8366_smi_version_printed++)
1584 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1585 " version " RTL8366S_DRIVER_VER"\n");
1587 pdata = pdev->dev.platform_data;
1589 dev_err(&pdev->dev, "no platform data specified\n");
1594 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1596 dev_err(&pdev->dev, "no memory for private data\n");
1601 rtl->parent = &pdev->dev;
1604 smi->parent = &pdev->dev;
1605 smi->gpio_sda = pdata->gpio_sda;
1606 smi->gpio_sck = pdata->gpio_sck;
1608 err = rtl8366_smi_init(smi);
1612 platform_set_drvdata(pdev, rtl);
1614 err = rtl8366s_setup(rtl);
1616 goto err_clear_drvdata;
1618 err = rtl8366s_mii_init(rtl);
1620 goto err_clear_drvdata;
1622 err = rtl8366s_switch_init(rtl);
1624 goto err_mii_cleanup;
1629 rtl8366s_mii_cleanup(rtl);
1631 platform_set_drvdata(pdev, NULL);
1632 rtl8366_smi_cleanup(smi);
1639 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1641 if (!rtl8366s_mii_bus_match(phydev->bus))
1647 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1652 static struct phy_driver rtl8366s_phy_driver = {
1653 .phy_id = 0x001cc960,
1654 .name = "Realtek RTL8366S",
1655 .phy_id_mask = 0x1ffffff0,
1656 .features = PHY_GBIT_FEATURES,
1657 .config_aneg = rtl8366s_phy_config_aneg,
1658 .config_init = rtl8366s_phy_config_init,
1659 .read_status = genphy_read_status,
1661 .owner = THIS_MODULE,
1665 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1667 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1670 rtl8366s_switch_cleanup(rtl);
1671 rtl8366s_debugfs_remove(rtl);
1672 rtl8366s_mii_cleanup(rtl);
1673 platform_set_drvdata(pdev, NULL);
1674 rtl8366_smi_cleanup(&rtl->smi);
1681 static struct platform_driver rtl8366s_driver = {
1683 .name = RTL8366S_DRIVER_NAME,
1684 .owner = THIS_MODULE,
1686 .probe = rtl8366s_probe,
1687 .remove = __devexit_p(rtl8366s_remove),
1690 static int __init rtl8366s_module_init(void)
1693 ret = platform_driver_register(&rtl8366s_driver);
1697 ret = phy_driver_register(&rtl8366s_phy_driver);
1699 goto err_platform_unregister;
1703 err_platform_unregister:
1704 platform_driver_unregister(&rtl8366s_driver);
1707 module_init(rtl8366s_module_init);
1709 static void __exit rtl8366s_module_exit(void)
1711 phy_driver_unregister(&rtl8366s_phy_driver);
1712 platform_driver_unregister(&rtl8366s_driver);
1714 module_exit(rtl8366s_module_exit);
1716 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1717 MODULE_VERSION(RTL8366S_DRIVER_VER);
1718 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1719 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1720 MODULE_LICENSE("GPL v2");
1721 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);