2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/phy.h>
20 #include <linux/rtl8366rb.h>
22 #include "rtl8366_smi.h"
24 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
25 #include <linux/debugfs.h>
28 #define RTL8366S_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
29 #define RTL8366S_DRIVER_VER "0.2.0"
31 #define RTL8366S_PHY_NO_MAX 4
32 #define RTL8366S_PHY_PAGE_MAX 7
33 #define RTL8366S_PHY_ADDR_MAX 31
35 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
36 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
37 #define RTL8366_CHIP_CTRL_VLAN_4KTB (1 << 14)
39 #define RTL8366_RESET_CTRL_REG 0x0100
40 #define RTL8366_CHIP_CTRL_RESET_HW 1
41 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
43 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x050A
44 #define RTL8366S_CHIP_VERSION_MASK 0xf
45 #define RTL8366S_CHIP_ID_REG 0x0509
46 #define RTL8366S_CHIP_ID_8366 0x5937
48 /* PHY registers control */
49 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8000
50 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8002
52 #define RTL8366S_PHY_CTRL_READ 1
53 #define RTL8366S_PHY_CTRL_WRITE 0
55 #define RTL8366S_PHY_REG_MASK 0x1f
56 #define RTL8366S_PHY_PAGE_OFFSET 5
57 #define RTL8366S_PHY_PAGE_MASK (0xf << 5)
58 #define RTL8366S_PHY_NO_OFFSET 9
59 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
61 /* LED control registers */
62 #define RTL8366_LED_BLINKRATE_REG 0x0430
63 #define RTL8366_LED_BLINKRATE_BIT 0
64 #define RTL8366_LED_BLINKRATE_MASK 0x0007
66 #define RTL8366_LED_CTRL_REG 0x0431
67 #define RTL8366_LED_0_1_CTRL_REG 0x0432
68 #define RTL8366_LED_2_3_CTRL_REG 0x0433
70 #define RTL8366S_MIB_COUNT 33
71 #define RTL8366S_GLOBAL_MIB_COUNT 1
72 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0050
73 #define RTL8366S_MIB_COUNTER_BASE 0x1000
74 #define RTL8366S_MIB_CTRL_REG 0x13F0
75 #define RTL8366S_MIB_CTRL_USER_MASK 0x0FFC
76 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
77 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0001
79 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
80 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
81 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
84 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0063
85 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
86 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
87 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
88 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
91 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018C
92 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0020
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0014
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124 #define RTL8366_PORT_5 (1 << 4) /* In userspace port 4 */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
146 #define RTL8366_PORT_ALL_INTERNAL RTL8366_PORT_CPU
149 struct device *parent;
150 struct rtl8366_smi smi;
151 struct mii_bus *mii_bus;
152 int mii_irq[PHY_MAX_ADDR];
153 struct switch_dev dev;
155 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
156 struct dentry *debugfs_root;
160 struct rtl8366rb_vlanconfig {
172 struct rtl8366rb_vlan4kentry {
182 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
192 static struct mib_counter rtl8366rb_mib_counters[RTL8366S_MIB_COUNT] = {
193 { 0, 4, "IfInOctets " },
194 { 4, 4, "EtherStatsOctets " },
195 { 8, 2, "EtherStatsUnderSizePkts " },
196 { 10, 2, "EtherFregament " },
197 { 12, 2, "EtherStatsPkts64Octets " },
198 { 14, 2, "EtherStatsPkts65to127Octets " },
199 { 16, 2, "EtherStatsPkts128to255Octets " },
200 { 18, 2, "EtherStatsPkts256to511Octets " },
201 { 20, 2, "EtherStatsPkts512to1023Octets " },
202 { 22, 2, "EtherStatsPkts1024to1518Octets " },
203 { 24, 2, "EtherOversizeStats " },
204 { 26, 2, "EtherStatsJabbers " },
205 { 28, 2, "IfInUcastPkts " },
206 { 30, 2, "EtherStatsMulticastPkts " },
207 { 32, 2, "EtherStatsBroadcastPkts " },
208 { 34, 2, "EtherStatsDropEvents " },
209 { 36, 2, "Dot3StatsFCSErrors " },
210 { 38, 2, "Dot3StatsSymbolErrors " },
211 { 40, 2, "Dot3InPauseFrames " },
212 { 42, 2, "Dot3ControlInUnknownOpcodes " },
213 { 44, 4, "IfOutOctets " },
214 { 48, 2, "Dot3StatsSingleCollisionFrames " },
215 { 50, 2, "Dot3StatMultipleCollisionFrames " },
216 { 52, 2, "Dot3sDeferredTransmissions " },
217 { 54, 2, "Dot3StatsLateCollisions " },
218 { 56, 2, "EtherStatsCollisions " },
219 { 58, 2, "Dot3StatsExcessiveCollisions " },
220 { 60, 2, "Dot3OutPauseFrames " },
221 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
222 { 64, 2, "Dot1dTpPortInDiscards " },
223 { 66, 2, "IfOutUcastPkts " },
224 { 68, 2, "IfOutMulticastPkts " },
225 { 70, 2, "IfOutBroadcastPkts " },
228 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
230 return container_of(sw, struct rtl8366rb, dev);
233 static int rtl8366rb_reset_chip(struct rtl8366rb *rtl)
235 struct rtl8366_smi *smi = &rtl->smi;
239 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
240 RTL8366_CHIP_CTRL_RESET_HW);
243 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
246 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
251 printk("Timeout waiting for the switch to reset\n");
258 static int rtl8366rb_read_phy_reg(struct rtl8366rb *rtl,
259 u32 phy_no, u32 page, u32 addr, u32 *data)
261 struct rtl8366_smi *smi = &rtl->smi;
265 if (phy_no > RTL8366S_PHY_NO_MAX)
268 if (page > RTL8366S_PHY_PAGE_MAX)
271 if (addr > RTL8366S_PHY_ADDR_MAX)
274 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
275 RTL8366S_PHY_CTRL_READ);
279 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
280 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
281 (addr & RTL8366S_PHY_REG_MASK);
283 ret = rtl8366_smi_write_reg(smi, reg, 0);
287 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
294 static int rtl8366rb_write_phy_reg(struct rtl8366rb *rtl,
295 u32 phy_no, u32 page, u32 addr, u32 data)
297 struct rtl8366_smi *smi = &rtl->smi;
301 if (phy_no > RTL8366S_PHY_NO_MAX)
304 if (page > RTL8366S_PHY_PAGE_MAX)
307 if (addr > RTL8366S_PHY_ADDR_MAX)
310 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
311 RTL8366S_PHY_CTRL_WRITE);
315 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
316 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
317 (addr & RTL8366S_PHY_REG_MASK);
319 ret = rtl8366_smi_write_reg(smi, reg, data);
326 static int rtl8366_get_mib_counter(struct rtl8366rb *rtl, int counter,
327 int port, unsigned long long *val)
329 struct rtl8366_smi *smi = &rtl->smi;
335 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
338 addr = RTL8366S_MIB_COUNTER_BASE +
339 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
340 rtl8366rb_mib_counters[counter].offset;
343 * Writing access counter address first
344 * then ASIC will prepare 64bits counter wait for being retrived
346 data = 0; /* writing data will be discard by ASIC */
347 err = rtl8366_smi_write_reg(smi, addr, data);
351 /* read MIB control register */
352 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
356 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
359 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
363 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
364 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
368 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
375 static int rtl8366rb_get_vlan_4k_entry(struct rtl8366rb *rtl, u32 vid,
376 struct rtl8366rb_vlan4kentry *vlan4k)
378 struct rtl8366_smi *smi = &rtl->smi;
383 memset(vlan4k, '\0', sizeof(struct rtl8366rb_vlan4kentry));
386 if (vid >= RTL8366_NUM_VIDS)
389 tableaddr = (u16 *)vlan4k;
393 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
397 /* write table access control word */
398 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
399 RTL8366S_TABLE_VLAN_READ_CTRL);
403 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
410 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
418 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 2,
428 static int rtl8366rb_set_vlan_4k_entry(struct rtl8366rb *rtl,
429 const struct rtl8366rb_vlan4kentry *vlan4k)
431 struct rtl8366_smi *smi = &rtl->smi;
436 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
437 vlan4k->member > RTL8366_PORT_ALL ||
438 vlan4k->untag > RTL8366_PORT_ALL ||
439 vlan4k->fid > RTL8366S_FIDMAX)
442 tableaddr = (u16 *)vlan4k;
446 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
454 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
463 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 2,
468 /* write table access control word */
469 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
470 RTL8366S_TABLE_VLAN_WRITE_CTRL);
475 static int rtl8366rb_get_vlan_member_config(struct rtl8366rb *rtl, u32 index,
476 struct rtl8366rb_vlanconfig *vlanmc)
478 struct rtl8366_smi *smi = &rtl->smi;
484 memset(vlanmc, '\0', sizeof(struct rtl8366rb_vlanconfig));
486 if (index >= RTL8366_NUM_VLANS)
489 tableaddr = (u16 *)vlanmc;
491 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
492 err = rtl8366_smi_read_reg(smi, addr, &data);
499 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
500 err = rtl8366_smi_read_reg(smi, addr, &data);
507 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
508 err = rtl8366_smi_read_reg(smi, addr, &data);
517 static int rtl8366rb_set_vlan_member_config(struct rtl8366rb *rtl, u32 index,
518 const struct rtl8366rb_vlanconfig
521 struct rtl8366_smi *smi = &rtl->smi;
527 if (index >= RTL8366_NUM_VLANS ||
528 vlanmc->vid >= RTL8366_NUM_VIDS ||
529 vlanmc->priority > RTL8366S_PRIORITYMAX ||
530 vlanmc->member > RTL8366_PORT_ALL ||
531 vlanmc->untag > RTL8366_PORT_ALL ||
532 vlanmc->fid > RTL8366S_FIDMAX)
535 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
537 tableaddr = (u16 *)vlanmc;
540 err = rtl8366_smi_write_reg(smi, addr, data);
544 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
549 err = rtl8366_smi_write_reg(smi, addr, data);
553 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
558 err = rtl8366_smi_write_reg(smi, addr, data);
564 static int rtl8366rb_get_port_vlan_index(struct rtl8366rb *rtl, int port,
567 struct rtl8366_smi *smi = &rtl->smi;
571 if (port >= RTL8366_NUM_PORTS)
574 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
579 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
580 RTL8366S_PORT_VLAN_CTRL_MASK;
586 static int rtl8366rb_get_vlan_port_pvid(struct rtl8366rb *rtl, int port,
589 struct rtl8366rb_vlanconfig vlanmc;
593 err = rtl8366rb_get_port_vlan_index(rtl, port, &index);
597 err = rtl8366rb_get_vlan_member_config(rtl, index, &vlanmc);
605 static int rtl8366rb_set_port_vlan_index(struct rtl8366rb *rtl, int port,
608 struct rtl8366_smi *smi = &rtl->smi;
612 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
615 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
620 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
621 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
622 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
623 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
625 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
630 static int rtl8366rb_set_vlan_port_pvid(struct rtl8366rb *rtl, int port, int val)
633 struct rtl8366rb_vlanconfig vlanmc;
634 struct rtl8366rb_vlan4kentry vlan4k;
636 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
639 /* Updating the 4K entry; lookup it and change the port member set */
640 rtl8366rb_get_vlan_4k_entry(rtl, val, &vlan4k);
641 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
642 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
643 rtl8366rb_set_vlan_4k_entry(rtl, &vlan4k);
646 * For the 16 entries more work needs to be done. First see if such
647 * VID is already there and change it
649 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
650 rtl8366rb_get_vlan_member_config(rtl, i, &vlanmc);
652 /* Try to find an existing vid and update port member set */
653 if (val == vlanmc.vid) {
654 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
655 rtl8366rb_set_vlan_member_config(rtl, i, &vlanmc);
657 /* Now update PVID register settings */
658 rtl8366rb_set_port_vlan_index(rtl, port, i);
665 * PVID could not be found from vlan table. Replace unused (one that
666 * has no member ports) with new one
668 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
669 rtl8366rb_get_vlan_member_config(rtl, i, &vlanmc);
672 * See if this vlan member configuration is unused. It is
673 * unused if member set contains no ports or CPU port only
675 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
678 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
679 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
682 rtl8366rb_set_vlan_member_config(rtl, i, &vlanmc);
684 /* Now update PVID register settings */
685 rtl8366rb_set_port_vlan_index(rtl, port, i);
692 "All 16 vlan member configurations are in use\n");
698 static int rtl8366rb_vlan_set_vlan(struct rtl8366rb *rtl, int enable)
700 struct rtl8366_smi *smi = &rtl->smi;
703 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
706 data |= RTL8366_CHIP_CTRL_VLAN;
708 data &= ~RTL8366_CHIP_CTRL_VLAN;
710 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
713 static int rtl8366rb_vlan_set_4ktable(struct rtl8366rb *rtl, int enable)
715 struct rtl8366_smi *smi = &rtl->smi;
718 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
721 data |= RTL8366_CHIP_CTRL_VLAN_4KTB;
723 data &= ~RTL8366_CHIP_CTRL_VLAN_4KTB;
725 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
728 static int rtl8366rb_reset_vlan(struct rtl8366rb *rtl)
730 struct rtl8366rb_vlan4kentry vlan4k;
731 struct rtl8366rb_vlanconfig vlanmc;
735 /* clear 16 VLAN member configuration */
741 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
742 err = rtl8366rb_set_vlan_member_config(rtl, i, &vlanmc);
747 /* Set a default VLAN with vid 1 to 4K table for all ports */
749 vlan4k.member = RTL8366_PORT_ALL;
750 vlan4k.untag = RTL8366_PORT_ALL;
752 err = rtl8366rb_set_vlan_4k_entry(rtl, &vlan4k);
756 /* Set all ports PVID to default VLAN */
757 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
758 err = rtl8366rb_set_vlan_port_pvid(rtl, i, 0);
766 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
767 static int rtl8366rb_debugfs_open(struct inode *inode, struct file *file)
769 file->private_data = inode->i_private;
773 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
774 char __user *user_buf,
775 size_t count, loff_t *ppos)
777 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
779 char *buf = rtl->buf;
781 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
782 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
784 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
787 for (i = 0; i < 33; ++i) {
788 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
789 i, rtl8366rb_mib_counters[i].name);
790 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
791 unsigned long long counter = 0;
793 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
794 len += snprintf(buf + len,
795 sizeof(rtl->buf) - len,
798 len += snprintf(buf + len,
799 sizeof(rtl->buf) - len,
802 if (j != RTL8366_NUM_PORTS - 1) {
803 if (counter < 100000)
804 len += snprintf(buf + len,
805 sizeof(rtl->buf) - len,
808 len += snprintf(buf + len,
809 sizeof(rtl->buf) - len,
813 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
816 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
818 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
821 static ssize_t rtl8366rb_read_debugfs_vlan(struct file *file,
822 char __user *user_buf,
823 size_t count, loff_t *ppos)
825 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
827 char *buf = rtl->buf;
829 len += snprintf(buf + len, sizeof(rtl->buf) - len,
830 "VLAN Member Config:\n");
831 len += snprintf(buf + len, sizeof(rtl->buf) - len,
832 "\t id \t vid \t prio \t member \t untag \t fid "
835 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
836 struct rtl8366rb_vlanconfig vlanmc;
838 rtl8366rb_get_vlan_member_config(rtl, i, &vlanmc);
840 len += snprintf(buf + len, sizeof(rtl->buf) - len,
841 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
842 "\t", i, vlanmc.vid, vlanmc.priority,
843 vlanmc.member, vlanmc.untag, vlanmc.fid);
845 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
847 if (!rtl8366rb_get_port_vlan_index(rtl, j, &index)) {
849 len += snprintf(buf + len,
850 sizeof(rtl->buf) - len,
854 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
857 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
860 static ssize_t rtl8366rb_read_debugfs_reg(struct file *file,
861 char __user *user_buf,
862 size_t count, loff_t *ppos)
864 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
865 struct rtl8366_smi *smi = &rtl->smi;
866 u32 t, reg = gl_dbg_reg;
868 char *buf = rtl->buf;
870 memset(buf, '\0', sizeof(rtl->buf));
872 err = rtl8366_smi_read_reg(smi, reg, &t);
874 len += snprintf(buf, sizeof(rtl->buf),
875 "Read failed (reg: 0x%04x)\n", reg);
876 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
879 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
882 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
885 static ssize_t rtl8366rb_write_debugfs_reg(struct file *file,
886 const char __user *user_buf,
887 size_t count, loff_t *ppos)
889 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
890 struct rtl8366_smi *smi = &rtl->smi;
892 u32 reg = gl_dbg_reg;
895 char *buf = rtl->buf;
897 len = min(count, sizeof(rtl->buf) - 1);
898 if (copy_from_user(buf, user_buf, len)) {
899 dev_err(rtl->parent, "copy from user failed\n");
904 if (len > 0 && buf[len - 1] == '\n')
908 if (strict_strtoul(buf, 16, &data)) {
909 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
911 err = rtl8366_smi_write_reg(smi, reg, data);
914 "writing reg 0x%04x val 0x%04lx failed\n",
922 static const struct file_operations fops_rtl8366rb_regs = {
923 .read = rtl8366rb_read_debugfs_reg,
924 .write = rtl8366rb_write_debugfs_reg,
925 .open = rtl8366rb_debugfs_open,
929 static const struct file_operations fops_rtl8366rb_vlan = {
930 .read = rtl8366rb_read_debugfs_vlan,
931 .open = rtl8366rb_debugfs_open,
935 static const struct file_operations fops_rtl8366rb_mibs = {
936 .read = rtl8366rb_read_debugfs_mibs,
937 .open = rtl8366rb_debugfs_open,
941 static void rtl8366rb_debugfs_init(struct rtl8366rb *rtl)
946 if (!rtl->debugfs_root)
947 rtl->debugfs_root = debugfs_create_dir("rtl8366rb", NULL);
949 if (!rtl->debugfs_root) {
950 dev_err(rtl->parent, "Unable to create debugfs dir\n");
953 root = rtl->debugfs_root;
955 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &gl_dbg_reg);
957 dev_err(rtl->parent, "Creating debugfs file reg failed\n");
961 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
962 &fops_rtl8366rb_regs);
964 dev_err(rtl->parent, "Creating debugfs file val failed\n");
968 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
969 &fops_rtl8366rb_vlan);
972 "Creating debugfs file vlan failed\n");
976 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
977 &fops_rtl8366rb_mibs);
980 "Creating debugfs file mibs failed\n");
985 static void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl)
987 if (rtl->debugfs_root) {
988 debugfs_remove_recursive(rtl->debugfs_root);
989 rtl->debugfs_root = NULL;
994 static inline void rtl8366rb_debugfs_init(struct rtl8366rb *rtl) {}
995 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl) {}
996 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
998 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
999 const struct switch_attr *attr,
1000 struct switch_val *val)
1002 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1003 struct rtl8366_smi *smi = &rtl->smi;
1006 if (val->value.i == 1) {
1007 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1009 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1015 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
1016 const struct switch_attr *attr,
1017 struct switch_val *val)
1019 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1020 struct rtl8366_smi *smi = &rtl->smi;
1023 if (attr->ofs == 1) {
1024 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1026 if (data & RTL8366_CHIP_CTRL_VLAN)
1030 } else if (attr->ofs == 2) {
1031 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1033 if (data & RTL8366_CHIP_CTRL_VLAN_4KTB)
1042 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
1043 const struct switch_attr *attr,
1044 struct switch_val *val)
1046 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1047 struct rtl8366_smi *smi = &rtl->smi;
1050 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1052 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1057 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
1058 const struct switch_attr *attr,
1059 struct switch_val *val)
1061 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1062 struct rtl8366_smi *smi = &rtl->smi;
1065 if (val->value.i >= 6)
1068 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1070 data &= ~RTL8366_LED_BLINKRATE_MASK;
1071 data |= val->value.i;
1073 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1078 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
1079 const struct switch_attr *attr,
1080 struct switch_val *val)
1082 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1085 return rtl8366rb_vlan_set_vlan(rtl, val->value.i);
1087 return rtl8366rb_vlan_set_4ktable(rtl, val->value.i);
1090 static const char *rtl8366rb_speed_str(unsigned speed)
1104 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
1105 const struct switch_attr *attr,
1106 struct switch_val *val)
1108 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1109 struct rtl8366_smi *smi = &rtl->smi;
1110 u32 len = 0, data = 0;
1112 if (val->port_vlan >= RTL8366_NUM_PORTS)
1115 memset(rtl->buf, '\0', sizeof(rtl->buf));
1116 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1117 (val->port_vlan / 2), &data);
1119 if (val->port_vlan % 2)
1122 len = snprintf(rtl->buf, sizeof(rtl->buf),
1123 "port:%d link:%s speed:%s %s-duplex %s%s%s",
1125 (data & RTL8366S_PORT_STATUS_LINK_MASK) ? "up" : "down",
1126 rtl8366rb_speed_str(data &
1127 RTL8366S_PORT_STATUS_SPEED_MASK),
1128 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1130 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1132 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1134 (data & RTL8366S_PORT_STATUS_AN_MASK) ? "nway ": "");
1136 val->value.s = rtl->buf;
1142 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
1143 const struct switch_attr *attr,
1144 struct switch_val *val)
1148 struct rtl8366rb_vlanconfig vlanmc;
1149 struct rtl8366rb_vlan4kentry vlan4k;
1150 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1151 char *buf = rtl->buf;
1153 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1156 memset(buf, '\0', sizeof(rtl->buf));
1158 rtl8366rb_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1159 rtl8366rb_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1161 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1164 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1166 if (!rtl8366rb_get_port_vlan_index(rtl, i, &index) &&
1167 index == val->port_vlan)
1168 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1171 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1173 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1174 "\t\t vid \t prio \t member \t untag \t fid\n");
1175 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1176 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1177 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1178 vlanmc.vid, vlanmc.priority, vlanmc.member,
1179 vlanmc.untag, vlanmc.fid);
1180 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1181 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1182 "%d \t \t 0x%04x \t 0x%04x \t %d",
1183 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1191 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
1192 const struct switch_attr *attr,
1193 struct switch_val *val)
1195 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1196 struct rtl8366_smi *smi = &rtl->smi;
1199 if (val->port_vlan >= RTL8366_NUM_PORTS)
1202 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1203 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1204 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1205 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1207 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1208 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1209 (val->value.i << (val->port_vlan * 4));
1210 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1216 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
1217 const struct switch_attr *attr,
1218 struct switch_val *val)
1220 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1221 struct rtl8366_smi *smi = &rtl->smi;
1224 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1227 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1228 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1233 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1234 const struct switch_attr *attr,
1235 struct switch_val *val)
1237 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1238 struct rtl8366_smi *smi = &rtl->smi;
1241 if (val->port_vlan >= RTL8366_NUM_PORTS)
1244 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1245 data |= (1 << (val->port_vlan + 3));
1246 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1251 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
1252 const struct switch_attr *attr,
1253 struct switch_val *val)
1255 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1257 unsigned long long counter = 0;
1258 char *buf = rtl->buf;
1260 if (val->port_vlan >= RTL8366_NUM_PORTS)
1263 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1264 "Port %d MIB counters\n",
1267 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1268 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1269 "%d:%s\t", i, rtl8366rb_mib_counters[i].name);
1270 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1271 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1272 "[%llu]\n", counter);
1274 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1283 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1284 struct switch_val *val)
1286 struct rtl8366rb_vlanconfig vlanmc;
1287 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1288 struct switch_port *port;
1291 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1294 rtl8366rb_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1296 port = &val->value.ports[0];
1298 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1299 if (!(vlanmc.member & BIT(i)))
1303 port->flags = (vlanmc.untag & BIT(i)) ?
1304 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1311 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1312 struct switch_val *val)
1314 struct rtl8366rb_vlanconfig vlanmc;
1315 struct rtl8366rb_vlan4kentry vlan4k;
1316 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1317 struct switch_port *port;
1320 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1323 rtl8366rb_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1324 rtl8366rb_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1329 port = &val->value.ports[0];
1330 for (i = 0; i < val->len; i++, port++) {
1331 vlanmc.member |= BIT(port->id);
1333 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1334 vlanmc.untag |= BIT(port->id);
1337 vlan4k.member = vlanmc.member;
1338 vlan4k.untag = vlanmc.untag;
1340 rtl8366rb_set_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1341 rtl8366rb_set_vlan_4k_entry(rtl, &vlan4k);
1345 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1347 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1348 return rtl8366rb_get_vlan_port_pvid(rtl, port, val);
1351 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1353 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1354 return rtl8366rb_set_vlan_port_pvid(rtl, port, val);
1357 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1359 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1362 err = rtl8366rb_reset_chip(rtl);
1366 return rtl8366rb_reset_vlan(rtl);
1369 static struct switch_attr rtl8366rb_globals[] = {
1371 .type = SWITCH_TYPE_INT,
1372 .name = "enable_vlan",
1373 .description = "Enable VLAN mode",
1374 .set = rtl8366rb_sw_set_vlan_enable,
1375 .get = rtl8366rb_sw_get_vlan_enable,
1379 .type = SWITCH_TYPE_INT,
1380 .name = "enable_vlan4k",
1381 .description = "Enable VLAN 4K mode",
1382 .set = rtl8366rb_sw_set_vlan_enable,
1383 .get = rtl8366rb_sw_get_vlan_enable,
1387 .type = SWITCH_TYPE_INT,
1388 .name = "reset_mibs",
1389 .description = "Reset all MIB counters",
1390 .set = rtl8366rb_sw_reset_mibs,
1394 .type = SWITCH_TYPE_INT,
1395 .name = "blinkrate",
1396 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1397 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1398 .set = rtl8366rb_sw_set_blinkrate,
1399 .get = rtl8366rb_sw_get_blinkrate,
1404 static struct switch_attr rtl8366rb_port[] = {
1406 .type = SWITCH_TYPE_STRING,
1408 .description = "Get port link information",
1411 .get = rtl8366rb_sw_get_port_link,
1413 .type = SWITCH_TYPE_INT,
1414 .name = "reset_mib",
1415 .description = "Reset single port MIB counters",
1417 .set = rtl8366rb_sw_reset_port_mibs,
1420 .type = SWITCH_TYPE_STRING,
1422 .description = "Get MIB counters for port",
1425 .get = rtl8366rb_sw_get_port_mib,
1427 .type = SWITCH_TYPE_INT,
1429 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1431 .set = rtl8366rb_sw_set_port_led,
1432 .get = rtl8366rb_sw_get_port_led,
1436 static struct switch_attr rtl8366rb_vlan[] = {
1438 .type = SWITCH_TYPE_STRING,
1440 .description = "Get vlan information",
1443 .get = rtl8366rb_sw_get_vlan_info,
1448 static struct switch_dev rtl8366_switch_dev = {
1450 .cpu_port = RTL8366_PORT_NUM_CPU,
1451 .ports = RTL8366_NUM_PORTS,
1452 .vlans = RTL8366_NUM_VLANS,
1454 .attr = rtl8366rb_globals,
1455 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1458 .attr = rtl8366rb_port,
1459 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1462 .attr = rtl8366rb_vlan,
1463 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1466 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1467 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1468 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1469 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1470 .reset_switch = rtl8366rb_sw_reset_switch,
1473 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1475 struct switch_dev *dev = &rtl->dev;
1478 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1480 dev->devname = dev_name(rtl->parent);
1482 err = register_switch(dev, NULL);
1484 dev_err(rtl->parent, "switch registration failed\n");
1489 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1491 unregister_switch(&rtl->dev);
1494 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1496 struct rtl8366rb *rtl = bus->priv;
1500 err = rtl8366rb_read_phy_reg(rtl, addr, 0, reg, &val);
1507 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1509 struct rtl8366rb *rtl = bus->priv;
1513 err = rtl8366rb_write_phy_reg(rtl, addr, 0, reg, val);
1515 (void) rtl8366rb_read_phy_reg(rtl, addr, 0, reg, &t);
1520 static int rtl8366rb_mii_init(struct rtl8366rb *rtl)
1525 rtl->mii_bus = mdiobus_alloc();
1526 if (rtl->mii_bus == NULL) {
1531 rtl->mii_bus->priv = (void *) rtl;
1532 rtl->mii_bus->name = "rtl8366-rtl";
1533 rtl->mii_bus->read = rtl8366rb_mii_read;
1534 rtl->mii_bus->write = rtl8366rb_mii_write;
1535 snprintf(rtl->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1536 dev_name(rtl->parent));
1537 rtl->mii_bus->parent = rtl->parent;
1538 rtl->mii_bus->phy_mask = ~(0x1f);
1539 rtl->mii_bus->irq = rtl->mii_irq;
1540 for (i = 0; i < PHY_MAX_ADDR; i++)
1541 rtl->mii_irq[i] = PHY_POLL;
1543 ret = mdiobus_register(rtl->mii_bus);
1550 mdiobus_free(rtl->mii_bus);
1555 static void rtl8366rb_mii_cleanup(struct rtl8366rb *rtl)
1557 mdiobus_unregister(rtl->mii_bus);
1558 mdiobus_free(rtl->mii_bus);
1561 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1563 return (bus->read == rtl8366rb_mii_read &&
1564 bus->write == rtl8366rb_mii_write);
1567 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1569 struct rtl8366_smi *smi = &rtl->smi;
1574 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1576 dev_err(rtl->parent, "unable to read chip id\n");
1581 case RTL8366S_CHIP_ID_8366:
1584 dev_err(rtl->parent, "unknown chip id (%04x)\n", chip_id);
1588 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1591 dev_err(rtl->parent, "unable to read chip version\n");
1595 dev_info(rtl->parent, "RTL%04x ver. %u chip found\n",
1596 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1598 ret = rtl8366rb_reset_chip(rtl);
1602 rtl8366rb_debugfs_init(rtl);
1606 static int __init rtl8366rb_probe(struct platform_device *pdev)
1608 static int rtl8366_smi_version_printed;
1609 struct rtl8366rb_platform_data *pdata;
1610 struct rtl8366rb *rtl;
1611 struct rtl8366_smi *smi;
1614 if (!rtl8366_smi_version_printed++)
1615 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1616 " version " RTL8366S_DRIVER_VER"\n");
1618 pdata = pdev->dev.platform_data;
1620 dev_err(&pdev->dev, "no platform data specified\n");
1625 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1627 dev_err(&pdev->dev, "no memory for private data\n");
1632 rtl->parent = &pdev->dev;
1635 smi->parent = &pdev->dev;
1636 smi->gpio_sda = pdata->gpio_sda;
1637 smi->gpio_sck = pdata->gpio_sck;
1639 err = rtl8366_smi_init(smi);
1643 platform_set_drvdata(pdev, rtl);
1645 err = rtl8366rb_setup(rtl);
1647 goto err_clear_drvdata;
1649 err = rtl8366rb_mii_init(rtl);
1651 goto err_clear_drvdata;
1653 err = rtl8366rb_switch_init(rtl);
1655 goto err_mii_cleanup;
1660 rtl8366rb_mii_cleanup(rtl);
1662 platform_set_drvdata(pdev, NULL);
1663 rtl8366_smi_cleanup(smi);
1670 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1672 if (!rtl8366rb_mii_bus_match(phydev->bus))
1678 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1683 static struct phy_driver rtl8366rb_phy_driver = {
1684 .phy_id = 0x001cc960,
1685 .name = "Realtek RTL8366RB",
1686 .phy_id_mask = 0x1ffffff0,
1687 .features = PHY_GBIT_FEATURES,
1688 .config_aneg = rtl8366rb_phy_config_aneg,
1689 .config_init = rtl8366rb_phy_config_init,
1690 .read_status = genphy_read_status,
1692 .owner = THIS_MODULE,
1696 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1698 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1701 rtl8366rb_switch_cleanup(rtl);
1702 rtl8366rb_debugfs_remove(rtl);
1703 rtl8366rb_mii_cleanup(rtl);
1704 platform_set_drvdata(pdev, NULL);
1705 rtl8366_smi_cleanup(&rtl->smi);
1712 static struct platform_driver rtl8366rb_driver = {
1714 .name = RTL8366RB_DRIVER_NAME,
1715 .owner = THIS_MODULE,
1717 .probe = rtl8366rb_probe,
1718 .remove = __devexit_p(rtl8366rb_remove),
1721 static int __init rtl8366rb_module_init(void)
1724 ret = platform_driver_register(&rtl8366rb_driver);
1728 ret = phy_driver_register(&rtl8366rb_phy_driver);
1730 goto err_platform_unregister;
1734 err_platform_unregister:
1735 platform_driver_unregister(&rtl8366rb_driver);
1738 module_init(rtl8366rb_module_init);
1740 static void __exit rtl8366rb_module_exit(void)
1742 phy_driver_unregister(&rtl8366rb_phy_driver);
1743 platform_driver_unregister(&rtl8366rb_driver);
1745 module_exit(rtl8366rb_module_exit);
1747 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1748 MODULE_VERSION(RTL8366S_DRIVER_VER);
1749 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1750 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1751 MODULE_LICENSE("GPL v2");
1752 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);