1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -48,12 +48,12 @@ config BCMA_DRIVER_MIPS
7 - depends on BCMA_DRIVER_MIPS && BROKEN
8 + depends on BCMA_DRIVER_MIPS
13 - depends on BCMA_DRIVER_MIPS && BROKEN
14 + depends on BCMA_DRIVER_MIPS
17 config BCMA_DRIVER_GMAC_CMN
18 @@ -65,6 +65,14 @@ config BCMA_DRIVER_GMAC_CMN
22 +config BCMA_DRIVER_GPIO
23 + bool "BCMA GPIO driver"
24 + depends on BCMA && GPIOLIB
26 + Driver to provide access to the GPIO pins of the bcma bus.
33 --- a/drivers/bcma/Makefile
34 +++ b/drivers/bcma/Makefile
35 @@ -6,6 +6,7 @@ bcma-y += driver_pci.o
36 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
37 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
38 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
39 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
40 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
41 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
42 obj-$(CONFIG_BCMA) += bcma.o
43 --- a/drivers/bcma/bcma_private.h
44 +++ b/drivers/bcma/bcma_private.h
45 @@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc
46 int bcma_bus_suspend(struct bcma_bus *bus);
47 int bcma_bus_resume(struct bcma_bus *bus);
49 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
53 int bcma_bus_scan(struct bcma_bus *bus);
54 @@ -48,12 +50,13 @@ void bcma_chipco_serial_init(struct bcma
55 #endif /* CONFIG_BCMA_DRIVER_MIPS */
57 /* driver_chipcommon_pmu.c */
58 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
59 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
60 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
61 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
63 #ifdef CONFIG_BCMA_SFLASH
64 /* driver_chipcommon_sflash.c */
65 int bcma_sflash_init(struct bcma_drv_cc *cc);
66 +extern struct platform_device bcma_sflash_dev;
68 static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
70 @@ -65,6 +68,7 @@ static inline int bcma_sflash_init(struc
71 #ifdef CONFIG_BCMA_NFLASH
72 /* driver_chipcommon_nflash.c */
73 int bcma_nflash_init(struct bcma_drv_cc *cc);
74 +extern struct platform_device bcma_nflash_dev;
76 static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
78 @@ -82,9 +86,21 @@ extern void __exit bcma_host_pci_exit(vo
80 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
82 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
84 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
85 bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
86 void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
87 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
89 +#ifdef CONFIG_BCMA_DRIVER_GPIO
91 +int bcma_gpio_init(struct bcma_drv_cc *cc);
93 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
97 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
100 --- a/drivers/bcma/core.c
101 +++ b/drivers/bcma/core.c
102 @@ -65,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma
104 case BCMA_CLKMODE_FAST:
105 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
107 + usleep_range(64, 300);
108 for (i = 0; i < 1500; i++) {
109 if (bcma_read32(core, BCMA_CLKCTLST) &
110 BCMA_CLKCTLST_HAVEHT) {
111 --- a/drivers/bcma/driver_chipcommon.c
112 +++ b/drivers/bcma/driver_chipcommon.c
115 * Copyright 2005, Broadcom Corporation
116 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
117 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
119 * Licensed under the GNU/GPL. See COPYING for details.
122 #include "bcma_private.h"
123 +#include <linux/bcm47xx_wdt.h>
124 #include <linux/export.h>
125 +#include <linux/platform_device.h>
126 #include <linux/bcma/bcma.h>
128 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
129 @@ -22,20 +25,120 @@ static inline u32 bcma_cc_write32_masked
133 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
134 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
137 - u32 leddc_off = 90;
138 + if (cc->capabilities & BCMA_CC_CAP_PMU)
139 + return bcma_pmu_get_alp_clock(cc);
141 - if (cc->setup_done)
144 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
146 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
148 + struct bcma_bus *bus = cc->core->bus;
151 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
152 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
154 + else if (cc->core->id.rev < 26)
157 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
164 + return (1 << nb) - 1;
167 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
170 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
172 + return bcma_chipco_watchdog_timer_set(cc, ticks);
175 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
178 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
181 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
182 + return ticks / cc->ticks_per_ms;
185 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
187 + struct bcma_bus *bus = cc->core->bus;
189 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
190 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
191 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
192 + return bcma_chipco_get_alp_clock(cc) / 4000;
194 + /* based on 32KHz ILP clock */
197 + return bcma_chipco_get_alp_clock(cc) / 1000;
201 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
203 + struct bcm47xx_wdt wdt = {};
204 + struct platform_device *pdev;
206 + wdt.driver_data = cc;
207 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
208 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
209 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
211 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
212 + cc->core->bus->num, &wdt,
215 + return PTR_ERR(pdev);
217 + cc->watchdog = pdev;
222 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
224 + if (cc->early_setup_done)
227 + spin_lock_init(&cc->gpio_lock);
229 if (cc->core->id.rev >= 11)
230 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
231 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
232 if (cc->core->id.rev >= 35)
233 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
235 + if (cc->capabilities & BCMA_CC_CAP_PMU)
236 + bcma_pmu_early_init(cc);
238 + cc->early_setup_done = true;
241 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
244 + u32 leddc_off = 90;
246 + if (cc->setup_done)
249 + bcma_core_chipcommon_early_init(cc);
251 if (cc->core->id.rev >= 20) {
252 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
253 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
254 @@ -56,15 +159,33 @@ void bcma_core_chipcommon_init(struct bc
255 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
256 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
258 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
260 cc->setup_done = true;
263 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
264 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
265 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
268 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
270 + enum bcma_clkmode clkmode;
272 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
273 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
276 + else if (ticks > maxt)
278 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
280 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
281 + bcma_core_set_clockmode(cc->core, clkmode);
285 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
290 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
291 @@ -84,28 +205,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
293 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
295 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
296 + unsigned long flags;
299 + spin_lock_irqsave(&cc->gpio_lock, flags);
300 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
301 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
305 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
307 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
309 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
310 + unsigned long flags;
313 + spin_lock_irqsave(&cc->gpio_lock, flags);
314 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
315 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
319 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
322 + * If the bit is set to 0, chipcommon controlls this GPIO,
323 + * if the bit is set to 1, it is used by some part of the chip and not our code.
325 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
327 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
328 + unsigned long flags;
331 + spin_lock_irqsave(&cc->gpio_lock, flags);
332 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
333 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
337 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
339 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
341 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
342 + unsigned long flags;
345 + spin_lock_irqsave(&cc->gpio_lock, flags);
346 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
347 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
352 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
354 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
355 + unsigned long flags;
358 + spin_lock_irqsave(&cc->gpio_lock, flags);
359 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
360 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
365 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
367 + unsigned long flags;
370 + if (cc->core->id.rev < 20)
373 + spin_lock_irqsave(&cc->gpio_lock, flags);
374 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
375 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
380 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
382 + unsigned long flags;
385 + if (cc->core->id.rev < 20)
388 + spin_lock_irqsave(&cc->gpio_lock, flags);
389 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
390 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
395 #ifdef CONFIG_BCMA_DRIVER_MIPS
396 @@ -118,8 +310,7 @@ void bcma_chipco_serial_init(struct bcma
397 struct bcma_serial_port *ports = cc->serial_ports;
399 if (ccrev >= 11 && ccrev != 15) {
400 - /* Fixed ALP clock */
401 - baud_base = bcma_pmu_alp_clock(cc);
402 + baud_base = bcma_chipco_get_alp_clock(cc);
404 /* Turn off UART clock before switching clocksource. */
405 bcma_cc_write32(cc, BCMA_CC_CORECTL,
406 --- a/drivers/bcma/driver_chipcommon_nflash.c
407 +++ b/drivers/bcma/driver_chipcommon_nflash.c
409 * Licensed under the GNU/GPL. See COPYING for details.
412 +#include <linux/platform_device.h>
413 #include <linux/bcma/bcma.h>
414 -#include <linux/bcma/bcma_driver_chipcommon.h>
415 -#include <linux/delay.h>
417 #include "bcma_private.h"
419 +struct platform_device bcma_nflash_dev = {
420 + .name = "bcma_nflash",
421 + .num_resources = 0,
424 /* Initialize NAND flash access */
425 int bcma_nflash_init(struct bcma_drv_cc *cc)
427 - bcma_err(cc->core->bus, "NAND flash support is broken\n");
428 + struct bcma_bus *bus = cc->core->bus;
430 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
431 + cc->core->id.rev != 0x38) {
432 + bcma_err(bus, "NAND flash on unsupported board!\n");
436 + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
437 + bcma_err(bus, "NAND flash not present according to ChipCommon\n");
441 + cc->nflash.present = true;
442 + if (cc->core->id.rev == 38 &&
443 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
444 + cc->nflash.boot = true;
446 + /* Prepare platform device, but don't register it yet. It's too early,
447 + * malloc (required by device_private_init) is not available yet. */
448 + bcma_nflash_dev.dev.platform_data = &cc->nflash;
452 --- a/drivers/bcma/driver_chipcommon_pmu.c
453 +++ b/drivers/bcma/driver_chipcommon_pmu.c
455 #include <linux/export.h>
456 #include <linux/bcma/bcma.h>
458 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
459 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
461 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
462 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
463 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
465 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
467 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
469 @@ -76,7 +77,10 @@ static void bcma_pmu_resources_init(stru
471 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
473 - /* Add some delay; allow resources to come up and settle. */
475 + * Add some delay; allow resources to come up and settle.
476 + * Delay is required for SoC (early init).
481 @@ -101,7 +105,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
482 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
485 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
486 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
488 struct bcma_bus *bus = cc->core->bus;
490 @@ -141,7 +145,7 @@ void bcma_pmu_workarounds(struct bcma_dr
494 -void bcma_pmu_init(struct bcma_drv_cc *cc)
495 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
499 @@ -150,7 +154,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
501 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
502 cc->pmu.rev, pmucap);
505 +void bcma_pmu_init(struct bcma_drv_cc *cc)
507 if (cc->pmu.rev == 1)
508 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
509 ~BCMA_CC_PMU_CTL_NOILPONW);
510 @@ -162,24 +169,40 @@ void bcma_pmu_init(struct bcma_drv_cc *c
511 bcma_pmu_workarounds(cc);
514 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
515 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
517 struct bcma_bus *bus = cc->core->bus;
519 switch (bus->chipinfo.id) {
520 + case BCMA_CHIP_ID_BCM4313:
521 + case BCMA_CHIP_ID_BCM43224:
522 + case BCMA_CHIP_ID_BCM43225:
523 + case BCMA_CHIP_ID_BCM43227:
524 + case BCMA_CHIP_ID_BCM43228:
525 + case BCMA_CHIP_ID_BCM4331:
526 + case BCMA_CHIP_ID_BCM43421:
527 + case BCMA_CHIP_ID_BCM43428:
528 + case BCMA_CHIP_ID_BCM43431:
529 case BCMA_CHIP_ID_BCM4716:
530 - case BCMA_CHIP_ID_BCM4748:
531 case BCMA_CHIP_ID_BCM47162:
532 - case BCMA_CHIP_ID_BCM4313:
533 - case BCMA_CHIP_ID_BCM5357:
534 + case BCMA_CHIP_ID_BCM4748:
535 case BCMA_CHIP_ID_BCM4749:
536 + case BCMA_CHIP_ID_BCM5357:
537 case BCMA_CHIP_ID_BCM53572:
538 + case BCMA_CHIP_ID_BCM6362:
541 - case BCMA_CHIP_ID_BCM5356:
542 case BCMA_CHIP_ID_BCM4706:
543 + case BCMA_CHIP_ID_BCM5356:
546 + case BCMA_CHIP_ID_BCM43460:
547 + case BCMA_CHIP_ID_BCM4352:
548 + case BCMA_CHIP_ID_BCM4360:
549 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
550 + return 40000 * 1000;
552 + return 20000 * 1000;
554 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
555 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
556 @@ -190,7 +213,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
557 /* Find the output of the "m" pll divider given pll controls that start with
558 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
560 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
561 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
563 u32 tmp, div, ndiv, p1, p2, fc;
564 struct bcma_bus *bus = cc->core->bus;
565 @@ -219,14 +242,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
566 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
568 /* Do calculation in Mhz */
569 - fc = bcma_pmu_alp_clock(cc) / 1000000;
570 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
571 fc = (p1 * ndiv * fc) / p2;
573 /* Return clock in Hertz */
574 return (fc / div) * 1000000;
577 -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
578 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
580 u32 tmp, ndiv, p1div, p2div;
582 @@ -257,7 +280,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
585 /* query bus clock frequency for PMU-enabled chipcommon */
586 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
587 +static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
589 struct bcma_bus *bus = cc->core->bus;
591 @@ -265,40 +288,42 @@ u32 bcma_pmu_get_clockcontrol(struct bcm
592 case BCMA_CHIP_ID_BCM4716:
593 case BCMA_CHIP_ID_BCM4748:
594 case BCMA_CHIP_ID_BCM47162:
595 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
596 - BCMA_CC_PMU5_MAINPLL_SSB);
597 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
598 + BCMA_CC_PMU5_MAINPLL_SSB);
599 case BCMA_CHIP_ID_BCM5356:
600 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
601 - BCMA_CC_PMU5_MAINPLL_SSB);
602 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
603 + BCMA_CC_PMU5_MAINPLL_SSB);
604 case BCMA_CHIP_ID_BCM5357:
605 case BCMA_CHIP_ID_BCM4749:
606 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
607 - BCMA_CC_PMU5_MAINPLL_SSB);
608 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
609 + BCMA_CC_PMU5_MAINPLL_SSB);
610 case BCMA_CHIP_ID_BCM4706:
611 - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
612 - BCMA_CC_PMU5_MAINPLL_SSB);
613 + return bcma_pmu_pll_clock_bcm4706(cc,
614 + BCMA_CC_PMU4706_MAINPLL_PLL0,
615 + BCMA_CC_PMU5_MAINPLL_SSB);
616 case BCMA_CHIP_ID_BCM53572:
619 - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
620 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
621 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
623 return BCMA_CC_PMU_HT_CLOCK;
626 /* query cpu clock frequency for PMU-enabled chipcommon */
627 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
628 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
630 struct bcma_bus *bus = cc->core->bus;
632 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
635 + /* New PMUs can have different clock for bus and CPU */
636 if (cc->pmu.rev >= 5) {
638 switch (bus->chipinfo.id) {
639 case BCMA_CHIP_ID_BCM4706:
640 - return bcma_pmu_clock_bcm4706(cc,
641 + return bcma_pmu_pll_clock_bcm4706(cc,
642 BCMA_CC_PMU4706_MAINPLL_PLL0,
643 BCMA_CC_PMU5_MAINPLL_CPU);
644 case BCMA_CHIP_ID_BCM5356:
645 @@ -313,10 +338,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
649 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
650 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
653 - return bcma_pmu_get_clockcontrol(cc);
654 + /* On old PMUs CPU has the same clock as the bus */
655 + return bcma_pmu_get_bus_clock(cc);
658 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
659 @@ -362,7 +388,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
660 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
661 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
664 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
667 case BCMA_CHIP_ID_BCM4331:
668 @@ -383,7 +409,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
669 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
673 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
676 case BCMA_CHIP_ID_BCM43224:
677 @@ -416,7 +442,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
678 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
682 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
685 case BCMA_CHIP_ID_BCM4716:
686 @@ -450,7 +476,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
691 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
694 case BCMA_CHIP_ID_BCM43227:
695 @@ -486,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
696 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
700 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
703 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
704 --- a/drivers/bcma/driver_chipcommon_sflash.c
705 +++ b/drivers/bcma/driver_chipcommon_sflash.c
707 * Licensed under the GNU/GPL. See COPYING for details.
710 +#include <linux/platform_device.h>
711 #include <linux/bcma/bcma.h>
712 -#include <linux/bcma/bcma_driver_chipcommon.h>
713 -#include <linux/delay.h>
715 #include "bcma_private.h"
717 +static struct resource bcma_sflash_resource = {
718 + .name = "bcma_sflash",
719 + .start = BCMA_SOC_FLASH2,
721 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
724 +struct platform_device bcma_sflash_dev = {
725 + .name = "bcma_sflash",
726 + .resource = &bcma_sflash_resource,
727 + .num_resources = 1,
730 +struct bcma_sflash_tbl_e {
737 +static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
738 + { "M25P20", 0x11, 0x10000, 4, },
739 + { "M25P40", 0x12, 0x10000, 8, },
741 + { "M25P16", 0x14, 0x10000, 32, },
742 + { "M25P32", 0x15, 0x10000, 64, },
743 + { "M25P64", 0x16, 0x10000, 128, },
744 + { "M25FL128", 0x17, 0x10000, 256, },
748 +static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
749 + { "SST25WF512", 1, 0x1000, 16, },
750 + { "SST25VF512", 0x48, 0x1000, 16, },
751 + { "SST25WF010", 2, 0x1000, 32, },
752 + { "SST25VF010", 0x49, 0x1000, 32, },
753 + { "SST25WF020", 3, 0x1000, 64, },
754 + { "SST25VF020", 0x43, 0x1000, 64, },
755 + { "SST25WF040", 4, 0x1000, 128, },
756 + { "SST25VF040", 0x44, 0x1000, 128, },
757 + { "SST25VF040B", 0x8d, 0x1000, 128, },
758 + { "SST25WF080", 5, 0x1000, 256, },
759 + { "SST25VF080B", 0x8e, 0x1000, 256, },
760 + { "SST25VF016", 0x41, 0x1000, 512, },
761 + { "SST25VF032", 0x4a, 0x1000, 1024, },
762 + { "SST25VF064", 0x4b, 0x1000, 2048, },
766 +static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
767 + { "AT45DB011", 0xc, 256, 512, },
768 + { "AT45DB021", 0x14, 256, 1024, },
769 + { "AT45DB041", 0x1c, 256, 2048, },
770 + { "AT45DB081", 0x24, 256, 4096, },
771 + { "AT45DB161", 0x2c, 512, 4096, },
772 + { "AT45DB321", 0x34, 512, 8192, },
773 + { "AT45DB642", 0x3c, 1024, 8192, },
777 +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
780 + bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
781 + BCMA_CC_FLASHCTL_START | opcode);
782 + for (i = 0; i < 1000; i++) {
783 + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
784 + BCMA_CC_FLASHCTL_BUSY))
788 + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
791 /* Initialize serial flash access */
792 int bcma_sflash_init(struct bcma_drv_cc *cc)
794 - bcma_err(cc->core->bus, "Serial flash support is broken\n");
795 + struct bcma_bus *bus = cc->core->bus;
796 + struct bcma_sflash *sflash = &cc->sflash;
797 + struct bcma_sflash_tbl_e *e;
800 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
801 + case BCMA_CC_FLASHT_STSER:
802 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
804 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
805 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
806 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
808 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
809 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
810 + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
814 + for (e = bcma_sflash_sst_tbl; e->name; e++) {
822 + for (e = bcma_sflash_st_tbl; e->name; e++) {
829 + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
834 + case BCMA_CC_FLASHT_ATSER:
835 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
836 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
838 + for (e = bcma_sflash_at_tbl; e->name; e++) {
843 + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
849 + bcma_err(bus, "Unsupported flash type\n");
853 + sflash->window = BCMA_SOC_FLASH2;
854 + sflash->blocksize = e->blocksize;
855 + sflash->numblocks = e->numblocks;
856 + sflash->size = sflash->blocksize * sflash->numblocks;
857 + sflash->present = true;
859 + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
860 + e->name, sflash->size / 1024, sflash->blocksize,
861 + sflash->numblocks);
863 + /* Prepare platform device, but don't register it yet. It's too early,
864 + * malloc (required by device_private_init) is not available yet. */
865 + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
867 + bcma_sflash_dev.dev.platform_data = sflash;
872 +++ b/drivers/bcma/driver_gpio.c
875 + * Broadcom specific AMBA
878 + * Copyright 2011, Broadcom Corporation
879 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
881 + * Licensed under the GNU/GPL. See COPYING for details.
884 +#include <linux/gpio.h>
885 +#include <linux/export.h>
886 +#include <linux/bcma/bcma.h>
888 +#include "bcma_private.h"
890 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
892 + return container_of(chip, struct bcma_drv_cc, gpio);
895 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
897 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
899 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
902 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
905 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
907 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
910 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
912 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
914 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
918 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
921 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
923 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
924 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
928 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
930 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
932 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
933 + /* clear pulldown */
934 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
936 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
941 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
943 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
946 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
949 +int bcma_gpio_init(struct bcma_drv_cc *cc)
951 + struct gpio_chip *chip = &cc->gpio;
953 + chip->label = "bcma_gpio";
954 + chip->owner = THIS_MODULE;
955 + chip->request = bcma_gpio_request;
956 + chip->free = bcma_gpio_free;
957 + chip->get = bcma_gpio_get_value;
958 + chip->set = bcma_gpio_set_value;
959 + chip->direction_input = bcma_gpio_direction_input;
960 + chip->direction_output = bcma_gpio_direction_output;
962 + /* There is just one SoC in one device and its GPIO addresses should be
963 + * deterministic to address them more easily. The other buses could get
964 + * a random base number. */
965 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
970 + return gpiochip_add(chip);
972 --- a/drivers/bcma/driver_mips.c
973 +++ b/drivers/bcma/driver_mips.c
974 @@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct
975 return dev->core_index;
976 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
978 - return flag & 0x1F;
980 + return flag & 0x1F;
985 /* Get the MIPS IRQ assignment for a specified device.
986 * If unassigned, 0 is returned.
987 + * If disabled, 5 is returned.
988 + * If not supported, 6 is returned.
990 unsigned int bcma_core_mips_irq(struct bcma_device *dev)
992 @@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b
995 irqflag = bcma_core_mips_irqflag(dev);
996 + if (irqflag == 0x3f)
999 - for (irq = 1; irq <= 4; irq++)
1000 + for (irq = 0; irq <= 4; irq++)
1001 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
1008 EXPORT_SYMBOL(bcma_core_mips_irq);
1010 @@ -114,8 +121,8 @@ static void bcma_core_mips_set_irq(struc
1011 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
1012 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
1015 - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
1016 + else if (oldirq != 5)
1017 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
1019 /* assign the new one */
1021 @@ -123,9 +130,9 @@ static void bcma_core_mips_set_irq(struc
1022 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
1025 - u32 oldirqflag = bcma_read32(mdev,
1026 - BCMA_MIPS_MIPS74K_INTMASK(irq));
1028 + u32 irqinitmask = bcma_read32(mdev,
1029 + BCMA_MIPS_MIPS74K_INTMASK(irq));
1030 + if (irqinitmask) {
1031 struct bcma_device *core;
1033 /* backplane irq line is in use, find out who uses
1034 @@ -133,7 +140,7 @@ static void bcma_core_mips_set_irq(struc
1036 list_for_each_entry(core, &bus->cores, list) {
1037 if ((1 << bcma_core_mips_irqflag(core)) ==
1040 bcma_core_mips_set_irq(core, 0);
1043 @@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc
1047 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1048 - dev->id.id, oldirq + 2, irq + 2);
1049 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1050 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
1053 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
1054 + u16 coreid, u8 unit)
1056 + struct bcma_device *core;
1058 + core = bcma_find_core_unit(bus, coreid, unit);
1061 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
1066 + bcma_core_mips_set_irq(core, irq);
1069 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
1072 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1073 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1074 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1075 for (i = 0; i <= 6; i++)
1076 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
1078 @@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1079 struct bcma_bus *bus = mcore->core->bus;
1081 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
1082 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
1083 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
1085 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
1087 @@ -181,85 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock);
1088 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1090 struct bcma_bus *bus = mcore->core->bus;
1091 + struct bcma_drv_cc *cc = &bus->drv_cc;
1093 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
1094 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1095 case BCMA_CC_FLASHT_STSER:
1096 case BCMA_CC_FLASHT_ATSER:
1097 bcma_debug(bus, "Found serial flash\n");
1098 - bcma_sflash_init(&bus->drv_cc);
1099 + bcma_sflash_init(cc);
1101 case BCMA_CC_FLASHT_PARA:
1102 bcma_debug(bus, "Found parallel flash\n");
1103 - bus->drv_cc.pflash.window = 0x1c000000;
1104 - bus->drv_cc.pflash.window_size = 0x02000000;
1105 + cc->pflash.present = true;
1106 + cc->pflash.window = BCMA_SOC_FLASH2;
1107 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
1109 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
1110 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
1111 BCMA_CC_FLASH_CFG_DS) == 0)
1112 - bus->drv_cc.pflash.buswidth = 1;
1113 + cc->pflash.buswidth = 1;
1115 - bus->drv_cc.pflash.buswidth = 2;
1116 + cc->pflash.buswidth = 2;
1119 bcma_err(bus, "Flash type not supported\n");
1122 - if (bus->drv_cc.core->id.rev == 38 ||
1123 + if (cc->core->id.rev == 38 ||
1124 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1125 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
1126 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
1127 bcma_debug(bus, "Found NAND flash\n");
1128 - bcma_nflash_init(&bus->drv_cc);
1129 + bcma_nflash_init(cc);
1134 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1136 + struct bcma_bus *bus = mcore->core->bus;
1138 + if (mcore->early_setup_done)
1141 + bcma_chipco_serial_init(&bus->drv_cc);
1142 + bcma_core_mips_flash_detect(mcore);
1144 + mcore->early_setup_done = true;
1147 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
1149 struct bcma_bus *bus;
1150 struct bcma_device *core;
1151 bus = mcore->core->bus;
1153 - bcma_info(bus, "Initializing MIPS core...\n");
1154 + if (mcore->setup_done)
1157 - if (!mcore->setup_done)
1158 - mcore->assigned_irqs = 1;
1159 + bcma_debug(bus, "Initializing MIPS core...\n");
1161 - /* Assign IRQs to all cores on the bus */
1162 - list_for_each_entry(core, &bus->cores, list) {
1167 - mips_irq = bcma_core_mips_irq(core);
1171 - core->irq = mips_irq + 2;
1172 - if (core->irq > 5)
1174 - switch (core->id.id) {
1175 - case BCMA_CORE_PCI:
1176 - case BCMA_CORE_PCIE:
1177 - case BCMA_CORE_ETHERNET:
1178 - case BCMA_CORE_ETHERNET_GBIT:
1179 - case BCMA_CORE_MAC_GBIT:
1180 - case BCMA_CORE_80211:
1181 - case BCMA_CORE_USB20_HOST:
1182 - /* These devices get their own IRQ line if available,
1183 - * the rest goes on IRQ0
1185 - if (mcore->assigned_irqs <= 4)
1186 - bcma_core_mips_set_irq(core,
1187 - mcore->assigned_irqs++);
1189 + bcma_core_mips_early_init(mcore);
1191 + switch (bus->chipinfo.id) {
1192 + case BCMA_CHIP_ID_BCM4716:
1193 + case BCMA_CHIP_ID_BCM4748:
1194 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1195 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1196 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1197 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
1198 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1199 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1201 + case BCMA_CHIP_ID_BCM5356:
1202 + case BCMA_CHIP_ID_BCM47162:
1203 + case BCMA_CHIP_ID_BCM53572:
1204 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1205 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1206 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1208 + case BCMA_CHIP_ID_BCM5357:
1209 + case BCMA_CHIP_ID_BCM4749:
1210 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1211 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1212 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1213 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1214 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1216 + case BCMA_CHIP_ID_BCM4706:
1217 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
1218 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
1220 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
1221 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
1222 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
1226 + list_for_each_entry(core, &bus->cores, list) {
1227 + core->irq = bcma_core_mips_irq(core) + 2;
1230 + "Unknown device (0x%x) found, can not configure IRQs\n",
1231 + bus->chipinfo.id);
1233 - bcma_info(bus, "IRQ reconfiguration done\n");
1234 + bcma_debug(bus, "IRQ reconfiguration done\n");
1235 bcma_core_mips_dump_irq(bus);
1237 - if (mcore->setup_done)
1240 - bcma_chipco_serial_init(&bus->drv_cc);
1241 - bcma_core_mips_flash_detect(mcore);
1242 mcore->setup_done = true;
1244 --- a/drivers/bcma/driver_pci.c
1245 +++ b/drivers/bcma/driver_pci.c
1246 @@ -51,7 +51,7 @@ static void bcma_pcie_mdio_set_phy(struc
1247 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1248 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1251 + usleep_range(1000, 2000);
1255 @@ -92,7 +92,7 @@ static u16 bcma_pcie_mdio_read(struct bc
1256 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
1260 + usleep_range(1000, 2000);
1262 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1264 @@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct
1265 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1266 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1269 + usleep_range(1000, 2000);
1271 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1273 --- a/drivers/bcma/driver_pci_host.c
1274 +++ b/drivers/bcma/driver_pci_host.c
1275 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
1276 chipid_top != 0x5300)
1279 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1280 - bcma_info(bus, "This PCI core is disabled and not working\n");
1284 bcma_core_enable(pc->core, 0);
1286 return !mips_busprobe32(tmp, pc->core->io_addr);
1287 @@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
1289 bcma_info(bus, "PCIEcore in host mode found\n");
1291 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1292 + bcma_info(bus, "This PCIE core is disabled and not working\n");
1296 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
1298 bcma_err(bus, "can not allocate memory");
1299 @@ -425,9 +425,9 @@ void __devinit bcma_core_pci_hostmode_in
1300 pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
1304 + usleep_range(3000, 5000);
1305 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
1307 + usleep_range(1000, 2000);
1308 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
1309 BCMA_CORE_PCI_CTL_RST_OE);
1311 @@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
1312 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1313 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1314 BCMA_SOC_PCI_MEM_SZ - 1;
1315 + pc_host->io_resource.start = 0x100;
1316 + pc_host->io_resource.end = 0x47F;
1317 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1318 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1319 tmp | BCMA_SOC_PCI_MEM);
1320 @@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
1321 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1322 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1323 BCMA_SOC_PCI_MEM_SZ - 1;
1324 + pc_host->io_resource.start = 0x480;
1325 + pc_host->io_resource.end = 0x7FF;
1326 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1327 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1328 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1329 @@ -481,7 +485,7 @@ void __devinit bcma_core_pci_hostmode_in
1330 * before issuing configuration requests to PCI Express
1336 bcma_core_pci_enable_crs(pc);
1338 @@ -501,7 +505,7 @@ void __devinit bcma_core_pci_hostmode_in
1339 set_io_port_base(pc_host->pci_controller.io_map_base);
1340 /* Give some time to the PCI controller to configure itself with the new
1341 * values. Not waiting at this point causes crashes of the machine. */
1343 + usleep_range(10000, 15000);
1344 register_pci_controller(&pc_host->pci_controller);
1347 @@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
1348 static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1350 struct resource *res;
1354 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1355 /* This is not a device on the PCI-core bridge. */
1356 @@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse
1358 for (pos = 0; pos < 6; pos++) {
1359 res = &dev->resource[pos];
1360 - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1361 - pci_assign_resource(dev, pos);
1362 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
1363 + err = pci_assign_resource(dev, pos);
1365 + pr_err("PCI: Problem fixing up the addresses on %s\n",
1370 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1371 --- a/drivers/bcma/host_pci.c
1372 +++ b/drivers/bcma/host_pci.c
1373 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
1376 #ifdef CONFIG_BCMA_BLOCKIO
1377 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
1378 - size_t count, u16 offset, u8 reg_width)
1379 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
1380 + size_t count, u16 offset, u8 reg_width)
1382 void __iomem *addr = core->bus->mmio + offset;
1383 if (core->bus->mapped_core != core)
1384 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
1388 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
1389 - size_t count, u16 offset, u8 reg_width)
1390 +static void bcma_host_pci_block_write(struct bcma_device *core,
1391 + const void *buffer, size_t count,
1392 + u16 offset, u8 reg_width)
1394 void __iomem *addr = core->bus->mmio + offset;
1395 if (core->bus->mapped_core != core)
1396 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
1397 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
1400 -const struct bcma_host_ops bcma_host_pci_ops = {
1401 +static const struct bcma_host_ops bcma_host_pci_ops = {
1402 .read8 = bcma_host_pci_read8,
1403 .read16 = bcma_host_pci_read16,
1404 .read32 = bcma_host_pci_read32,
1405 @@ -237,7 +238,7 @@ static void __devexit bcma_host_pci_remo
1406 pci_set_drvdata(dev, NULL);
1410 +#ifdef CONFIG_PM_SLEEP
1411 static int bcma_host_pci_suspend(struct device *dev)
1413 struct pci_dev *pdev = to_pci_dev(dev);
1414 @@ -260,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
1415 bcma_host_pci_resume);
1416 #define BCMA_PM_OPS (&bcma_pm_ops)
1418 -#else /* CONFIG_PM */
1419 +#else /* CONFIG_PM_SLEEP */
1421 #define BCMA_PM_OPS NULL
1423 -#endif /* CONFIG_PM */
1424 +#endif /* CONFIG_PM_SLEEP */
1426 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1427 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1428 @@ -272,6 +273,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
1429 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
1430 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
1431 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1432 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
1433 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
1434 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
1436 --- a/drivers/bcma/host_soc.c
1437 +++ b/drivers/bcma/host_soc.c
1438 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
1439 writel(value, core->io_wrap + offset);
1442 -const struct bcma_host_ops bcma_host_soc_ops = {
1443 +static const struct bcma_host_ops bcma_host_soc_ops = {
1444 .read8 = bcma_host_soc_read8,
1445 .read16 = bcma_host_soc_read16,
1446 .read32 = bcma_host_soc_read32,
1447 --- a/drivers/bcma/main.c
1448 +++ b/drivers/bcma/main.c
1451 #include "bcma_private.h"
1452 #include <linux/module.h>
1453 +#include <linux/platform_device.h>
1454 #include <linux/bcma/bcma.h>
1455 #include <linux/slab.h>
1457 @@ -80,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
1459 EXPORT_SYMBOL_GPL(bcma_find_core);
1461 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1464 + struct bcma_device *core;
1466 + list_for_each_entry(core, &bus->cores, list) {
1467 + if (core->id.id == coreid && core->core_unit == unit)
1473 static void bcma_release_core_dev(struct device *dev)
1475 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1476 @@ -136,6 +149,33 @@ static int bcma_register_cores(struct bc
1480 +#ifdef CONFIG_BCMA_SFLASH
1481 + if (bus->drv_cc.sflash.present) {
1482 + err = platform_device_register(&bcma_sflash_dev);
1484 + bcma_err(bus, "Error registering serial flash\n");
1488 +#ifdef CONFIG_BCMA_NFLASH
1489 + if (bus->drv_cc.nflash.present) {
1490 + err = platform_device_register(&bcma_nflash_dev);
1492 + bcma_err(bus, "Error registering NAND flash\n");
1495 + err = bcma_gpio_init(&bus->drv_cc);
1496 + if (err == -ENOTSUPP)
1497 + bcma_debug(bus, "GPIO driver not activated\n");
1499 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
1501 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1502 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
1504 + bcma_err(bus, "Error registering watchdog driver\n");
1510 @@ -148,6 +188,8 @@ static void bcma_unregister_cores(struct
1511 if (core->dev_registered)
1512 device_unregister(&core->dev);
1514 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
1515 + platform_device_unregister(bus->drv_cc.watchdog);
1518 int __devinit bcma_bus_register(struct bcma_bus *bus)
1519 @@ -166,6 +208,20 @@ int __devinit bcma_bus_register(struct b
1523 + /* Early init CC core */
1524 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
1526 + bus->drv_cc.core = core;
1527 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1530 + /* Try to get SPROM */
1531 + err = bcma_sprom_get(bus);
1532 + if (err == -ENOENT) {
1533 + bcma_err(bus, "No SPROM available\n");
1535 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
1538 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1540 @@ -181,10 +237,17 @@ int __devinit bcma_bus_register(struct b
1543 /* Init PCIE core */
1544 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
1545 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
1547 + bus->drv_pci[0].core = core;
1548 + bcma_core_pci_init(&bus->drv_pci[0]);
1551 + /* Init PCIE core */
1552 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
1554 - bus->drv_pci.core = core;
1555 - bcma_core_pci_init(&bus->drv_pci);
1556 + bus->drv_pci[1].core = core;
1557 + bcma_core_pci_init(&bus->drv_pci[1]);
1560 /* Init GBIT MAC COMMON core */
1561 @@ -194,13 +257,6 @@ int __devinit bcma_bus_register(struct b
1562 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
1565 - /* Try to get SPROM */
1566 - err = bcma_sprom_get(bus);
1567 - if (err == -ENOENT) {
1568 - bcma_err(bus, "No SPROM available\n");
1570 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
1572 /* Register found cores */
1573 bcma_register_cores(bus);
1575 @@ -211,7 +267,17 @@ int __devinit bcma_bus_register(struct b
1577 void bcma_bus_unregister(struct bcma_bus *bus)
1579 + struct bcma_device *cores[3];
1581 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1582 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
1583 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1585 bcma_unregister_cores(bus);
1592 int __init bcma_bus_early_register(struct bcma_bus *bus,
1593 @@ -248,18 +314,18 @@ int __init bcma_bus_early_register(struc
1597 - /* Init CC core */
1598 + /* Early init CC core */
1599 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1601 bus->drv_cc.core = core;
1602 - bcma_core_chipcommon_init(&bus->drv_cc);
1603 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1606 - /* Init MIPS core */
1607 + /* Early init MIPS core */
1608 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1610 bus->drv_mips.core = core;
1611 - bcma_core_mips_init(&bus->drv_mips);
1612 + bcma_core_mips_early_init(&bus->drv_mips);
1615 bcma_info(bus, "Early bus registered\n");
1616 --- a/drivers/bcma/sprom.c
1617 +++ b/drivers/bcma/sprom.c
1618 @@ -507,7 +507,9 @@ static bool bcma_sprom_onchip_available(
1619 /* for these chips OTP is always available */
1622 + case BCMA_CHIP_ID_BCM43227:
1623 case BCMA_CHIP_ID_BCM43228:
1624 + case BCMA_CHIP_ID_BCM43428:
1625 present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
1628 @@ -593,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
1629 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1631 err = bcma_sprom_valid(sprom);
1634 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1635 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1639 bcma_sprom_extract_r8(bus, sprom);
1641 --- a/include/linux/bcma/bcma.h
1642 +++ b/include/linux/bcma/bcma.h
1644 #include <linux/bcma/bcma_driver_gmac_cmn.h>
1645 #include <linux/ssb/ssb.h> /* SPROM sharing */
1647 -#include "bcma_regs.h"
1648 +#include <linux/bcma/bcma_regs.h>
1652 @@ -134,6 +134,7 @@ struct bcma_host_ops {
1653 #define BCMA_CORE_I2S 0x834
1654 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
1655 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
1656 +#define BCMA_CORE_ARM_CR4 0x83e
1657 #define BCMA_CORE_DEFAULT 0xFFF
1659 #define BCMA_MAX_NR_CORES 16
1660 @@ -157,6 +158,7 @@ struct bcma_host_ops {
1662 /* Chip IDs of SoCs */
1663 #define BCMA_CHIP_ID_BCM4706 0x5300
1664 +#define BCMA_PKG_ID_BCM4706L 1
1665 #define BCMA_CHIP_ID_BCM4716 0x4716
1666 #define BCMA_PKG_ID_BCM4716 8
1667 #define BCMA_PKG_ID_BCM4717 9
1668 @@ -166,7 +168,11 @@ struct bcma_host_ops {
1669 #define BCMA_CHIP_ID_BCM4749 0x4749
1670 #define BCMA_CHIP_ID_BCM5356 0x5356
1671 #define BCMA_CHIP_ID_BCM5357 0x5357
1672 +#define BCMA_PKG_ID_BCM5358 9
1673 +#define BCMA_PKG_ID_BCM47186 10
1674 +#define BCMA_PKG_ID_BCM5357 11
1675 #define BCMA_CHIP_ID_BCM53572 53572
1676 +#define BCMA_PKG_ID_BCM47188 9
1678 struct bcma_device {
1679 struct bcma_bus *bus;
1680 @@ -251,7 +257,7 @@ struct bcma_bus {
1683 struct bcma_drv_cc drv_cc;
1684 - struct bcma_drv_pci drv_pci;
1685 + struct bcma_drv_pci drv_pci[2];
1686 struct bcma_drv_mips drv_mips;
1687 struct bcma_drv_gmac_cmn drv_gmac_cmn;
1689 @@ -345,6 +351,7 @@ extern void bcma_core_set_clockmode(stru
1690 enum bcma_clkmode clkmode);
1691 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
1693 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
1694 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
1695 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
1696 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
1697 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1698 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1700 #ifndef LINUX_BCMA_DRIVER_CC_H_
1701 #define LINUX_BCMA_DRIVER_CC_H_
1703 +#include <linux/platform_device.h>
1704 +#include <linux/gpio.h>
1706 /** ChipCommon core registers. **/
1707 #define BCMA_CC_ID 0x0000
1708 #define BCMA_CC_ID_ID 0x0000FFFF
1710 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
1711 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
1712 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
1713 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
1714 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
1715 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
1716 #define BCMA_CC_JCMD_START 0x80000000
1717 #define BCMA_CC_JCMD_BUSY 0x80000000
1718 @@ -266,6 +271,29 @@
1719 #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
1720 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
1721 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
1722 +/* Block 0x140 - 0x190 registers are chipset specific */
1723 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
1724 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
1725 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
1726 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
1727 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
1728 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
1729 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
1730 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
1731 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
1732 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
1733 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
1734 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
1735 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
1736 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
1737 +/* NAND flash registers for BCM4706 (corerev = 31) */
1738 +#define BCMA_CC_NFLASH_CTL 0x01A0
1739 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
1740 +#define BCMA_CC_NFLASH_CONF 0x01A4
1741 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
1742 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
1743 +#define BCMA_CC_NFLASH_DATA 0x01B0
1744 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
1745 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
1746 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1747 #define BCMA_CC_UART0_DATA 0x0300
1749 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
1750 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
1751 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
1752 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
1753 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
1754 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
1755 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
1756 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
1757 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
1758 @@ -325,6 +356,60 @@
1759 #define BCMA_CC_PLLCTL_ADDR 0x0660
1760 #define BCMA_CC_PLLCTL_DATA 0x0664
1761 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1762 +/* NAND flash MLC controller registers (corerev >= 38) */
1763 +#define BCMA_CC_NAND_REVISION 0x0C00
1764 +#define BCMA_CC_NAND_CMD_START 0x0C04
1765 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
1766 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
1767 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
1768 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
1769 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
1770 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
1771 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
1772 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
1773 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
1774 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
1775 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
1776 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
1777 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
1778 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
1779 +#define BCMA_CC_NAND_CONFIG 0x0C48
1780 +#define BCMA_CC_NAND_TIMING_1 0x0C50
1781 +#define BCMA_CC_NAND_TIMING_2 0x0C54
1782 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
1783 +#define BCMA_CC_NAND_DEVID 0x0C60
1784 +#define BCMA_CC_NAND_DEVID_X 0x0C64
1785 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
1786 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
1787 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
1788 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
1789 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
1790 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
1791 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
1792 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
1793 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
1794 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
1795 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
1796 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
1797 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
1798 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
1799 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
1800 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
1801 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
1802 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
1803 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
1804 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
1805 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
1806 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
1807 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
1808 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
1809 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
1810 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
1811 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
1812 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
1813 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
1814 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
1815 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
1817 /* Divider allocation in 4716/47162/5356 */
1818 #define BCMA_CC_PMU5_MAINPLL_CPU 1
1819 @@ -415,6 +500,13 @@
1820 /* 4313 Chip specific ChipControl register bits */
1821 #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
1823 +/* BCM5357 ChipControl register bits */
1824 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
1825 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
1826 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
1827 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
1828 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
1830 /* Data for the PMU, if available.
1831 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1833 @@ -425,11 +517,35 @@ struct bcma_chipcommon_pmu {
1835 #ifdef CONFIG_BCMA_DRIVER_MIPS
1836 struct bcma_pflash {
1843 +#ifdef CONFIG_BCMA_SFLASH
1844 +struct bcma_sflash {
1851 + struct mtd_info *mtd;
1855 +#ifdef CONFIG_BCMA_NFLASH
1858 +struct bcma_nflash {
1860 + bool boot; /* This is the flash the SoC boots from */
1862 + struct mtd_info *mtd;
1866 struct bcma_serial_port {
1868 unsigned long clockspeed;
1869 @@ -445,15 +561,30 @@ struct bcma_drv_cc {
1871 u32 capabilities_ext;
1873 + u8 early_setup_done:1;
1874 /* Fast Powerup Delay constant */
1875 u16 fast_pwrup_delay;
1876 struct bcma_chipcommon_pmu pmu;
1877 #ifdef CONFIG_BCMA_DRIVER_MIPS
1878 struct bcma_pflash pflash;
1879 +#ifdef CONFIG_BCMA_SFLASH
1880 + struct bcma_sflash sflash;
1882 +#ifdef CONFIG_BCMA_NFLASH
1883 + struct bcma_nflash nflash;
1886 int nr_serial_ports;
1887 struct bcma_serial_port serial_ports[4];
1888 #endif /* CONFIG_BCMA_DRIVER_MIPS */
1890 + struct platform_device *watchdog;
1892 + /* Lock for GPIO register access. */
1893 + spinlock_t gpio_lock;
1894 +#ifdef CONFIG_BCMA_DRIVER_GPIO
1895 + struct gpio_chip gpio;
1899 /* Register access */
1900 @@ -470,14 +601,16 @@ struct bcma_drv_cc {
1901 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
1903 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
1904 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
1906 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
1907 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
1909 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
1911 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
1913 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
1915 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
1917 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1919 @@ -490,9 +623,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
1920 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
1921 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1922 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
1923 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
1924 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
1927 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
1928 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
1930 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
1932 --- a/include/linux/bcma/bcma_driver_mips.h
1933 +++ b/include/linux/bcma/bcma_driver_mips.h
1934 @@ -35,13 +35,15 @@ struct bcma_device;
1935 struct bcma_drv_mips {
1936 struct bcma_device *core;
1938 - unsigned int assigned_irqs;
1939 + u8 early_setup_done:1;
1942 #ifdef CONFIG_BCMA_DRIVER_MIPS
1943 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
1944 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
1946 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
1947 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
1950 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
1951 --- a/include/linux/bcma/bcma_regs.h
1952 +++ b/include/linux/bcma/bcma_regs.h
1954 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1955 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1956 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
1957 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
1958 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1959 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1960 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
1961 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
1962 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
1963 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
1964 /* Is there any BCM4328 on BCMA bus? */
1965 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1966 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1968 #define BCMA_IOST_BIST_DONE 0x8000
1969 #define BCMA_RESET_CTL 0x0800
1970 #define BCMA_RESET_CTL_RESET 0x0001
1971 +#define BCMA_RESET_ST 0x0804
1973 /* BCMA PCI config space registers. */
1974 #define BCMA_PCI_PMCSR 0x44
1976 * (2 ZettaBytes), high 32 bits
1979 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
1980 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
1981 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
1982 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
1984 #endif /* LINUX_BCMA_REGS_H_ */
1985 --- a/drivers/net/wireless/b43/main.c
1986 +++ b/drivers/net/wireless/b43/main.c
1987 @@ -4622,7 +4622,7 @@ static int b43_wireless_core_init(struct
1988 switch (dev->dev->bus_type) {
1989 #ifdef CONFIG_B43_BCMA
1991 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
1992 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
1993 dev->dev->bdev, true);
1996 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1997 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1998 @@ -695,7 +695,7 @@ void ai_pci_up(struct si_pub *sih)
1999 sii = container_of(sih, struct si_info, pub);
2001 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
2002 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
2003 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
2006 /* Unconfigure and/or apply various WARs when going down */
2007 @@ -706,7 +706,7 @@ void ai_pci_down(struct si_pub *sih)
2008 sii = container_of(sih, struct si_info, pub);
2010 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
2011 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
2012 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
2015 /* Enable BT-COEX & Ex-PA for 4313 */
2016 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
2017 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
2018 @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
2019 * Configure pci/pcmcia here instead of in brcms_c_attach()
2020 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
2022 - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
2023 + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,