1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -29,7 +29,7 @@ config BCMA_HOST_PCI
5 config BCMA_DRIVER_PCI_HOSTMODE
6 bool "Driver for PCI core working in hostmode"
7 - depends on BCMA && MIPS
8 + depends on BCMA && MIPS && BCMA_HOST_PCI
10 PCI core hostmode operation (external PCI bus).
12 --- a/drivers/bcma/bcma_private.h
13 +++ b/drivers/bcma/bcma_private.h
18 -int bcma_bus_register(struct bcma_bus *bus);
19 +int __devinit bcma_bus_register(struct bcma_bus *bus);
20 void bcma_bus_unregister(struct bcma_bus *bus);
21 int __init bcma_bus_early_register(struct bcma_bus *bus,
22 struct bcma_device *core_cc,
23 @@ -48,8 +48,12 @@ extern int __init bcma_host_pci_init(voi
24 extern void __exit bcma_host_pci_exit(void);
25 #endif /* CONFIG_BCMA_HOST_PCI */
28 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
30 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
31 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
32 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
33 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
34 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
37 --- a/drivers/bcma/core.c
38 +++ b/drivers/bcma/core.c
39 @@ -30,6 +30,7 @@ void bcma_core_disable(struct bcma_devic
42 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
43 + bcma_aread32(core, BCMA_RESET_CTL);
46 EXPORT_SYMBOL_GPL(bcma_core_disable);
47 @@ -77,7 +78,7 @@ void bcma_core_set_clockmode(struct bcma
48 pr_err("HT force timeout\n");
50 case BCMA_CLKMODE_DYNAMIC:
51 - pr_warn("Dynamic clockmode not supported yet!\n");
52 + bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
56 --- a/drivers/bcma/driver_chipcommon_pmu.c
57 +++ b/drivers/bcma/driver_chipcommon_pmu.c
59 * ChipCommon Power Management Unit driver
61 * Copyright 2009, Michael Buesch <m@bues.ch>
62 - * Copyright 2007, Broadcom Corporation
63 + * Copyright 2007, 2011, Broadcom Corporation
64 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
66 * Licensed under the GNU/GPL. See COPYING for details.
68 @@ -54,38 +55,19 @@ void bcma_chipco_regctl_maskset(struct b
70 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
72 -static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
74 - struct bcma_bus *bus = cc->core->bus;
76 - switch (bus->chipinfo.id) {
83 - pr_err("PLL init unknown for device 0x%04X\n",
88 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
90 struct bcma_bus *bus = cc->core->bus;
91 u32 min_msk = 0, max_msk = 0;
93 switch (bus->chipinfo.id) {
95 + case BCMA_CHIP_ID_BCM4313:
103 - pr_err("PMU resource config unknown for device 0x%04X\n",
105 + pr_debug("PMU resource config unknown or not needed for device 0x%04X\n",
109 /* Set the resource masks. */
110 @@ -93,22 +75,9 @@ static void bcma_pmu_resources_init(stru
111 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
113 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
116 -void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
118 - struct bcma_bus *bus = cc->core->bus;
120 - switch (bus->chipinfo.id) {
127 - pr_err("PMU switch/regulators init unknown for device "
128 - "0x%04X\n", bus->chipinfo.id);
130 + /* Add some delay; allow resources to come up and settle. */
134 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
135 @@ -122,8 +91,11 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
136 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
137 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
138 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
139 + else if (bus->chipinfo.rev > 0)
140 + val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
142 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
143 + val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
144 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
146 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
147 @@ -134,26 +106,38 @@ void bcma_pmu_workarounds(struct bcma_dr
148 struct bcma_bus *bus = cc->core->bus;
150 switch (bus->chipinfo.id) {
152 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
153 + case BCMA_CHIP_ID_BCM4313:
154 + /* enable 12 mA drive strenth for 4313 and set chipControl
156 + bcma_chipco_chipctl_maskset(cc, 0,
157 + BCMA_CCTRL_4313_12MA_LED_DRIVE,
158 + BCMA_CCTRL_4313_12MA_LED_DRIVE);
161 - /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
162 + case BCMA_CHIP_ID_BCM4331:
163 + case BCMA_CHIP_ID_BCM43431:
164 + /* Ext PA lines must be enabled for tx on BCM4331 */
165 + bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
168 + case BCMA_CHIP_ID_BCM43224:
169 + case BCMA_CHIP_ID_BCM43421:
170 + /* enable 12 mA drive strenth for 43224 and set chipControl
172 if (bus->chipinfo.rev == 0) {
173 - pr_err("Workarounds for 43224 rev 0 not fully "
175 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
176 + bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
177 + BCMA_CCTRL_43224_GPIO_TOGGLE,
178 + BCMA_CCTRL_43224_GPIO_TOGGLE);
179 + bcma_chipco_chipctl_maskset(cc, 0,
180 + BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
181 + BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
183 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
184 + bcma_chipco_chipctl_maskset(cc, 0,
185 + BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
186 + BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
192 - pr_err("Workarounds unknown for device 0x%04X\n",
194 + pr_debug("Workarounds unknown or not needed for device 0x%04X\n",
199 @@ -174,12 +158,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
200 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
201 BCMA_CC_PMU_CTL_NOILPONW);
203 - if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
204 - pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
206 - bcma_pmu_pll_init(cc);
207 bcma_pmu_resources_init(cc);
208 - bcma_pmu_swreg_init(cc);
209 bcma_pmu_workarounds(cc);
212 @@ -188,17 +167,17 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
213 struct bcma_bus *bus = cc->core->bus;
215 switch (bus->chipinfo.id) {
223 + case BCMA_CHIP_ID_BCM4716:
224 + case BCMA_CHIP_ID_BCM4748:
225 + case BCMA_CHIP_ID_BCM47162:
226 + case BCMA_CHIP_ID_BCM4313:
227 + case BCMA_CHIP_ID_BCM5357:
228 + case BCMA_CHIP_ID_BCM4749:
229 + case BCMA_CHIP_ID_BCM53572:
234 + case BCMA_CHIP_ID_BCM5356:
235 + case BCMA_CHIP_ID_BCM4706:
239 @@ -221,7 +200,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
243 - if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
244 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
245 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
246 /* Detect failure in clock setting */
247 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
249 @@ -253,22 +233,22 @@ u32 bcma_pmu_get_clockcontrol(struct bcm
250 struct bcma_bus *bus = cc->core->bus;
252 switch (bus->chipinfo.id) {
256 + case BCMA_CHIP_ID_BCM4716:
257 + case BCMA_CHIP_ID_BCM4748:
258 + case BCMA_CHIP_ID_BCM47162:
259 return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
260 BCMA_CC_PMU5_MAINPLL_SSB);
262 + case BCMA_CHIP_ID_BCM5356:
263 return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
264 BCMA_CC_PMU5_MAINPLL_SSB);
267 + case BCMA_CHIP_ID_BCM5357:
268 + case BCMA_CHIP_ID_BCM4749:
269 return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
270 BCMA_CC_PMU5_MAINPLL_SSB);
272 + case BCMA_CHIP_ID_BCM4706:
273 return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
274 BCMA_CC_PMU5_MAINPLL_SSB);
276 + case BCMA_CHIP_ID_BCM53572:
279 pr_warn("No backplane clock specified for %04X device, "
280 @@ -283,17 +263,17 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
282 struct bcma_bus *bus = cc->core->bus;
284 - if (bus->chipinfo.id == 53572)
285 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
288 if (cc->pmu.rev >= 5) {
290 switch (bus->chipinfo.id) {
292 + case BCMA_CHIP_ID_BCM5356:
293 pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
297 + case BCMA_CHIP_ID_BCM5357:
298 + case BCMA_CHIP_ID_BCM4749:
299 pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
302 @@ -301,10 +281,190 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
306 - /* TODO: if (bus->chipinfo.id == 0x5300)
307 + /* TODO: if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
308 return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
309 return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
312 return bcma_pmu_get_clockcontrol(cc);
315 +static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
318 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
319 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
322 +void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
325 + u8 phypll_offset = 0;
326 + u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
327 + u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
328 + struct bcma_bus *bus = cc->core->bus;
330 + switch (bus->chipinfo.id) {
331 + case BCMA_CHIP_ID_BCM5357:
332 + case BCMA_CHIP_ID_BCM4749:
333 + case BCMA_CHIP_ID_BCM53572:
334 + /* 5357[ab]0, 43236[ab]0, and 6362b0 */
336 + /* BCM5357 needs to touch PLL1_PLLCTL[02],
337 + so offset PLL0_PLLCTL[02] by 6 */
338 + phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
339 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
340 + bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
342 + /* RMW only the P1 divider */
343 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
344 + BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
345 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
346 + tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
347 + tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
348 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
350 + /* RMW only the int feedback divider */
351 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
352 + BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
353 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
354 + tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
355 + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
356 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
361 + case BCMA_CHIP_ID_BCM4331:
362 + case BCMA_CHIP_ID_BCM43431:
363 + if (spuravoid == 2) {
364 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
366 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
368 + } else if (spuravoid == 1) {
369 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
371 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
374 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
376 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
382 + case BCMA_CHIP_ID_BCM43224:
383 + case BCMA_CHIP_ID_BCM43225:
384 + case BCMA_CHIP_ID_BCM43421:
385 + if (spuravoid == 1) {
386 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
388 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
390 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
392 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
394 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
396 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
399 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
401 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
403 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
405 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
407 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
409 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
415 + case BCMA_CHIP_ID_BCM4716:
416 + case BCMA_CHIP_ID_BCM4748:
417 + case BCMA_CHIP_ID_BCM47162:
418 + if (spuravoid == 1) {
419 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
421 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
423 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
425 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
427 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
429 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
432 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
434 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
436 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
438 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
440 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
442 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
449 + case BCMA_CHIP_ID_BCM43227:
450 + case BCMA_CHIP_ID_BCM43228:
451 + case BCMA_CHIP_ID_BCM43428:
453 + /* PLL Settings for spur avoidance on/off mode,
454 + no on2 support for 43228A0 */
455 + if (spuravoid == 1) {
456 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
458 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
460 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
462 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
464 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
466 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
469 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
471 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
473 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
475 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
477 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
479 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
485 + pr_err("unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
490 + tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
491 + bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
493 +EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
494 --- a/drivers/bcma/driver_mips.c
495 +++ b/drivers/bcma/driver_mips.c
497 /* The 47162a0 hangs when reading MIPS DMP registers registers */
498 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
500 - return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
501 - dev->id.id == BCMA_CORE_MIPS_74K;
502 + return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
503 + dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
506 /* The 5357b0 hangs when reading USB20H DMP registers */
507 static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
509 - return (dev->bus->chipinfo.id == 0x5357 ||
510 - dev->bus->chipinfo.id == 0x4749) &&
511 + return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
512 + dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
513 dev->bus->chipinfo.pkg == 11 &&
514 dev->id.id == BCMA_CORE_USB20_HOST;
516 --- a/drivers/bcma/driver_pci.c
517 +++ b/drivers/bcma/driver_pci.c
519 * Broadcom specific AMBA
522 - * Copyright 2005, Broadcom Corporation
523 + * Copyright 2005, 2011, Broadcom Corporation
524 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
525 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
527 * Licensed under the GNU/GPL. See COPYING for details.
531 **************************************************/
533 -static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
534 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
536 - pcicore_write32(pc, 0x130, address);
537 - pcicore_read32(pc, 0x130);
538 - return pcicore_read32(pc, 0x134);
539 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
540 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
541 + return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
545 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
547 - pcicore_write32(pc, 0x130, address);
548 - pcicore_read32(pc, 0x130);
549 - pcicore_write32(pc, 0x134, data);
550 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
551 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
552 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
556 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
558 - const u16 mdio_control = 0x128;
559 - const u16 mdio_data = 0x12C;
563 - v = (1 << 30); /* Start of Transaction */
564 - v |= (1 << 28); /* Write Transaction */
565 - v |= (1 << 17); /* Turnaround */
567 + v = BCMA_CORE_PCI_MDIODATA_START;
568 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
569 + v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
570 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
571 + v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
572 + BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
573 + v |= BCMA_CORE_PCI_MDIODATA_TA;
575 - pcicore_write32(pc, mdio_data, v);
576 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
579 for (i = 0; i < 200; i++) {
580 - v = pcicore_read32(pc, mdio_control);
581 - if (v & 0x100 /* Trans complete */)
582 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
583 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
587 @@ -57,79 +57,84 @@ static void bcma_pcie_mdio_set_phy(struc
589 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
591 - const u16 mdio_control = 0x128;
592 - const u16 mdio_data = 0x12C;
593 int max_retries = 10;
598 - v = 0x80; /* Enable Preamble Sequence */
599 - v |= 0x2; /* MDIO Clock Divisor */
600 - pcicore_write32(pc, mdio_control, v);
601 + /* enable mdio access to SERDES */
602 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
603 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
604 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
606 if (pc->core->id.rev >= 10) {
608 bcma_pcie_mdio_set_phy(pc, device);
609 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
610 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
611 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
613 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
614 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
617 - v = (1 << 30); /* Start of Transaction */
618 - v |= (1 << 29); /* Read Transaction */
619 - v |= (1 << 17); /* Turnaround */
620 - if (pc->core->id.rev < 10)
621 - v |= (u32)device << 22;
622 - v |= (u32)address << 18;
623 - pcicore_write32(pc, mdio_data, v);
624 + v = BCMA_CORE_PCI_MDIODATA_START;
625 + v |= BCMA_CORE_PCI_MDIODATA_READ;
626 + v |= BCMA_CORE_PCI_MDIODATA_TA;
628 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
629 /* Wait for the device to complete the transaction */
631 for (i = 0; i < max_retries; i++) {
632 - v = pcicore_read32(pc, mdio_control);
633 - if (v & 0x100 /* Trans complete */) {
634 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
635 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
637 - ret = pcicore_read32(pc, mdio_data);
638 + ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
643 - pcicore_write32(pc, mdio_control, 0);
644 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
648 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
649 u8 address, u16 data)
651 - const u16 mdio_control = 0x128;
652 - const u16 mdio_data = 0x12C;
653 int max_retries = 10;
657 - v = 0x80; /* Enable Preamble Sequence */
658 - v |= 0x2; /* MDIO Clock Divisor */
659 - pcicore_write32(pc, mdio_control, v);
660 + /* enable mdio access to SERDES */
661 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
662 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
663 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
665 if (pc->core->id.rev >= 10) {
667 bcma_pcie_mdio_set_phy(pc, device);
668 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
669 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
670 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
672 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
673 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
676 - v = (1 << 30); /* Start of Transaction */
677 - v |= (1 << 28); /* Write Transaction */
678 - v |= (1 << 17); /* Turnaround */
679 - if (pc->core->id.rev < 10)
680 - v |= (u32)device << 22;
681 - v |= (u32)address << 18;
682 + v = BCMA_CORE_PCI_MDIODATA_START;
683 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
684 + v |= BCMA_CORE_PCI_MDIODATA_TA;
686 - pcicore_write32(pc, mdio_data, v);
687 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
688 /* Wait for the device to complete the transaction */
690 for (i = 0; i < max_retries; i++) {
691 - v = pcicore_read32(pc, mdio_control);
692 - if (v & 0x100 /* Trans complete */)
693 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
694 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
698 - pcicore_write32(pc, mdio_control, 0);
699 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
702 /**************************************************
703 @@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct
705 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
707 - return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
710 + tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
711 + if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
712 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
713 + BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
715 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
718 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
720 - const u8 serdes_pll_device = 0x1D;
721 - const u8 serdes_rx_device = 0x1F;
724 - bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
725 - bcma_pcicore_polarity_workaround(pc));
726 - tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
728 - bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
729 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
730 + BCMA_CORE_PCI_SERDES_RX_CTRL,
731 + bcma_pcicore_polarity_workaround(pc));
732 + tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
733 + BCMA_CORE_PCI_SERDES_PLL_CTRL);
734 + if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
735 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
736 + BCMA_CORE_PCI_SERDES_PLL_CTRL,
737 + tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
740 +static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
742 + struct bcma_device *core = pc->core;
743 + u16 val16, core_index;
746 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
747 + core_index = (u16)core->core_index;
749 + val16 = pcicore_read16(pc, regoff);
750 + if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
752 + val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
753 + (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
754 + pcicore_write16(pc, regoff, val16);
758 +/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
759 +/* Needs to happen when coming out of 'standby'/'hibernate' */
760 +static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
765 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
767 + val16 = pcicore_read16(pc, regoff);
769 + if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
770 + val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
771 + pcicore_write16(pc, regoff, val16);
775 /**************************************************
777 **************************************************/
779 -static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
780 +static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
782 + bcma_core_pci_fixcfg(pc);
783 bcma_pcicore_serdes_workaround(pc);
784 + bcma_core_pci_config_fixup(pc);
787 -static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
789 - struct bcma_bus *bus = pc->core->bus;
792 - chipid_top = (bus->chipinfo.id & 0xFF00);
793 - if (chipid_top != 0x4700 &&
794 - chipid_top != 0x5300)
797 -#ifdef CONFIG_SSB_DRIVER_PCICORE
798 - if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
800 -#endif /* CONFIG_SSB_DRIVER_PCICORE */
803 - /* TODO: on BCMA we use address from EROM instead of magic formula */
805 - return !mips_busprobe32(tmp, (bus->mmio +
806 - (pc->core->core_index * BCMA_CORE_SIZE)));
812 -void bcma_core_pci_init(struct bcma_drv_pci *pc)
813 +void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
818 - if (bcma_core_pci_is_in_hostmode(pc)) {
819 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
820 + pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
822 bcma_core_pci_hostmode_init(pc);
824 - pr_err("Driver compiled without support for hostmode PCI\n");
825 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
827 - bcma_core_pci_clientmode_init(pc);
830 - pc->setup_done = true;
832 + bcma_core_pci_clientmode_init(pc);
835 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
838 - struct pci_dev *pdev = pc->core->bus->host_pci;
839 + struct pci_dev *pdev;
843 - if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
844 + if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
845 /* This bcma device is not on a PCI host-bus. So the IRQs are
846 * not routed through the PCI core.
847 * So we must not enable routing through the PCI core. */
851 + pdev = pc->core->bus->host_pci;
853 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
856 @@ -236,3 +261,17 @@ out:
859 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
861 +void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
865 + w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
867 + w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
869 + w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
870 + bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
871 + bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
873 +EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
874 --- a/drivers/bcma/driver_pci_host.c
875 +++ b/drivers/bcma/driver_pci_host.c
877 * Broadcom specific AMBA
878 * PCI Core in hostmode
880 + * Copyright 2005 - 2011, Broadcom Corporation
881 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
882 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
884 * Licensed under the GNU/GPL. See COPYING for details.
887 #include "bcma_private.h"
888 +#include <linux/pci.h>
889 +#include <linux/export.h>
890 #include <linux/bcma/bcma.h>
891 +#include <asm/paccess.h>
893 +/* Probe a 32bit value on the bus and catch bus exceptions.
894 + * Returns nonzero on a bus exception.
895 + * This is MIPS specific */
896 +#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
898 +/* Assume one-hot slot wiring */
899 +#define BCMA_PCI_SLOT_MAX 16
900 +#define PCI_CONFIG_SPACE_SIZE 256
902 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
904 + struct bcma_bus *bus = pc->core->bus;
908 + chipid_top = (bus->chipinfo.id & 0xFF00);
909 + if (chipid_top != 0x4700 &&
910 + chipid_top != 0x5300)
913 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
914 + pr_info("This PCI core is disabled and not working\n");
918 + bcma_core_enable(pc->core, 0);
920 + return !mips_busprobe32(tmp, pc->core->io_addr);
923 +static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
925 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
926 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
927 + return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
930 +static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
933 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
934 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
935 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
938 +static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
939 + unsigned int func, unsigned int off)
943 + /* Issue config commands only when the data link is up (atleast
944 + * one external pcie device is present).
946 + if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
947 + & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
950 + /* Type 0 transaction */
951 + /* Slide the PCI window to the appropriate slot */
952 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
953 + /* Calculate the address */
954 + addr = pc->host_controller->host_cfg_addr;
955 + addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
956 + addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
957 + addr |= (off & ~3);
963 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
964 +static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
965 + unsigned int func, unsigned int off,
966 + void *buf, int len)
968 - pr_err("No support for PCI core in hostmode yet\n");
971 + void __iomem *mmio = 0;
973 + WARN_ON(!pc->hostmode);
974 + if (unlikely(len != 1 && len != 2 && len != 4))
977 + /* we support only two functions on device 0 */
981 + /* accesses to config registers with offsets >= 256
982 + * requires indirect access.
984 + if (off >= PCI_CONFIG_SPACE_SIZE) {
985 + addr = (func << 12);
986 + addr |= (off & 0x0FFF);
987 + val = bcma_pcie_read_config(pc, addr);
989 + addr = BCMA_CORE_PCI_PCICFG0;
990 + addr |= (func << 8);
991 + addr |= (off & 0xfc);
992 + val = pcicore_read32(pc, addr);
995 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
996 + if (unlikely(!addr))
999 + mmio = ioremap_nocache(addr, sizeof(val));
1003 + if (mips_busprobe32(val, mmio)) {
1008 + val = readl(mmio);
1010 + val >>= (8 * (off & 3));
1014 + *((u8 *)buf) = (u8)val;
1017 + *((u16 *)buf) = (u16)val;
1020 + *((u32 *)buf) = (u32)val;
1031 +static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
1032 + unsigned int func, unsigned int off,
1033 + const void *buf, int len)
1035 + int err = -EINVAL;
1036 + u32 addr = 0, val = 0;
1037 + void __iomem *mmio = 0;
1038 + u16 chipid = pc->core->bus->chipinfo.id;
1040 + WARN_ON(!pc->hostmode);
1041 + if (unlikely(len != 1 && len != 2 && len != 4))
1044 + /* accesses to config registers with offsets >= 256
1045 + * requires indirect access.
1047 + if (off < PCI_CONFIG_SPACE_SIZE) {
1048 + addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
1049 + addr |= (func << 8);
1050 + addr |= (off & 0xfc);
1051 + mmio = ioremap_nocache(addr, sizeof(val));
1056 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
1057 + if (unlikely(!addr))
1060 + mmio = ioremap_nocache(addr, sizeof(val));
1064 + if (mips_busprobe32(val, mmio)) {
1072 + val = readl(mmio);
1073 + val &= ~(0xFF << (8 * (off & 3)));
1074 + val |= *((const u8 *)buf) << (8 * (off & 3));
1077 + val = readl(mmio);
1078 + val &= ~(0xFFFF << (8 * (off & 3)));
1079 + val |= *((const u16 *)buf) << (8 * (off & 3));
1082 + val = *((const u32 *)buf);
1085 + if (dev == 0 && !addr) {
1086 + /* accesses to config registers with offsets >= 256
1087 + * requires indirect access.
1089 + addr = (func << 12);
1090 + addr |= (off & 0x0FFF);
1091 + bcma_pcie_write_config(pc, addr, val);
1093 + writel(val, mmio);
1095 + if (chipid == BCMA_CHIP_ID_BCM4716 ||
1096 + chipid == BCMA_CHIP_ID_BCM4748)
1108 +static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
1109 + unsigned int devfn,
1110 + int reg, int size, u32 *val)
1112 + unsigned long flags;
1114 + struct bcma_drv_pci *pc;
1115 + struct bcma_drv_pci_host *pc_host;
1117 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
1118 + pc = pc_host->pdev;
1120 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
1121 + err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
1122 + PCI_FUNC(devfn), reg, val, size);
1123 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
1125 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
1128 +static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
1129 + unsigned int devfn,
1130 + int reg, int size, u32 val)
1132 + unsigned long flags;
1134 + struct bcma_drv_pci *pc;
1135 + struct bcma_drv_pci_host *pc_host;
1137 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
1138 + pc = pc_host->pdev;
1140 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
1141 + err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
1142 + PCI_FUNC(devfn), reg, &val, size);
1143 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
1145 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
1148 +/* return cap_offset if requested capability exists in the PCI config space */
1149 +static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
1151 + unsigned int func, u8 req_cap_id,
1152 + unsigned char *buf, u32 *buflen)
1159 + /* check for Header type 0 */
1160 + bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
1162 + if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
1165 + /* check if the capability pointer field exists */
1166 + bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
1168 + if (!(byte_val & PCI_STATUS_CAP_LIST))
1171 + /* check if the capability pointer is 0x00 */
1172 + bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
1174 + if (cap_ptr == 0x00)
1177 + /* loop thr'u the capability list and see if the requested capabilty
1179 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
1180 + while (cap_id != req_cap_id) {
1181 + bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
1183 + if (cap_ptr == 0x00)
1185 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
1189 + /* found the caller requested capability */
1190 + if ((buf != NULL) && (buflen != NULL)) {
1193 + bufsize = *buflen;
1199 + /* copy the cpability data excluding cap ID and next ptr */
1200 + cap_data = cap_ptr + 2;
1201 + if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
1202 + bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
1203 + *buflen = bufsize;
1204 + while (bufsize--) {
1205 + bcma_extpci_read_config(pc, dev, func, cap_data, buf,
1215 +/* If the root port is capable of returning Config Request
1216 + * Retry Status (CRS) Completion Status to software then
1217 + * enable the feature.
1219 +static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
1221 + u8 cap_ptr, root_ctrl, root_cap, dev;
1225 + cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
1227 + root_cap = cap_ptr + PCI_EXP_RTCAP;
1228 + bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
1229 + if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
1230 + /* Enable CRS software visibility */
1231 + root_ctrl = cap_ptr + PCI_EXP_RTCTL;
1232 + val16 = PCI_EXP_RTCTL_CRSSVE;
1233 + bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
1236 + /* Initiate a configuration request to read the vendor id
1237 + * field of the device function's config space header after
1238 + * 100 ms wait time from the end of Reset. If the device is
1239 + * not done with its internal initialization, it must at
1240 + * least return a completion TLP, with a completion status
1241 + * of "Configuration Request Retry Status (CRS)". The root
1242 + * complex must complete the request to the host by returning
1243 + * a read-data value of 0001h for the Vendor ID field and
1244 + * all 1s for any additional bytes included in the request.
1245 + * Poll using the config reads for max wait time of 1 sec or
1246 + * until we receive the successful completion status. Repeat
1247 + * the procedure for all the devices.
1249 + for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
1250 + for (i = 0; i < 100000; i++) {
1251 + bcma_extpci_read_config(pc, dev, 0,
1252 + PCI_VENDOR_ID, &val16,
1259 + pr_err("PCI: Broken device in slot %d\n", dev);
1264 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
1266 + struct bcma_bus *bus = pc->core->bus;
1267 + struct bcma_drv_pci_host *pc_host;
1269 + u32 pci_membase_1G;
1270 + unsigned long io_map_base;
1272 + pr_info("PCIEcore in host mode found\n");
1274 + pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
1276 + pr_err("can not allocate memory");
1280 + pc->host_controller = pc_host;
1281 + pc_host->pci_controller.io_resource = &pc_host->io_resource;
1282 + pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
1283 + pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
1284 + pc_host->pdev = pc;
1286 + pci_membase_1G = BCMA_SOC_PCI_DMA;
1287 + pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
1289 + pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
1290 + pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
1292 + pc_host->mem_resource.name = "BCMA PCIcore external memory",
1293 + pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
1294 + pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
1295 + pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
1297 + pc_host->io_resource.name = "BCMA PCIcore external I/O",
1298 + pc_host->io_resource.start = 0x100;
1299 + pc_host->io_resource.end = 0x7FF;
1300 + pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
1304 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
1306 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
1307 + BCMA_CORE_PCI_CTL_RST_OE);
1309 + /* 64 MB I/O access window. On 4716, use
1310 + * sbtopcie0 to access the device registers. We
1311 + * can't use address match 2 (1 GB window) region
1312 + * as mips can't generate 64-bit address on the
1315 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
1316 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
1317 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1318 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1319 + BCMA_SOC_PCI_MEM_SZ - 1;
1320 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1321 + BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
1322 + } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1323 + tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
1324 + tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
1325 + tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
1326 + if (pc->core->core_unit == 0) {
1327 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1328 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1329 + BCMA_SOC_PCI_MEM_SZ - 1;
1330 + pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1331 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1332 + tmp | BCMA_SOC_PCI_MEM);
1333 + } else if (pc->core->core_unit == 1) {
1334 + pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1335 + pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1336 + BCMA_SOC_PCI_MEM_SZ - 1;
1337 + pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1338 + pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1339 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1340 + tmp | BCMA_SOC_PCI1_MEM);
1343 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1344 + BCMA_CORE_PCI_SBTOPCI_IO);
1346 + /* 64 MB configuration access window */
1347 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
1349 + /* 1 GB memory access window */
1350 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
1351 + BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
1354 + /* As per PCI Express Base Spec 1.1 we need to wait for
1355 + * at least 100 ms from the end of a reset (cold/warm/hot)
1356 + * before issuing configuration requests to PCI Express
1361 + bcma_core_pci_enable_crs(pc);
1363 + /* Enable PCI bridge BAR0 memory & master access */
1364 + tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1365 + bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
1367 + /* Enable PCI interrupts */
1368 + pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
1370 + /* Ok, ready to run, register it to the system.
1371 + * The following needs change, if we want to port hostmode
1372 + * to non-MIPS platform. */
1373 + io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start,
1374 + resource_size(&pc_host->mem_resource));
1375 + pc_host->pci_controller.io_map_base = io_map_base;
1376 + set_io_port_base(pc_host->pci_controller.io_map_base);
1377 + /* Give some time to the PCI controller to configure itself with the new
1378 + * values. Not waiting at this point causes crashes of the machine. */
1380 + register_pci_controller(&pc_host->pci_controller);
1384 +/* Early PCI fixup for a device on the PCI-core bridge. */
1385 +static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
1387 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1388 + /* This is not a device on the PCI-core bridge. */
1391 + if (PCI_SLOT(dev->devfn) != 0)
1394 + pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
1396 + /* Enable PCI bridge bus mastering and memory space */
1397 + pci_set_master(dev);
1398 + if (pcibios_enable_device(dev, ~0) < 0) {
1399 + pr_err("PCI: BCMA bridge enable failed\n");
1403 + /* Enable PCI bridge BAR1 prefetch and burst */
1404 + pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
1406 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
1408 +/* Early PCI fixup for all PCI-cores to set the correct memory address. */
1409 +static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1411 + struct resource *res;
1414 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1415 + /* This is not a device on the PCI-core bridge. */
1418 + if (PCI_SLOT(dev->devfn) == 0)
1421 + pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
1423 + for (pos = 0; pos < 6; pos++) {
1424 + res = &dev->resource[pos];
1425 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1426 + pci_assign_resource(dev, pos);
1429 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1431 +/* This function is called when doing a pci_enable_device().
1432 + * We must first check if the device is a device on the PCI-core bridge. */
1433 +int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
1435 + struct bcma_drv_pci_host *pc_host;
1437 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1438 + /* This is not a device on the PCI-core bridge. */
1441 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1444 + pr_info("PCI: Fixing up device %s\n", pci_name(dev));
1446 + /* Fix up interrupt lines */
1447 + dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
1448 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1452 +EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
1454 +/* PCI device IRQ mapping. */
1455 +int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
1457 + struct bcma_drv_pci_host *pc_host;
1459 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1460 + /* This is not a device on the PCI-core bridge. */
1464 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1466 + return bcma_core_mips_irq(pc_host->pdev->core) + 2;
1468 +EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
1469 --- a/drivers/bcma/host_pci.c
1470 +++ b/drivers/bcma/host_pci.c
1471 @@ -154,8 +154,8 @@ const struct bcma_host_ops bcma_host_pci
1472 .awrite32 = bcma_host_pci_awrite32,
1475 -static int bcma_host_pci_probe(struct pci_dev *dev,
1476 - const struct pci_device_id *id)
1477 +static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
1478 + const struct pci_device_id *id)
1480 struct bcma_bus *bus;
1482 @@ -201,6 +201,9 @@ static int bcma_host_pci_probe(struct pc
1483 bus->hosttype = BCMA_HOSTTYPE_PCI;
1484 bus->ops = &bcma_host_pci_ops;
1486 + bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
1487 + bus->boardinfo.type = bus->host_pci->subsystem_device;
1490 err = bcma_bus_register(bus);
1492 @@ -222,7 +225,7 @@ err_kfree_bus:
1496 -static void bcma_host_pci_remove(struct pci_dev *dev)
1497 +static void __devexit bcma_host_pci_remove(struct pci_dev *dev)
1499 struct bcma_bus *bus = pci_get_drvdata(dev);
1501 @@ -265,6 +268,7 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
1503 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1504 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1505 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
1506 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
1507 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
1508 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1509 @@ -277,7 +281,7 @@ static struct pci_driver bcma_pci_bridge
1510 .name = "bcma-pci-bridge",
1511 .id_table = bcma_pci_bridge_tbl,
1512 .probe = bcma_host_pci_probe,
1513 - .remove = bcma_host_pci_remove,
1514 + .remove = __devexit_p(bcma_host_pci_remove),
1515 .driver.pm = BCMA_PM_OPS,
1518 --- a/drivers/bcma/main.c
1519 +++ b/drivers/bcma/main.c
1521 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
1522 MODULE_LICENSE("GPL");
1524 +/* contains the number the next bus should get. */
1525 +static unsigned int bcma_bus_next_num = 0;
1527 +/* bcma_buses_mutex locks the bcma_bus_next_num */
1528 +static DEFINE_MUTEX(bcma_buses_mutex);
1530 static int bcma_bus_match(struct device *dev, struct device_driver *drv);
1531 static int bcma_device_probe(struct device *dev);
1532 static int bcma_device_remove(struct device *dev);
1533 @@ -55,7 +61,7 @@ static struct bus_type bcma_bus_type = {
1534 .dev_attrs = bcma_device_attrs,
1537 -static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
1538 +struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
1540 struct bcma_device *core;
1542 @@ -65,6 +71,7 @@ static struct bcma_device *bcma_find_cor
1546 +EXPORT_SYMBOL_GPL(bcma_find_core);
1548 static void bcma_release_core_dev(struct device *dev)
1550 @@ -93,7 +100,7 @@ static int bcma_register_cores(struct bc
1552 core->dev.release = bcma_release_core_dev;
1553 core->dev.bus = &bcma_bus_type;
1554 - dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
1555 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
1557 switch (bus->hosttype) {
1558 case BCMA_HOSTTYPE_PCI:
1559 @@ -132,11 +139,15 @@ static void bcma_unregister_cores(struct
1563 -int bcma_bus_register(struct bcma_bus *bus)
1564 +int __devinit bcma_bus_register(struct bcma_bus *bus)
1567 struct bcma_device *core;
1569 + mutex_lock(&bcma_buses_mutex);
1570 + bus->num = bcma_bus_next_num++;
1571 + mutex_unlock(&bcma_buses_mutex);
1573 /* Scan for devices (cores) */
1574 err = bcma_bus_scan(bus);
1576 --- a/drivers/bcma/scan.c
1577 +++ b/drivers/bcma/scan.c
1578 @@ -19,15 +19,27 @@ struct bcma_device_id_name {
1582 -struct bcma_device_id_name bcma_device_names[] = {
1584 +static const struct bcma_device_id_name bcma_arm_device_names[] = {
1585 + { BCMA_CORE_ARM_1176, "ARM 1176" },
1586 + { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
1587 + { BCMA_CORE_ARM_CM3, "ARM CM3" },
1590 +static const struct bcma_device_id_name bcma_bcm_device_names[] = {
1591 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
1592 + { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
1593 + { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
1594 + { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
1595 + { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
1596 + { BCMA_CORE_ALTA, "ALTA (I2S)" },
1597 + { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
1598 { BCMA_CORE_INVALID, "Invalid" },
1599 { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
1600 { BCMA_CORE_ILINE20, "ILine 20" },
1601 { BCMA_CORE_SRAM, "SRAM" },
1602 { BCMA_CORE_SDRAM, "SDRAM" },
1603 { BCMA_CORE_PCI, "PCI" },
1604 - { BCMA_CORE_MIPS, "MIPS" },
1605 { BCMA_CORE_ETHERNET, "Fast Ethernet" },
1606 { BCMA_CORE_V90, "V90" },
1607 { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
1608 @@ -44,7 +56,6 @@ struct bcma_device_id_name bcma_device_n
1609 { BCMA_CORE_PHY_A, "PHY A" },
1610 { BCMA_CORE_PHY_B, "PHY B" },
1611 { BCMA_CORE_PHY_G, "PHY G" },
1612 - { BCMA_CORE_MIPS_3302, "MIPS 3302" },
1613 { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
1614 { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
1615 { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
1616 @@ -58,15 +69,11 @@ struct bcma_device_id_name bcma_device_n
1617 { BCMA_CORE_PHY_N, "PHY N" },
1618 { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
1619 { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
1620 - { BCMA_CORE_ARM_1176, "ARM 1176" },
1621 - { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
1622 { BCMA_CORE_PHY_LP, "PHY LP" },
1623 { BCMA_CORE_PMU, "PMU" },
1624 { BCMA_CORE_PHY_SSN, "PHY SSN" },
1625 { BCMA_CORE_SDIO_DEV, "SDIO Device" },
1626 - { BCMA_CORE_ARM_CM3, "ARM CM3" },
1627 { BCMA_CORE_PHY_HT, "PHY HT" },
1628 - { BCMA_CORE_MIPS_74K, "MIPS 74K" },
1629 { BCMA_CORE_MAC_GBIT, "GBit MAC" },
1630 { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
1631 { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
1632 @@ -79,16 +86,41 @@ struct bcma_device_id_name bcma_device_n
1633 { BCMA_CORE_SHIM, "SHIM" },
1634 { BCMA_CORE_DEFAULT, "Default" },
1636 -const char *bcma_device_name(struct bcma_device_id *id)
1638 +static const struct bcma_device_id_name bcma_mips_device_names[] = {
1639 + { BCMA_CORE_MIPS, "MIPS" },
1640 + { BCMA_CORE_MIPS_3302, "MIPS 3302" },
1641 + { BCMA_CORE_MIPS_74K, "MIPS 74K" },
1644 +static const char *bcma_device_name(const struct bcma_device_id *id)
1647 + const struct bcma_device_id_name *names;
1650 - if (id->manuf == BCMA_MANUF_BCM) {
1651 - for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
1652 - if (bcma_device_names[i].id == id->id)
1653 - return bcma_device_names[i].name;
1655 + /* search manufacturer specific names */
1656 + switch (id->manuf) {
1657 + case BCMA_MANUF_ARM:
1658 + names = bcma_arm_device_names;
1659 + size = ARRAY_SIZE(bcma_arm_device_names);
1661 + case BCMA_MANUF_BCM:
1662 + names = bcma_bcm_device_names;
1663 + size = ARRAY_SIZE(bcma_bcm_device_names);
1665 + case BCMA_MANUF_MIPS:
1666 + names = bcma_mips_device_names;
1667 + size = ARRAY_SIZE(bcma_mips_device_names);
1673 + for (i = 0; i < size; i++) {
1674 + if (names[i].id == id->id)
1675 + return names[i].name;
1681 @@ -212,6 +244,17 @@ static struct bcma_device *bcma_find_cor
1685 +static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
1687 + struct bcma_device *core;
1689 + list_for_each_entry_reverse(core, &bus->cores, list) {
1690 + if (core->id.id == coreid)
1696 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
1697 struct bcma_device_id *match, int core_num,
1698 struct bcma_device *core)
1699 @@ -286,6 +329,23 @@ static int bcma_get_next_core(struct bcm
1703 + /* First Slave Address Descriptor should be port 0:
1704 + * the main register space for the core
1706 + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
1708 + /* Try again to see if it is a bridge */
1709 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
1710 + SCAN_ADDR_TYPE_BRIDGE, 0);
1714 + pr_info("Bridge found\n");
1720 /* get & parse slave ports */
1721 for (i = 0; i < ports[1]; i++) {
1722 for (j = 0; ; j++) {
1723 @@ -298,7 +358,7 @@ static int bcma_get_next_core(struct bcm
1726 if (i == 0 && j == 0)
1728 + core->addr1 = tmp;
1732 @@ -353,6 +413,7 @@ static int bcma_get_next_core(struct bcm
1733 void bcma_init_bus(struct bcma_bus *bus)
1736 + struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
1740 @@ -363,9 +424,12 @@ void bcma_init_bus(struct bcma_bus *bus)
1741 bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
1743 tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
1744 - bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
1745 - bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
1746 - bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
1747 + chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
1748 + chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
1749 + chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
1750 + pr_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1751 + chipinfo->id, chipinfo->rev, chipinfo->pkg);
1753 bus->init_done = true;
1756 @@ -392,6 +456,7 @@ int bcma_bus_scan(struct bcma_bus *bus)
1757 bcma_scan_switch_core(bus, erombase);
1759 while (eromptr < eromend) {
1760 + struct bcma_device *other_core;
1761 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
1764 @@ -414,6 +479,8 @@ int bcma_bus_scan(struct bcma_bus *bus)
1766 core->core_index = core_num++;
1768 + other_core = bcma_find_core_reverse(bus, core->id.id);
1769 + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
1771 pr_info("Core %d found: %s "
1772 "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
1773 --- a/drivers/bcma/sprom.c
1774 +++ b/drivers/bcma/sprom.c
1776 * Broadcom specific AMBA
1779 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
1781 * Licensed under the GNU/GPL. See COPYING for details.
1785 #include <linux/dma-mapping.h>
1786 #include <linux/slab.h>
1788 -#define SPOFF(offset) ((offset) / sizeof(u16))
1789 +static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out);
1792 + * bcma_arch_register_fallback_sprom - Registers a method providing a
1793 + * fallback SPROM if no SPROM is found.
1795 + * @sprom_callback: The callback function.
1797 + * With this function the architecture implementation may register a
1798 + * callback handler which fills the SPROM data structure. The fallback is
1799 + * used for PCI based BCMA devices, where no valid SPROM can be found
1800 + * in the shadow registers and to provide the SPROM for SoCs where BCMA is
1801 + * to controll the system bus.
1803 + * This function is useful for weird architectures that have a half-assed
1804 + * BCMA device hardwired to their PCI bus.
1806 + * This function is available for architecture code, only. So it is not
1809 +int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus,
1810 + struct ssb_sprom *out))
1812 + if (get_fallback_sprom)
1814 + get_fallback_sprom = sprom_callback;
1819 +static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
1820 + struct ssb_sprom *out)
1824 + if (!get_fallback_sprom) {
1829 + err = get_fallback_sprom(bus, out);
1833 + pr_debug("Using SPROM revision %d provided by"
1834 + " platform.\n", bus->sprom.revision);
1837 + pr_warn("Using fallback SPROM failed (err %d)\n", err);
1841 /**************************************************
1843 @@ -124,10 +176,37 @@ static int bcma_sprom_valid(const u16 *s
1845 **************************************************/
1847 +#define SPOFF(offset) ((offset) / sizeof(u16))
1849 +#define SPEX(_field, _offset, _mask, _shift) \
1850 + bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
1852 +#define SPEX32(_field, _offset, _mask, _shift) \
1853 + bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
1854 + sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
1856 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
1858 + SPEX(_field[0], _offset + 0, _mask, _shift); \
1859 + SPEX(_field[1], _offset + 2, _mask, _shift); \
1860 + SPEX(_field[2], _offset + 4, _mask, _shift); \
1861 + SPEX(_field[3], _offset + 6, _mask, _shift); \
1862 + SPEX(_field[4], _offset + 8, _mask, _shift); \
1863 + SPEX(_field[5], _offset + 10, _mask, _shift); \
1864 + SPEX(_field[6], _offset + 12, _mask, _shift); \
1865 + SPEX(_field[7], _offset + 14, _mask, _shift); \
1868 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
1873 + u16 pwr_info_offset[] = {
1874 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1875 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1877 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1878 + ARRAY_SIZE(bus->sprom.core_pwr_info));
1880 bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
1881 SSB_SPROM_REVISION_REV;
1882 @@ -137,102 +216,378 @@ static void bcma_sprom_extract_r8(struct
1883 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
1886 - bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
1887 + SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
1889 - bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
1890 - SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
1891 - bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
1892 - SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
1893 - bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
1894 - SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
1895 - bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
1896 - SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
1898 - bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
1899 - SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
1900 - bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
1901 - SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
1902 - bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
1903 - SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
1904 - bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
1905 - SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
1907 - bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
1908 - SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
1909 - bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
1910 - SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
1911 - bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
1912 - SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
1913 - bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
1914 - SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
1916 - bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
1917 - SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
1918 - bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
1919 - SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
1920 - bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
1921 - SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
1922 - bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
1923 - SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
1925 - bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
1926 - bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
1927 - bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
1928 - bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
1930 - bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
1932 - bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
1933 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
1934 - bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
1935 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
1936 - bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
1937 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
1938 - bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
1939 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
1940 - bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
1941 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
1943 - bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
1944 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
1945 - bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
1946 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
1947 - bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
1948 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
1949 - bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
1950 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
1951 - bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
1952 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
1953 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
1954 + SSB_SPROM4_TXPID2G0_SHIFT);
1955 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
1956 + SSB_SPROM4_TXPID2G1_SHIFT);
1957 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
1958 + SSB_SPROM4_TXPID2G2_SHIFT);
1959 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
1960 + SSB_SPROM4_TXPID2G3_SHIFT);
1962 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
1963 + SSB_SPROM4_TXPID5GL0_SHIFT);
1964 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
1965 + SSB_SPROM4_TXPID5GL1_SHIFT);
1966 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
1967 + SSB_SPROM4_TXPID5GL2_SHIFT);
1968 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
1969 + SSB_SPROM4_TXPID5GL3_SHIFT);
1971 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
1972 + SSB_SPROM4_TXPID5G0_SHIFT);
1973 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
1974 + SSB_SPROM4_TXPID5G1_SHIFT);
1975 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
1976 + SSB_SPROM4_TXPID5G2_SHIFT);
1977 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
1978 + SSB_SPROM4_TXPID5G3_SHIFT);
1980 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
1981 + SSB_SPROM4_TXPID5GH0_SHIFT);
1982 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
1983 + SSB_SPROM4_TXPID5GH1_SHIFT);
1984 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
1985 + SSB_SPROM4_TXPID5GH2_SHIFT);
1986 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
1987 + SSB_SPROM4_TXPID5GH3_SHIFT);
1989 + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
1990 + SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
1991 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
1992 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
1994 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
1995 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
1997 + /* Extract cores power info info */
1998 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1999 + o = pwr_info_offset[i];
2000 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
2001 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
2002 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
2003 + SSB_SPROM8_2G_MAXP, 0);
2005 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
2006 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
2007 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
2009 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
2010 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
2011 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
2012 + SSB_SPROM8_5G_MAXP, 0);
2013 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
2014 + SSB_SPROM8_5GH_MAXP, 0);
2015 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
2016 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
2018 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
2019 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
2020 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
2021 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
2022 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
2023 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
2024 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
2025 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
2026 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
2029 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
2030 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
2031 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
2032 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
2033 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
2034 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
2035 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
2036 + SSB_SROM8_FEM_TR_ISO_SHIFT);
2037 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
2038 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
2040 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
2041 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
2042 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
2043 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
2044 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
2045 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
2046 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
2047 + SSB_SROM8_FEM_TR_ISO_SHIFT);
2048 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
2049 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
2051 + SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
2052 + SSB_SPROM8_ANTAVAIL_A_SHIFT);
2053 + SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
2054 + SSB_SPROM8_ANTAVAIL_BG_SHIFT);
2055 + SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
2056 + SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
2057 + SSB_SPROM8_ITSSI_BG_SHIFT);
2058 + SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
2059 + SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
2060 + SSB_SPROM8_ITSSI_A_SHIFT);
2061 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
2062 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
2063 + SSB_SPROM8_MAXP_AL_SHIFT);
2064 + SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
2065 + SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
2066 + SSB_SPROM8_GPIOA_P1_SHIFT);
2067 + SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
2068 + SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
2069 + SSB_SPROM8_GPIOB_P3_SHIFT);
2070 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
2071 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
2072 + SSB_SPROM8_TRI5G_SHIFT);
2073 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
2074 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
2075 + SSB_SPROM8_TRI5GH_SHIFT);
2076 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G,
2077 + SSB_SPROM8_RXPO2G_SHIFT);
2078 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
2079 + SSB_SPROM8_RXPO5G_SHIFT);
2080 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
2081 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
2082 + SSB_SPROM8_RSSISMC2G_SHIFT);
2083 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
2084 + SSB_SPROM8_RSSISAV2G_SHIFT);
2085 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
2086 + SSB_SPROM8_BXA2G_SHIFT);
2087 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
2088 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
2089 + SSB_SPROM8_RSSISMC5G_SHIFT);
2090 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
2091 + SSB_SPROM8_RSSISAV5G_SHIFT);
2092 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
2093 + SSB_SPROM8_BXA5G_SHIFT);
2095 + SPEX(pa0b0, SSB_SPROM8_PA0B0, ~0, 0);
2096 + SPEX(pa0b1, SSB_SPROM8_PA0B1, ~0, 0);
2097 + SPEX(pa0b2, SSB_SPROM8_PA0B2, ~0, 0);
2098 + SPEX(pa1b0, SSB_SPROM8_PA1B0, ~0, 0);
2099 + SPEX(pa1b1, SSB_SPROM8_PA1B1, ~0, 0);
2100 + SPEX(pa1b2, SSB_SPROM8_PA1B2, ~0, 0);
2101 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, ~0, 0);
2102 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, ~0, 0);
2103 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, ~0, 0);
2104 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, ~0, 0);
2105 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, ~0, 0);
2106 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, ~0, 0);
2107 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, ~0, 0);
2108 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, ~0, 0);
2109 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, ~0, 0);
2110 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, ~0, 0);
2111 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
2113 + /* Extract the antenna gain values. */
2114 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
2115 + SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
2116 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
2117 + SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
2118 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
2119 + SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
2120 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
2121 + SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
2123 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
2124 + SSB_SPROM8_LEDDC_ON_SHIFT);
2125 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
2126 + SSB_SPROM8_LEDDC_OFF_SHIFT);
2128 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
2129 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
2130 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
2131 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
2132 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
2133 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
2135 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
2137 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
2138 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
2139 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
2140 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
2142 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
2143 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
2144 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
2145 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
2146 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
2147 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
2148 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
2149 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
2150 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
2151 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
2152 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
2153 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
2154 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
2155 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
2156 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
2157 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
2158 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
2159 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
2160 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
2161 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
2163 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
2164 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
2165 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
2166 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
2168 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
2169 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
2170 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
2171 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
2172 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
2173 + SSB_SPROM8_TEMPDELTA_PHYCAL,
2174 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
2175 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
2176 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
2177 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
2178 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
2179 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
2183 + * Indicates the presence of external SPROM.
2185 +static bool bcma_sprom_ext_available(struct bcma_bus *bus)
2191 + if (bus->drv_cc.core->id.rev >= 31) {
2192 + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
2195 + srom_control = bcma_read32(bus->drv_cc.core,
2196 + BCMA_CC_SROM_CONTROL);
2197 + return srom_control & BCMA_CC_SROM_CONTROL_PRESENT;
2200 + /* older chipcommon revisions use chip status register */
2201 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
2202 + switch (bus->chipinfo.id) {
2203 + case BCMA_CHIP_ID_BCM4313:
2204 + present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
2207 + case BCMA_CHIP_ID_BCM4331:
2208 + present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
2215 + return chip_status & present_mask;
2219 + * Indicates that on-chip OTP memory is present and enabled.
2221 +static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
2227 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
2228 + switch (bus->chipinfo.id) {
2229 + case BCMA_CHIP_ID_BCM4313:
2230 + present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
2233 + case BCMA_CHIP_ID_BCM4331:
2234 + present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
2237 + case BCMA_CHIP_ID_BCM43224:
2238 + case BCMA_CHIP_ID_BCM43225:
2239 + /* for these chips OTP is always available */
2249 + otpsize = bus->drv_cc.capabilities & BCMA_CC_CAP_OTPS;
2250 + otpsize >>= BCMA_CC_CAP_OTPS_SHIFT;
2253 + return otpsize != 0;
2257 + * Verify OTP is filled and determine the byte
2258 + * offset where SPROM data is located.
2260 + * On error, returns 0; byte offset otherwise.
2262 +static int bcma_sprom_onchip_offset(struct bcma_bus *bus)
2264 + struct bcma_device *cc = bus->drv_cc.core;
2267 + /* verify OTP status */
2268 + if ((bcma_read32(cc, BCMA_CC_OTPS) & BCMA_CC_OTPS_GU_PROG_HW) == 0)
2271 + /* obtain bit offset from otplayout register */
2272 + offset = (bcma_read32(cc, BCMA_CC_OTPL) & BCMA_CC_OTPL_GURGN_OFFSET);
2273 + return BCMA_CC_SPROM + (offset >> 3);
2276 int bcma_sprom_get(struct bcma_bus *bus)
2279 + u16 offset = BCMA_CC_SPROM;
2283 if (!bus->drv_cc.core)
2286 - if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
2288 + if (!bcma_sprom_ext_available(bus)) {
2289 + bool sprom_onchip;
2292 + * External SPROM takes precedence so check
2293 + * on-chip OTP only when no external SPROM
2296 + sprom_onchip = bcma_sprom_onchip_available(bus);
2297 + if (sprom_onchip) {
2298 + /* determine offset */
2299 + offset = bcma_sprom_onchip_offset(bus);
2301 + if (!offset || !sprom_onchip) {
2303 + * Maybe there is no SPROM on the device?
2304 + * Now we ask the arch code if there is some sprom
2305 + * available for this device in some other storage.
2307 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
2312 sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
2317 - if (bus->chipinfo.id == 0x4331)
2318 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
2319 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2320 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
2322 - /* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
2323 - * According to brcm80211 this applies to cards with PCIe rev >= 6
2324 - * TODO: understand this condition and use it */
2325 - offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
2326 - BCMA_CC_SPROM_PCIE6;
2327 + pr_debug("SPROM offset 0x%x\n", offset);
2328 bcma_sprom_read(bus, offset, sprom);
2330 - if (bus->chipinfo.id == 0x4331)
2331 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
2332 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2333 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
2335 err = bcma_sprom_valid(sprom);
2336 --- a/include/linux/bcma/bcma.h
2337 +++ b/include/linux/bcma/bcma.h
2338 @@ -26,6 +26,11 @@ struct bcma_chipinfo {
2342 +struct bcma_boardinfo {
2349 BCMA_CLKMODE_DYNAMIC,
2350 @@ -65,6 +70,13 @@ struct bcma_host_ops {
2352 /* Core-ID values. */
2353 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
2354 +#define BCMA_CORE_4706_CHIPCOMMON 0x500
2355 +#define BCMA_CORE_4706_SOC_RAM 0x50E
2356 +#define BCMA_CORE_4706_MAC_GBIT 0x52D
2357 +#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
2358 +#define BCMA_CORE_ALTA 0x534 /* I2S core */
2359 +#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC
2360 +#define BCMA_CORE_DDR23_PHY 0x5DD
2361 #define BCMA_CORE_INVALID 0x700
2362 #define BCMA_CORE_CHIPCOMMON 0x800
2363 #define BCMA_CORE_ILINE20 0x801
2364 @@ -125,6 +137,36 @@ struct bcma_host_ops {
2366 #define BCMA_MAX_NR_CORES 16
2368 +/* Chip IDs of PCIe devices */
2369 +#define BCMA_CHIP_ID_BCM4313 0x4313
2370 +#define BCMA_CHIP_ID_BCM43224 43224
2371 +#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
2372 +#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
2373 +#define BCMA_CHIP_ID_BCM43225 43225
2374 +#define BCMA_CHIP_ID_BCM43227 43227
2375 +#define BCMA_CHIP_ID_BCM43228 43228
2376 +#define BCMA_CHIP_ID_BCM43421 43421
2377 +#define BCMA_CHIP_ID_BCM43428 43428
2378 +#define BCMA_CHIP_ID_BCM43431 43431
2379 +#define BCMA_CHIP_ID_BCM43460 43460
2380 +#define BCMA_CHIP_ID_BCM4331 0x4331
2381 +#define BCMA_CHIP_ID_BCM6362 0x6362
2382 +#define BCMA_CHIP_ID_BCM4360 0x4360
2383 +#define BCMA_CHIP_ID_BCM4352 0x4352
2385 +/* Chip IDs of SoCs */
2386 +#define BCMA_CHIP_ID_BCM4706 0x5300
2387 +#define BCMA_CHIP_ID_BCM4716 0x4716
2388 +#define BCMA_PKG_ID_BCM4716 8
2389 +#define BCMA_PKG_ID_BCM4717 9
2390 +#define BCMA_PKG_ID_BCM4718 10
2391 +#define BCMA_CHIP_ID_BCM47162 47162
2392 +#define BCMA_CHIP_ID_BCM4748 0x4748
2393 +#define BCMA_CHIP_ID_BCM4749 0x4749
2394 +#define BCMA_CHIP_ID_BCM5356 0x5356
2395 +#define BCMA_CHIP_ID_BCM5357 0x5357
2396 +#define BCMA_CHIP_ID_BCM53572 53572
2398 struct bcma_device {
2399 struct bcma_bus *bus;
2400 struct bcma_device_id id;
2401 @@ -136,8 +178,10 @@ struct bcma_device {
2402 bool dev_registered;
2411 void __iomem *io_addr;
2412 @@ -175,6 +219,12 @@ int __bcma_driver_register(struct bcma_d
2414 extern void bcma_driver_unregister(struct bcma_driver *drv);
2416 +/* Set a fallback SPROM.
2417 + * See kdoc at the function definition for complete documentation. */
2418 +extern int bcma_arch_register_fallback_sprom(
2419 + int (*sprom_callback)(struct bcma_bus *bus,
2420 + struct ssb_sprom *out));
2423 /* The MMIO area. */
2425 @@ -191,10 +241,13 @@ struct bcma_bus {
2427 struct bcma_chipinfo chipinfo;
2429 + struct bcma_boardinfo boardinfo;
2431 struct bcma_device *mapped_core;
2432 struct list_head cores;
2437 struct bcma_drv_cc drv_cc;
2438 struct bcma_drv_pci drv_pci;
2439 @@ -282,6 +335,7 @@ static inline void bcma_maskset16(struct
2440 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
2443 +extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
2444 extern bool bcma_core_is_enabled(struct bcma_device *core);
2445 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
2446 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
2447 --- a/include/linux/bcma/bcma_driver_chipcommon.h
2448 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
2450 #define BCMA_CC_OTPS_HW_PROTECT 0x00000001
2451 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002
2452 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004
2453 +#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
2454 +#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
2455 +#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
2456 #define BCMA_CC_OTPC 0x0014 /* OTP control */
2457 #define BCMA_CC_OTPC_RECWAIT 0xFF000000
2458 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
2460 #define BCMA_CC_OTPP_READ 0x40000000
2461 #define BCMA_CC_OTPP_START 0x80000000
2462 #define BCMA_CC_OTPP_BUSY 0x80000000
2463 +#define BCMA_CC_OTPL 0x001C /* OTP layout */
2464 +#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
2465 #define BCMA_CC_IRQSTAT 0x0020
2466 #define BCMA_CC_IRQMASK 0x0024
2467 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
2469 #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
2470 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
2471 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
2472 +#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
2473 +#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
2474 +#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
2475 +#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
2476 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
2477 #define BCMA_CC_JCMD_START 0x80000000
2478 #define BCMA_CC_JCMD_BUSY 0x80000000
2479 @@ -181,6 +190,22 @@
2480 #define BCMA_CC_FLASH_CFG 0x0128
2481 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
2482 #define BCMA_CC_FLASH_WAITCNT 0x012C
2483 +#define BCMA_CC_SROM_CONTROL 0x0190
2484 +#define BCMA_CC_SROM_CONTROL_START 0x80000000
2485 +#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
2486 +#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
2487 +#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
2488 +#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
2489 +#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
2490 +#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
2491 +#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
2492 +#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
2493 +#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
2494 +#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
2495 +#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
2496 +#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
2497 +#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
2498 +#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
2499 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
2500 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
2501 #define BCMA_CC_UART0_DATA 0x0300
2503 #define BCMA_CC_PLLCTL_ADDR 0x0660
2504 #define BCMA_CC_PLLCTL_DATA 0x0664
2505 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
2506 -#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
2508 /* Divider allocation in 4716/47162/5356 */
2509 #define BCMA_CC_PMU5_MAINPLL_CPU 1
2510 @@ -284,6 +308,19 @@
2511 #define BCMA_CC_PPL_PCHI_OFF 5
2512 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f
2514 +#define BCMA_CC_PMU_PLL_CTL0 0
2515 +#define BCMA_CC_PMU_PLL_CTL1 1
2516 +#define BCMA_CC_PMU_PLL_CTL2 2
2517 +#define BCMA_CC_PMU_PLL_CTL3 3
2518 +#define BCMA_CC_PMU_PLL_CTL4 4
2519 +#define BCMA_CC_PMU_PLL_CTL5 5
2521 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
2522 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
2524 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
2525 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
2527 /* BCM4331 ChipControl numbers. */
2528 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
2529 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
2530 @@ -297,9 +334,18 @@
2531 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
2532 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
2533 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
2534 +#define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
2535 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
2536 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
2538 +/* 43224 chip-specific ChipControl register bits */
2539 +#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
2540 +#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
2541 +#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
2543 +/* 4313 Chip specific ChipControl register bits */
2544 +#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
2546 /* Data for the PMU, if available.
2547 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
2549 @@ -387,5 +433,6 @@ extern void bcma_chipco_chipctl_maskset(
2550 u32 offset, u32 mask, u32 set);
2551 extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
2552 u32 offset, u32 mask, u32 set);
2553 +extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
2555 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
2556 --- a/include/linux/bcma/bcma_driver_pci.h
2557 +++ b/include/linux/bcma/bcma_driver_pci.h
2558 @@ -53,11 +53,47 @@ struct pci_dev;
2559 #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
2560 #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
2561 #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
2562 +#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
2563 +#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
2564 +#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
2565 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
2566 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
2567 +#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
2568 +#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
2569 +#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
2570 +#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
2571 +#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
2572 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
2573 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
2574 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
2575 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
2576 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
2577 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
2578 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
2579 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
2580 +#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
2581 +#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
2582 +#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
2583 +#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
2584 +#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
2585 +#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
2586 +#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
2587 +#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
2588 +#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
2589 +#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
2590 +#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
2591 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
2592 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
2593 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
2594 #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
2595 #define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
2596 +#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */
2597 +#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */
2598 +#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */
2599 +#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */
2600 +#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
2601 +#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
2602 +#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */
2605 #define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
2606 @@ -72,20 +108,118 @@ struct pci_dev;
2607 #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
2608 #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
2610 +/* PCIE protocol PHY diagnostic registers */
2611 +#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
2612 +#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
2613 +#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
2614 +#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
2615 +#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
2616 +#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
2617 +#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
2618 +#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
2619 +#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
2620 +#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
2621 +#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
2622 +#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
2623 +#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
2624 +#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
2625 +#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
2626 +#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
2627 +#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
2629 +/* PCIE protocol DLLP diagnostic registers */
2630 +#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
2631 +#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
2632 +#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
2633 +#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
2634 +#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
2635 +#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
2636 +#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
2637 +#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
2638 +#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
2639 +#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
2640 +#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
2641 +#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
2642 +#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
2643 +#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
2644 +#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
2645 +#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
2646 +#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
2647 +#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
2648 +#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
2649 +#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
2650 +#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
2651 +#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
2652 +#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
2653 +#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
2655 +/* SERDES RX registers */
2656 +#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
2657 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
2658 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
2659 +#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
2660 +#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
2661 +#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
2663 +/* SERDES PLL registers */
2664 +#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
2665 +#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
2667 /* PCIcore specific boardflags */
2668 #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
2670 +/* PCIE Config space accessing MACROS */
2671 +#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
2672 +#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
2673 +#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
2674 +#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
2676 +#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
2677 +#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
2678 +#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
2679 +#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
2681 +/* PCIE Root Capability Register bits (Host mode only) */
2682 +#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
2684 +struct bcma_drv_pci;
2686 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
2687 +struct bcma_drv_pci_host {
2688 + struct bcma_drv_pci *pdev;
2690 + u32 host_cfg_addr;
2691 + spinlock_t cfgspace_lock;
2693 + struct pci_controller pci_controller;
2694 + struct pci_ops pci_ops;
2695 + struct resource mem_resource;
2696 + struct resource io_resource;
2700 struct bcma_drv_pci {
2701 struct bcma_device *core;
2705 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
2706 + struct bcma_drv_pci_host *host_controller;
2710 /* Register access */
2711 +#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
2712 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
2713 +#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
2714 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
2716 -extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
2717 +extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
2718 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
2719 struct bcma_device *core, bool enable);
2720 +extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
2722 +extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
2723 +extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
2725 #endif /* LINUX_BCMA_DRIVER_PCI_H_ */
2726 --- a/include/linux/bcma/bcma_regs.h
2727 +++ b/include/linux/bcma/bcma_regs.h
2729 #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
2730 #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
2732 +/* SiliconBackplane Address Map.
2733 + * All regions may not exist on all chips.
2735 +#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
2736 +#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
2737 +#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
2738 +#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
2739 +#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
2740 +#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
2743 +#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
2744 +#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
2745 +#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
2746 +#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
2747 + * (2 ZettaBytes), low 32 bits
2749 +#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
2750 + * (2 ZettaBytes), high 32 bits
2753 +#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
2754 +#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
2755 +#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
2756 + * (2 ZettaBytes), high 32 bits
2759 #endif /* LINUX_BCMA_REGS_H_ */