2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/rtl8366s.h>
20 #include "rtl8366_smi.h"
22 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
23 #define RTL8366S_DRIVER_VER "0.2.2"
25 #define RTL8366S_PHY_NO_MAX 4
26 #define RTL8366S_PHY_PAGE_MAX 7
27 #define RTL8366S_PHY_ADDR_MAX 31
29 /* Switch Global Configuration register */
30 #define RTL8366S_SGCR 0x0000
31 #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
32 #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
33 #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
34 #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
35 #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
36 #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
37 #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
38 #define RTL8366S_SGCR_EN_VLAN BIT(13)
40 /* Port Enable Control register */
41 #define RTL8366S_PECR 0x0001
43 /* Switch Security Control registers */
44 #define RTL8366S_SSCR0 0x0002
45 #define RTL8366S_SSCR1 0x0003
46 #define RTL8366S_SSCR2 0x0004
47 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
49 #define RTL8366S_RESET_CTRL_REG 0x0100
50 #define RTL8366S_CHIP_CTRL_RESET_HW 1
51 #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
53 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
54 #define RTL8366S_CHIP_VERSION_MASK 0xf
55 #define RTL8366S_CHIP_ID_REG 0x0105
56 #define RTL8366S_CHIP_ID_8366 0x8366
58 /* PHY registers control */
59 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
60 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
62 #define RTL8366S_PHY_CTRL_READ 1
63 #define RTL8366S_PHY_CTRL_WRITE 0
65 #define RTL8366S_PHY_REG_MASK 0x1f
66 #define RTL8366S_PHY_PAGE_OFFSET 5
67 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
68 #define RTL8366S_PHY_NO_OFFSET 9
69 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
71 /* LED control registers */
72 #define RTL8366S_LED_BLINKRATE_REG 0x0420
73 #define RTL8366S_LED_BLINKRATE_BIT 0
74 #define RTL8366S_LED_BLINKRATE_MASK 0x0007
76 #define RTL8366S_LED_CTRL_REG 0x0421
77 #define RTL8366S_LED_0_1_CTRL_REG 0x0422
78 #define RTL8366S_LED_2_3_CTRL_REG 0x0423
80 #define RTL8366S_MIB_COUNT 33
81 #define RTL8366S_GLOBAL_MIB_COUNT 1
82 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
83 #define RTL8366S_MIB_COUNTER_BASE 0x1000
84 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
85 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
86 #define RTL8366S_MIB_CTRL_REG 0x11F0
87 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
88 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
89 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
91 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
92 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
93 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
96 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
97 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
98 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
99 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
100 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
103 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
104 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
106 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
108 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
109 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
110 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
112 #define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2)
114 #define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379
116 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
117 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
118 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
119 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
120 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
121 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
122 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
125 #define RTL8366S_PORT_NUM_CPU 5
126 #define RTL8366S_NUM_PORTS 6
127 #define RTL8366S_NUM_VLANS 16
128 #define RTL8366S_NUM_LEDGROUPS 4
129 #define RTL8366S_NUM_VIDS 4096
130 #define RTL8366S_PRIORITYMAX 7
131 #define RTL8366S_FIDMAX 7
134 #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
135 #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
136 #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
137 #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
139 #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
140 #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
142 #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
146 RTL8366S_PORT_UNKNOWN | \
149 #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
153 RTL8366S_PORT_UNKNOWN)
155 #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
160 #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
163 #define RTL8366S_VLAN_VID_MASK 0xfff
164 #define RTL8366S_VLAN_PRIORITY_SHIFT 12
165 #define RTL8366S_VLAN_PRIORITY_MASK 0x7
166 #define RTL8366S_VLAN_MEMBER_MASK 0x3f
167 #define RTL8366S_VLAN_UNTAG_SHIFT 6
168 #define RTL8366S_VLAN_UNTAG_MASK 0x3f
169 #define RTL8366S_VLAN_FID_SHIFT 12
170 #define RTL8366S_VLAN_FID_MASK 0x7
173 struct device *parent;
174 struct rtl8366_smi smi;
177 static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
178 { 0, 0, 4, "IfInOctets" },
179 { 0, 4, 4, "EtherStatsOctets" },
180 { 0, 8, 2, "EtherStatsUnderSizePkts" },
181 { 0, 10, 2, "EtherFragments" },
182 { 0, 12, 2, "EtherStatsPkts64Octets" },
183 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
184 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
185 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
186 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
187 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
188 { 0, 24, 2, "EtherOversizeStats" },
189 { 0, 26, 2, "EtherStatsJabbers" },
190 { 0, 28, 2, "IfInUcastPkts" },
191 { 0, 30, 2, "EtherStatsMulticastPkts" },
192 { 0, 32, 2, "EtherStatsBroadcastPkts" },
193 { 0, 34, 2, "EtherStatsDropEvents" },
194 { 0, 36, 2, "Dot3StatsFCSErrors" },
195 { 0, 38, 2, "Dot3StatsSymbolErrors" },
196 { 0, 40, 2, "Dot3InPauseFrames" },
197 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
198 { 0, 44, 4, "IfOutOctets" },
199 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
200 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
201 { 0, 52, 2, "Dot3sDeferredTransmissions" },
202 { 0, 54, 2, "Dot3StatsLateCollisions" },
203 { 0, 56, 2, "EtherStatsCollisions" },
204 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
205 { 0, 60, 2, "Dot3OutPauseFrames" },
206 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
209 * The following counters are accessible at a different
212 { 1, 0, 2, "Dot1dTpPortInDiscards" },
213 { 1, 2, 2, "IfOutUcastPkts" },
214 { 1, 4, 2, "IfOutMulticastPkts" },
215 { 1, 6, 2, "IfOutBroadcastPkts" },
218 #define REG_WR(_smi, _reg, _val) \
220 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
225 #define REG_RMW(_smi, _reg, _mask, _val) \
227 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
232 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
234 return container_of(smi, struct rtl8366s, smi);
237 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
239 struct rtl8366_smi *smi = sw_to_rtl8366_smi(sw);
240 return smi_to_rtl8366s(smi);
243 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
248 rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
249 RTL8366S_CHIP_CTRL_RESET_HW);
252 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
255 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
260 printk("Timeout waiting for the switch to reset\n");
267 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
271 /* set maximum packet length to 1536 bytes */
272 REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
273 RTL8366S_SGCR_MAX_LENGTH_1536);
275 /* enable all ports */
276 REG_WR(smi, RTL8366S_PECR, 0);
278 /* disable learning for all ports */
279 REG_WR(smi, RTL8366S_SSCR0, RTL8366S_PORT_ALL);
281 /* disable auto ageing for all ports */
282 REG_WR(smi, RTL8366S_SSCR1, RTL8366S_PORT_ALL);
285 * discard VLAN tagged packets if the port is not a member of
286 * the VLAN with which the packets is associated.
288 REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
290 /* don't drop packets whose DA has not been learned */
291 REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
296 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
297 u32 phy_no, u32 page, u32 addr, u32 *data)
302 if (phy_no > RTL8366S_PHY_NO_MAX)
305 if (page > RTL8366S_PHY_PAGE_MAX)
308 if (addr > RTL8366S_PHY_ADDR_MAX)
311 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
312 RTL8366S_PHY_CTRL_READ);
316 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
317 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
318 (addr & RTL8366S_PHY_REG_MASK);
320 ret = rtl8366_smi_write_reg(smi, reg, 0);
324 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
331 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
332 u32 phy_no, u32 page, u32 addr, u32 data)
337 if (phy_no > RTL8366S_PHY_NO_MAX)
340 if (page > RTL8366S_PHY_PAGE_MAX)
343 if (addr > RTL8366S_PHY_ADDR_MAX)
346 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
347 RTL8366S_PHY_CTRL_WRITE);
351 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
352 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
353 (addr & RTL8366S_PHY_REG_MASK);
355 ret = rtl8366_smi_write_reg(smi, reg, data);
362 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
363 int port, unsigned long long *val)
370 if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
373 switch (rtl8366s_mib_counters[counter].base) {
375 addr = RTL8366S_MIB_COUNTER_BASE +
376 RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
380 addr = RTL8366S_MIB_COUNTER_BASE2 +
381 RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
388 addr += rtl8366s_mib_counters[counter].offset;
391 * Writing access counter address first
392 * then ASIC will prepare 64bits counter wait for being retrived
394 data = 0; /* writing data will be discard by ASIC */
395 err = rtl8366_smi_write_reg(smi, addr, data);
399 /* read MIB control register */
400 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
404 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
407 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
411 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
412 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
416 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
423 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
424 struct rtl8366_vlan_4k *vlan4k)
430 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
432 if (vid >= RTL8366S_NUM_VIDS)
436 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
437 vid & RTL8366S_VLAN_VID_MASK);
441 /* write table access control word */
442 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
443 RTL8366S_TABLE_VLAN_READ_CTRL);
447 for (i = 0; i < 2; i++) {
448 err = rtl8366_smi_read_reg(smi,
449 RTL8366S_VLAN_TABLE_READ_BASE + i,
456 vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
457 RTL8366S_VLAN_UNTAG_MASK;
458 vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
459 vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
460 RTL8366S_VLAN_FID_MASK;
465 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
466 const struct rtl8366_vlan_4k *vlan4k)
472 if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
473 vlan4k->member > RTL8366S_PORT_ALL ||
474 vlan4k->untag > RTL8366S_PORT_ALL ||
475 vlan4k->fid > RTL8366S_FIDMAX)
478 data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
479 data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
480 ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
481 RTL8366S_VLAN_UNTAG_SHIFT) |
482 ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
483 RTL8366S_VLAN_FID_SHIFT);
485 for (i = 0; i < 2; i++) {
486 err = rtl8366_smi_write_reg(smi,
487 RTL8366S_VLAN_TABLE_WRITE_BASE + i,
493 /* write table access control word */
494 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
495 RTL8366S_TABLE_VLAN_WRITE_CTRL);
500 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
501 struct rtl8366_vlan_mc *vlanmc)
507 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
509 if (index >= RTL8366S_NUM_VLANS)
512 for (i = 0; i < 2; i++) {
513 err = rtl8366_smi_read_reg(smi,
514 RTL8366S_VLAN_MC_BASE(index) + i,
520 vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
521 vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
522 RTL8366S_VLAN_PRIORITY_MASK;
523 vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
524 RTL8366S_VLAN_UNTAG_MASK;
525 vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
526 vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
527 RTL8366S_VLAN_FID_MASK;
532 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
533 const struct rtl8366_vlan_mc *vlanmc)
539 if (index >= RTL8366S_NUM_VLANS ||
540 vlanmc->vid >= RTL8366S_NUM_VIDS ||
541 vlanmc->priority > RTL8366S_PRIORITYMAX ||
542 vlanmc->member > RTL8366S_PORT_ALL ||
543 vlanmc->untag > RTL8366S_PORT_ALL ||
544 vlanmc->fid > RTL8366S_FIDMAX)
547 data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
548 ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
549 RTL8366S_VLAN_PRIORITY_SHIFT);
550 data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
551 ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
552 RTL8366S_VLAN_UNTAG_SHIFT) |
553 ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
554 RTL8366S_VLAN_FID_SHIFT);
556 for (i = 0; i < 2; i++) {
557 err = rtl8366_smi_write_reg(smi,
558 RTL8366S_VLAN_MC_BASE(index) + i,
567 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
572 if (port >= RTL8366S_NUM_PORTS)
575 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
580 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
581 RTL8366S_PORT_VLAN_CTRL_MASK;
586 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
588 if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
591 return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
592 RTL8366S_PORT_VLAN_CTRL_MASK <<
593 RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
594 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
595 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
598 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
600 return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
601 (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
604 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
606 return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
607 1, (enable) ? 1 : 0);
610 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
611 const struct switch_attr *attr,
612 struct switch_val *val)
614 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
616 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
619 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
620 const struct switch_attr *attr,
621 struct switch_val *val)
623 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
626 if (attr->ofs == 1) {
627 rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
629 if (data & RTL8366S_SGCR_EN_VLAN)
633 } else if (attr->ofs == 2) {
634 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
645 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
646 const struct switch_attr *attr,
647 struct switch_val *val)
649 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
652 rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
654 val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
659 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
660 const struct switch_attr *attr,
661 struct switch_val *val)
663 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
665 if (val->value.i >= 6)
668 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
669 RTL8366S_LED_BLINKRATE_MASK,
673 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
674 const struct switch_attr *attr,
675 struct switch_val *val)
677 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
680 return rtl8366s_vlan_set_vlan(smi, val->value.i);
682 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
685 static const char *rtl8366s_speed_str(unsigned speed)
699 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
700 const struct switch_attr *attr,
701 struct switch_val *val)
703 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
704 u32 len = 0, data = 0;
706 if (val->port_vlan >= RTL8366S_NUM_PORTS)
709 memset(smi->buf, '\0', sizeof(smi->buf));
710 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
711 (val->port_vlan / 2), &data);
713 if (val->port_vlan % 2)
716 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
717 len = snprintf(smi->buf, sizeof(smi->buf),
718 "port:%d link:up speed:%s %s-duplex %s%s%s",
720 rtl8366s_speed_str(data &
721 RTL8366S_PORT_STATUS_SPEED_MASK),
722 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
724 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
726 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
728 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
731 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
735 val->value.s = smi->buf;
741 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
742 const struct switch_attr *attr,
743 struct switch_val *val)
747 struct rtl8366_vlan_4k vlan4k;
748 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
749 char *buf = smi->buf;
752 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
755 memset(buf, '\0', sizeof(smi->buf));
757 err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
761 len += snprintf(buf + len, sizeof(smi->buf) - len,
762 "VLAN %d: Ports: '", vlan4k.vid);
764 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
765 if (!(vlan4k.member & (1 << i)))
768 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
769 (vlan4k.untag & (1 << i)) ? "" : "t");
772 len += snprintf(buf + len, sizeof(smi->buf) - len,
773 "', members=%04x, untag=%04x, fid=%u",
774 vlan4k.member, vlan4k.untag, vlan4k.fid);
782 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
783 const struct switch_attr *attr,
784 struct switch_val *val)
786 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
791 if (val->port_vlan >= RTL8366S_NUM_PORTS ||
792 (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
795 if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
796 reg = RTL8366S_LED_BLINKRATE_REG;
798 data = val->value.i << 4;
800 reg = RTL8366S_LED_CTRL_REG;
801 mask = 0xF << (val->port_vlan * 4),
802 data = val->value.i << (val->port_vlan * 4);
805 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data);
808 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
809 const struct switch_attr *attr,
810 struct switch_val *val)
812 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
815 if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
818 rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
819 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
824 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
825 const struct switch_attr *attr,
826 struct switch_val *val)
828 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
830 if (val->port_vlan >= RTL8366S_NUM_PORTS)
834 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
835 0, (1 << (val->port_vlan + 3)));
838 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
839 const struct switch_attr *attr,
840 struct switch_val *val)
842 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
844 unsigned long long counter = 0;
845 char *buf = smi->buf;
847 if (val->port_vlan >= RTL8366S_NUM_PORTS)
850 len += snprintf(buf + len, sizeof(smi->buf) - len,
851 "Port %d MIB counters\n",
854 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
855 len += snprintf(buf + len, sizeof(smi->buf) - len,
856 "%-36s: ", rtl8366s_mib_counters[i].name);
857 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
858 len += snprintf(buf + len, sizeof(smi->buf) - len,
861 len += snprintf(buf + len, sizeof(smi->buf) - len,
870 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
871 struct switch_val *val)
873 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
874 struct switch_port *port;
875 struct rtl8366_vlan_4k vlan4k;
878 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
881 rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
883 port = &val->value.ports[0];
885 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
886 if (!(vlan4k.member & BIT(i)))
890 port->flags = (vlan4k.untag & BIT(i)) ?
891 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
898 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
899 struct switch_val *val)
901 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
902 struct switch_port *port;
907 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
910 port = &val->value.ports[0];
911 for (i = 0; i < val->len; i++, port++) {
912 member |= BIT(port->id);
914 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
915 untag |= BIT(port->id);
918 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
921 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
923 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
924 return rtl8366_get_pvid(smi, port, val);
927 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
929 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
930 return rtl8366_set_pvid(smi, port, val);
933 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
935 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
938 err = rtl8366s_reset_chip(smi);
942 err = rtl8366s_hw_init(smi);
946 return rtl8366_reset_vlan(smi);
949 static struct switch_attr rtl8366s_globals[] = {
951 .type = SWITCH_TYPE_INT,
952 .name = "enable_vlan",
953 .description = "Enable VLAN mode",
954 .set = rtl8366s_sw_set_vlan_enable,
955 .get = rtl8366s_sw_get_vlan_enable,
959 .type = SWITCH_TYPE_INT,
960 .name = "enable_vlan4k",
961 .description = "Enable VLAN 4K mode",
962 .set = rtl8366s_sw_set_vlan_enable,
963 .get = rtl8366s_sw_get_vlan_enable,
967 .type = SWITCH_TYPE_NOVAL,
968 .name = "reset_mibs",
969 .description = "Reset all MIB counters",
970 .set = rtl8366s_sw_reset_mibs,
972 .type = SWITCH_TYPE_INT,
974 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
975 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
976 .set = rtl8366s_sw_set_blinkrate,
977 .get = rtl8366s_sw_get_blinkrate,
982 static struct switch_attr rtl8366s_port[] = {
984 .type = SWITCH_TYPE_STRING,
986 .description = "Get port link information",
989 .get = rtl8366s_sw_get_port_link,
991 .type = SWITCH_TYPE_NOVAL,
993 .description = "Reset single port MIB counters",
994 .set = rtl8366s_sw_reset_port_mibs,
996 .type = SWITCH_TYPE_STRING,
998 .description = "Get MIB counters for port",
1001 .get = rtl8366s_sw_get_port_mib,
1003 .type = SWITCH_TYPE_INT,
1005 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1007 .set = rtl8366s_sw_set_port_led,
1008 .get = rtl8366s_sw_get_port_led,
1012 static struct switch_attr rtl8366s_vlan[] = {
1014 .type = SWITCH_TYPE_STRING,
1016 .description = "Get vlan information",
1019 .get = rtl8366s_sw_get_vlan_info,
1024 static struct switch_dev rtl8366_switch_dev = {
1026 .cpu_port = RTL8366S_PORT_NUM_CPU,
1027 .ports = RTL8366S_NUM_PORTS,
1028 .vlans = RTL8366S_NUM_VLANS,
1030 .attr = rtl8366s_globals,
1031 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1034 .attr = rtl8366s_port,
1035 .n_attr = ARRAY_SIZE(rtl8366s_port),
1038 .attr = rtl8366s_vlan,
1039 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1042 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1043 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1044 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1045 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1046 .reset_switch = rtl8366s_sw_reset_switch,
1049 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1051 struct switch_dev *dev = &rtl->smi.sw_dev;
1054 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1056 dev->devname = dev_name(rtl->parent);
1058 err = register_switch(dev, NULL);
1060 dev_err(rtl->parent, "switch registration failed\n");
1065 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1067 unregister_switch(&rtl->smi.sw_dev);
1070 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1072 struct rtl8366_smi *smi = bus->priv;
1076 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1083 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1085 struct rtl8366_smi *smi = bus->priv;
1089 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1091 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1096 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1098 return (bus->read == rtl8366s_mii_read &&
1099 bus->write == rtl8366s_mii_write);
1102 static int rtl8366s_setup(struct rtl8366s *rtl)
1104 struct rtl8366_smi *smi = &rtl->smi;
1107 ret = rtl8366s_reset_chip(smi);
1111 ret = rtl8366s_hw_init(smi);
1115 static int rtl8366s_detect(struct rtl8366_smi *smi)
1121 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1123 dev_err(smi->parent, "unable to read chip id\n");
1128 case RTL8366S_CHIP_ID_8366:
1131 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1135 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1138 dev_err(smi->parent, "unable to read chip version\n");
1142 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1143 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1148 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1149 .detect = rtl8366s_detect,
1150 .mii_read = rtl8366s_mii_read,
1151 .mii_write = rtl8366s_mii_write,
1153 .get_vlan_mc = rtl8366s_get_vlan_mc,
1154 .set_vlan_mc = rtl8366s_set_vlan_mc,
1155 .get_vlan_4k = rtl8366s_get_vlan_4k,
1156 .set_vlan_4k = rtl8366s_set_vlan_4k,
1157 .get_mc_index = rtl8366s_get_mc_index,
1158 .set_mc_index = rtl8366s_set_mc_index,
1159 .get_mib_counter = rtl8366_get_mib_counter,
1162 static int __init rtl8366s_probe(struct platform_device *pdev)
1164 static int rtl8366_smi_version_printed;
1165 struct rtl8366s_platform_data *pdata;
1166 struct rtl8366s *rtl;
1167 struct rtl8366_smi *smi;
1170 if (!rtl8366_smi_version_printed++)
1171 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1172 " version " RTL8366S_DRIVER_VER"\n");
1174 pdata = pdev->dev.platform_data;
1176 dev_err(&pdev->dev, "no platform data specified\n");
1181 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1183 dev_err(&pdev->dev, "no memory for private data\n");
1188 rtl->parent = &pdev->dev;
1191 smi->parent = &pdev->dev;
1192 smi->gpio_sda = pdata->gpio_sda;
1193 smi->gpio_sck = pdata->gpio_sck;
1194 smi->ops = &rtl8366s_smi_ops;
1195 smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1196 smi->num_ports = RTL8366S_NUM_PORTS;
1197 smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1198 smi->mib_counters = rtl8366s_mib_counters;
1199 smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
1201 err = rtl8366_smi_init(smi);
1205 platform_set_drvdata(pdev, rtl);
1207 err = rtl8366s_setup(rtl);
1209 goto err_clear_drvdata;
1211 err = rtl8366s_switch_init(rtl);
1213 goto err_clear_drvdata;
1218 platform_set_drvdata(pdev, NULL);
1219 rtl8366_smi_cleanup(smi);
1226 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1228 if (!rtl8366s_mii_bus_match(phydev->bus))
1234 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1239 static struct phy_driver rtl8366s_phy_driver = {
1240 .phy_id = 0x001cc960,
1241 .name = "Realtek RTL8366S",
1242 .phy_id_mask = 0x1ffffff0,
1243 .features = PHY_GBIT_FEATURES,
1244 .config_aneg = rtl8366s_phy_config_aneg,
1245 .config_init = rtl8366s_phy_config_init,
1246 .read_status = genphy_read_status,
1248 .owner = THIS_MODULE,
1252 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1254 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1257 rtl8366s_switch_cleanup(rtl);
1258 platform_set_drvdata(pdev, NULL);
1259 rtl8366_smi_cleanup(&rtl->smi);
1266 static struct platform_driver rtl8366s_driver = {
1268 .name = RTL8366S_DRIVER_NAME,
1269 .owner = THIS_MODULE,
1271 .probe = rtl8366s_probe,
1272 .remove = __devexit_p(rtl8366s_remove),
1275 static int __init rtl8366s_module_init(void)
1278 ret = platform_driver_register(&rtl8366s_driver);
1282 ret = phy_driver_register(&rtl8366s_phy_driver);
1284 goto err_platform_unregister;
1288 err_platform_unregister:
1289 platform_driver_unregister(&rtl8366s_driver);
1292 module_init(rtl8366s_module_init);
1294 static void __exit rtl8366s_module_exit(void)
1296 phy_driver_unregister(&rtl8366s_phy_driver);
1297 platform_driver_unregister(&rtl8366s_driver);
1299 module_exit(rtl8366s_module_exit);
1301 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1302 MODULE_VERSION(RTL8366S_DRIVER_VER);
1303 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1304 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1305 MODULE_LICENSE("GPL v2");
1306 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);