2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
21 #include "rtl8366_smi.h"
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
27 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
28 #define RTL8366RB_DRIVER_VER "0.2.2"
30 #define RTL8366RB_PHY_NO_MAX 4
31 #define RTL8366RB_PHY_PAGE_MAX 7
32 #define RTL8366RB_PHY_ADDR_MAX 31
34 #define RTL8366RB_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366RB_CHIP_CTRL_VLAN (1 << 13)
36 #define RTL8366RB_CHIP_CTRL_VLAN_4KTB (1 << 14)
38 /* Switch Global Configuration register */
39 #define RTL8366RB_SGCR 0x0000
40 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
41 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
42 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
43 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
44 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
45 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
46 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
48 /* Port Enable Control register */
49 #define RTL8366RB_PECR 0x0001
51 /* Switch Security Control registers */
52 #define RTL8366RB_SSCR0 0x0002
53 #define RTL8366RB_SSCR1 0x0003
54 #define RTL8366RB_SSCR2 0x0004
55 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
57 #define RTL8366RB_RESET_CTRL_REG 0x0100
58 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
59 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
61 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
62 #define RTL8366RB_CHIP_VERSION_MASK 0xf
63 #define RTL8366RB_CHIP_ID_REG 0x0509
64 #define RTL8366RB_CHIP_ID_8366 0x5937
66 /* PHY registers control */
67 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
68 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
70 #define RTL8366RB_PHY_CTRL_READ 1
71 #define RTL8366RB_PHY_CTRL_WRITE 0
73 #define RTL8366RB_PHY_REG_MASK 0x1f
74 #define RTL8366RB_PHY_PAGE_OFFSET 5
75 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
76 #define RTL8366RB_PHY_NO_OFFSET 9
77 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
79 /* LED control registers */
80 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
81 #define RTL8366RB_LED_BLINKRATE_BIT 0
82 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
84 #define RTL8366RB_LED_CTRL_REG 0x0431
85 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
86 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
88 #define RTL8366RB_MIB_COUNT 33
89 #define RTL8366RB_GLOBAL_MIB_COUNT 1
90 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
91 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
92 #define RTL8366RB_MIB_CTRL_REG 0x13F0
93 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
94 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
95 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
96 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
97 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
99 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
100 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
101 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
102 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
103 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
106 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
107 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
110 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
111 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
112 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
114 #define RTL8366RB_VLAN_MEMCONF_BASE 0x0020
117 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
118 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
119 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
120 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
121 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
122 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
123 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
126 #define RTL8366RB_PORT_NUM_CPU 5
127 #define RTL8366RB_NUM_PORTS 6
128 #define RTL8366RB_NUM_VLANS 16
129 #define RTL8366RB_NUM_LEDGROUPS 4
130 #define RTL8366RB_NUM_VIDS 4096
131 #define RTL8366RB_PRIORITYMAX 7
132 #define RTL8366RB_FIDMAX 7
135 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
136 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
137 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
138 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
139 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
141 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
143 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
150 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
156 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
161 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
164 struct device *parent;
165 struct rtl8366_smi smi;
166 struct switch_dev dev;
167 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
168 struct dentry *debugfs_root;
172 struct rtl8366rb_vlan_mc {
184 struct rtl8366rb_vlan_4k {
193 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
203 static struct mib_counter rtl8366rb_mib_counters[RTL8366RB_MIB_COUNT] = {
204 { 0, 4, "IfInOctets" },
205 { 4, 4, "EtherStatsOctets" },
206 { 8, 2, "EtherStatsUnderSizePkts" },
207 { 10, 2, "EtherFragments" },
208 { 12, 2, "EtherStatsPkts64Octets" },
209 { 14, 2, "EtherStatsPkts65to127Octets" },
210 { 16, 2, "EtherStatsPkts128to255Octets" },
211 { 18, 2, "EtherStatsPkts256to511Octets" },
212 { 20, 2, "EtherStatsPkts512to1023Octets" },
213 { 22, 2, "EtherStatsPkts1024to1518Octets" },
214 { 24, 2, "EtherOversizeStats" },
215 { 26, 2, "EtherStatsJabbers" },
216 { 28, 2, "IfInUcastPkts" },
217 { 30, 2, "EtherStatsMulticastPkts" },
218 { 32, 2, "EtherStatsBroadcastPkts" },
219 { 34, 2, "EtherStatsDropEvents" },
220 { 36, 2, "Dot3StatsFCSErrors" },
221 { 38, 2, "Dot3StatsSymbolErrors" },
222 { 40, 2, "Dot3InPauseFrames" },
223 { 42, 2, "Dot3ControlInUnknownOpcodes" },
224 { 44, 4, "IfOutOctets" },
225 { 48, 2, "Dot3StatsSingleCollisionFrames" },
226 { 50, 2, "Dot3StatMultipleCollisionFrames" },
227 { 52, 2, "Dot3sDeferredTransmissions" },
228 { 54, 2, "Dot3StatsLateCollisions" },
229 { 56, 2, "EtherStatsCollisions" },
230 { 58, 2, "Dot3StatsExcessiveCollisions" },
231 { 60, 2, "Dot3OutPauseFrames" },
232 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
233 { 64, 2, "Dot1dTpPortInDiscards" },
234 { 66, 2, "IfOutUcastPkts" },
235 { 68, 2, "IfOutMulticastPkts" },
236 { 70, 2, "IfOutBroadcastPkts" },
239 #define REG_WR(_smi, _reg, _val) \
241 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
246 #define REG_RMW(_smi, _reg, _mask, _val) \
248 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
253 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
255 return container_of(smi, struct rtl8366rb, smi);
258 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
260 return container_of(sw, struct rtl8366rb, dev);
263 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
265 struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
269 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
274 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
275 RTL8366RB_CHIP_CTRL_RESET_HW);
278 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
281 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
286 printk("Timeout waiting for the switch to reset\n");
293 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
297 /* set maximum packet length to 1536 bytes */
298 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
299 RTL8366RB_SGCR_MAX_LENGTH_1536);
301 /* enable all ports */
302 REG_WR(smi, RTL8366RB_PECR, 0);
304 /* disable learning for all ports */
305 REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
307 /* disable auto ageing for all ports */
308 REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
310 /* don't drop packets whose DA has not been learned */
311 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
316 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
317 u32 phy_no, u32 page, u32 addr, u32 *data)
322 if (phy_no > RTL8366RB_PHY_NO_MAX)
325 if (page > RTL8366RB_PHY_PAGE_MAX)
328 if (addr > RTL8366RB_PHY_ADDR_MAX)
331 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
332 RTL8366RB_PHY_CTRL_READ);
336 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
337 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
338 (addr & RTL8366RB_PHY_REG_MASK);
340 ret = rtl8366_smi_write_reg(smi, reg, 0);
344 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
351 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
352 u32 phy_no, u32 page, u32 addr, u32 data)
357 if (phy_no > RTL8366RB_PHY_NO_MAX)
360 if (page > RTL8366RB_PHY_PAGE_MAX)
363 if (addr > RTL8366RB_PHY_ADDR_MAX)
366 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
367 RTL8366RB_PHY_CTRL_WRITE);
371 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
372 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
373 (addr & RTL8366RB_PHY_REG_MASK);
375 ret = rtl8366_smi_write_reg(smi, reg, data);
382 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
383 int port, unsigned long long *val)
390 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
393 addr = RTL8366RB_MIB_COUNTER_BASE +
394 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
395 rtl8366rb_mib_counters[counter].offset;
398 * Writing access counter address first
399 * then ASIC will prepare 64bits counter wait for being retrived
401 data = 0; /* writing data will be discard by ASIC */
402 err = rtl8366_smi_write_reg(smi, addr, data);
406 /* read MIB control register */
407 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
411 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
414 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
418 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
419 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
423 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
430 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
431 struct rtl8366_vlan_4k *vlan4k)
433 struct rtl8366rb_vlan_4k vlan4k_priv;
438 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
439 vlan4k_priv.vid = vid;
441 if (vid >= RTL8366RB_NUM_VIDS)
444 tableaddr = (u16 *)&vlan4k_priv;
448 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
452 /* write table access control word */
453 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
454 RTL8366RB_TABLE_VLAN_READ_CTRL);
458 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
465 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
473 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
480 vlan4k->untag = vlan4k_priv.untag;
481 vlan4k->member = vlan4k_priv.member;
482 vlan4k->fid = vlan4k_priv.fid;
487 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
488 const struct rtl8366_vlan_4k *vlan4k)
490 struct rtl8366rb_vlan_4k vlan4k_priv;
495 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
496 vlan4k->member > RTL8366RB_PORT_ALL ||
497 vlan4k->untag > RTL8366RB_PORT_ALL ||
498 vlan4k->fid > RTL8366RB_FIDMAX)
501 vlan4k_priv.vid = vlan4k->vid;
502 vlan4k_priv.untag = vlan4k->untag;
503 vlan4k_priv.member = vlan4k->member;
504 vlan4k_priv.fid = vlan4k->fid;
506 tableaddr = (u16 *)&vlan4k_priv;
510 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
518 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
527 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
532 /* write table access control word */
533 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
534 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
539 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
540 struct rtl8366_vlan_mc *vlanmc)
542 struct rtl8366rb_vlan_mc vlanmc_priv;
548 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
550 if (index >= RTL8366RB_NUM_VLANS)
553 tableaddr = (u16 *)&vlanmc_priv;
555 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
556 err = rtl8366_smi_read_reg(smi, addr, &data);
563 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
564 err = rtl8366_smi_read_reg(smi, addr, &data);
571 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
572 err = rtl8366_smi_read_reg(smi, addr, &data);
578 vlanmc->vid = vlanmc_priv.vid;
579 vlanmc->priority = vlanmc_priv.priority;
580 vlanmc->untag = vlanmc_priv.untag;
581 vlanmc->member = vlanmc_priv.member;
582 vlanmc->fid = vlanmc_priv.fid;
587 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
588 const struct rtl8366_vlan_mc *vlanmc)
590 struct rtl8366rb_vlan_mc vlanmc_priv;
596 if (index >= RTL8366RB_NUM_VLANS ||
597 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
598 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
599 vlanmc->member > RTL8366RB_PORT_ALL ||
600 vlanmc->untag > RTL8366RB_PORT_ALL ||
601 vlanmc->fid > RTL8366RB_FIDMAX)
604 vlanmc_priv.vid = vlanmc->vid;
605 vlanmc_priv.priority = vlanmc->priority;
606 vlanmc_priv.untag = vlanmc->untag;
607 vlanmc_priv.member = vlanmc->member;
608 vlanmc_priv.stag_mbr = 0;
609 vlanmc_priv.stag_idx = 0;
610 vlanmc_priv.fid = vlanmc->fid;
612 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
614 tableaddr = (u16 *)&vlanmc_priv;
617 err = rtl8366_smi_write_reg(smi, addr, data);
621 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
626 err = rtl8366_smi_write_reg(smi, addr, data);
630 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
635 err = rtl8366_smi_write_reg(smi, addr, data);
641 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
646 if (port >= RTL8366RB_NUM_PORTS)
649 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
654 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
655 RTL8366RB_PORT_VLAN_CTRL_MASK;
661 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
663 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
666 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
667 RTL8366RB_PORT_VLAN_CTRL_MASK <<
668 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
669 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
670 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
673 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
675 return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
676 RTL8366RB_CHIP_CTRL_VLAN,
677 (enable) ? RTL8366RB_CHIP_CTRL_VLAN : 0);
680 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
682 return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
683 RTL8366RB_CHIP_CTRL_VLAN_4KTB,
684 (enable) ? RTL8366RB_CHIP_CTRL_VLAN_4KTB : 0);
687 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
688 static int rtl8366rb_debugfs_open(struct inode *inode, struct file *file)
690 file->private_data = inode->i_private;
694 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
695 char __user *user_buf,
696 size_t count, loff_t *ppos)
698 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
699 struct rtl8366_smi *smi = &rtl->smi;
701 char *buf = smi->buf;
703 len += snprintf(buf + len, sizeof(smi->buf) - len,
704 "%-36s %12s %12s %12s %12s %12s %12s\n",
706 "Port 0", "Port 1", "Port 2",
707 "Port 3", "Port 4", "Port 5");
709 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
710 len += snprintf(buf + len, sizeof(smi->buf) - len, "%-36s ",
711 rtl8366rb_mib_counters[i].name);
712 for (j = 0; j < RTL8366RB_NUM_PORTS; ++j) {
713 unsigned long long counter = 0;
715 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
716 len += snprintf(buf + len,
717 sizeof(smi->buf) - len,
720 len += snprintf(buf + len,
721 sizeof(smi->buf) - len,
724 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
727 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
730 static ssize_t rtl8366rb_read_debugfs_vlan_mc(struct file *file,
731 char __user *user_buf,
732 size_t count, loff_t *ppos)
734 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
735 struct rtl8366_smi *smi = &rtl->smi;
737 char *buf = smi->buf;
739 len += snprintf(buf + len, sizeof(smi->buf) - len,
740 "%2s %6s %4s %6s %6s %3s\n",
741 "id", "vid","prio", "member", "untag", "fid");
743 for (i = 0; i < RTL8366RB_NUM_VLANS; ++i) {
744 struct rtl8366_vlan_mc vlanmc;
746 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
748 len += snprintf(buf + len, sizeof(smi->buf) - len,
749 "%2d %6d %4d 0x%04x 0x%04x %3d\n",
750 i, vlanmc.vid, vlanmc.priority,
751 vlanmc.member, vlanmc.untag, vlanmc.fid);
754 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
757 static ssize_t rtl8366rb_read_debugfs_reg(struct file *file,
758 char __user *user_buf,
759 size_t count, loff_t *ppos)
761 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
762 struct rtl8366_smi *smi = &rtl->smi;
763 u32 t, reg = gl_dbg_reg;
765 char *buf = smi->buf;
767 memset(buf, '\0', sizeof(smi->buf));
769 err = rtl8366_smi_read_reg(smi, reg, &t);
771 len += snprintf(buf, sizeof(smi->buf),
772 "Read failed (reg: 0x%04x)\n", reg);
773 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
776 len += snprintf(buf, sizeof(smi->buf), "reg = 0x%04x, val = 0x%04x\n",
779 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
782 static ssize_t rtl8366rb_write_debugfs_reg(struct file *file,
783 const char __user *user_buf,
784 size_t count, loff_t *ppos)
786 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
787 struct rtl8366_smi *smi = &rtl->smi;
789 u32 reg = gl_dbg_reg;
792 char *buf = smi->buf;
794 len = min(count, sizeof(smi->buf) - 1);
795 if (copy_from_user(buf, user_buf, len)) {
796 dev_err(rtl->parent, "copy from user failed\n");
801 if (len > 0 && buf[len - 1] == '\n')
805 if (strict_strtoul(buf, 16, &data)) {
806 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
808 err = rtl8366_smi_write_reg(smi, reg, data);
811 "writing reg 0x%04x val 0x%04lx failed\n",
819 static const struct file_operations fops_rtl8366rb_regs = {
820 .read = rtl8366rb_read_debugfs_reg,
821 .write = rtl8366rb_write_debugfs_reg,
822 .open = rtl8366rb_debugfs_open,
826 static const struct file_operations fops_rtl8366rb_vlan_mc = {
827 .read = rtl8366rb_read_debugfs_vlan_mc,
828 .open = rtl8366rb_debugfs_open,
832 static const struct file_operations fops_rtl8366rb_mibs = {
833 .read = rtl8366rb_read_debugfs_mibs,
834 .open = rtl8366rb_debugfs_open,
838 static void rtl8366rb_debugfs_init(struct rtl8366rb *rtl)
843 if (!rtl->debugfs_root)
844 rtl->debugfs_root = debugfs_create_dir("rtl8366rb", NULL);
846 if (!rtl->debugfs_root) {
847 dev_err(rtl->parent, "Unable to create debugfs dir\n");
850 root = rtl->debugfs_root;
852 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &gl_dbg_reg);
854 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
859 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
860 &fops_rtl8366rb_regs);
862 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
867 node = debugfs_create_file("vlan_mc", S_IRUSR, root, rtl,
868 &fops_rtl8366rb_vlan_mc);
870 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
875 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
876 &fops_rtl8366rb_mibs);
878 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
884 static void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl)
886 if (rtl->debugfs_root) {
887 debugfs_remove_recursive(rtl->debugfs_root);
888 rtl->debugfs_root = NULL;
893 static inline void rtl8366rb_debugfs_init(struct rtl8366rb *rtl) {}
894 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl) {}
895 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
897 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
898 const struct switch_attr *attr,
899 struct switch_val *val)
901 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
904 if (val->value.i == 1)
905 err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
906 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
911 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
912 const struct switch_attr *attr,
913 struct switch_val *val)
915 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
918 if (attr->ofs == 1) {
919 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
921 if (data & RTL8366RB_CHIP_CTRL_VLAN)
925 } else if (attr->ofs == 2) {
926 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
928 if (data & RTL8366RB_CHIP_CTRL_VLAN_4KTB)
937 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
938 const struct switch_attr *attr,
939 struct switch_val *val)
941 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
944 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
946 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
951 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
952 const struct switch_attr *attr,
953 struct switch_val *val)
955 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
957 if (val->value.i >= 6)
960 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
961 RTL8366RB_LED_BLINKRATE_MASK,
965 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
966 const struct switch_attr *attr,
967 struct switch_val *val)
969 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
972 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
974 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
977 static const char *rtl8366rb_speed_str(unsigned speed)
991 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
992 const struct switch_attr *attr,
993 struct switch_val *val)
995 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
996 u32 len = 0, data = 0;
998 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1001 memset(smi->buf, '\0', sizeof(smi->buf));
1002 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
1003 (val->port_vlan / 2), &data);
1005 if (val->port_vlan % 2)
1008 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
1009 len = snprintf(smi->buf, sizeof(smi->buf),
1010 "port:%d link:up speed:%s %s-duplex %s%s%s",
1012 rtl8366rb_speed_str(data &
1013 RTL8366RB_PORT_STATUS_SPEED_MASK),
1014 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
1016 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
1018 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
1020 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
1023 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
1027 val->value.s = smi->buf;
1033 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
1034 const struct switch_attr *attr,
1035 struct switch_val *val)
1039 struct rtl8366_vlan_4k vlan4k;
1040 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1041 char *buf = smi->buf;
1044 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1047 memset(buf, '\0', sizeof(smi->buf));
1049 err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1053 len += snprintf(buf + len, sizeof(smi->buf) - len,
1054 "VLAN %d: Ports: '", vlan4k.vid);
1056 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1057 if (!(vlan4k.member & (1 << i)))
1060 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
1061 (vlan4k.untag & (1 << i)) ? "" : "t");
1064 len += snprintf(buf + len, sizeof(smi->buf) - len,
1065 "', members=%04x, untag=%04x, fid=%u",
1066 vlan4k.member, vlan4k.untag, vlan4k.fid);
1074 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
1075 const struct switch_attr *attr,
1076 struct switch_val *val)
1078 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1083 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1086 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
1087 reg = RTL8366RB_LED_BLINKRATE_REG;
1089 data = val->value.i << 4;
1091 reg = RTL8366RB_LED_CTRL_REG;
1092 mask = 0xF << (val->port_vlan * 4),
1093 data = val->value.i << (val->port_vlan * 4);
1096 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
1099 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
1100 const struct switch_attr *attr,
1101 struct switch_val *val)
1103 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1106 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
1109 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
1110 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1115 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1116 const struct switch_attr *attr,
1117 struct switch_val *val)
1119 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1121 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1124 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
1125 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
1128 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
1129 const struct switch_attr *attr,
1130 struct switch_val *val)
1132 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1134 unsigned long long counter = 0;
1135 char *buf = smi->buf;
1137 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1140 len += snprintf(buf + len, sizeof(smi->buf) - len,
1141 "Port %d MIB counters\n",
1144 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
1145 len += snprintf(buf + len, sizeof(smi->buf) - len,
1146 "%-36s: ", rtl8366rb_mib_counters[i].name);
1147 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1148 len += snprintf(buf + len, sizeof(smi->buf) - len,
1151 len += snprintf(buf + len, sizeof(smi->buf) - len,
1160 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1161 struct switch_val *val)
1163 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1164 struct switch_port *port;
1165 struct rtl8366_vlan_4k vlan4k;
1168 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1171 rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1173 port = &val->value.ports[0];
1175 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1176 if (!(vlan4k.member & BIT(i)))
1180 port->flags = (vlan4k.untag & BIT(i)) ?
1181 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1188 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1189 struct switch_val *val)
1191 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1192 struct switch_port *port;
1197 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1200 port = &val->value.ports[0];
1201 for (i = 0; i < val->len; i++, port++) {
1202 member |= BIT(port->id);
1204 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1205 untag |= BIT(port->id);
1208 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1211 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1213 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1214 return rtl8366_get_pvid(smi, port, val);
1217 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1219 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1220 return rtl8366_set_pvid(smi, port, val);
1223 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1225 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1228 err = rtl8366rb_reset_chip(smi);
1232 err = rtl8366rb_hw_init(smi);
1236 return rtl8366_reset_vlan(smi);
1239 static struct switch_attr rtl8366rb_globals[] = {
1241 .type = SWITCH_TYPE_INT,
1242 .name = "enable_vlan",
1243 .description = "Enable VLAN mode",
1244 .set = rtl8366rb_sw_set_vlan_enable,
1245 .get = rtl8366rb_sw_get_vlan_enable,
1249 .type = SWITCH_TYPE_INT,
1250 .name = "enable_vlan4k",
1251 .description = "Enable VLAN 4K mode",
1252 .set = rtl8366rb_sw_set_vlan_enable,
1253 .get = rtl8366rb_sw_get_vlan_enable,
1257 .type = SWITCH_TYPE_INT,
1258 .name = "reset_mibs",
1259 .description = "Reset all MIB counters",
1260 .set = rtl8366rb_sw_reset_mibs,
1264 .type = SWITCH_TYPE_INT,
1265 .name = "blinkrate",
1266 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1267 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1268 .set = rtl8366rb_sw_set_blinkrate,
1269 .get = rtl8366rb_sw_get_blinkrate,
1274 static struct switch_attr rtl8366rb_port[] = {
1276 .type = SWITCH_TYPE_STRING,
1278 .description = "Get port link information",
1281 .get = rtl8366rb_sw_get_port_link,
1283 .type = SWITCH_TYPE_INT,
1284 .name = "reset_mib",
1285 .description = "Reset single port MIB counters",
1287 .set = rtl8366rb_sw_reset_port_mibs,
1290 .type = SWITCH_TYPE_STRING,
1292 .description = "Get MIB counters for port",
1295 .get = rtl8366rb_sw_get_port_mib,
1297 .type = SWITCH_TYPE_INT,
1299 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1301 .set = rtl8366rb_sw_set_port_led,
1302 .get = rtl8366rb_sw_get_port_led,
1306 static struct switch_attr rtl8366rb_vlan[] = {
1308 .type = SWITCH_TYPE_STRING,
1310 .description = "Get vlan information",
1313 .get = rtl8366rb_sw_get_vlan_info,
1318 static struct switch_dev rtl8366_switch_dev = {
1320 .cpu_port = RTL8366RB_PORT_NUM_CPU,
1321 .ports = RTL8366RB_NUM_PORTS,
1322 .vlans = RTL8366RB_NUM_VLANS,
1324 .attr = rtl8366rb_globals,
1325 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1328 .attr = rtl8366rb_port,
1329 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1332 .attr = rtl8366rb_vlan,
1333 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1336 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1337 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1338 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1339 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1340 .reset_switch = rtl8366rb_sw_reset_switch,
1343 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1345 struct switch_dev *dev = &rtl->dev;
1348 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1350 dev->devname = dev_name(rtl->parent);
1352 err = register_switch(dev, NULL);
1354 dev_err(rtl->parent, "switch registration failed\n");
1359 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1361 unregister_switch(&rtl->dev);
1364 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1366 struct rtl8366_smi *smi = bus->priv;
1370 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1377 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1379 struct rtl8366_smi *smi = bus->priv;
1383 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1385 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1390 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1392 return (bus->read == rtl8366rb_mii_read &&
1393 bus->write == rtl8366rb_mii_write);
1396 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1398 struct rtl8366_smi *smi = &rtl->smi;
1401 rtl8366rb_debugfs_init(rtl);
1403 ret = rtl8366rb_reset_chip(smi);
1407 ret = rtl8366rb_hw_init(smi);
1411 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1417 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1419 dev_err(smi->parent, "unable to read chip id\n");
1424 case RTL8366RB_CHIP_ID_8366:
1427 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1431 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1434 dev_err(smi->parent, "unable to read chip version\n");
1438 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1439 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1444 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1445 .detect = rtl8366rb_detect,
1446 .mii_read = rtl8366rb_mii_read,
1447 .mii_write = rtl8366rb_mii_write,
1449 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1450 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1451 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1452 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1453 .get_mc_index = rtl8366rb_get_mc_index,
1454 .set_mc_index = rtl8366rb_set_mc_index,
1457 static int __init rtl8366rb_probe(struct platform_device *pdev)
1459 static int rtl8366_smi_version_printed;
1460 struct rtl8366rb_platform_data *pdata;
1461 struct rtl8366rb *rtl;
1462 struct rtl8366_smi *smi;
1465 if (!rtl8366_smi_version_printed++)
1466 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1467 " version " RTL8366RB_DRIVER_VER"\n");
1469 pdata = pdev->dev.platform_data;
1471 dev_err(&pdev->dev, "no platform data specified\n");
1476 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1478 dev_err(&pdev->dev, "no memory for private data\n");
1483 rtl->parent = &pdev->dev;
1486 smi->parent = &pdev->dev;
1487 smi->gpio_sda = pdata->gpio_sda;
1488 smi->gpio_sck = pdata->gpio_sck;
1489 smi->ops = &rtl8366rb_smi_ops;
1490 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1491 smi->num_ports = RTL8366RB_NUM_PORTS;
1492 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1494 err = rtl8366_smi_init(smi);
1498 platform_set_drvdata(pdev, rtl);
1500 err = rtl8366rb_setup(rtl);
1502 goto err_clear_drvdata;
1504 err = rtl8366rb_switch_init(rtl);
1506 goto err_clear_drvdata;
1511 platform_set_drvdata(pdev, NULL);
1512 rtl8366_smi_cleanup(smi);
1519 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1521 if (!rtl8366rb_mii_bus_match(phydev->bus))
1527 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1532 static struct phy_driver rtl8366rb_phy_driver = {
1533 .phy_id = 0x001cc960,
1534 .name = "Realtek RTL8366RB",
1535 .phy_id_mask = 0x1ffffff0,
1536 .features = PHY_GBIT_FEATURES,
1537 .config_aneg = rtl8366rb_phy_config_aneg,
1538 .config_init = rtl8366rb_phy_config_init,
1539 .read_status = genphy_read_status,
1541 .owner = THIS_MODULE,
1545 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1547 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1550 rtl8366rb_switch_cleanup(rtl);
1551 rtl8366rb_debugfs_remove(rtl);
1552 platform_set_drvdata(pdev, NULL);
1553 rtl8366_smi_cleanup(&rtl->smi);
1560 static struct platform_driver rtl8366rb_driver = {
1562 .name = RTL8366RB_DRIVER_NAME,
1563 .owner = THIS_MODULE,
1565 .probe = rtl8366rb_probe,
1566 .remove = __devexit_p(rtl8366rb_remove),
1569 static int __init rtl8366rb_module_init(void)
1572 ret = platform_driver_register(&rtl8366rb_driver);
1576 ret = phy_driver_register(&rtl8366rb_phy_driver);
1578 goto err_platform_unregister;
1582 err_platform_unregister:
1583 platform_driver_unregister(&rtl8366rb_driver);
1586 module_init(rtl8366rb_module_init);
1588 static void __exit rtl8366rb_module_exit(void)
1590 phy_driver_unregister(&rtl8366rb_phy_driver);
1591 platform_driver_unregister(&rtl8366rb_driver);
1593 module_exit(rtl8366rb_module_exit);
1595 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1596 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1597 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1598 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1599 MODULE_LICENSE("GPL v2");
1600 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);