2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
21 #include "rtl8366_smi.h"
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
27 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
28 #define RTL8366RB_DRIVER_VER "0.2.2"
30 #define RTL8366RB_PHY_NO_MAX 4
31 #define RTL8366RB_PHY_PAGE_MAX 7
32 #define RTL8366RB_PHY_ADDR_MAX 31
34 #define RTL8366RB_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366RB_CHIP_CTRL_VLAN (1 << 13)
36 #define RTL8366RB_CHIP_CTRL_VLAN_4KTB (1 << 14)
38 /* Switch Global Configuration register */
39 #define RTL8366RB_SGCR 0x0000
40 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
41 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
42 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
43 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
44 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
45 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
46 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
48 /* Port Enable Control register */
49 #define RTL8366RB_PECR 0x0001
51 /* Switch Security Control registers */
52 #define RTL8366RB_SSCR0 0x0002
53 #define RTL8366RB_SSCR1 0x0003
54 #define RTL8366RB_SSCR2 0x0004
55 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
57 #define RTL8366RB_RESET_CTRL_REG 0x0100
58 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
59 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
61 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
62 #define RTL8366RB_CHIP_VERSION_MASK 0xf
63 #define RTL8366RB_CHIP_ID_REG 0x0509
64 #define RTL8366RB_CHIP_ID_8366 0x5937
66 /* PHY registers control */
67 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
68 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
70 #define RTL8366RB_PHY_CTRL_READ 1
71 #define RTL8366RB_PHY_CTRL_WRITE 0
73 #define RTL8366RB_PHY_REG_MASK 0x1f
74 #define RTL8366RB_PHY_PAGE_OFFSET 5
75 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
76 #define RTL8366RB_PHY_NO_OFFSET 9
77 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
79 /* LED control registers */
80 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
81 #define RTL8366RB_LED_BLINKRATE_BIT 0
82 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
84 #define RTL8366RB_LED_CTRL_REG 0x0431
85 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
86 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
88 #define RTL8366RB_MIB_COUNT 33
89 #define RTL8366RB_GLOBAL_MIB_COUNT 1
90 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
91 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
92 #define RTL8366RB_MIB_CTRL_REG 0x13F0
93 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
94 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
95 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
96 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
97 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
99 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
100 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
101 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
102 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
103 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
106 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
107 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
110 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
111 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
112 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
114 #define RTL8366RB_VLAN_MEMCONF_BASE 0x0020
117 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
118 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
119 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
120 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
121 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
122 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
123 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
126 #define RTL8366RB_PORT_NUM_CPU 5
127 #define RTL8366RB_NUM_PORTS 6
128 #define RTL8366RB_NUM_VLANS 16
129 #define RTL8366RB_NUM_LEDGROUPS 4
130 #define RTL8366RB_NUM_VIDS 4096
131 #define RTL8366RB_PRIORITYMAX 7
132 #define RTL8366RB_FIDMAX 7
135 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
136 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
137 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
138 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
139 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
141 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
143 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
150 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
156 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
161 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
164 struct device *parent;
165 struct rtl8366_smi smi;
166 struct switch_dev dev;
169 struct rtl8366rb_vlan_mc {
181 struct rtl8366rb_vlan_4k {
196 static struct mib_counter rtl8366rb_mib_counters[RTL8366RB_MIB_COUNT] = {
197 { 0, 4, "IfInOctets" },
198 { 4, 4, "EtherStatsOctets" },
199 { 8, 2, "EtherStatsUnderSizePkts" },
200 { 10, 2, "EtherFragments" },
201 { 12, 2, "EtherStatsPkts64Octets" },
202 { 14, 2, "EtherStatsPkts65to127Octets" },
203 { 16, 2, "EtherStatsPkts128to255Octets" },
204 { 18, 2, "EtherStatsPkts256to511Octets" },
205 { 20, 2, "EtherStatsPkts512to1023Octets" },
206 { 22, 2, "EtherStatsPkts1024to1518Octets" },
207 { 24, 2, "EtherOversizeStats" },
208 { 26, 2, "EtherStatsJabbers" },
209 { 28, 2, "IfInUcastPkts" },
210 { 30, 2, "EtherStatsMulticastPkts" },
211 { 32, 2, "EtherStatsBroadcastPkts" },
212 { 34, 2, "EtherStatsDropEvents" },
213 { 36, 2, "Dot3StatsFCSErrors" },
214 { 38, 2, "Dot3StatsSymbolErrors" },
215 { 40, 2, "Dot3InPauseFrames" },
216 { 42, 2, "Dot3ControlInUnknownOpcodes" },
217 { 44, 4, "IfOutOctets" },
218 { 48, 2, "Dot3StatsSingleCollisionFrames" },
219 { 50, 2, "Dot3StatMultipleCollisionFrames" },
220 { 52, 2, "Dot3sDeferredTransmissions" },
221 { 54, 2, "Dot3StatsLateCollisions" },
222 { 56, 2, "EtherStatsCollisions" },
223 { 58, 2, "Dot3StatsExcessiveCollisions" },
224 { 60, 2, "Dot3OutPauseFrames" },
225 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
226 { 64, 2, "Dot1dTpPortInDiscards" },
227 { 66, 2, "IfOutUcastPkts" },
228 { 68, 2, "IfOutMulticastPkts" },
229 { 70, 2, "IfOutBroadcastPkts" },
232 #define REG_WR(_smi, _reg, _val) \
234 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
239 #define REG_RMW(_smi, _reg, _mask, _val) \
241 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
246 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
248 return container_of(smi, struct rtl8366rb, smi);
251 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
253 return container_of(sw, struct rtl8366rb, dev);
256 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
258 struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
262 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
267 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
268 RTL8366RB_CHIP_CTRL_RESET_HW);
271 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
274 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
279 printk("Timeout waiting for the switch to reset\n");
286 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
290 /* set maximum packet length to 1536 bytes */
291 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
292 RTL8366RB_SGCR_MAX_LENGTH_1536);
294 /* enable all ports */
295 REG_WR(smi, RTL8366RB_PECR, 0);
297 /* disable learning for all ports */
298 REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
300 /* disable auto ageing for all ports */
301 REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
303 /* don't drop packets whose DA has not been learned */
304 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
309 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
310 u32 phy_no, u32 page, u32 addr, u32 *data)
315 if (phy_no > RTL8366RB_PHY_NO_MAX)
318 if (page > RTL8366RB_PHY_PAGE_MAX)
321 if (addr > RTL8366RB_PHY_ADDR_MAX)
324 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
325 RTL8366RB_PHY_CTRL_READ);
329 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
330 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
331 (addr & RTL8366RB_PHY_REG_MASK);
333 ret = rtl8366_smi_write_reg(smi, reg, 0);
337 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
344 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
345 u32 phy_no, u32 page, u32 addr, u32 data)
350 if (phy_no > RTL8366RB_PHY_NO_MAX)
353 if (page > RTL8366RB_PHY_PAGE_MAX)
356 if (addr > RTL8366RB_PHY_ADDR_MAX)
359 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
360 RTL8366RB_PHY_CTRL_WRITE);
364 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
365 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
366 (addr & RTL8366RB_PHY_REG_MASK);
368 ret = rtl8366_smi_write_reg(smi, reg, data);
375 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
376 int port, unsigned long long *val)
383 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
386 addr = RTL8366RB_MIB_COUNTER_BASE +
387 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
388 rtl8366rb_mib_counters[counter].offset;
391 * Writing access counter address first
392 * then ASIC will prepare 64bits counter wait for being retrived
394 data = 0; /* writing data will be discard by ASIC */
395 err = rtl8366_smi_write_reg(smi, addr, data);
399 /* read MIB control register */
400 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
404 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
407 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
411 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
412 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
416 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
423 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
424 struct rtl8366_vlan_4k *vlan4k)
426 struct rtl8366rb_vlan_4k vlan4k_priv;
431 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
432 vlan4k_priv.vid = vid;
434 if (vid >= RTL8366RB_NUM_VIDS)
437 tableaddr = (u16 *)&vlan4k_priv;
441 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
445 /* write table access control word */
446 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
447 RTL8366RB_TABLE_VLAN_READ_CTRL);
451 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
458 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
466 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
473 vlan4k->untag = vlan4k_priv.untag;
474 vlan4k->member = vlan4k_priv.member;
475 vlan4k->fid = vlan4k_priv.fid;
480 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
481 const struct rtl8366_vlan_4k *vlan4k)
483 struct rtl8366rb_vlan_4k vlan4k_priv;
488 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
489 vlan4k->member > RTL8366RB_PORT_ALL ||
490 vlan4k->untag > RTL8366RB_PORT_ALL ||
491 vlan4k->fid > RTL8366RB_FIDMAX)
494 vlan4k_priv.vid = vlan4k->vid;
495 vlan4k_priv.untag = vlan4k->untag;
496 vlan4k_priv.member = vlan4k->member;
497 vlan4k_priv.fid = vlan4k->fid;
499 tableaddr = (u16 *)&vlan4k_priv;
503 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
511 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
520 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
525 /* write table access control word */
526 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
527 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
532 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
533 struct rtl8366_vlan_mc *vlanmc)
535 struct rtl8366rb_vlan_mc vlanmc_priv;
541 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
543 if (index >= RTL8366RB_NUM_VLANS)
546 tableaddr = (u16 *)&vlanmc_priv;
548 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
549 err = rtl8366_smi_read_reg(smi, addr, &data);
556 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
557 err = rtl8366_smi_read_reg(smi, addr, &data);
564 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
565 err = rtl8366_smi_read_reg(smi, addr, &data);
571 vlanmc->vid = vlanmc_priv.vid;
572 vlanmc->priority = vlanmc_priv.priority;
573 vlanmc->untag = vlanmc_priv.untag;
574 vlanmc->member = vlanmc_priv.member;
575 vlanmc->fid = vlanmc_priv.fid;
580 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
581 const struct rtl8366_vlan_mc *vlanmc)
583 struct rtl8366rb_vlan_mc vlanmc_priv;
589 if (index >= RTL8366RB_NUM_VLANS ||
590 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
591 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
592 vlanmc->member > RTL8366RB_PORT_ALL ||
593 vlanmc->untag > RTL8366RB_PORT_ALL ||
594 vlanmc->fid > RTL8366RB_FIDMAX)
597 vlanmc_priv.vid = vlanmc->vid;
598 vlanmc_priv.priority = vlanmc->priority;
599 vlanmc_priv.untag = vlanmc->untag;
600 vlanmc_priv.member = vlanmc->member;
601 vlanmc_priv.stag_mbr = 0;
602 vlanmc_priv.stag_idx = 0;
603 vlanmc_priv.fid = vlanmc->fid;
605 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
607 tableaddr = (u16 *)&vlanmc_priv;
610 err = rtl8366_smi_write_reg(smi, addr, data);
614 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
619 err = rtl8366_smi_write_reg(smi, addr, data);
623 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
628 err = rtl8366_smi_write_reg(smi, addr, data);
634 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
639 if (port >= RTL8366RB_NUM_PORTS)
642 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
647 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
648 RTL8366RB_PORT_VLAN_CTRL_MASK;
654 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
656 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
659 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
660 RTL8366RB_PORT_VLAN_CTRL_MASK <<
661 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
662 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
663 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
666 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
668 return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
669 RTL8366RB_CHIP_CTRL_VLAN,
670 (enable) ? RTL8366RB_CHIP_CTRL_VLAN : 0);
673 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
675 return rtl8366_smi_rmwr(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG,
676 RTL8366RB_CHIP_CTRL_VLAN_4KTB,
677 (enable) ? RTL8366RB_CHIP_CTRL_VLAN_4KTB : 0);
680 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
681 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
682 char __user *user_buf,
683 size_t count, loff_t *ppos)
685 struct rtl8366_smi *smi = file->private_data;
687 char *buf = smi->buf;
689 len += snprintf(buf + len, sizeof(smi->buf) - len,
690 "%-36s %12s %12s %12s %12s %12s %12s\n",
692 "Port 0", "Port 1", "Port 2",
693 "Port 3", "Port 4", "Port 5");
695 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
696 len += snprintf(buf + len, sizeof(smi->buf) - len, "%-36s ",
697 rtl8366rb_mib_counters[i].name);
698 for (j = 0; j < RTL8366RB_NUM_PORTS; ++j) {
699 unsigned long long counter = 0;
701 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
702 len += snprintf(buf + len,
703 sizeof(smi->buf) - len,
706 len += snprintf(buf + len,
707 sizeof(smi->buf) - len,
710 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
713 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
716 static const struct file_operations fops_rtl8366rb_mibs = {
717 .read = rtl8366rb_read_debugfs_mibs,
718 .open = rtl8366_debugfs_open,
722 static void rtl8366rb_debugfs_init(struct rtl8366_smi *smi)
726 if (!smi->debugfs_root)
729 node = debugfs_create_file("mibs", S_IRUSR, smi->debugfs_root, smi,
730 &fops_rtl8366rb_mibs);
732 dev_err(smi->parent, "Creating debugfs file '%s' failed\n",
737 static inline void rtl8366rb_debugfs_init(struct rtl8366_smi *smi) {}
738 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
740 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
741 const struct switch_attr *attr,
742 struct switch_val *val)
744 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
747 if (val->value.i == 1)
748 err = rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
749 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
754 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
755 const struct switch_attr *attr,
756 struct switch_val *val)
758 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
761 if (attr->ofs == 1) {
762 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
764 if (data & RTL8366RB_CHIP_CTRL_VLAN)
768 } else if (attr->ofs == 2) {
769 rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_GLOBAL_CTRL_REG, &data);
771 if (data & RTL8366RB_CHIP_CTRL_VLAN_4KTB)
780 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
781 const struct switch_attr *attr,
782 struct switch_val *val)
784 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
787 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
789 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
794 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
795 const struct switch_attr *attr,
796 struct switch_val *val)
798 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
800 if (val->value.i >= 6)
803 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
804 RTL8366RB_LED_BLINKRATE_MASK,
808 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
809 const struct switch_attr *attr,
810 struct switch_val *val)
812 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
815 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
817 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
820 static const char *rtl8366rb_speed_str(unsigned speed)
834 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
835 const struct switch_attr *attr,
836 struct switch_val *val)
838 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
839 u32 len = 0, data = 0;
841 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
844 memset(smi->buf, '\0', sizeof(smi->buf));
845 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
846 (val->port_vlan / 2), &data);
848 if (val->port_vlan % 2)
851 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
852 len = snprintf(smi->buf, sizeof(smi->buf),
853 "port:%d link:up speed:%s %s-duplex %s%s%s",
855 rtl8366rb_speed_str(data &
856 RTL8366RB_PORT_STATUS_SPEED_MASK),
857 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
859 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
861 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
863 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
866 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
870 val->value.s = smi->buf;
876 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
877 const struct switch_attr *attr,
878 struct switch_val *val)
882 struct rtl8366_vlan_4k vlan4k;
883 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
884 char *buf = smi->buf;
887 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
890 memset(buf, '\0', sizeof(smi->buf));
892 err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
896 len += snprintf(buf + len, sizeof(smi->buf) - len,
897 "VLAN %d: Ports: '", vlan4k.vid);
899 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
900 if (!(vlan4k.member & (1 << i)))
903 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
904 (vlan4k.untag & (1 << i)) ? "" : "t");
907 len += snprintf(buf + len, sizeof(smi->buf) - len,
908 "', members=%04x, untag=%04x, fid=%u",
909 vlan4k.member, vlan4k.untag, vlan4k.fid);
917 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
918 const struct switch_attr *attr,
919 struct switch_val *val)
921 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
926 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
929 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
930 reg = RTL8366RB_LED_BLINKRATE_REG;
932 data = val->value.i << 4;
934 reg = RTL8366RB_LED_CTRL_REG;
935 mask = 0xF << (val->port_vlan * 4),
936 data = val->value.i << (val->port_vlan * 4);
939 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
942 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
943 const struct switch_attr *attr,
944 struct switch_val *val)
946 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
949 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
952 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
953 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
958 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
959 const struct switch_attr *attr,
960 struct switch_val *val)
962 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
964 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
967 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
968 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
971 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
972 const struct switch_attr *attr,
973 struct switch_val *val)
975 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
977 unsigned long long counter = 0;
978 char *buf = smi->buf;
980 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
983 len += snprintf(buf + len, sizeof(smi->buf) - len,
984 "Port %d MIB counters\n",
987 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
988 len += snprintf(buf + len, sizeof(smi->buf) - len,
989 "%-36s: ", rtl8366rb_mib_counters[i].name);
990 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
991 len += snprintf(buf + len, sizeof(smi->buf) - len,
994 len += snprintf(buf + len, sizeof(smi->buf) - len,
1003 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1004 struct switch_val *val)
1006 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1007 struct switch_port *port;
1008 struct rtl8366_vlan_4k vlan4k;
1011 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1014 rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1016 port = &val->value.ports[0];
1018 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1019 if (!(vlan4k.member & BIT(i)))
1023 port->flags = (vlan4k.untag & BIT(i)) ?
1024 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1031 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1032 struct switch_val *val)
1034 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1035 struct switch_port *port;
1040 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
1043 port = &val->value.ports[0];
1044 for (i = 0; i < val->len; i++, port++) {
1045 member |= BIT(port->id);
1047 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1048 untag |= BIT(port->id);
1051 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1054 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1056 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1057 return rtl8366_get_pvid(smi, port, val);
1060 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1062 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1063 return rtl8366_set_pvid(smi, port, val);
1066 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1068 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1071 err = rtl8366rb_reset_chip(smi);
1075 err = rtl8366rb_hw_init(smi);
1079 return rtl8366_reset_vlan(smi);
1082 static struct switch_attr rtl8366rb_globals[] = {
1084 .type = SWITCH_TYPE_INT,
1085 .name = "enable_vlan",
1086 .description = "Enable VLAN mode",
1087 .set = rtl8366rb_sw_set_vlan_enable,
1088 .get = rtl8366rb_sw_get_vlan_enable,
1092 .type = SWITCH_TYPE_INT,
1093 .name = "enable_vlan4k",
1094 .description = "Enable VLAN 4K mode",
1095 .set = rtl8366rb_sw_set_vlan_enable,
1096 .get = rtl8366rb_sw_get_vlan_enable,
1100 .type = SWITCH_TYPE_INT,
1101 .name = "reset_mibs",
1102 .description = "Reset all MIB counters",
1103 .set = rtl8366rb_sw_reset_mibs,
1107 .type = SWITCH_TYPE_INT,
1108 .name = "blinkrate",
1109 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1110 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1111 .set = rtl8366rb_sw_set_blinkrate,
1112 .get = rtl8366rb_sw_get_blinkrate,
1117 static struct switch_attr rtl8366rb_port[] = {
1119 .type = SWITCH_TYPE_STRING,
1121 .description = "Get port link information",
1124 .get = rtl8366rb_sw_get_port_link,
1126 .type = SWITCH_TYPE_INT,
1127 .name = "reset_mib",
1128 .description = "Reset single port MIB counters",
1130 .set = rtl8366rb_sw_reset_port_mibs,
1133 .type = SWITCH_TYPE_STRING,
1135 .description = "Get MIB counters for port",
1138 .get = rtl8366rb_sw_get_port_mib,
1140 .type = SWITCH_TYPE_INT,
1142 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1144 .set = rtl8366rb_sw_set_port_led,
1145 .get = rtl8366rb_sw_get_port_led,
1149 static struct switch_attr rtl8366rb_vlan[] = {
1151 .type = SWITCH_TYPE_STRING,
1153 .description = "Get vlan information",
1156 .get = rtl8366rb_sw_get_vlan_info,
1161 static struct switch_dev rtl8366_switch_dev = {
1163 .cpu_port = RTL8366RB_PORT_NUM_CPU,
1164 .ports = RTL8366RB_NUM_PORTS,
1165 .vlans = RTL8366RB_NUM_VLANS,
1167 .attr = rtl8366rb_globals,
1168 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1171 .attr = rtl8366rb_port,
1172 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1175 .attr = rtl8366rb_vlan,
1176 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1179 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1180 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1181 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1182 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1183 .reset_switch = rtl8366rb_sw_reset_switch,
1186 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1188 struct switch_dev *dev = &rtl->dev;
1191 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1193 dev->devname = dev_name(rtl->parent);
1195 err = register_switch(dev, NULL);
1197 dev_err(rtl->parent, "switch registration failed\n");
1202 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1204 unregister_switch(&rtl->dev);
1207 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1209 struct rtl8366_smi *smi = bus->priv;
1213 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1220 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1222 struct rtl8366_smi *smi = bus->priv;
1226 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1228 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1233 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1235 return (bus->read == rtl8366rb_mii_read &&
1236 bus->write == rtl8366rb_mii_write);
1239 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1241 struct rtl8366_smi *smi = &rtl->smi;
1244 rtl8366rb_debugfs_init(smi);
1246 ret = rtl8366rb_reset_chip(smi);
1250 ret = rtl8366rb_hw_init(smi);
1254 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1260 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1262 dev_err(smi->parent, "unable to read chip id\n");
1267 case RTL8366RB_CHIP_ID_8366:
1270 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1274 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1277 dev_err(smi->parent, "unable to read chip version\n");
1281 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1282 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1287 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1288 .detect = rtl8366rb_detect,
1289 .mii_read = rtl8366rb_mii_read,
1290 .mii_write = rtl8366rb_mii_write,
1292 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1293 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1294 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1295 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1296 .get_mc_index = rtl8366rb_get_mc_index,
1297 .set_mc_index = rtl8366rb_set_mc_index,
1300 static int __init rtl8366rb_probe(struct platform_device *pdev)
1302 static int rtl8366_smi_version_printed;
1303 struct rtl8366rb_platform_data *pdata;
1304 struct rtl8366rb *rtl;
1305 struct rtl8366_smi *smi;
1308 if (!rtl8366_smi_version_printed++)
1309 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1310 " version " RTL8366RB_DRIVER_VER"\n");
1312 pdata = pdev->dev.platform_data;
1314 dev_err(&pdev->dev, "no platform data specified\n");
1319 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1321 dev_err(&pdev->dev, "no memory for private data\n");
1326 rtl->parent = &pdev->dev;
1329 smi->parent = &pdev->dev;
1330 smi->gpio_sda = pdata->gpio_sda;
1331 smi->gpio_sck = pdata->gpio_sck;
1332 smi->ops = &rtl8366rb_smi_ops;
1333 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1334 smi->num_ports = RTL8366RB_NUM_PORTS;
1335 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1337 err = rtl8366_smi_init(smi);
1341 platform_set_drvdata(pdev, rtl);
1343 err = rtl8366rb_setup(rtl);
1345 goto err_clear_drvdata;
1347 err = rtl8366rb_switch_init(rtl);
1349 goto err_clear_drvdata;
1354 platform_set_drvdata(pdev, NULL);
1355 rtl8366_smi_cleanup(smi);
1362 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1364 if (!rtl8366rb_mii_bus_match(phydev->bus))
1370 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1375 static struct phy_driver rtl8366rb_phy_driver = {
1376 .phy_id = 0x001cc960,
1377 .name = "Realtek RTL8366RB",
1378 .phy_id_mask = 0x1ffffff0,
1379 .features = PHY_GBIT_FEATURES,
1380 .config_aneg = rtl8366rb_phy_config_aneg,
1381 .config_init = rtl8366rb_phy_config_init,
1382 .read_status = genphy_read_status,
1384 .owner = THIS_MODULE,
1388 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1390 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1393 rtl8366rb_switch_cleanup(rtl);
1394 platform_set_drvdata(pdev, NULL);
1395 rtl8366_smi_cleanup(&rtl->smi);
1402 static struct platform_driver rtl8366rb_driver = {
1404 .name = RTL8366RB_DRIVER_NAME,
1405 .owner = THIS_MODULE,
1407 .probe = rtl8366rb_probe,
1408 .remove = __devexit_p(rtl8366rb_remove),
1411 static int __init rtl8366rb_module_init(void)
1414 ret = platform_driver_register(&rtl8366rb_driver);
1418 ret = phy_driver_register(&rtl8366rb_phy_driver);
1420 goto err_platform_unregister;
1424 err_platform_unregister:
1425 platform_driver_unregister(&rtl8366rb_driver);
1428 module_init(rtl8366rb_module_init);
1430 static void __exit rtl8366rb_module_exit(void)
1432 phy_driver_unregister(&rtl8366rb_phy_driver);
1433 platform_driver_unregister(&rtl8366rb_driver);
1435 module_exit(rtl8366rb_module_exit);
1437 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1438 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1439 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1440 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1441 MODULE_LICENSE("GPL v2");
1442 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);