2 * Platform driver for the Realtek RTL8366RB ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
18 #include <linux/of_platform.h>
19 #include <linux/delay.h>
20 #include <linux/skbuff.h>
21 #include <linux/rtl8366.h>
23 #include "rtl8366_smi.h"
25 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
26 #define RTL8366RB_DRIVER_VER "0.2.3"
28 #define RTL8366RB_PHY_NO_MAX 4
29 #define RTL8366RB_PHY_PAGE_MAX 7
30 #define RTL8366RB_PHY_ADDR_MAX 31
32 /* Switch Global Configuration register */
33 #define RTL8366RB_SGCR 0x0000
34 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
35 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
36 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
39 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
40 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
41 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
42 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
44 /* Port Enable Control register */
45 #define RTL8366RB_PECR 0x0001
47 /* Switch Security Control registers */
48 #define RTL8366RB_SSCR0 0x0002
49 #define RTL8366RB_SSCR1 0x0003
50 #define RTL8366RB_SSCR2 0x0004
51 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
53 #define RTL8366RB_RESET_CTRL_REG 0x0100
54 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
55 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
57 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
58 #define RTL8366RB_CHIP_VERSION_MASK 0xf
59 #define RTL8366RB_CHIP_ID_REG 0x0509
60 #define RTL8366RB_CHIP_ID_8366 0x5937
62 /* PHY registers control */
63 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
64 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
66 #define RTL8366RB_PHY_CTRL_READ 1
67 #define RTL8366RB_PHY_CTRL_WRITE 0
69 #define RTL8366RB_PHY_REG_MASK 0x1f
70 #define RTL8366RB_PHY_PAGE_OFFSET 5
71 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
72 #define RTL8366RB_PHY_NO_OFFSET 9
73 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
75 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
77 /* LED control registers */
78 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
79 #define RTL8366RB_LED_BLINKRATE_BIT 0
80 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
82 #define RTL8366RB_LED_CTRL_REG 0x0431
83 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
84 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
86 #define RTL8366RB_MIB_COUNT 33
87 #define RTL8366RB_GLOBAL_MIB_COUNT 1
88 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
89 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
90 #define RTL8366RB_MIB_CTRL_REG 0x13F0
91 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
92 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
93 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
94 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
95 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
97 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
98 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
99 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
100 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
101 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
104 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
105 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
108 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
109 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
110 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
112 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
115 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
116 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
117 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
118 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
119 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
120 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
121 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
124 #define RTL8366RB_PORT_NUM_CPU 5
125 #define RTL8366RB_NUM_PORTS 6
126 #define RTL8366RB_NUM_VLANS 16
127 #define RTL8366RB_NUM_LEDGROUPS 4
128 #define RTL8366RB_NUM_VIDS 4096
129 #define RTL8366RB_PRIORITYMAX 7
130 #define RTL8366RB_FIDMAX 7
133 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
134 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
135 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
136 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
137 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
139 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
141 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
148 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
154 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
159 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
161 #define RTL8366RB_VLAN_VID_MASK 0xfff
162 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
163 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
164 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
165 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
166 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
167 #define RTL8366RB_VLAN_FID_MASK 0x7
170 /* Port ingress bandwidth control */
171 #define RTL8366RB_IB_BASE 0x0200
172 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum)
173 #define RTL8366RB_IB_BDTH_MASK 0x3fff
174 #define RTL8366RB_IB_PREIFG_OFFSET 14
175 #define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET)
177 /* Port egress bandwidth control */
178 #define RTL8366RB_EB_BASE 0x02d1
179 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum)
180 #define RTL8366RB_EB_BDTH_MASK 0x3fff
181 #define RTL8366RB_EB_PREIFG_REG 0x02f8
182 #define RTL8366RB_EB_PREIFG_OFFSET 9
183 #define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET)
185 #define RTL8366RB_BDTH_SW_MAX 1048512
186 #define RTL8366RB_BDTH_UNIT 64
187 #define RTL8366RB_BDTH_REG_DEFAULT 16383
190 #define RTL8366RB_QOS_BIT 15
191 #define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT)
192 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
193 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
196 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
197 { 0, 0, 4, "IfInOctets" },
198 { 0, 4, 4, "EtherStatsOctets" },
199 { 0, 8, 2, "EtherStatsUnderSizePkts" },
200 { 0, 10, 2, "EtherFragments" },
201 { 0, 12, 2, "EtherStatsPkts64Octets" },
202 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
203 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
204 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
205 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
206 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
207 { 0, 24, 2, "EtherOversizeStats" },
208 { 0, 26, 2, "EtherStatsJabbers" },
209 { 0, 28, 2, "IfInUcastPkts" },
210 { 0, 30, 2, "EtherStatsMulticastPkts" },
211 { 0, 32, 2, "EtherStatsBroadcastPkts" },
212 { 0, 34, 2, "EtherStatsDropEvents" },
213 { 0, 36, 2, "Dot3StatsFCSErrors" },
214 { 0, 38, 2, "Dot3StatsSymbolErrors" },
215 { 0, 40, 2, "Dot3InPauseFrames" },
216 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
217 { 0, 44, 4, "IfOutOctets" },
218 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
219 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
220 { 0, 52, 2, "Dot3sDeferredTransmissions" },
221 { 0, 54, 2, "Dot3StatsLateCollisions" },
222 { 0, 56, 2, "EtherStatsCollisions" },
223 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
224 { 0, 60, 2, "Dot3OutPauseFrames" },
225 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
226 { 0, 64, 2, "Dot1dTpPortInDiscards" },
227 { 0, 66, 2, "IfOutUcastPkts" },
228 { 0, 68, 2, "IfOutMulticastPkts" },
229 { 0, 70, 2, "IfOutBroadcastPkts" },
232 #define REG_WR(_smi, _reg, _val) \
234 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
239 #define REG_RMW(_smi, _reg, _mask, _val) \
241 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
246 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
251 rtl8366_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,
252 RTL8366RB_CHIP_CTRL_RESET_HW);
255 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
258 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
263 printk("Timeout waiting for the switch to reset\n");
270 static int rtl8366rb_setup(struct rtl8366_smi *smi)
274 /* set maximum packet length to 1536 bytes */
275 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
276 RTL8366RB_SGCR_MAX_LENGTH_1536);
278 /* enable learning for all ports */
279 REG_WR(smi, RTL8366RB_SSCR0, 0);
281 /* enable auto ageing for all ports */
282 REG_WR(smi, RTL8366RB_SSCR1, 0);
285 * discard VLAN tagged packets if the port is not a member of
286 * the VLAN with which the packets is associated.
288 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
290 /* don't drop packets whose DA has not been learned */
291 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
296 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
297 u32 phy_no, u32 page, u32 addr, u32 *data)
302 if (phy_no > RTL8366RB_PHY_NO_MAX)
305 if (page > RTL8366RB_PHY_PAGE_MAX)
308 if (addr > RTL8366RB_PHY_ADDR_MAX)
311 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
312 RTL8366RB_PHY_CTRL_READ);
316 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
317 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
318 (addr & RTL8366RB_PHY_REG_MASK);
320 ret = rtl8366_smi_write_reg(smi, reg, 0);
324 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
331 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
332 u32 phy_no, u32 page, u32 addr, u32 data)
337 if (phy_no > RTL8366RB_PHY_NO_MAX)
340 if (page > RTL8366RB_PHY_PAGE_MAX)
343 if (addr > RTL8366RB_PHY_ADDR_MAX)
346 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
347 RTL8366RB_PHY_CTRL_WRITE);
351 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
352 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
353 (addr & RTL8366RB_PHY_REG_MASK);
355 ret = rtl8366_smi_write_reg(smi, reg, data);
362 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
363 int port, unsigned long long *val)
370 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
373 addr = RTL8366RB_MIB_COUNTER_BASE +
374 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
375 rtl8366rb_mib_counters[counter].offset;
378 * Writing access counter address first
379 * then ASIC will prepare 64bits counter wait for being retrived
381 data = 0; /* writing data will be discard by ASIC */
382 err = rtl8366_smi_write_reg(smi, addr, data);
386 /* read MIB control register */
387 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
391 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
394 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
398 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
399 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
403 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
410 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
411 struct rtl8366_vlan_4k *vlan4k)
417 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
419 if (vid >= RTL8366RB_NUM_VIDS)
423 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
424 vid & RTL8366RB_VLAN_VID_MASK);
428 /* write table access control word */
429 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
430 RTL8366RB_TABLE_VLAN_READ_CTRL);
434 for (i = 0; i < 3; i++) {
435 err = rtl8366_smi_read_reg(smi,
436 RTL8366RB_VLAN_TABLE_READ_BASE + i,
443 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
444 RTL8366RB_VLAN_UNTAG_MASK;
445 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
446 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
451 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
452 const struct rtl8366_vlan_4k *vlan4k)
458 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
459 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
460 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
461 vlan4k->fid > RTL8366RB_FIDMAX)
464 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
465 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
466 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
467 RTL8366RB_VLAN_UNTAG_SHIFT);
468 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
470 for (i = 0; i < 3; i++) {
471 err = rtl8366_smi_write_reg(smi,
472 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
478 /* write table access control word */
479 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
480 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
485 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
486 struct rtl8366_vlan_mc *vlanmc)
492 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
494 if (index >= RTL8366RB_NUM_VLANS)
497 for (i = 0; i < 3; i++) {
498 err = rtl8366_smi_read_reg(smi,
499 RTL8366RB_VLAN_MC_BASE(index) + i,
505 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
506 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
507 RTL8366RB_VLAN_PRIORITY_MASK;
508 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
509 RTL8366RB_VLAN_UNTAG_MASK;
510 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
511 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
516 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
517 const struct rtl8366_vlan_mc *vlanmc)
523 if (index >= RTL8366RB_NUM_VLANS ||
524 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
525 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
526 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
527 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
528 vlanmc->fid > RTL8366RB_FIDMAX)
531 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
532 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
533 RTL8366RB_VLAN_PRIORITY_SHIFT);
534 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
535 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
536 RTL8366RB_VLAN_UNTAG_SHIFT);
537 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
539 for (i = 0; i < 3; i++) {
540 err = rtl8366_smi_write_reg(smi,
541 RTL8366RB_VLAN_MC_BASE(index) + i,
550 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
555 if (port >= RTL8366RB_NUM_PORTS)
558 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
563 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
564 RTL8366RB_PORT_VLAN_CTRL_MASK;
570 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
572 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
575 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
576 RTL8366RB_PORT_VLAN_CTRL_MASK <<
577 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
578 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
579 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
582 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
584 unsigned max = RTL8366RB_NUM_VLANS;
586 if (smi->vlan4k_enabled)
587 max = RTL8366RB_NUM_VIDS - 1;
589 if (vlan == 0 || vlan >= max)
595 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
597 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
598 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
601 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
603 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
604 RTL8366RB_SGCR_EN_VLAN_4KTB,
605 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
608 static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)
610 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),
611 (enable) ? 0 : (1 << port));
614 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
615 const struct switch_attr *attr,
616 struct switch_val *val)
618 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
620 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
621 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
624 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
625 const struct switch_attr *attr,
626 struct switch_val *val)
628 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
631 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
633 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
638 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
639 const struct switch_attr *attr,
640 struct switch_val *val)
642 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
644 if (val->value.i >= 6)
647 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
648 RTL8366RB_LED_BLINKRATE_MASK,
652 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
653 const struct switch_attr *attr,
654 struct switch_val *val)
656 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
659 rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
660 val->value.i = !data;
666 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
667 const struct switch_attr *attr,
668 struct switch_val *val)
670 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
675 portmask = RTL8366RB_PORT_ALL;
677 /* set learning for all ports */
678 REG_WR(smi, RTL8366RB_SSCR0, portmask);
680 /* set auto ageing for all ports */
681 REG_WR(smi, RTL8366RB_SSCR1, portmask);
686 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
688 struct switch_port_link *link)
690 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
694 if (port >= RTL8366RB_NUM_PORTS)
697 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + (port / 2),
703 link->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK);
707 link->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK);
708 link->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK);
709 link->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK);
710 link->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK);
712 speed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK);
715 link->speed = SWITCH_PORT_SPEED_10;
718 link->speed = SWITCH_PORT_SPEED_100;
721 link->speed = SWITCH_PORT_SPEED_1000;
724 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
731 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
732 const struct switch_attr *attr,
733 struct switch_val *val)
735 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
740 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
743 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
744 reg = RTL8366RB_LED_BLINKRATE_REG;
746 data = val->value.i << 4;
748 reg = RTL8366RB_LED_CTRL_REG;
749 mask = 0xF << (val->port_vlan * 4),
750 data = val->value.i << (val->port_vlan * 4);
753 return rtl8366_smi_rmwr(smi, reg, mask, data);
756 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
757 const struct switch_attr *attr,
758 struct switch_val *val)
760 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
763 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
766 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
767 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
772 static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
773 const struct switch_attr *attr,
774 struct switch_val *val)
776 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
779 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
782 mask = 1 << val->port_vlan ;
788 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
791 static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
792 const struct switch_attr *attr,
793 struct switch_val *val)
795 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
798 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
801 rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
802 if (data & (1 << val->port_vlan))
810 static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
811 const struct switch_attr *attr,
812 struct switch_val *val)
814 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
816 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
819 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
820 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
822 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
824 return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
825 RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
827 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
831 static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
832 const struct switch_attr *attr,
833 struct switch_val *val)
835 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
838 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
841 rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
842 data &= RTL8366RB_IB_BDTH_MASK;
843 if (data < RTL8366RB_IB_BDTH_MASK)
846 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
851 static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
852 const struct switch_attr *attr,
853 struct switch_val *val)
855 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
857 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
860 rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
861 RTL8366RB_EB_PREIFG_MASK,
862 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
864 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
865 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
867 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
869 return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
870 RTL8366RB_EB_BDTH_MASK, val->value.i );
874 static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
875 const struct switch_attr *attr,
876 struct switch_val *val)
878 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
881 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
884 rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
885 data &= RTL8366RB_EB_BDTH_MASK;
886 if (data < RTL8366RB_EB_BDTH_MASK)
889 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
894 static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
895 const struct switch_attr *attr,
896 struct switch_val *val)
898 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
902 data = RTL8366RB_QOS_MASK;
906 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
909 static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
910 const struct switch_attr *attr,
911 struct switch_val *val)
913 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
916 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
917 if (data & RTL8366RB_QOS_MASK)
925 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
926 const struct switch_attr *attr,
927 struct switch_val *val)
929 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
931 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
934 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
935 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
938 static struct switch_attr rtl8366rb_globals[] = {
940 .type = SWITCH_TYPE_INT,
941 .name = "enable_learning",
942 .description = "Enable learning, enable aging",
943 .set = rtl8366rb_sw_set_learning_enable,
944 .get = rtl8366rb_sw_get_learning_enable,
947 .type = SWITCH_TYPE_INT,
948 .name = "enable_vlan",
949 .description = "Enable VLAN mode",
950 .set = rtl8366_sw_set_vlan_enable,
951 .get = rtl8366_sw_get_vlan_enable,
955 .type = SWITCH_TYPE_INT,
956 .name = "enable_vlan4k",
957 .description = "Enable VLAN 4K mode",
958 .set = rtl8366_sw_set_vlan_enable,
959 .get = rtl8366_sw_get_vlan_enable,
963 .type = SWITCH_TYPE_NOVAL,
964 .name = "reset_mibs",
965 .description = "Reset all MIB counters",
966 .set = rtl8366rb_sw_reset_mibs,
968 .type = SWITCH_TYPE_INT,
970 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
971 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
972 .set = rtl8366rb_sw_set_blinkrate,
973 .get = rtl8366rb_sw_get_blinkrate,
976 .type = SWITCH_TYPE_INT,
977 .name = "enable_qos",
978 .description = "Enable QOS",
979 .set = rtl8366rb_sw_set_qos_enable,
980 .get = rtl8366rb_sw_get_qos_enable,
985 static struct switch_attr rtl8366rb_port[] = {
987 .type = SWITCH_TYPE_NOVAL,
989 .description = "Reset single port MIB counters",
990 .set = rtl8366rb_sw_reset_port_mibs,
992 .type = SWITCH_TYPE_STRING,
994 .description = "Get MIB counters for port",
997 .get = rtl8366_sw_get_port_mib,
999 .type = SWITCH_TYPE_INT,
1001 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1003 .set = rtl8366rb_sw_set_port_led,
1004 .get = rtl8366rb_sw_get_port_led,
1006 .type = SWITCH_TYPE_INT,
1008 .description = "Get/Set port state (enabled or disabled)",
1010 .set = rtl8366rb_sw_set_port_disable,
1011 .get = rtl8366rb_sw_get_port_disable,
1013 .type = SWITCH_TYPE_INT,
1015 .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
1016 .max = RTL8366RB_BDTH_SW_MAX,
1017 .set = rtl8366rb_sw_set_port_rate_in,
1018 .get = rtl8366rb_sw_get_port_rate_in,
1020 .type = SWITCH_TYPE_INT,
1022 .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
1023 .max = RTL8366RB_BDTH_SW_MAX,
1024 .set = rtl8366rb_sw_set_port_rate_out,
1025 .get = rtl8366rb_sw_get_port_rate_out,
1029 static struct switch_attr rtl8366rb_vlan[] = {
1031 .type = SWITCH_TYPE_STRING,
1033 .description = "Get vlan information",
1036 .get = rtl8366_sw_get_vlan_info,
1038 .type = SWITCH_TYPE_INT,
1040 .description = "Get/Set vlan FID",
1041 .max = RTL8366RB_FIDMAX,
1042 .set = rtl8366_sw_set_vlan_fid,
1043 .get = rtl8366_sw_get_vlan_fid,
1047 static const struct switch_dev_ops rtl8366_ops = {
1049 .attr = rtl8366rb_globals,
1050 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1053 .attr = rtl8366rb_port,
1054 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1057 .attr = rtl8366rb_vlan,
1058 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1061 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1062 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1063 .get_port_pvid = rtl8366_sw_get_port_pvid,
1064 .set_port_pvid = rtl8366_sw_set_port_pvid,
1065 .reset_switch = rtl8366_sw_reset_switch,
1066 .get_port_link = rtl8366rb_sw_get_port_link,
1069 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
1071 struct switch_dev *dev = &smi->sw_dev;
1074 dev->name = "RTL8366RB";
1075 dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
1076 dev->ports = RTL8366RB_NUM_PORTS;
1077 dev->vlans = RTL8366RB_NUM_VIDS;
1078 dev->ops = &rtl8366_ops;
1079 dev->alias = dev_name(smi->parent);
1081 err = register_switch(dev, NULL);
1083 dev_err(smi->parent, "switch registration failed\n");
1088 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
1090 unregister_switch(&smi->sw_dev);
1093 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1095 struct rtl8366_smi *smi = bus->priv;
1099 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1106 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1108 struct rtl8366_smi *smi = bus->priv;
1112 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1114 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1119 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1125 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1127 dev_err(smi->parent, "unable to read chip id\n");
1132 case RTL8366RB_CHIP_ID_8366:
1135 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1139 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1142 dev_err(smi->parent, "unable to read chip version\n");
1146 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1147 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1152 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1153 .detect = rtl8366rb_detect,
1154 .reset_chip = rtl8366rb_reset_chip,
1155 .setup = rtl8366rb_setup,
1157 .mii_read = rtl8366rb_mii_read,
1158 .mii_write = rtl8366rb_mii_write,
1160 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1161 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1162 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1163 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1164 .get_mc_index = rtl8366rb_get_mc_index,
1165 .set_mc_index = rtl8366rb_set_mc_index,
1166 .get_mib_counter = rtl8366rb_get_mib_counter,
1167 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1168 .enable_vlan = rtl8366rb_enable_vlan,
1169 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1170 .enable_port = rtl8366rb_enable_port,
1173 static int rtl8366rb_probe(struct platform_device *pdev)
1175 static int rtl8366_smi_version_printed;
1176 struct rtl8366_smi *smi;
1179 if (!rtl8366_smi_version_printed++)
1180 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1181 " version " RTL8366RB_DRIVER_VER"\n");
1183 smi = rtl8366_smi_probe(pdev);
1187 smi->clk_delay = 10;
1188 smi->cmd_read = 0xa9;
1189 smi->cmd_write = 0xa8;
1190 smi->ops = &rtl8366rb_smi_ops;
1191 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1192 smi->num_ports = RTL8366RB_NUM_PORTS;
1193 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1194 smi->mib_counters = rtl8366rb_mib_counters;
1195 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1197 err = rtl8366_smi_init(smi);
1201 platform_set_drvdata(pdev, smi);
1203 err = rtl8366rb_switch_init(smi);
1205 goto err_clear_drvdata;
1210 platform_set_drvdata(pdev, NULL);
1211 rtl8366_smi_cleanup(smi);
1217 static int rtl8366rb_remove(struct platform_device *pdev)
1219 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1222 rtl8366rb_switch_cleanup(smi);
1223 platform_set_drvdata(pdev, NULL);
1224 rtl8366_smi_cleanup(smi);
1232 static const struct of_device_id rtl8366rb_match[] = {
1233 { .compatible = "rtl8366rb" },
1236 MODULE_DEVICE_TABLE(of, rtl8366rb_match);
1239 static struct platform_driver rtl8366rb_driver = {
1241 .name = RTL8366RB_DRIVER_NAME,
1242 .owner = THIS_MODULE,
1243 .of_match_table = of_match_ptr(rtl8366rb_match),
1245 .probe = rtl8366rb_probe,
1246 .remove = rtl8366rb_remove,
1249 static int __init rtl8366rb_module_init(void)
1251 return platform_driver_register(&rtl8366rb_driver);
1253 module_init(rtl8366rb_module_init);
1255 static void __exit rtl8366rb_module_exit(void)
1257 platform_driver_unregister(&rtl8366rb_driver);
1259 module_exit(rtl8366rb_module_exit);
1261 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1262 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1263 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1264 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1265 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1266 MODULE_LICENSE("GPL v2");
1267 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);