target/linux/coldfire/patches/052-m547x_8x_dspi.patch

   1 From acc2bc0cd419c176820d4a384eb36498a066366d Mon Sep 17 00:00:00 2001
   2 From: Kurt Mahan <kmahan@freescale.com>
   3 Date: Wed, 30 Apr 2008 14:20:48 -0600
   4 Subject: [PATCH] DSPI support for M547x/M548x.
   5
   6 LTIBName: m547x-8x-dspi
   7 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
   8 ---
   9  arch/m68k/coldfire/Makefile           |    1 +
  10  arch/m68k/coldfire/m547x_8x-devices.c |  150 +++++++++++++
  11  drivers/spi/Makefile                  |    3 +-
  12  drivers/spi/spi_coldfire.c            |  382 ++++++++++++++++-----------------
  13  include/asm-m68k/m5485dspi.h          |  144 +++++++++++++
  14  include/asm-m68k/mcfqspi.h            |    1 +
  15  include/asm-m68k/mcfsim.h             |    1 +
  16  7 files changed, 485 insertions(+), 197 deletions(-)
  17  create mode 100644 arch/m68k/coldfire/m547x_8x-devices.c
  18  create mode 100644 include/asm-m68k/m5485dspi.h
  19
  20 --- a/arch/m68k/coldfire/Makefile
  21 +++ b/arch/m68k/coldfire/Makefile
  22 @@ -10,4 +10,5 @@ endif
  23
  24  obj-$(CONFIG_PCI)      += pci.o mcf5445x-pci.o iomap.o
  25  obj-$(CONFIG_M54455)   += mcf5445x-devices.o
  26 +obj-$(CONFIG_M547X_8X) += m547x_8x-devices.o
  27  obj-$(CONFIG_MCD_DMA)  += m547x_8x-dma.o
  28 --- /dev/null
  29 +++ b/arch/m68k/coldfire/m547x_8x-devices.c
  30 @@ -0,0 +1,150 @@
  31 +/*
  32 + * arch/m68k/coldfire/m547x_8x-devices.c
  33 + *
  34 + * Coldfire M547x/M548x Platform Device Configuration
  35 + *
  36 + * Copyright (c) 2008 Freescale Semiconductor, Inc.
  37 + *     Kurt Mahan <kmahan@freescale.com>
  38 + */
  39 +#include <linux/module.h>
  40 +#include <linux/kernel.h>
  41 +#include <linux/init.h>
  42 +#include <linux/platform_device.h>
  43 +#include <linux/fsl_devices.h>
  44 +#include <linux/spi/spi.h>
  45 +
  46 +#include <asm/coldfire.h>
  47 +#include <asm/mcfsim.h>
  48 +#include <asm/mcfqspi.h>
  49 +
  50 +
  51 +#ifdef CONFIG_SPI
  52 +/*
  53 + *
  54 + * DSPI
  55 + *
  56 + */
  57 +
  58 +/* number of supported SPI selects */
  59 +#define SPI_NUM_CHIPSELECTS    4
  60 +
  61 +void coldfire_spi_cs_control(u8 cs, u8 command)
  62 +{
  63 +       /* nothing special required */
  64 +}
  65 +
  66 +static struct spi_board_info spi_board_info[] = {
  67 +       /* no board info */
  68 +};
  69 +
  70 +static int spi_irq_list[] = {
  71 +       /* IRQ, ICR Offset, ICR Val, Mask */
  72 +       64 + ISC_DSPI_OVRFW, 0, 0, 0,
  73 +       64 + ISC_DSPI_RFOF,  0, 0, 0,
  74 +       64 + ISC_DSPI_RFDF,  0, 0, 0,
  75 +       64 + ISC_DSPI_TFUF,  0, 0, 0,
  76 +       64 + ISC_DSPI_TCF,   0, 0, 0,
  77 +       64 + ISC_DSPI_TFFF,  0, 0, 0,
  78 +       64 + ISC_DSPI_EOQF,  0, 0, 0,
  79 +       0,0,0,0,
  80 +};
  81 +
  82 +static struct coldfire_spi_master coldfire_master_info = {
  83 +       .bus_num = 1,
  84 +       .num_chipselect = SPI_NUM_CHIPSELECTS,
  85 +       .irq_list = spi_irq_list,
  86 +       .irq_source = 0,        /* not used */
  87 +       .irq_vector = 0,        /* not used */
  88 +       .irq_mask = 0,          /* not used */
  89 +       .irq_lp = 0,            /* not used */
  90 +       .par_val = 0,           /* not used */
  91 +       .cs_control = coldfire_spi_cs_control,
  92 +};
  93 +
  94 +static struct resource coldfire_spi_resources[] = {
  95 +       [0] = {
  96 +               .name = "spi-par",
  97 +               .start = MCF_MBAR + 0x00000a50, /* PAR_DSPI */
  98 +               .end = MCF_MBAR + 0x00000a50,   /* PAR_DSPI */
  99 +               .flags = IORESOURCE_MEM
 100 +       },
 101 +
 102 +       [1] = {
 103 +               .name = "spi-module",
 104 +               .start = MCF_MBAR + 0x00008a00, /* DSPI MCR Base */
 105 +               .end = MCF_MBAR + 0x00008ab8,   /* DSPI mem map end */
 106 +               .flags = IORESOURCE_MEM
 107 +       },
 108 +
 109 +       [2] = {
 110 +               .name = "spi-int-level",
 111 +               .start = MCF_MBAR + 0x740,               /* ICR start */
 112 +               .end = MCF_MBAR + 0x740 + ISC_DSPI_EOQF, /* ICR end */
 113 +               .flags = IORESOURCE_MEM
 114 +       },
 115 +
 116 +       [3] = {
 117 +               .name = "spi-int-mask",
 118 +               .start = MCF_MBAR + 0x70c,      /* IMRL */
 119 +               .end = MCF_MBAR + 0x70c,        /* IMRL */
 120 +               .flags = IORESOURCE_MEM
 121 +       }
 122 +};
 123 +
 124 +static struct platform_device coldfire_spi = {
 125 +       .name = "spi_coldfire",
 126 +       .id = -1,
 127 +       .resource = coldfire_spi_resources,
 128 +       .num_resources = ARRAY_SIZE(coldfire_spi_resources),
 129 +       .dev = {
 130 +               .platform_data = &coldfire_master_info,
 131 +       }
 132 +};
 133 +
 134 +/**
 135 + * m547x_8x_spi_init - Initialize SPI
 136 + */
 137 +static int __init m547x_8x_spi_init(void)
 138 +{
 139 +       int retval;
 140 +
 141 +       /* initialize the DSPI PAR */
 142 +       MCF_GPIO_PAR_DSPI = (MCF_GPIO_PAR_DSPI_PAR_CS5 |
 143 +                            MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS |
 144 +                            MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS |
 145 +                            MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS |
 146 +                            MCF_GPIO_PAR_DSPI_PAR_SCK_SCK |
 147 +                            MCF_GPIO_PAR_DSPI_PAR_SIN_SIN |
 148 +                            MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT);
 149 +
 150 +       /* register device */
 151 +       retval = platform_device_register(&coldfire_spi);
 152 +       if (retval < 0) {
 153 +               printk(KERN_ERR "SPI-m547x_8x: platform_device_register failed with code=%d\n", retval);
 154 +               goto out;
 155 +       }
 156 +
 157 +       /* register board info */
 158 +       if (ARRAY_SIZE(spi_board_info))
 159 +               retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
 160 +
 161 +out:
 162 +       return retval;
 163 +}
 164 +#endif
 165 +
 166 +
 167 +/**
 168 + * m547x_8x_init_devices - Initialize M547X_8X devices
 169 + *
 170 + * Returns 0 on success.
 171 + */
 172 +static int __init m547x_8x_init_devices(void)
 173 +{
 174 +#ifdef CONFIG_SPI
 175 +       m547x_8x_spi_init();
 176 +#endif
 177 +
 178 +       return 0;
 179 +}
 180 +arch_initcall(m547x_8x_init_devices);
 181 --- a/drivers/spi/Makefile
 182 +++ b/drivers/spi/Makefile
 183 @@ -18,7 +18,8 @@ obj-$(CONFIG_SPI_BFIN)                        += spi_bfin5xx.
 184  obj-$(CONFIG_SPI_BITBANG)              += spi_bitbang.o
 185  obj-$(CONFIG_SPI_AU1550)               += au1550_spi.o
 186  obj-$(CONFIG_SPI_BUTTERFLY)            += spi_butterfly.o
 187 -obj-$(CONFIG_SPI_COLDFIRE)             += spi_coldfire.o spi-m5445x.o
 188 +# obj-$(CONFIG_SPI_COLDFIRE)           += spi_coldfire.o spi-m5445x.o
 189 +obj-$(CONFIG_SPI_COLDFIRE)             += spi_coldfire.o
 190  obj-$(CONFIG_SPI_GPIO)                 += spi_gpio.o
 191  obj-$(CONFIG_SPI_IMX)                  += spi_imx.o
 192  obj-$(CONFIG_SPI_LM70_LLP)             += spi_lm70llp.o
 193 --- a/drivers/spi/spi_coldfire.c
 194 +++ b/drivers/spi/spi_coldfire.c
 195 @@ -1,29 +1,39 @@
 196 -/****************************************************************************/
 197 -
 198  /*
 199 - *     spi_coldfire.c - Master QSPI/DSPI controller for the ColdFire processors
 200 + * spi_coldfire.c - Master QSPI/DSPI controller for the ColdFire processors
 201 + *
 202   *
 203   *     (C) Copyright 2005, Intec Automation,
 204   *                         Mike Lavender (mike@steroidmicros)
 205   *
 206 - *     (C) Copyright 2007, Freescale Inc,
 207 - *                         Yaroslav Vinogradov (yaroslav.vinogradov@freescale.com)
 208 + *     (C) Copyright 2007-2008, Freescale Inc,
 209 + *                     Yaroslav Vinogradov
 210 + *                     Andrey Butok
 211 + *                     Kurt Mahan
 212   *
 213 -
 214 -     This program is free software; you can redistribute it and/or modify
 215 -     it under the terms of the GNU General Public License as published by
 216 -     the Free Software Foundation; either version 2 of the License, or
 217 -     (at your option) any later version.
 218 -
 219 -     This program is distributed in the hope that it will be useful,
 220 -     but WITHOUT ANY WARRANTY; without even the implied warranty of
 221 -     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 222 -     GNU General Public License for more details.
 223 -
 224 -     You should have received a copy of the GNU General Public License
 225 -     along with this program; if not, write to the Free Software
 226 -     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.              */
 227 -/* ------------------------------------------------------------------------- */
 228 + * This program is free software; you can redistribute  it and/or modify it
 229 + * under  the terms of  the GNU General  Public License as published by the
 230 + * Free Software Foundation;  either version 2 of the  License, or (at your
 231 + * option) any later version.
 232 + *
 233 + * This program is distributed in the hope that it will be useful,
 234 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 235 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 236 + * GNU General Public License for more details.
 237 + *
 238 + * You should have received a copy of the GNU General Public License
 239 + * along with this program; if not, write to the Free Software
 240 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 241 + *
 242 + ***************************************************************************
 243 + * Changes:
 244 + *   v0.003    12 February 2008        Andrey Butok, Freescale Semiconductor
 245 + *             Added suport of MCF5227x DSPI module.
 246 + *   v0.002    2007    Yaroslav Vinogradov, Freescale Semiconductor
 247 + *             Added suport of MCF5445x DSPI module.
 248 + *   v0.001    2005            Mike Lavender, Intec Automation,
 249 + *             Intial version. Coldfire QSPI master driver.
 250 + *
 251 + */
 252
 253
 254  /****************************************************************************/
 255 @@ -46,41 +56,52 @@
 256  #include <asm/mcfsim.h>
 257  #include <asm/mcfqspi.h>
 258  #include <asm/coldfire.h>
 259 -#include <asm/virtconvert.h>
 260
 261  #if defined(CONFIG_M54455)
 262 +       #include <asm/virtconvert.h>
 263 +
 264         #define SPI_DSPI
 265         #if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
 266                 #define SPI_DSPI_EDMA
 267                 #ifdef CONFIG_MMU
 268                         #define SPI_USE_MMU
 269                 #endif
 270 +               #include <asm/mcf5445x_edma.h>
 271         #endif
 272 +
 273 +       #include <asm/mcf5445x_dspi.h>
 274  #endif
 275
 276 -#ifdef SPI_DSPI
 277 -#include <asm/mcf5445x_dspi.h>
 278 +#if defined(CONFIG_M547X_8X)
 279 +       #define SPI_DSPI
 280 +
 281 +       #include <asm/virtconvert.h>
 282 +       #include <asm/m5485dspi.h>
 283 +#endif
 284
 285 +#ifdef CONFIG_M5227x
 286 +       #define SPI_DSPI
 287
 288 +       #if defined(CONFIG_SPI_COLDFIRE_DSPI_EDMA)
 289 +               #define SPI_DSPI_EDMA
 290 +       #endif
 291  #endif
 292
 293 +
 294  #if defined(SPI_DSPI_EDMA)
 295
 296  /* edma buffer size in transfer units (32bits) */
 297  #define EDMA_BUFFER_SIZE       (PAGE_SIZE/4)
 298 -#define EDMA_BUFSIZE_KMALLOC (EDMA_BUFFER_SIZE*4)
 299 -
 300 -#define DSPI_DMA_RX_TCD        12
 301 -#define DSPI_DMA_TX_TCD 13
 302 +#define EDMA_BUFSIZE_KMALLOC   (EDMA_BUFFER_SIZE*4)
 303
 304 +#define DSPI_DMA_RX_TCD                MCF_EDMA_CHAN_DSPI_RX
 305 +#define DSPI_DMA_TX_TCD        MCF_EDMA_CHAN_DSPI_TX
 306
 307 -#include <asm/coldfire_edma.h>
 308 -#include <asm/mcf5445x_edma.h>
 309 +#include <asm/mcf_edma.h>
 310  #endif
 311
 312 -
 313  MODULE_AUTHOR("Mike Lavender");
 314 -MODULE_DESCRIPTION("ColdFire QSPI Contoller");
 315 +MODULE_DESCRIPTION("ColdFire SPI Contoller");
 316  MODULE_LICENSE("GPL");
 317
 318  #define DRIVER_NAME "Coldfire QSPI/DSPI"
 319 @@ -92,7 +113,6 @@ MODULE_LICENSE("GPL");
 320   */
 321
 322  #define QSPI_RAM_SIZE          0x10    /* 16 word table */
 323 -
 324  #define QSPI_TRANSMIT_RAM      0x00
 325  #define QSPI_RECEIVE_RAM       0x10
 326  #define QSPI_COMMAND_RAM       0x20
 327 @@ -296,13 +316,10 @@ struct driver_data {
 328         u32 *dspi_rser;         /* DSPI RSER register */
 329         u32 *dspi_sr;           /* DSPI status register */
 330         u8      dspi_ctas;              /* DSPI CTAS value*/
 331 -
 332  #if defined(SPI_DSPI_EDMA)
 333         void*   edma_tx_buf;
 334         void*   edma_rx_buf;
 335  #endif
 336 -
 337 -
 338  #else
 339         u16 *qmr;          /* QSPI mode register      */
 340         u16 *qdlyr;        /* QSPI delay register     */
 341 @@ -312,7 +329,11 @@ struct driver_data {
 342         u16 *qdr;          /* QSPI data register      */
 343         u16 *qcr;          /* QSPI command register   */
 344  #endif
 345 +#if defined(CONFIG_M532x) || defined(CONFIG_M537x)
 346 +       u16 *par;          /* Pin assignment register */
 347 +#else
 348         u8  *par;          /* Pin assignment register */
 349 +#endif
 350         u8  *int_icr;      /* Interrupt level and priority register */
 351         u32 *int_mr;       /* Interrupt mask register */
 352         void (*cs_control)(u8 cs, u8 command);
 353 @@ -327,8 +348,6 @@ struct driver_data {
 354   * SPI local functions
 355   */
 356
 357 -//#define SPI_COLDFIRE_DEBUG
 358 -
 359  static void *next_transfer(struct driver_data *drv_data)
 360  {
 361         struct spi_message *msg = drv_data->cur_msg;
 362 @@ -387,11 +406,9 @@ static int write(struct driver_data *drv
 363         int tx_word;
 364
 365  #if defined(SPI_DSPI)
 366 -
 367  #if defined(SPI_DSPI_EDMA)
 368         u32* edma_wr;
 369  #endif
 370 -
 371         u16 d16;
 372         u8  d8;
 373         u32 dspi_pushr;
 374 @@ -400,9 +417,9 @@ static int write(struct driver_data *drv
 375
 376         tx_word = is_word_transfer(drv_data);
 377
 378 -       // If we are in word mode, but only have a single byte to transfer
 379 -       // then switch to byte mode temporarily.  Will switch back at the
 380 -       // end of the transfer.
 381 +       /* If we are in word mode, but only have a single byte to transfer
 382 +        * then switch to byte mode temporarily.  Will switch back at the
 383 +        * end of the transfer. */
 384         if (tx_word && ((drv_data->tx_end - drv_data->tx) == 1)) {
 385                 drv_data->flags |= TRAN_STATE_WORD_ODD_NUM;
 386                 set_8bit_transfer_mode(drv_data);
 387 @@ -411,12 +428,10 @@ static int write(struct driver_data *drv
 388
 389
 390  #if defined(SPI_DSPI)
 391 -
 392  #if defined(SPI_DSPI_EDMA)
 393         edma_wr = (u32*)(drv_data->edma_tx_buf);
 394  #endif
 395
 396 -
 397  #if defined(SPI_DSPI_EDMA)
 398         while ((drv_data->tx < drv_data->tx_end) && (tx_count < EDMA_BUFFER_SIZE)) {
 399  #else
 400 @@ -432,19 +447,16 @@ static int write(struct driver_data *drv
 401                         }
 402
 403                         dspi_pushr = MCF_DSPI_DTFR_TXDATA(d16)
 404 -                                                 | DSPI_CS(drv_data->cs)
 405 -                                                | MCF_DSPI_DTFR_CTAS(drv_data->dspi_ctas)
 406 -                                                //| MCF_DSPI_DTFR_CONT
 407 -                                                ;
 408 -
 409 +                                       | DSPI_CS(drv_data->cs)
 410 +                                       | MCF_DSPI_DTFR_CTAS(drv_data->dspi_ctas);
 411                         drv_data->tx += 2;
 412
 413  #if defined(SPI_DSPI_EDMA)
 414                         if (drv_data->tx == drv_data->tx_end  || tx_count==EDMA_BUFFER_SIZE-1) {
 415 -#else
 416 +#else
 417                         if (drv_data->tx == drv_data->tx_end  || tx_count==DSPI_FIFO_SIZE-1) {
 418 -#endif
 419 -                               // last transfer in queue
 420 +#endif
 421 +                               /* last transfer in the queue */
 422                                 dspi_pushr |= MCF_DSPI_DTFR_EOQ;
 423                                 if (drv_data->cs_change) {
 424                                         dspi_pushr &= ~MCF_DSPI_DTFR_CONT;
 425 @@ -453,14 +465,13 @@ static int write(struct driver_data *drv
 426
 427                         if (first) {
 428                                 first = 0;
 429 -                               dspi_pushr |= MCF_DSPI_DTFR_CTCNT; // clear counter
 430 +                               dspi_pushr |= MCF_DSPI_DTFR_CTCNT; /* clear counter */
 431                         }
 432  #if defined(SPI_DSPI_EDMA)
 433                         *edma_wr = dspi_pushr;
 434 -                       edma_wr++;
 435 +                       edma_wr++;
 436  #else
 437                         *drv_data->dspi_dtfr = dspi_pushr;
 438 -                       //MCF_DSPI_DTFR = dspi_pushr;
 439  #endif
 440
 441
 442 @@ -473,14 +484,13 @@ static int write(struct driver_data *drv
 443
 444                         dspi_pushr = MCF_DSPI_DTFR_TXDATA(d8)
 445                                                  | DSPI_CS(drv_data->cs)
 446 -                                                /* | MCF_DSPI_DTFR_PCS5 | */
 447                                                  | MCF_DSPI_DTFR_CTAS(drv_data->dspi_ctas)
 448                                                  | MCF_DSPI_DTFR_CONT;
 449
 450                         drv_data->tx++;
 451
 452                         if (drv_data->tx == drv_data->tx_end  || tx_count==DSPI_FIFO_SIZE-1) {
 453 -                               // last transfer in queue
 454 +                               /* last transfer in the queue */
 455                                 dspi_pushr |= MCF_DSPI_DTFR_EOQ;
 456                                 if (drv_data->cs_change) {
 457                                         dspi_pushr &= ~MCF_DSPI_DTFR_CONT;
 458 @@ -489,16 +499,15 @@ static int write(struct driver_data *drv
 459
 460                         if (first) {
 461                                 first = 0;
 462 -                               dspi_pushr |= MCF_DSPI_DTFR_CTCNT; // clear counter
 463 +                               dspi_pushr |= MCF_DSPI_DTFR_CTCNT; /* clear counter */
 464                         }
 465
 466  #if defined(SPI_DSPI_EDMA)
 467                         *edma_wr = dspi_pushr;
 468 -                       edma_wr++;
 469 -#else
 470 +                       edma_wr++;
 471 +#else
 472                         *drv_data->dspi_dtfr = dspi_pushr;
 473 -                       //MCF_DSPI_DTFR = dspi_pushr;
 474 -#endif
 475 +#endif
 476
 477                 }
 478                 tx_count++;
 479 @@ -508,8 +517,8 @@ static int write(struct driver_data *drv
 480
 481         if (tx_count>0) {
 482
 483 -               // TODO: initiate eDMA transfer
 484 -               set_edma_params(DSPI_DMA_TX_TCD,
 485 +               /* TBD: initiate eDMA transfer */
 486 +               mcf_edma_set_tcd_params(DSPI_DMA_TX_TCD,
 487  #ifdef SPI_USE_MMU
 488                                         virt_to_phys(drv_data->edma_tx_buf),
 489  #else
 490 @@ -517,18 +526,18 @@ static int write(struct driver_data *drv
 491  #endif
 492                                         (u32)drv_data->dspi_dtfr,
 493                                         MCF_EDMA_TCD_ATTR_SSIZE_32BIT | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
 494 -                                       4,  // soff
 495 -                                       4,  // nbytes
 496 -                                       0,  // slast
 497 -                                       tx_count, // citer
 498 -                                       tx_count, // biter
 499 -                                       0, // doff
 500 -                                       0, // dlastsga
 501 -                                       0, // major_int
 502 -                                       1  // disable_req
 503 +                                       4, /* soff */
 504 +                                       4, /* nbytes */
 505 +                                       0, /* slast */
 506 +                                       tx_count, /* citer */
 507 +                                       tx_count, /* biter */
 508 +                                       0, /* doff */
 509 +                                       0, /* dlastsga */
 510 +                                       0, /* major_int */
 511 +                                       1  /* disable_req */
 512                                         );
 513
 514 -               set_edma_params(DSPI_DMA_RX_TCD,
 515 +               mcf_edma_set_tcd_params(DSPI_DMA_RX_TCD,
 516                                         (u32)drv_data->dspi_drfr,
 517  #ifdef SPI_USE_MMU
 518                                         virt_to_phys(drv_data->edma_rx_buf),
 519 @@ -536,20 +545,20 @@ static int write(struct driver_data *drv
 520                                         drv_data->edma_rx_buf,
 521  #endif
 522                                         MCF_EDMA_TCD_ATTR_SSIZE_32BIT | MCF_EDMA_TCD_ATTR_DSIZE_32BIT,
 523 -                                       0,  // soff
 524 -                                       4,  // nbytes
 525 -                                       0,  // slast
 526 -                                       tx_count, // citer
 527 -                                       tx_count, // biter
 528 -                                       4, // doff
 529 -                                       0,  // dlastsga
 530 -                    0,   // major_int
 531 -                                       1       // disable_req
 532 +                                       0, /* soff */
 533 +                                       4, /* nbytes */
 534 +                                       0, /* slast */
 535 +                                       tx_count, /* citer */
 536 +                                       tx_count, /* biter */
 537 +                                       4, /* doff */
 538 +                                       0, /* dlastsga */
 539 +                                       0, /* major_int */
 540 +                                       1  /* disable_req */
 541                                         );
 542
 543
 544 -               start_edma_transfer(DSPI_DMA_TX_TCD); // transmit SPI data
 545 -               start_edma_transfer(DSPI_DMA_RX_TCD); // receive SPI data
 546 +               start_edma_transfer(DSPI_DMA_TX_TCD); /* transmit SPI data */
 547 +               start_edma_transfer(DSPI_DMA_RX_TCD); /* receive SPI data */
 548         }
 549  #endif
 550
 551 @@ -583,9 +592,9 @@ static int write(struct driver_data *drv
 552                           | QCR_CONT
 553                           | (~((0x01 << drv_data->cs) << 8) & 0x0F00);
 554
 555 -               if (       (cmd_count == tx_count - 1)
 556 -                       && (drv_data->tx == drv_data->tx_end)
 557 -                       && (drv_data->cs_change) ) {
 558 +               if ( (cmd_count == tx_count - 1)
 559 +                    && (drv_data->tx == drv_data->tx_end)
 560 +                    && (drv_data->cs_change) ) {
 561                         qcr &= ~QCR_CONT;
 562                 }
 563                 *drv_data->qcr = qcr;
 564 @@ -613,7 +622,6 @@ static int read(struct driver_data *drv_
 565         rx_word = is_word_transfer(drv_data);
 566
 567  #if defined(SPI_DSPI)
 568 -
 569  #if defined(SPI_DSPI_EDMA)
 570         rx_edma = (u32*) drv_data->edma_tx_buf;
 571         while ((drv_data->rx < drv_data->rx_end) && (rx_count < EDMA_BUFFER_SIZE)) {
 572 @@ -646,10 +654,7 @@ static int read(struct driver_data *drv_
 573                 }
 574                 rx_count++;
 575         }
 576 -
 577 -
 578  #else
 579 -
 580         *drv_data->qar = QSPI_RECEIVE_RAM;
 581         while ((drv_data->rx < drv_data->rx_end) && (rx_count < QSPI_RAM_SIZE)) {
 582                 if (rx_word) {
 583 @@ -680,19 +685,18 @@ static inline void qspi_setup_chip(struc
 584
 585         *drv_data->mcr = chip->mcr_val;
 586
 587 -       // TODO: remove later
 588 +       /* TBD: remove later */
 589 +/* JKM -- validate */
 590         chip->ctar_val = 0x78560118;
 591
 592         *drv_data->ctar = chip->ctar_val;
 593         *drv_data->dspi_rser =  0
 594 -                                                       | MCF_DSPI_DRSER_EOQFE
 595 +                               | MCF_DSPI_DRSER_EOQFE
 596  #if defined(SPI_DSPI_EDMA)
 597 -                                                       | MCF_DSPI_DRSER_TFFFE
 598 -                                                       | MCF_DSPI_DRSER_TFFFS
 599 +                               | MCF_DSPI_DRSER_TFFFE
 600 +                               | MCF_DSPI_DRSER_TFFFS
 601  #endif
 602 -                                                       ;
 603 -
 604 -
 605 +                               ;
 606  #else
 607         *drv_data->qmr = chip->qmr_val;
 608         *drv_data->qdlyr = chip->qdlyr_val;
 609 @@ -770,7 +774,6 @@ static irqreturn_t qspi_interrupt(int ir
 610                          * transfer tasklet
 611                          */
 612                         if (drv_data->flags & TRAN_STATE_WORD_ODD_NUM) {
 613 -                               //*drv_data->qmr &= ~QMR_BITS;
 614                                 set_16bit_transfer_mode(drv_data);
 615                         }
 616
 617 @@ -857,10 +860,8 @@ static void pump_transfers(unsigned long
 618         if (message->state == START_STATE) {
 619                 qspi_setup_chip(drv_data);
 620
 621 -               if (drv_data->cs_control) {
 622 -                       //printk( "m s\n" );
 623 -                       drv_data->cs_control(message->spi->chip_select, QSPI_CS_ASSERT);
 624 -               }
 625 +               if (drv_data->cs_control)
 626 +                       drv_data->cs_control(message->spi->chip_select, QSPI_CS_ASSERT);
 627         }
 628
 629         /* Delay if requested at end of transfer*/
 630 @@ -902,12 +903,12 @@ static void pump_transfers(unsigned long
 631  }
 632
 633
 634 -static void pump_messages(struct work_struct * work)
 635 +static void pump_messages(struct work_struct *work)
 636  {
 637         struct driver_data *drv_data;
 638         unsigned long flags;
 639
 640 -       drv_data = container_of(work,  struct driver_data, pump_messages);
 641 +       drv_data = container_of(work, struct driver_data, pump_messages);
 642
 643         /* Lock queue and check for queue work */
 644         spin_lock_irqsave(&drv_data->lock, flags);
 645 @@ -1002,7 +1003,7 @@ static int setup(struct spi_device *spi)
 646         chip->mcr.cont_scke = 0;
 647         chip->mcr.dconf = 0;
 648         chip->mcr.frz = 0;
 649 -       chip->mcr.mtfe = 1;
 650 +       chip->mcr.mtfe = 0;
 651         chip->mcr.pcsse = 0;
 652         chip->mcr.rooe = 0;
 653         chip->mcr.pcsis = 0xFF;
 654 @@ -1019,7 +1020,7 @@ static int setup(struct spi_device *spi)
 655         if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
 656                 chip->ctar.fmsz = spi->bits_per_word-1;
 657         } else {
 658 -               printk(KERN_ERR "coldfire-qspi: invalid wordsize\n");
 659 +               printk(KERN_ERR "coldfire-spi: invalid wordsize\n");
 660                 kfree(chip);
 661                 return -ENODEV;
 662         }
 663 @@ -1056,9 +1057,9 @@ static int setup(struct spi_device *spi)
 664
 665  #else
 666
 667 -       chip->qwr.csiv = 1;    // Chip selects are active low
 668 -       chip->qmr.master = 1;  // Must set to master mode
 669 -       chip->qmr.dohie = 1;   // Data output high impediance enabled
 670 +       chip->qwr.csiv = 1;    /* Chip selects are active low */
 671 +       chip->qmr.master = 1;  /* Must set to master mode */
 672 +       chip->qmr.dohie = 1;   /* Data output high impediance enabled */
 673         chip->void_write_data = chip_info->void_write_data;
 674
 675         chip->qdlyr.qcd = chip_info->del_cs_to_clk;
 676 @@ -1075,8 +1076,8 @@ static int setup(struct spi_device *spi)
 677
 678         chip->qmr.baud = baud_divisor;
 679
 680 -       //printk( "QSPI: spi->max_speed_hz %d\n", spi->max_speed_hz );
 681 -       //printk( "QSPI: Baud set to %d\n", chip->qmr.baud );
 682 +       /*printk( "SPI: spi->max_speed_hz %d\n", spi->max_speed_hz );*/
 683 +       /*printk( "SPI: Baud set to %d\n", chip->qmr.baud );*/
 684
 685         if (spi->mode & SPI_CPHA)
 686                 chip->qmr.cpha = 1;
 687 @@ -1089,7 +1090,7 @@ static int setup(struct spi_device *spi)
 688         } else if ((spi->bits_per_word >= 8) && (spi->bits_per_word <= 15)) {
 689                 chip->qmr.bits = spi->bits_per_word;
 690         } else {
 691 -               printk(KERN_ERR "coldfire-qspi: invalid wordsize\n");
 692 +               printk(KERN_ERR "coldfire-spi: invalid wordsize\n");
 693                 kfree(chip);
 694                 return -ENODEV;
 695         }
 696 @@ -1112,7 +1113,7 @@ static int init_queue(struct driver_data
 697         tasklet_init(&drv_data->pump_transfers,
 698                         pump_transfers, (unsigned long)drv_data);
 699
 700 -       INIT_WORK(&drv_data->pump_messages, pump_messages/*, drv_data*/);
 701 +       INIT_WORK(&drv_data->pump_messages, pump_messages);
 702
 703         drv_data->workqueue = create_singlethread_workqueue(
 704                                         drv_data->master->dev.parent->bus_id);
 705 @@ -1185,7 +1186,7 @@ static int destroy_queue(struct driver_d
 706  }
 707
 708
 709 -static void cleanup(const struct spi_device *spi)
 710 +static void cleanup(struct spi_device *spi)
 711  {
 712         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
 713
 714 @@ -1213,11 +1214,7 @@ static int coldfire_spi_probe(struct pla
 715         int status = 0;
 716         int i;
 717
 718 -#if defined(SPI_DSPI_EDMA)
 719 -       init_edma();
 720 -#endif
 721 -
 722 -       platform_info = (struct coldfire_spi_master *)pdev->dev.platform_data;
 723 +       platform_info = (struct coldfire_spi_master *)pdev->dev.platform_data;
 724
 725         master = spi_alloc_master(dev, sizeof(struct driver_data));
 726         if (!master)
 727 @@ -1241,7 +1238,7 @@ static int coldfire_spi_probe(struct pla
 728                         drv_data->cs_control(i, QSPI_CS_INIT | QSPI_CS_DROP);
 729
 730         /* Setup register addresses */
 731 -       memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi-module");
 732 +       memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spi-module");
 733         if (!memory_resource) {
 734                 dev_dbg(dev, "can not find platform module memory\n");
 735                 goto out_error_master_alloc;
 736 @@ -1259,13 +1256,13 @@ static int coldfire_spi_probe(struct pla
 737                 dev_dbg(dev, "cannot allocate eDMA RX memory\n");
 738                 goto out_error_master_alloc;
 739         }
 740 -#endif
 741 +#endif
 742
 743  #if defined(SPI_DSPI)
 744
 745 -       drv_data->mcr           = (void *)(memory_resource->start + 0x00000000);
 746 -       drv_data->ctar          = (void *)(memory_resource->start + 0x0000000C);
 747 -       drv_data->dspi_sr       = (void *)(memory_resource->start + 0x0000002C);
 748 +       drv_data->mcr       = (void *)(memory_resource->start + 0x00000000);
 749 +       drv_data->ctar      = (void *)(memory_resource->start + 0x0000000C);
 750 +       drv_data->dspi_sr   = (void *)(memory_resource->start + 0x0000002C);
 751         drv_data->dspi_rser = (void *)(memory_resource->start + 0x00000030);
 752         drv_data->dspi_dtfr = (void *)(memory_resource->start + 0x00000034);
 753         drv_data->dspi_drfr = (void *)(memory_resource->start + 0x00000038);
 754 @@ -1283,7 +1280,7 @@ static int coldfire_spi_probe(struct pla
 755  #endif
 756
 757         /* Setup register addresses */
 758 -       memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi-par");
 759 +       memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spi-par");
 760         if (!memory_resource) {
 761                 dev_dbg(dev, "can not find platform par memory\n");
 762                 goto out_error_master_alloc;
 763 @@ -1292,7 +1289,7 @@ static int coldfire_spi_probe(struct pla
 764         drv_data->par = (void *)memory_resource->start;
 765
 766         /* Setup register addresses */
 767 -       memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi-int-level");
 768 +       memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spi-int-level");
 769         if (!memory_resource) {
 770                 dev_dbg(dev, "can not find platform par memory\n");
 771                 goto out_error_master_alloc;
 772 @@ -1301,7 +1298,7 @@ static int coldfire_spi_probe(struct pla
 773         drv_data->int_icr = (void *)memory_resource->start;
 774
 775         /* Setup register addresses */
 776 -       memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi-int-mask");
 777 +       memory_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spi-int-mask");
 778         if (!memory_resource) {
 779                 dev_dbg(dev, "can not find platform par memory\n");
 780                 goto out_error_master_alloc;
 781 @@ -1309,32 +1306,52 @@ static int coldfire_spi_probe(struct pla
 782
 783         drv_data->int_mr = (void *)memory_resource->start;
 784
 785 -       irq = platform_info->irq_vector;
 786 +       if (platform_info->irq_list) {
 787 +               /* multiple IRQs */
 788 +               int *irqlist = platform_info->irq_list;
 789 +               while ((irq = *irqlist++)) {
 790 +                       int off = *irqlist++;
 791 +                       int lvl = *irqlist++;
 792 +                       int msk = *irqlist++;
 793 +                       status = request_irq(irq, qspi_interrupt, IRQF_DISABLED,
 794 +                                            dev->bus_id, drv_data);
 795 +                       if (status < 0) {
 796 +                               dev_err(&pdev->dev,
 797 +                                       "unable to attach ColdFire DSPI interrupt\n");
 798 +                               goto out_error_master_alloc;
 799 +                       }
 800 +
 801 +                       if (lvl)
 802 +                               *(drv_data->int_icr + off) = lvl;
 803
 804 -       status = request_irq(platform_info->irq_vector, qspi_interrupt, IRQF_DISABLED, dev->bus_id, drv_data);
 805 -       if (status < 0) {
 806 -               dev_err(&pdev->dev, "unable to attach ColdFire QSPI interrupt\n");
 807 -               goto out_error_master_alloc;
 808 +                       if (msk)
 809 +                               *drv_data->int_mr &= ~msk;
 810 +               }
 811         }
 812 +       else {
 813 +               irq = platform_info->irq_vector;
 814
 815 -       /* Now that we have all the addresses etc.  Let's set it up */
 816 -       // TODO:
 817 -       //*drv_data->par = platform_info->par_val;
 818 +               status = request_irq(platform_info->irq_vector, qspi_interrupt,
 819 +                                    IRQF_DISABLED, dev->bus_id, drv_data);
 820 +               if (status < 0) {
 821 +                       dev_err(&pdev->dev, "unable to attach ColdFire QSPI interrupt\n");
 822 +                       goto out_error_master_alloc;
 823 +               }
 824
 825 -       MCF_GPIO_PAR_DSPI = 0
 826 -               | MCF_GPIO_PAR_DSPI_PCS5_PCS5
 827 -               | MCF_GPIO_PAR_DSPI_PCS2_PCS2
 828 -               | MCF_GPIO_PAR_DSPI_PCS1_PCS1
 829 -               | MCF_GPIO_PAR_DSPI_PCS0_PCS0
 830 -               | MCF_GPIO_PAR_DSPI_SIN_SIN
 831 -               | MCF_GPIO_PAR_DSPI_SOUT_SOUT
 832 -               | MCF_GPIO_PAR_DSPI_SCK_SCK;
 833 +               *drv_data->int_icr = platform_info->irq_lp;
 834 +               *drv_data->int_mr &= ~platform_info->irq_mask;
 835 +       }
 836 +
 837 +       /* Now that we have all the addresses etc.  Let's set it up */
 838 +       if (platform_info->par_val)
 839 +               *drv_data->par = platform_info->par_val;
 840
 841 -       *drv_data->int_icr = platform_info->irq_lp;
 842 -       *drv_data->int_mr &= ~platform_info->irq_mask;
 843 +#ifdef CONFIG_M5227x
 844 +       MCF_GPIO_PAR_IRQ = 0x04; /* Mistake in RM documentation */
 845 +#endif
 846
 847  #ifdef SPI_DSPI
 848 -       drv_data->dspi_ctas = 0; // TODO: change later
 849 +       drv_data->dspi_ctas = 0; /* TBD: change later */
 850  #endif
 851
 852         /* Initial and start queue */
 853 @@ -1359,40 +1376,37 @@ static int coldfire_spi_probe(struct pla
 854         }
 855
 856  #if defined(SPI_DSPI_EDMA)
 857 -       if (request_edma_channel(DSPI_DMA_TX_TCD,
 858 -                                                       edma_tx_handler,
 859 -                                                       NULL,
 860 -                                                       pdev,
 861 -                                                       NULL, /* spinlock */
 862 -                                                       DRIVER_NAME
 863 -                                                       )!=0)
 864 -       {
 865 +       if (mcf_edma_request_channel(DSPI_DMA_TX_TCD,
 866 +                                    edma_tx_handler,
 867 +                                    NULL,
 868 +                                    pdev,
 869 +                                    NULL, /* spinlock */
 870 +                                    DRIVER_NAME
 871 +                                    )!=0) {
 872                 dev_err(&pdev->dev, "problem requesting edma transmit channel\n");
 873                 status = -EINVAL;
 874 -        goto out_error_queue_alloc;
 875 +               goto out_error_queue_alloc;
 876         }
 877
 878 -       if (request_edma_channel(DSPI_DMA_RX_TCD,
 879 -                                                       edma_rx_handler,
 880 -                                                       NULL,
 881 -                                                       pdev,
 882 -                                                       NULL, /* spinlock */
 883 -                                                       DRIVER_NAME
 884 -                                                       )!=0)
 885 -       {
 886 +       if (mcf_edma_request_channel(DSPI_DMA_RX_TCD,
 887 +                                    edma_rx_handler,
 888 +                                    NULL,
 889 +                                    pdev,
 890 +                                    NULL, /* spinlock */
 891 +                                    DRIVER_NAME
 892 +                                    )!=0) {
 893                 dev_err(&pdev->dev, "problem requesting edma receive channel\n");
 894                 status = -EINVAL;
 895 -        goto out_edma_transmit;
 896 +               goto out_edma_transmit;
 897         }
 898  #endif
 899
 900 -       printk( "SPI: Coldfire master initialized\n" );
 901 -       //dev_info(&pdev->dev, "driver initialized\n");
 902 +       printk(KERN_INFO "SPI: Coldfire master initialized\n" );
 903         return status;
 904
 905  #if defined(SPI_DSPI_EDMA)
 906  out_edma_transmit:
 907 -       free_edma_channel(DSPI_DMA_TX_TCD, pdev);
 908 +       mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev);
 909  #endif
 910
 911  out_error_queue_alloc:
 912 @@ -1417,8 +1431,8 @@ static int coldfire_spi_remove(struct pl
 913                 return 0;
 914
 915  #if defined(SPI_DSPI_EDMA)
 916 -       free_edma_channel(DSPI_DMA_TX_TCD, pdev);
 917 -       free_edma_channel(DSPI_DMA_RX_TCD, pdev);
 918 +       mcf_edma_free_channel(DSPI_DMA_TX_TCD, pdev);
 919 +       mcf_edma_free_channel(DSPI_DMA_RX_TCD, pdev);
 920  #endif
 921
 922         /* Remove the queue */
 923 @@ -1426,27 +1440,8 @@ static int coldfire_spi_remove(struct pl
 924         if (status != 0)
 925                 return status;
 926
 927 -       /* Disable the SSP at the peripheral and SOC level */
 928 -       /*write_SSCR0(0, drv_data->ioaddr);
 929 -       pxa_set_cken(drv_data->master_info->clock_enable, 0);*/
 930 -
 931 -       /* Release DMA */
 932 -       /*if (drv_data->master_info->enable_dma) {
 933 -               if (drv_data->ioaddr == SSP1_VIRT) {
 934 -                       DRCMRRXSSDR = 0;
 935 -                       DRCMRTXSSDR = 0;
 936 -               } else if (drv_data->ioaddr == SSP2_VIRT) {
 937 -                       DRCMRRXSS2DR = 0;
 938 -                       DRCMRTXSS2DR = 0;
 939 -               } else if (drv_data->ioaddr == SSP3_VIRT) {
 940 -                       DRCMRRXSS3DR = 0;
 941 -                       DRCMRTXSS3DR = 0;
 942 -               }
 943 -               pxa_free_dma(drv_data->tx_channel);
 944 -               pxa_free_dma(drv_data->rx_channel);
 945 -       }*/
 946 -
 947         /* Release IRQ */
 948 +/* JKM -- check for list and remove list */
 949         irq = platform_get_irq(pdev, 0);
 950         if (irq >= 0)
 951                 free_irq(irq, drv_data);
 952 @@ -1496,8 +1491,6 @@ static int coldfire_spi_suspend(struct p
 953         status = stop_queue(drv_data);
 954         if (status != 0)
 955                 return status;
 956 -       /*write_SSCR0(0, drv_data->ioaddr);
 957 -       pxa_set_cken(drv_data->master_info->clock_enable, 0);*/
 958
 959         return 0;
 960  }
 961 @@ -1507,9 +1500,6 @@ static int coldfire_spi_resume(struct pl
 962         struct driver_data *drv_data = platform_get_drvdata(pdev);
 963         int status = 0;
 964
 965 -       /* Enable the SSP clock */
 966 -       /*pxa_set_cken(drv_data->master_info->clock_enable, 1);*/
 967 -
 968         /* Start the queue running */
 969         status = start_queue(drv_data);
 970         if (status != 0) {
 971 --- /dev/null
 972 +++ b/include/asm-m68k/m5485dspi.h
 973 @@ -0,0 +1,144 @@
 974 +/*
 975 + * File:       mcf548x_dspi.h
 976 + * Purpose:    Register and bit definitions for the MCF548X
 977 + *
 978 + * Notes:
 979 + *
 980 + */
 981 +
 982 +#ifndef _M5485DSPI_H_
 983 +#define _M5485DSPI_H_
 984 +
 985 +/*
 986 + *
 987 + * DMA Serial Peripheral Interface (DSPI)
 988 + *
 989 + */
 990 +
 991 +/* Register read/write macros */
 992 +#define MCF_DSPI_DMCR         MCF_REG32(0x008A00)
 993 +#define MCF_DSPI_DTCR         MCF_REG32(0x008A08)
 994 +#define MCF_DSPI_DCTAR0       MCF_REG32(0x008A0C)
 995 +#define MCF_DSPI_DCTAR1       MCF_REG32(0x008A10)
 996 +#define MCF_DSPI_DCTAR2       MCF_REG32(0x008A14)
 997 +#define MCF_DSPI_DCTAR3       MCF_REG32(0x008A18)
 998 +#define MCF_DSPI_DCTAR4       MCF_REG32(0x008A1C)
 999 +#define MCF_DSPI_DCTAR5       MCF_REG32(0x008A20)
1000 +#define MCF_DSPI_DCTAR6       MCF_REG32(0x008A24)
1001 +#define MCF_DSPI_DCTAR7       MCF_REG32(0x008A28)
1002 +#define MCF_DSPI_DCTARn(x)    MCF_REG32(0x008A0C+(x*4))
1003 +#define MCF_DSPI_DSR          MCF_REG32(0x008A2C)
1004 +#define MCF_DSPI_DRSER        MCF_REG32(0x008A30)
1005 +#define MCF_DSPI_DTFR         MCF_REG32(0x008A34)
1006 +#define MCF_DSPI_DRFR         MCF_REG32(0x008A38)
1007 +#define MCF_DSPI_DTFDR0       MCF_REG32(0x008A3C)
1008 +#define MCF_DSPI_DTFDR1       MCF_REG32(0x008A40)
1009 +#define MCF_DSPI_DTFDR2       MCF_REG32(0x008A44)
1010 +#define MCF_DSPI_DTFDR3       MCF_REG32(0x008A48)
1011 +#define MCF_DSPI_DTFDRn(x)    MCF_REG32(0x008A3C+(x*4))
1012 +#define MCF_DSPI_DRFDR0       MCF_REG32(0x008A7C)
1013 +#define MCF_DSPI_DRFDR1       MCF_REG32(0x008A80)
1014 +#define MCF_DSPI_DRFDR2       MCF_REG32(0x008A84)
1015 +#define MCF_DSPI_DRFDR3       MCF_REG32(0x008A88)
1016 +#define MCF_DSPI_DRFDRn(x)    MCF_REG32(0x008A7C+(x*4))
1017 +
1018 +/* Bit definitions and macros for MCF_DSPI_DMCR */
1019 +#define MCF_DSPI_DMCR_HALT             (0x00000001)
1020 +#define MCF_DSPI_DMCR_SMPL_PT(x)       (((x)&0x00000003)<<8)
1021 +#define MCF_DSPI_DMCR_CRXF             (0x00000400)
1022 +#define MCF_DSPI_DMCR_CTXF             (0x00000800)
1023 +#define MCF_DSPI_DMCR_DRXF             (0x00001000)
1024 +#define MCF_DSPI_DMCR_DTXF             (0x00002000)
1025 +#define MCF_DSPI_DMCR_CSIS0            (0x00010000)
1026 +#define MCF_DSPI_DMCR_CSIS2            (0x00040000)
1027 +#define MCF_DSPI_DMCR_CSIS3            (0x00080000)
1028 +#define MCF_DSPI_DMCR_CSIS5            (0x00200000)
1029 +#define MCF_DSPI_DMCR_ROOE             (0x01000000)
1030 +#define MCF_DSPI_DMCR_PCSSE            (0x02000000)
1031 +#define MCF_DSPI_DMCR_MTFE             (0x04000000)
1032 +#define MCF_DSPI_DMCR_FRZ              (0x08000000)
1033 +#define MCF_DSPI_DMCR_DCONF(x)         (((x)&0x00000003)<<28)
1034 +#define MCF_DSPI_DMCR_CSCK             (0x40000000)
1035 +#define MCF_DSPI_DMCR_MSTR             (0x80000000)
1036 +
1037 +/* Bit definitions and macros for MCF_DSPI_DTCR */
1038 +#define MCF_DSPI_DTCR_SPI_TCNT(x)      (((x)&0x0000FFFF)<<16)
1039 +
1040 +/* Bit definitions and macros for MCF_DSPI_DCTARn */
1041 +#define MCF_DSPI_DCTAR_BR(x)          (((x)&0x0000000F)<<0)
1042 +#define MCF_DSPI_DCTAR_DT(x)          (((x)&0x0000000F)<<4)
1043 +#define MCF_DSPI_DCTAR_ASC(x)         (((x)&0x0000000F)<<8)
1044 +#define MCF_DSPI_DCTAR_CSSCK(x)       (((x)&0x0000000F)<<12)
1045 +#define MCF_DSPI_DCTAR_PBR(x)         (((x)&0x00000003)<<16)
1046 +#define MCF_DSPI_DCTAR_PDT(x)         (((x)&0x00000003)<<18)
1047 +#define MCF_DSPI_DCTAR_PASC(x)        (((x)&0x00000003)<<20)
1048 +#define MCF_DSPI_DCTAR_PCSSCK(x)      (((x)&0x00000003)<<22)
1049 +#define MCF_DSPI_DCTAR_LSBFE          (0x01000000)
1050 +#define MCF_DSPI_DCTAR_CPHA           (0x02000000)
1051 +#define MCF_DSPI_DCTAR_CPOL           (0x04000000)
1052 +/* #define MCF_DSPI_DCTAR_TRSZ(x)        (((x)&0x0000000F)<<27) */
1053 +#define MCF_DSPI_DCTAR_FMSZ(x)        (((x)&0x0000000F)<<27)
1054 +#define MCF_DSPI_DCTAR_PCSSCK_1CLK    (0x00000000)
1055 +#define MCF_DSPI_DCTAR_PCSSCK_3CLK    (0x00400000)
1056 +#define MCF_DSPI_DCTAR_PCSSCK_5CLK    (0x00800000)
1057 +#define MCF_DSPI_DCTAR_PCSSCK_7CLK    (0x00A00000)
1058 +#define MCF_DSPI_DCTAR_PASC_1CLK      (0x00000000)
1059 +#define MCF_DSPI_DCTAR_PASC_3CLK      (0x00100000)
1060 +#define MCF_DSPI_DCTAR_PASC_5CLK      (0x00200000)
1061 +#define MCF_DSPI_DCTAR_PASC_7CLK      (0x00300000)
1062 +#define MCF_DSPI_DCTAR_PDT_1CLK       (0x00000000)
1063 +#define MCF_DSPI_DCTAR_PDT_3CLK       (0x00040000)
1064 +#define MCF_DSPI_DCTAR_PDT_5CLK       (0x00080000)
1065 +#define MCF_DSPI_DCTAR_PDT_7CLK       (0x000A0000)
1066 +#define MCF_DSPI_DCTAR_PBR_1CLK       (0x00000000)
1067 +#define MCF_DSPI_DCTAR_PBR_3CLK       (0x00010000)
1068 +#define MCF_DSPI_DCTAR_PBR_5CLK       (0x00020000)
1069 +#define MCF_DSPI_DCTAR_PBR_7CLK       (0x00030000)
1070 +
1071 +/* Bit definitions and macros for MCF_DSPI_DSR */
1072 +#define MCF_DSPI_DSR_RXPTR(x)          (((x)&0x0000000F)<<0)
1073 +#define MCF_DSPI_DSR_RXCTR(x)          (((x)&0x0000000F)<<4)
1074 +#define MCF_DSPI_DSR_TXPTR(x)          (((x)&0x0000000F)<<8)
1075 +#define MCF_DSPI_DSR_TXCTR(x)          (((x)&0x0000000F)<<12)
1076 +#define MCF_DSPI_DSR_RFDF              (0x00020000)
1077 +#define MCF_DSPI_DSR_RFOF              (0x00080000)
1078 +#define MCF_DSPI_DSR_TFFF              (0x02000000)
1079 +#define MCF_DSPI_DSR_TFUF              (0x08000000)
1080 +#define MCF_DSPI_DSR_EOQF              (0x10000000)
1081 +#define MCF_DSPI_DSR_TXRXS             (0x40000000)
1082 +#define MCF_DSPI_DSR_TCF               (0x80000000)
1083 +
1084 +/* Bit definitions and macros for MCF_DSPI_DRSER */
1085 +#define MCF_DSPI_DRSER_RFDFS           (0x00010000)
1086 +#define MCF_DSPI_DRSER_RFDFE           (0x00020000)
1087 +#define MCF_DSPI_DRSER_RFOFE           (0x00080000)
1088 +#define MCF_DSPI_DRSER_TFFFS           (0x01000000)
1089 +#define MCF_DSPI_DRSER_TFFFE           (0x02000000)
1090 +#define MCF_DSPI_DRSER_TFUFE           (0x08000000)
1091 +#define MCF_DSPI_DRSER_EOQFE           (0x10000000)
1092 +#define MCF_DSPI_DRSER_TCFE            (0x80000000)
1093 +
1094 +/* Bit definitions and macros for MCF_DSPI_DTFR */
1095 +#define MCF_DSPI_DTFR_TXDATA(x)        (((x)&0x0000FFFF)<<0)
1096 +#define MCF_DSPI_DTFR_CS0              (0x00010000)
1097 +#define MCF_DSPI_DTFR_CS2              (0x00040000)
1098 +#define MCF_DSPI_DTFR_CS3              (0x00080000)
1099 +#define MCF_DSPI_DTFR_CS5              (0x00200000)
1100 +#define MCF_DSPI_DTFR_CTCNT            (0x04000000)
1101 +#define MCF_DSPI_DTFR_EOQ              (0x08000000)
1102 +#define MCF_DSPI_DTFR_CTAS(x)          (((x)&0x00000007)<<28)
1103 +#define MCF_DSPI_DTFR_CONT             (0x80000000)
1104 +
1105 +/* Bit definitions and macros for MCF_DSPI_DRFR */
1106 +#define MCF_DSPI_DRFR_RXDATA(x)        (((x)&0x0000FFFF)<<0)
1107 +
1108 +/* Bit definitions and macros for MCF_DSPI_DTFDRn */
1109 +#define MCF_DSPI_DTFDRn_TXDATA(x)      (((x)&0x0000FFFF)<<0)
1110 +#define MCF_DSPI_DTFDRn_TXCMD(x)       (((x)&0x0000FFFF)<<16)
1111 +
1112 +/* Bit definitions and macros for MCF_DSPI_DRFDRn */
1113 +#define MCF_DSPI_DRFDRn_RXDATA(x)      (((x)&0x0000FFFF)<<0)
1114 +
1115 +/********************************************************************/
1116 +
1117 +#endif /* _M5485DSPI_H_ */
1118 --- a/include/asm-m68k/mcfqspi.h
1119 +++ b/include/asm-m68k/mcfqspi.h
1120 @@ -36,6 +36,7 @@ struct coldfire_spi_master {
1121         u32 irq_mask;
1122         u8  irq_lp;
1123         u8  par_val;
1124 +       u32 *irq_list;
1125         void (*cs_control)(u8 cs, u8 command);
1126  };
1127
1128 --- a/include/asm-m68k/mcfsim.h
1129 +++ b/include/asm-m68k/mcfsim.h
1130 @@ -25,6 +25,7 @@
1131  #include <asm/mcf5445x_dtim.h>
1132  #elif defined(CONFIG_M547X_8X)
1133  #include <asm/m5485sim.h>
1134 +#include <asm/m5485gpio.h>
1135  #endif
1136
1137  /*