1 From c1de95e3a608c48b5576e32181480930d9106ac4 Mon Sep 17 00:00:00 2001
2 From: Alison Wang <b18965@freescale.com>
3 Date: Thu, 4 Aug 2011 09:59:44 +0800
4 Subject: [PATCH 18/52] Add SSD1289 TFT LCD framebuffer driver on TWR-MCF5441X
6 Add SSD1289 TFT LCD framebuffer driver on TWR-MCF5441X. Flexbus and spi
7 interfaces are both supported.
9 Signed-off-by: Alison Wang <b18965@freescale.com>
11 arch/m68k/coldfire/m5441x/config.c | 1 +
12 arch/m68k/coldfire/m5441x/devices.c | 1 +
13 arch/m68k/include/asm/fsl-ssd1289-fb.h | 93 ++++
14 drivers/video/Kconfig | 24 +
15 drivers/video/Makefile | 1 +
16 drivers/video/fsl-ssd1289-fb.c | 791 ++++++++++++++++++++++++++++++++
17 6 files changed, 911 insertions(+), 0 deletions(-)
18 create mode 100644 arch/m68k/include/asm/fsl-ssd1289-fb.h
19 create mode 100644 drivers/video/fsl-ssd1289-fb.c
21 --- a/arch/m68k/coldfire/m5441x/config.c
22 +++ b/arch/m68k/coldfire/m5441x/config.c
24 #include <asm/mcf5441x_fbcs.h>
25 #include <asm/mcf5441x_dtim.h>
26 #include <asm/mcf5441x_xbs.h>
27 +#include <asm/fsl-ssd1289-fb.h>
29 extern int get_irq_list(struct seq_file *p, void *v);
30 extern char _text, _end;
31 --- a/arch/m68k/coldfire/m5441x/devices.c
32 +++ b/arch/m68k/coldfire/m5441x/devices.c
34 #include <asm/mcfqspi.h>
35 #include <asm/mcfdspi.h>
36 #include <asm/cf_io.h>
37 +#include <asm/fsl-ssd1289-fb.h>
40 * I2C: only support i2c0 module on m5441x platform
42 +++ b/arch/m68k/include/asm/fsl-ssd1289-fb.h
45 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
47 + * Freescale MCF54418 SSD1289 TFT LCD framebuffer driver
49 + * This program is free software; you can redistribute it and/or modify it
50 + * under the terms of the GNU General Public License as published by the
51 + * Free Software Foundation; either version 2 of the License, or (at your
52 + * option) any later version.
55 +#ifndef __FSL_SSD1289_FB_H__
56 +#define __FSL_SSD1289_FB_H__
58 +#define SSD1289_REG_OSCILLATION 0x00
59 +#define SSD1289_REG_DRIVER_OUT_CTRL 0x01
60 +#define SSD1289_REG_LCD_DRIVE_AC 0x02
61 +#define SSD1289_REG_POWER_CTRL_1 0x03
62 +#define SSD1289_REG_COMPARE_1 0x05
63 +#define SSD1289_REG_COMPARE_2 0x06
64 +#define SSD1289_REG_DISPLAY_CTRL 0x07
65 +#define SSD1289_REG_FRAME_CYCLE 0x0b
66 +#define SSD1289_REG_POWER_CTRL_2 0x0c
67 +#define SSD1289_REG_POWER_CTRL_3 0x0d
68 +#define SSD1289_REG_POWER_CTRL_4 0x0e
69 +#define SSD1289_REG_GATE_SCAN_START 0x0f
70 +#define SSD1289_REG_SLEEP_MODE 0x10
71 +#define SSD1289_REG_ENTRY_MODE 0x11
72 +#define SSD1289_REG_OPT_SPEED_3 0x12
73 +#define SSD1289_REG_H_PORCH 0x16
74 +#define SSD1289_REG_V_PORCH 0x17
75 +#define SSD1289_REG_POWER_CTRL_5 0x1e
76 +#define SSD1289_REG_GDDRAM_DATA 0x22
77 +#define SSD1289_REG_WR_DATA_MASK_1 0x23
78 +#define SSD1289_REG_WR_DATA_MASK_2 0x24
79 +#define SSD1289_REG_FRAME_FREQUENCY 0x25
80 +#define SSD1289_REG_OPT_SPEED_1 0x28
81 +#define SSD1289_REG_OPT_SPEED_2 0x2f
82 +#define SSD1289_REG_GAMMA_CTRL_1 0x30
83 +#define SSD1289_REG_GAMMA_CTRL_2 0x31
84 +#define SSD1289_REG_GAMMA_CTRL_3 0x32
85 +#define SSD1289_REG_GAMMA_CTRL_4 0x33
86 +#define SSD1289_REG_GAMMA_CTRL_5 0x34
87 +#define SSD1289_REG_GAMMA_CTRL_6 0x35
88 +#define SSD1289_REG_GAMMA_CTRL_7 0x36
89 +#define SSD1289_REG_GAMMA_CTRL_8 0x37
90 +#define SSD1289_REG_GAMMA_CTRL_9 0x3a
91 +#define SSD1289_REG_GAMMA_CTRL_10 0x3b
92 +#define SSD1289_REG_V_SCROLL_CTRL_1 0x41
93 +#define SSD1289_REG_V_SCROLL_CTRL_2 0x42
94 +#define SSD1289_REG_H_RAM_ADR_POS 0x44
95 +#define SSD1289_REG_V_RAM_ADR_START 0x45
96 +#define SSD1289_REG_V_RAM_ADR_END 0x46
97 +#define SSD1289_REG_FIRST_WIN_START 0x48
98 +#define SSD1289_REG_FIRST_WIN_END 0x49
99 +#define SSD1289_REG_SECND_WIN_START 0x4a
100 +#define SSD1289_REG_SECND_WIN_END 0x4b
101 +#define SSD1289_REG_GDDRAM_X_ADDR 0x4e
102 +#define SSD1289_REG_GDDRAM_Y_ADDR 0x4f
106 + void __iomem *data;
109 +struct fsl_ssd1289_fb_info {
110 + struct device *dev;
111 + struct ssd1289 ssd1289_reg;
113 + struct spi_device *spidev;
115 + struct task_struct *task;
116 + unsigned long pseudo_palette[16];
119 +/* LCD description */
120 +struct fsl_ssd1289_fb_display {
122 + unsigned short width;
123 + unsigned short height;
126 + unsigned short xres;
127 + unsigned short yres;
128 + unsigned short bpp;
131 +#define FLEXBUS_LCD_CMD_ADDRESS 0xc0000000
132 +#define FLEXBUS_LCD_DATA_ADDRESS 0xc0010000
134 +#define SPI_LCD_BLOCK_SIZE 4096
135 +#define SPI_LCD_BLOCK_HALF_SIZE 2048
137 --- a/drivers/video/Kconfig
138 +++ b/drivers/video/Kconfig
139 @@ -1980,6 +1980,30 @@ config FB_FSL_DIU
141 Framebuffer driver for the Freescale SoC DIU
143 +config FB_FSL_SSD1289
144 + tristate "SSD1289 TFT LCD (Freescale MCF54418)"
145 + depends on FB && M5441X
146 + select FB_CFB_FILLRECT
147 + select FB_CFB_COPYAREA
148 + select FB_CFB_IMAGEBLIT
151 + This is the framebuffer device driver for a Solomon Systech 240RGBx320
155 + prompt "SSD1289 LCD Controller Interface mode"
156 + depends on FB_FSL_SSD1289
158 +config SSD1289_FLEXBUS_MODE
159 + bool "SSD1289 LCD Controller Flexbus Interface mode"
161 +config SSD1289_SPI_MODE
162 + bool "SSD1289 LCD Controller SPI Interface mode"
163 + depends on SPI_DSPI && DSPI0
168 tristate "W100 frame buffer support"
169 depends on FB && ARCH_PXA
170 --- a/drivers/video/Makefile
171 +++ b/drivers/video/Makefile
172 @@ -120,6 +120,7 @@ obj-$(CONFIG_FB_IMX) += imx
173 obj-$(CONFIG_FB_S3C) += s3c-fb.o
174 obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
175 obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o
176 +obj-$(CONFIG_FB_FSL_SSD1289) += fsl-ssd1289-fb.o
177 obj-$(CONFIG_FB_COBALT) += cobalt_lcdfb.o
178 obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/
179 obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/
181 +++ b/drivers/video/fsl-ssd1289-fb.c
184 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
186 + * Freescale MCF54418 SSD1289 TFT LCD framebuffer driver
188 + * Author: Alison Wang <b18965@freescale.com>
189 + * Jason Jin <Jason.jin@freescale.com>
191 + * This program is free software; you can redistribute it and/or modify it
192 + * under the terms of the GNU General Public License as published by the
193 + * Free Software Foundation; either version 2 of the License, or (at your
194 + * option) any later version.
197 +#include <linux/module.h>
198 +#include <linux/kernel.h>
199 +#include <linux/errno.h>
200 +#include <linux/string.h>
201 +#include <linux/mm.h>
202 +#include <linux/slab.h>
203 +#include <linux/delay.h>
204 +#include <linux/fb.h>
205 +#include <linux/init.h>
206 +#include <linux/interrupt.h>
207 +#include <linux/platform_device.h>
208 +#include <linux/dma-mapping.h>
209 +#include <linux/clk.h>
210 +#include <linux/uaccess.h>
211 +#include <linux/timer.h>
212 +#include <linux/kthread.h>
213 +#include <linux/spi/spi.h>
215 +#include <asm/mcf5441x_fbcs.h>
216 +#include <asm/mcf5441x_dspi.h>
217 +#include <asm/fsl-ssd1289-fb.h>
218 +#include <asm/mcf5441x_gpio.h>
219 +#include <asm/mcf5441x_ccm.h>
220 +#include <asm/mcf_edma.h>
223 +#include <linux/pm.h>
226 +#if defined(CONFIG_SSD1289_SPI_MODE)
227 +unsigned char spi_block_buffer[SPI_LCD_BLOCK_SIZE];
229 +static int ssd1289_spi_writeblock(struct fb_info *info,
230 + unsigned char *daddr, int flag)
232 + struct fsl_ssd1289_fb_info *fbinfo = info->par;
233 + struct spi_device *devtmp;
236 + for (i = 0; i < SPI_LCD_BLOCK_SIZE; i++) {
238 + spi_block_buffer[i] = 0x01;
239 + else if (flag == 1)
240 + spi_block_buffer[i] = *(daddr + (i >> 1));
241 + else if (flag == 0)
242 + spi_block_buffer[i] = 0;
245 + devtmp = fbinfo->spidev;
246 + spi_write(devtmp, (const unsigned char *)spi_block_buffer,
247 + SPI_LCD_BLOCK_SIZE);
251 +static int ssd1289_spi_write(struct fb_info *info,
252 + unsigned short value, unsigned int flag)
254 + struct fsl_ssd1289_fb_info *fbinfo = info->par;
255 + struct spi_device *devtmp;
256 + unsigned short tmpl;
257 + unsigned short tmph;
259 + devtmp = fbinfo->spidev;
262 + tmph = ((value >> 8) & 0xff) + 0x0100;
263 + tmpl = (value & 0xff) + 0x0100;
264 + spi_write(devtmp, (const u8 *)&tmph, sizeof(tmph));
265 + spi_write(devtmp, (const u8 *)&tmpl, sizeof(tmpl));
268 + tmpl = (value & 0xff);
269 + spi_write(devtmp, (const u8 *)&tmpl, sizeof(tmpl));
273 +#elif defined(CONFIG_SSD1289_FLEXBUS_MODE)
274 +static int ssd1289_flexbus_write(struct fb_info *info, unsigned short value,
277 + struct fsl_ssd1289_fb_info *fbinfo = info->par;
278 + void __iomem *cmd_addr, *data_addr;
280 + cmd_addr = fbinfo->ssd1289_reg.cmd;
281 + data_addr = fbinfo->ssd1289_reg.data;
284 + out_be16(cmd_addr, value);
286 + out_be16(data_addr, value);
292 +static int ssd1289_write(struct fb_info *info, unsigned short value,
295 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
296 + ssd1289_flexbus_write(info, value, flag);
297 +#elif defined(CONFIG_SSD1289_SPI_MODE)
298 + ssd1289_spi_write(info, value, flag);
303 +static void fsl_ssd1289_enable_lcd(struct fb_info *info)
307 +#if defined(CONFIG_SSD1289_SPI_MODE)
309 +#elif defined(CONFIG_SSD1289_FLEXBUS_MODE)
310 + /* GPIO configuration */
311 + MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_BE3_FB_A1 | MCF_GPIO_PAR_BE_BE2_FB_A0
312 + | MCF_GPIO_PAR_BE_BE1_BE1 | MCF_GPIO_PAR_BE_BE0_BE0;
313 + MCF_GPIO_PAR_CS |= MCF_GPIO_PAR_CS_CS0_CS0;
316 + ssd1289_write(info, SSD1289_REG_DISPLAY_CTRL, 0);
317 + ssd1289_write(info, 0x0200, 1);
319 + ssd1289_write(info, SSD1289_REG_OSCILLATION, 0);
320 + ssd1289_write(info, 0x0000, 1);
324 + /* turn on the oscillator */
325 + ssd1289_write(info, SSD1289_REG_OSCILLATION, 0);
326 + ssd1289_write(info, 0x0001, 1);
329 + /* power control 1 */
330 + ssd1289_write(info, SSD1289_REG_POWER_CTRL_1, 0);
331 + ssd1289_write(info, 0xaeac, 1);
333 + /* power control 2 */
334 + ssd1289_write(info, SSD1289_REG_POWER_CTRL_2, 0);
335 + ssd1289_write(info, 0x0007, 1);
337 + /* power control 3 */
338 + ssd1289_write(info, SSD1289_REG_POWER_CTRL_3, 0);
339 + ssd1289_write(info, 0x000f, 1);
341 + /* power control 4 */
342 + ssd1289_write(info, SSD1289_REG_POWER_CTRL_4, 0);
343 + ssd1289_write(info, 0x2900, 1);
345 + /* power control 5 */
346 + ssd1289_write(info, SSD1289_REG_POWER_CTRL_5, 0);
347 + ssd1289_write(info, 0x00b3, 1);
350 + /* driver output control */
351 + ssd1289_write(info, SSD1289_REG_DRIVER_OUT_CTRL, 0);
352 + ssd1289_write(info, 0x2b3f, 1);
354 + /* lcd-driving-waveform control */
355 + ssd1289_write(info, SSD1289_REG_LCD_DRIVE_AC, 0);
356 + ssd1289_write(info, 0x0600, 1);
359 + ssd1289_write(info, SSD1289_REG_SLEEP_MODE, 0);
360 + ssd1289_write(info, 0x0000, 1);
363 + ssd1289_write(info, SSD1289_REG_ENTRY_MODE, 0);
364 + ssd1289_write(info, 0x60a8, 1);
367 + /* compare register */
368 + ssd1289_write(info, SSD1289_REG_COMPARE_1, 0);
369 + ssd1289_write(info, 0x0000, 1);
371 + ssd1289_write(info, SSD1289_REG_COMPARE_2, 0);
372 + ssd1289_write(info, 0x0000, 1);
374 + /* horizontal porch */
375 + ssd1289_write(info, SSD1289_REG_H_PORCH, 0);
376 + ssd1289_write(info, 0xef1c, 1);
378 + /* vertical porch */
379 + ssd1289_write(info, SSD1289_REG_V_PORCH, 0);
380 + ssd1289_write(info, 0x0003, 1);
382 + /* display control */
383 + ssd1289_write(info, SSD1289_REG_DISPLAY_CTRL, 0);
384 + ssd1289_write(info, 0x0233, 1);
386 + /* frame cycle control */
387 + ssd1289_write(info, SSD1289_REG_FRAME_CYCLE, 0);
388 + ssd1289_write(info, 0x5312, 1);
390 + /* gate scan position */
391 + ssd1289_write(info, SSD1289_REG_GATE_SCAN_START, 0);
392 + ssd1289_write(info, 0x0000, 1);
395 + /* vertical scroll control */
396 + ssd1289_write(info, SSD1289_REG_V_SCROLL_CTRL_1, 0);
397 + ssd1289_write(info, 0x0000, 1);
399 + ssd1289_write(info, SSD1289_REG_V_SCROLL_CTRL_2, 0);
400 + ssd1289_write(info, 0x0000, 1);
402 + /* 1st screen driving position */
403 + ssd1289_write(info, SSD1289_REG_FIRST_WIN_START, 0);
404 + ssd1289_write(info, 0x0000, 1);
406 + ssd1289_write(info, SSD1289_REG_FIRST_WIN_END, 0);
407 + ssd1289_write(info, 0x013F, 1);
409 + /* 2nd screen driving position */
410 + ssd1289_write(info, SSD1289_REG_SECND_WIN_START, 0);
411 + ssd1289_write(info, 0x0000, 1);
413 + ssd1289_write(info, SSD1289_REG_SECND_WIN_END, 0);
414 + ssd1289_write(info, 0x0000, 1);
417 + /* gamma control */
418 + ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_1, 0);
419 + ssd1289_write(info, 0x0707, 1);
421 + ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_2, 0);
422 + ssd1289_write(info, 0x0704, 1);
424 + ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_3, 0);
425 + ssd1289_write(info, 0x0204, 1);
427 + ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_4, 0);
428 + ssd1289_write(info, 0x0201, 1);
430 + ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_5, 0);
431 + ssd1289_write(info, 0x0203, 1);
433 + ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_6, 0);
434 + ssd1289_write(info, 0x0204, 1);
436 + ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_7, 0);
437 + ssd1289_write(info, 0x0204, 1);
439 + ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_8, 0);
440 + ssd1289_write(info, 0x0502, 1);
442 + ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_9, 0);
443 + ssd1289_write(info, 0x0302, 1);
445 + ssd1289_write(info, SSD1289_REG_GAMMA_CTRL_10, 0);
446 + ssd1289_write(info, 0x0500, 1);
448 + /* ram write data mask */
449 + ssd1289_write(info, SSD1289_REG_WR_DATA_MASK_1, 0);
450 + ssd1289_write(info, 0x0000, 1);
452 + ssd1289_write(info, SSD1289_REG_WR_DATA_MASK_2, 0);
453 + ssd1289_write(info, 0x0000, 1);
455 + /* frame frequency control */
456 + ssd1289_write(info, SSD1289_REG_FRAME_FREQUENCY, 0);
457 + ssd1289_write(info, 0xe000, 1);
459 + /* optimize data access speed */
460 + ssd1289_write(info, SSD1289_REG_OPT_SPEED_1, 0);
461 + ssd1289_write(info, 0x0006, 1);
463 + ssd1289_write(info, SSD1289_REG_OPT_SPEED_2, 0);
464 + ssd1289_write(info, 0x12ae, 1);
466 + ssd1289_write(info, SSD1289_REG_OPT_SPEED_3, 0);
467 + ssd1289_write(info, 0x6ceb, 1);
469 + /* horizontal ram address position */
470 + ssd1289_write(info, SSD1289_REG_H_RAM_ADR_POS, 0);
471 + ssd1289_write(info, 0xef00, 1);
473 + /* vertical ram address position */
474 + ssd1289_write(info, SSD1289_REG_V_RAM_ADR_START, 0);
475 + ssd1289_write(info, 0x0000, 1);
477 + ssd1289_write(info, SSD1289_REG_V_RAM_ADR_END, 0);
478 + ssd1289_write(info, 0x013f, 1);
482 + /* set start address counter */
483 + ssd1289_write(info, SSD1289_REG_GDDRAM_X_ADDR, 0);
484 + ssd1289_write(info, 0x00ef, 1);
486 + ssd1289_write(info, SSD1289_REG_GDDRAM_Y_ADDR, 0);
487 + ssd1289_write(info, 0x0000, 1);
489 + ssd1289_write(info, SSD1289_REG_GDDRAM_DATA, 0);
491 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
492 + for (i = 0; i < info->screen_size; i += 2)
493 + ssd1289_write(info, 0, 1);
494 +#elif defined(CONFIG_SSD1289_SPI_MODE)
495 + count = info->screen_size / SPI_LCD_BLOCK_HALF_SIZE;
496 + for (i = 0; i < count; i++)
497 + ssd1289_spi_writeblock(info, NULL, 0);
501 +static void fsl_ssd1289_disable_lcd(struct fb_info *info)
503 + ssd1289_write(info, SSD1289_REG_DISPLAY_CTRL, 0);
504 + ssd1289_write(info, 0x0200, 1);
506 + ssd1289_write(info, SSD1289_REG_OSCILLATION, 0);
507 + ssd1289_write(info, 0x0000, 1);
510 +static int ssd1289fbd(void *arg)
512 + struct fb_info *info = arg;
514 + unsigned short *buf_p;
515 + struct fsl_ssd1289_fb_info *fbinfo = info->par;
516 +#if defined(CONFIG_SSD1289_SPI_MODE)
517 + unsigned char *bufspi_p;
521 + while (!kthread_should_stop()) {
522 + set_current_state(TASK_INTERRUPTIBLE);
524 + if (fbinfo->openflag == 1) {
525 + buf_p = (unsigned short *)(info->screen_base);
527 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
528 + for (i = 0; i < info->screen_size; i += 2) {
529 + ssd1289_write(info, *buf_p, 1);
532 +#elif defined(CONFIG_SSD1289_SPI_MODE)
533 + bufspi_p = (unsigned char *)buf_p;
534 + count = info->screen_size / SPI_LCD_BLOCK_HALF_SIZE;
535 + for (i = 0; i < count; i++)
536 + ssd1289_spi_writeblock(info, (bufspi_p +
537 + SPI_LCD_BLOCK_HALF_SIZE * i), 1);
540 + schedule_timeout(HZ/25);
546 +static int fsl_ssd1289_check_var(struct fb_var_screeninfo *var,
547 + struct fb_info *info)
549 + if (var->xres_virtual < var->xres)
550 + var->xres_virtual = var->xres;
551 + if (var->yres_virtual < var->yres)
552 + var->yres_virtual = var->yres;
554 + if (var->xoffset < 0)
557 + if (var->yoffset < 0)
560 + if (var->xoffset + info->var.xres > info->var.xres_virtual)
561 + var->xoffset = info->var.xres_virtual - info->var.xres;
563 + if (var->yoffset + info->var.yres > info->var.yres_virtual)
564 + var->yoffset = info->var.yres_virtual - info->var.yres;
566 + switch (var->bits_per_pixel) {
568 + /* 8 bpp, 332 format */
569 + var->red.length = 3;
570 + var->red.offset = 5;
571 + var->red.msb_right = 0;
573 + var->green.length = 3;
574 + var->green.offset = 2;
575 + var->green.msb_right = 0;
577 + var->blue.length = 2;
578 + var->blue.offset = 0;
579 + var->blue.msb_right = 0;
581 + var->transp.length = 0;
582 + var->transp.offset = 0;
583 + var->transp.msb_right = 0;
586 + /* 16 bpp, 565 format */
587 + var->red.length = 5;
588 + var->red.offset = 11;
589 + var->red.msb_right = 0;
591 + var->green.length = 6;
592 + var->green.offset = 5;
593 + var->green.msb_right = 0;
595 + var->blue.length = 5;
596 + var->blue.offset = 0;
597 + var->blue.msb_right = 0;
599 + var->transp.length = 0;
600 + var->transp.offset = 0;
601 + var->transp.msb_right = 0;
604 + printk(KERN_ERR "Depth not supported: %u BPP\n",
605 + var->bits_per_pixel);
611 +static int fsl_ssd1289_set_par(struct fb_info *info)
613 + struct fb_var_screeninfo *var = &info->var;
615 + switch (var->bits_per_pixel) {
617 + info->fix.visual = FB_VISUAL_TRUECOLOR;
620 + info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
623 + info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
630 +static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
632 + return ((val<<width) + 0x7FFF - val)>>16;
635 +static int fsl_ssd1289_setcolreg(unsigned regno,
636 + unsigned red, unsigned green, unsigned blue,
637 + unsigned transp, struct fb_info *info)
642 + * If greyscale is true, then we convert the RGB value
643 + * to greyscale no matter what visual we are using.
645 + if (info->var.grayscale)
646 + red = green = blue = (19595 * red + 38470 * green +
647 + 7471 * blue) >> 16;
648 + switch (info->fix.visual) {
649 + case FB_VISUAL_TRUECOLOR:
651 + u32 *pal = info->pseudo_palette;
654 + red = CNVT_TOHW(red, info->var.red.length);
655 + green = CNVT_TOHW(green, info->var.green.length);
656 + blue = CNVT_TOHW(blue, info->var.blue.length);
657 + transp = CNVT_TOHW(transp, info->var.transp.length);
659 + value = (red << info->var.red.offset) |
660 + (green << info->var.green.offset) |
661 + (blue << info->var.blue.offset) |
662 + (transp << info->var.transp.offset);
664 + pal[regno] = value;
668 + case FB_VISUAL_STATIC_PSEUDOCOLOR:
669 + case FB_VISUAL_PSEUDOCOLOR:
675 +static int fsl_ssd1289_blank(int blank_mode, struct fb_info *info)
677 + if (blank_mode == FB_BLANK_POWERDOWN)
678 + fsl_ssd1289_disable_lcd(info);
680 + fsl_ssd1289_enable_lcd(info);
685 +static int fsl_ssd1289_open(struct fb_info *info, int user)
687 + struct fsl_ssd1289_fb_info *fbinfo = info->par;
688 + struct task_struct *task;
691 + if (fbinfo->openflag == 0) {
692 + memset(info->screen_base, 0, info->screen_size);
693 + fsl_ssd1289_enable_lcd(info);
695 + task = kthread_run(ssd1289fbd, info, "SSD1289 LCD");
696 + if (IS_ERR(task)) {
697 + ret = PTR_ERR(task);
700 + fbinfo->task = task;
703 + fbinfo->openflag = 1;
707 +static int fsl_ssd1289_release(struct fb_info *info, int user)
709 + struct fsl_ssd1289_fb_info *fbinfo = info->par;
711 + fbinfo->openflag = 0;
712 + if (fbinfo->task) {
713 + struct task_struct *task = fbinfo->task;
714 + fbinfo->task = NULL;
715 + kthread_stop(task);
718 + memset(info->screen_base, 0, info->screen_size);
719 + fsl_ssd1289_disable_lcd(info);
723 +static struct fb_ops fsl_ssd1289_ops = {
724 + .owner = THIS_MODULE,
725 + .fb_check_var = fsl_ssd1289_check_var,
726 + .fb_set_par = fsl_ssd1289_set_par,
727 + .fb_setcolreg = fsl_ssd1289_setcolreg,
728 + .fb_blank = fsl_ssd1289_blank,
729 + .fb_open = fsl_ssd1289_open,
730 + .fb_release = fsl_ssd1289_release,
731 + .fb_copyarea = cfb_copyarea,
732 + .fb_fillrect = cfb_fillrect,
733 + .fb_imageblit = cfb_imageblit,
736 +static int fsl_ssd1289_map_video_memory(struct fb_info *info)
738 + unsigned int map_size = info->fix.smem_len;
740 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
741 + struct fsl_ssd1289_fb_info *fbinfo = info->par;
743 + fbinfo->ssd1289_reg.cmd =
744 + ioremap_nocache(FLEXBUS_LCD_CMD_ADDRESS, 2);
745 + fbinfo->ssd1289_reg.data =
746 + ioremap_nocache(FLEXBUS_LCD_DATA_ADDRESS, 2);
749 + info->screen_base = kmalloc(map_size, GFP_KERNEL);
750 + info->fix.smem_start = virt_to_phys(info->screen_base);
751 + info->screen_size = info->fix.smem_len;
753 + if (info->screen_base)
754 + memset(info->screen_base, 0, map_size);
756 + return info->screen_base ? 0 : -ENOMEM;
759 +static inline void fsl_ssd1289_unmap_video_memory(struct fb_info *info)
761 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
762 + struct fsl_ssd1289_fb_info *fbinfo = info->par;
764 + iounmap(fbinfo->ssd1289_reg.cmd);
765 + iounmap(fbinfo->ssd1289_reg.data);
767 + kfree(info->screen_base);
771 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
772 +static int fsl_ssd1289_probe(struct platform_device *pdev)
773 +#elif defined(CONFIG_SSD1289_SPI_MODE)
774 +static int fsl_ssd1289_probe(struct spi_device *spi)
777 + struct fsl_ssd1289_fb_info *fbinfo;
778 + struct fb_info *info;
779 + struct fsl_ssd1289_fb_display *display;
781 + unsigned long smem_len;
783 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
784 + info = framebuffer_alloc(sizeof(struct fsl_ssd1289_fb_info),
789 + platform_set_drvdata(pdev, info);
791 + fbinfo = info->par;
792 + fbinfo->dev = &pdev->dev;
793 + display = pdev->dev.platform_data;
794 +#elif defined(CONFIG_SSD1289_SPI_MODE)
795 + info = framebuffer_alloc(sizeof(struct fsl_ssd1289_fb_info),
800 + dev_set_drvdata(&spi->dev, info);
802 + fbinfo = info->par;
803 + fbinfo->dev = &spi->dev;
804 + fbinfo->spidev = spi;
805 + display = spi->dev.platform_data;
808 + fbinfo->openflag = 0;
809 + info->fix.type = FB_TYPE_PACKED_PIXELS;
810 + info->fix.type_aux = 0;
811 + info->fix.xpanstep = 0;
812 + info->fix.ypanstep = 0;
813 + info->fix.ywrapstep = 0;
814 + info->fix.accel = FB_ACCEL_NONE;
816 + info->var.nonstd = 0;
817 + info->var.activate = FB_ACTIVATE_NOW;
818 + info->var.accel_flags = 0;
819 + info->var.vmode = FB_VMODE_NONINTERLACED;
821 + info->fbops = &fsl_ssd1289_ops;
822 + info->flags = FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT
823 + | FBINFO_HWACCEL_COPYAREA;
824 + info->pseudo_palette = &fbinfo->pseudo_palette;
826 + /* find maximum required memory size for display */
827 + smem_len = display->xres;
828 + smem_len *= display->yres;
829 + smem_len *= display->bpp;
831 + if (info->fix.smem_len < smem_len)
832 + info->fix.smem_len = smem_len;
834 + /* Intialize video memory */
835 + ret = fsl_ssd1289_map_video_memory(info);
837 + printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
842 + info->var.xres = display->xres;
843 + info->var.yres = display->yres;
844 + info->var.bits_per_pixel = display->bpp;
845 + info->fix.line_length = (info->var.xres * info->var.bits_per_pixel) / 8;
847 + fsl_ssd1289_check_var(&info->var, info);
849 + ret = register_framebuffer(info);
851 + printk(KERN_ERR "Failed to register framebuffer device: %d\n",
853 + goto free_video_memory;
856 + printk(KERN_INFO "fb: SSD1289 TFT LCD Framebuffer Driver\n");
860 + fsl_ssd1289_unmap_video_memory(info);
862 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
863 + platform_set_drvdata(pdev, NULL);
864 +#elif defined(CONFIG_SSD1289_SPI_MODE)
865 + dev_set_drvdata(&spi->dev, NULL);
867 + framebuffer_release(info);
871 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
872 +static int fsl_ssd1289_remove(struct platform_device *pdev)
874 + struct fb_info *info = platform_get_drvdata(pdev);
876 + platform_set_drvdata(pdev, NULL);
877 +#elif defined(CONFIG_SSD1289_SPI_MODE)
878 +static int fsl_ssd1289_remove(struct spi_device *spi)
880 + struct fb_info *info = dev_get_drvdata(&spi->dev);
882 + dev_set_drvdata(&spi->dev, NULL);
884 + unregister_framebuffer(info);
885 + fsl_ssd1289_unmap_video_memory(info);
886 + framebuffer_release(info);
891 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
892 +static int fsl_ssd1289_suspend(struct platform_device *dev, pm_message_t state)
894 + struct fb_info *info = platform_get_drvdata(dev);
895 +#elif defined(CONFIG_SSD1289_SPI_MODE)
896 +static int fsl_ssd1289_suspend(struct spi_device *spi, pm_message_t state)
898 + struct fb_info *info = dev_get_drvdata(&spi->dev);
900 + /* enter into sleep mode */
901 + ssd1289_write(info, SSD1289_REG_SLEEP_MODE, 0);
902 + ssd1289_write(info, 0x0001, 1);
906 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
907 +static int fsl_ssd1289_resume(struct platform_device *dev)
909 + struct fb_info *info = platform_get_drvdata(dev);
910 +#elif defined(CONFIG_SSD1289_SPI_MODE)
911 +static int fsl_ssd1289_resume(struct spi_device *spi)
913 + struct fb_info *info = dev_get_drvdata(&spi->dev);
915 + /* leave sleep mode */
916 + ssd1289_write(info, SSD1289_REG_SLEEP_MODE, 0);
917 + ssd1289_write(info, 0x0000, 1);
921 +#define fsl_ssd1289_suspend NULL
922 +#define fsl_ssd1289_resume NULL
925 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
926 +static struct platform_driver fsl_ssd1289_driver = {
927 + .probe = fsl_ssd1289_probe,
928 + .remove = fsl_ssd1289_remove,
929 + .suspend = fsl_ssd1289_suspend,
930 + .resume = fsl_ssd1289_resume,
932 + .name = "fsl-ssd1289",
933 + .owner = THIS_MODULE,
936 +#elif defined(CONFIG_SSD1289_SPI_MODE)
937 +static struct spi_driver spi_ssd1289_driver = {
939 + .name = "spi-ssd1289",
940 + .bus = &spi_bus_type,
941 + .owner = THIS_MODULE,
943 + .probe = fsl_ssd1289_probe,
944 + .remove = fsl_ssd1289_remove,
945 + .suspend = fsl_ssd1289_suspend,
946 + .resume = fsl_ssd1289_resume,
950 +static int __devinit fsl_ssd1289_init(void)
952 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
953 + return platform_driver_register(&fsl_ssd1289_driver);
954 +#elif defined(CONFIG_SSD1289_SPI_MODE)
955 + return spi_register_driver(&spi_ssd1289_driver);
959 +static void __exit fsl_ssd1289_exit(void)
961 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
962 + return platform_driver_unregister(&fsl_ssd1289_driver);
963 +#elif defined(CONFIG_SSD1289_SPI_MODE)
964 + return spi_unregister_driver(&spi_ssd1289_driver);
968 +module_init(fsl_ssd1289_init);
969 +module_exit(fsl_ssd1289_exit);
971 +MODULE_AUTHOR("Alison Wang <b18965@freescale.com>");
972 +MODULE_DESCRIPTION("Freescale MCF54418 SSD1289 TFT LCD Framebuffer Driver");
973 +MODULE_LICENSE("GPL");