target/linux/coldfire/patches/016-m5445x_usb_initial_port.patch

   1 From 6694c72448723499ce8a8603b4830bbd9d2fa0df Mon Sep 17 00:00:00 2001
   2 From: Bruce Schmid <duck@freescale.com>
   3 Date: Tue, 20 Nov 2007 11:06:14 -0700
   4 Subject: [PATCH] USB: initial port
   5
   6 LTIBName: m5445x-usb-initial-port
   7 Signed-off-by: Duck <duck@freescale.com>
   8 ---
   9  arch/m68k/coldfire/usb.c            |  182 +++
  10  arch/m68k/coldfire/usb/Makefile     |   28 +
  11  arch/m68k/coldfire/usb/otg_cmn.c    |  106 ++
  12  arch/m68k/coldfire/usb/otg_device.c |   89 ++
  13  arch/m68k/coldfire/usb/otg_host.c   |   68 +
  14  arch/m68k/coldfire/usb/otg_otg.c    |   96 ++
  15  arch/m68k/coldfire/usb/xcvr.c       |  156 ++
  16  drivers/usb/Kconfig                 |    1 +
  17  drivers/usb/Makefile                |    2 +
  18  drivers/usb/core/usb.c              |    2 +-
  19  drivers/usb/gadget/Kconfig          |   43 +-
  20  drivers/usb/gadget/Makefile         |    1 +
  21  drivers/usb/gadget/ether.c          |    3 +
  22  drivers/usb/gadget/fsl_usb2_udc.h   |  194 +---
  23  drivers/usb/gadget/gadget_chips.h   |    7 +
  24  drivers/usb/gadget/mcf5445x_udc.c   | 2758 +++++++++++++++++++++++++++++++++++
  25  drivers/usb/host/Kconfig            |   21 +-
  26  drivers/usb/host/ehci-arc.c         |  431 ++++++
  27  drivers/usb/host/ehci-fsl.h         |   28 +-
  28  drivers/usb/host/ehci-hcd.c         |    5 +
  29  drivers/usb/host/ehci-mem.c         |    9 +-
  30  drivers/usb/host/ehci.h             |   22 +
  31  drivers/usb/otg/Makefile            |    5 +
  32  drivers/usb/otg/fsl_otg.c           | 1515 +++++++++++++++++++
  33  drivers/usb/otg/fsl_otg.h           |  139 ++
  34  drivers/usb/otg/otg_fsm.c           |  381 +++++
  35  drivers/usb/otg/otg_fsm.h           |  170 +++
  36  include/asm-m68k/mcf5445x_usb.h     |    3 +-
  37  include/linux/fsl_devices.h         |   42 +-
  38  include/linux/usb/fsl_usb2.h        |  464 ++++++
  39  include/linux/usb/fsl_xcvr.h        |   42 +
  40  31 files changed, 6809 insertions(+), 204 deletions(-)
  41  create mode 100644 arch/m68k/coldfire/usb.c
  42  create mode 100644 arch/m68k/coldfire/usb/Makefile
  43  create mode 100644 arch/m68k/coldfire/usb/otg_cmn.c
  44  create mode 100644 arch/m68k/coldfire/usb/otg_device.c
  45  create mode 100644 arch/m68k/coldfire/usb/otg_host.c
  46  create mode 100644 arch/m68k/coldfire/usb/otg_otg.c
  47  create mode 100644 arch/m68k/coldfire/usb/xcvr.c
  48  create mode 100644 drivers/usb/gadget/mcf5445x_udc.c
  49  create mode 100644 drivers/usb/host/ehci-arc.c
  50  create mode 100644 drivers/usb/otg/Makefile
  51  create mode 100644 drivers/usb/otg/fsl_otg.c
  52  create mode 100644 drivers/usb/otg/fsl_otg.h
  53  create mode 100644 drivers/usb/otg/otg_fsm.c
  54  create mode 100644 drivers/usb/otg/otg_fsm.h
  55  create mode 100644 include/linux/usb/fsl_usb2.h
  56  create mode 100644 include/linux/usb/fsl_xcvr.h
  57
  58 --- /dev/null
  59 +++ b/arch/m68k/coldfire/usb.c
  60 @@ -0,0 +1,182 @@
  61 +/*
  62 + *
  63 + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  64 + *
  65 + *     otg_{get,set}_transceiver() are from arm/plat-omap/usb.c.
  66 + *     which is Copyright (C) 2004 Texas Instruments, Inc.
  67 + */
  68 +
  69 +/*
  70 + * The code contained herein is licensed under the GNU General Public
  71 + * License. You may obtain a copy of the GNU General Public License
  72 + * Version 2 or later at the following locations:
  73 + *
  74 + * http://www.opensource.org/licenses/gpl-license.html
  75 + * http://www.gnu.org/copyleft/gpl.html
  76 + */
  77 +
  78 +#include <linux/module.h>
  79 +#include <linux/kernel.h>
  80 +#include <linux/types.h>
  81 +#include <linux/errno.h>
  82 +#include <linux/init.h>
  83 +#include <linux/io.h>
  84 +#include <linux/err.h>
  85 +#include <linux/platform_device.h>
  86 +#include <linux/usb/otg.h>
  87 +#include <linux/delay.h>
  88 +#include <linux/fsl_devices.h>
  89 +#include <linux/usb/fsl_xcvr.h>
  90 +
  91 +
  92 +/* The dmamask must be set for EHCI to work */
  93 +static u64 ehci_dmamask = ~(u32) 0;
  94 +
  95 +struct fsl_xcvr_ops *xc_ops[3] = { NULL };
  96 +
  97 +void fsl_usb_enable_clk(void)
  98 +{
  99 +}
 100 +EXPORT_SYMBOL(fsl_usb_enable_clk);
 101 +
 102 +void fsl_usb_disable_clk(void)
 103 +{
 104 +}
 105 +EXPORT_SYMBOL(fsl_usb_disable_clk);
 106 +
 107 +void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops)
 108 +{
 109 +       pr_debug("%s ctrlr=%d\n", __FUNCTION__, xcvr_ops->ctrlr);
 110 +       xc_ops[xcvr_ops->ctrlr] = xcvr_ops;
 111 +
 112 +}
 113 +EXPORT_SYMBOL(fsl_usb_xcvr_register);
 114 +
 115 +void fsl_usb_xcvr_unregister(enum fsl_usb_ctrlr ctrlr)
 116 +{
 117 +       pr_debug("%s ctrlr=%d\n", __FUNCTION__, ctrlr);
 118 +       xc_ops[ctrlr] = NULL;
 119 +}
 120 +EXPORT_SYMBOL(fsl_usb_xcvr_unregister);
 121 +
 122 +/*!
 123 + * Register an instance of a USB host platform device.
 124 + *
 125 + * @param      res:    resource pointer
 126 + * @param       n_res: number of resources
 127 + * @param       config: config pointer
 128 + *
 129 + * @return      newly-registered platform_device
 130 + *
 131 + * DDD fix this comment:
 132 + * The USB controller supports 3 host interfaces, and the
 133 + * kernel can be configured to support some number of them.
 134 + * Each supported host interface is registered as an instance
 135 + * of the "fsl-ehci" device.  Call this function multiple times
 136 + * to register each host interface.
 137 + */
 138 +static int instance_id;
 139 +struct platform_device *host_pdev_register(struct resource *res, int n_res,
 140 +                                         struct fsl_usb2_platform_data *config)
 141 +{
 142 +       struct platform_device *pdev;
 143 +
 144 +       pr_debug("register host res=0x%p, size=%d\n", res, n_res);
 145 +
 146 +       pdev = platform_device_register_simple("fsl-ehci",
 147 +                                              instance_id, res, n_res);
 148 +       if (IS_ERR(pdev)) {
 149 +               printk(KERN_ERR "usb: can't register %s Host, %ld\n",
 150 +                      config->name, PTR_ERR(pdev));
 151 +               return NULL;
 152 +       }
 153 +
 154 +       pdev->dev.coherent_dma_mask = 0xffffffff;
 155 +       pdev->dev.dma_mask = &ehci_dmamask;
 156 +
 157 +       /*
 158 +        * platform_device_add_data() makes a copy of
 159 +        * the platform_data passed in.  That makes it
 160 +        * impossible to share the same config struct for
 161 +        * all OTG devices (host,gadget,otg).  So, just
 162 +        * set the platform_data pointer ourselves.
 163 +        */
 164 +       pdev->dev.platform_data = config;
 165 +
 166 +       printk(KERN_INFO "usb: %s Host registered\n", config->name);
 167 +       pr_debug("pdev=0x%p  dev=0x%p  resources=0x%p  pdata=0x%p\n",
 168 +                pdev, &pdev->dev, pdev->resource, pdev->dev.platform_data);
 169 +
 170 +       instance_id++;
 171 +
 172 +       return pdev;
 173 +}
 174 +
 175 +
 176 +int fsl_usb_mem_init(struct platform_device *pdev)
 177 +{
 178 +       struct resource *res;
 179 +       struct fsl_usb2_platform_data *pdata;
 180 +
 181 +       pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
 182 +
 183 +       pr_debug("%s: pdev=0x%p  pdata=0x%p\n", __FUNCTION__, pdev, pdata);
 184 +
 185 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 186 +       if (!res) {
 187 +               dev_err(&pdev->dev, "no MEM resource.\n");
 188 +               return -ENODEV;
 189 +       }
 190 +
 191 +       pdata->r_start = res->start;
 192 +       pdata->r_len = res->end - res->start + 1;
 193 +       pr_debug("%s: MEM resource start=0x%x  len=0x%x\n", pdata->name,
 194 +                res->start, pdata->r_len);
 195 +
 196 +       if (!request_mem_region(pdata->r_start, pdata->r_len, "OTG")) {
 197 +               dev_err(&pdev->dev, "request_mem_region failed\n");
 198 +               return -EBUSY;
 199 +       }
 200 +       pdata->regs = ioremap(pdata->r_start, pdata->r_len);
 201 +       pr_debug("ioremapped to 0x%p\n", pdata->regs);
 202 +
 203 +       if (pdata->regs == NULL) {
 204 +               dev_err(&pdev->dev, "ioremap failed\n");
 205 +               release_mem_region(pdata->r_start, pdata->r_len);
 206 +               return -EFAULT;
 207 +       }
 208 +
 209 +       pr_debug("%s: success\n", __FUNCTION__);
 210 +       return 0;
 211 +}
 212 +
 213 +
 214 +#if defined(CONFIG_USB_OTG)
 215 +static struct otg_transceiver *xceiv;
 216 +
 217 +/**
 218 + * otg_get_transceiver - find the (single) OTG transceiver driver
 219 + *
 220 + * Returns the transceiver driver, after getting a refcount to it; or
 221 + * null if there is no such transceiver.  The caller is responsible for
 222 + * releasing that count.
 223 + */
 224 +struct otg_transceiver *otg_get_transceiver(void)
 225 +{
 226 +       pr_debug("%s xceiv=0x%p\n", __FUNCTION__, xceiv);
 227 +       if (xceiv)
 228 +               get_device(xceiv->dev);
 229 +       return xceiv;
 230 +}
 231 +EXPORT_SYMBOL(otg_get_transceiver);
 232 +
 233 +int otg_set_transceiver(struct otg_transceiver *x)
 234 +{
 235 +       pr_debug("%s xceiv=0x%p  x=0x%p\n", __FUNCTION__, xceiv, x);
 236 +       if (xceiv && x)
 237 +               return -EBUSY;
 238 +       xceiv = x;
 239 +       return 0;
 240 +}
 241 +EXPORT_SYMBOL(otg_set_transceiver);
 242 +#endif
 243 --- /dev/null
 244 +++ b/arch/m68k/coldfire/usb/Makefile
 245 @@ -0,0 +1,28 @@
 246 +#
 247 +# Makefile for the linux kernel.
 248 +#
 249 +
 250 +# Object file lists.
 251 +
 252 +ifneq ($(CONFIG_USB_EHCI_HCD),)
 253 +       obj-y   += otg_host.o
 254 +endif
 255 +
 256 +ifneq ($(CONFIG_USB_GADGET_MCF5445X),)
 257 +       obj-y   += otg_device.o
 258 +endif
 259 +
 260 +ifneq ($(strip $(CONFIG_USB_GADGET_MCF5445X) $(CONFIG_USB_EHCI_HCD)),)
 261 +       obj-y   += otg_cmn.o
 262 +endif
 263 +
 264 +ifneq ($(CONFIG_USB_OTG),)
 265 +       obj-y   += otg_otg.o
 266 +endif
 267 +
 268 +
 269 +# USB Transceiver driver:
 270 +ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_MCF5445X)),)
 271 +       obj-y   += xcvr.o
 272 +endif
 273 +
 274 --- /dev/null
 275 +++ b/arch/m68k/coldfire/usb/otg_cmn.c
 276 @@ -0,0 +1,106 @@
 277 +/*
 278 + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 279 + */
 280 +
 281 +/*
 282 + * The code contained herein is licensed under the GNU General Public
 283 + * License. You may obtain a copy of the GNU General Public License
 284 + * Version 2 or later at the following locations:
 285 + *
 286 + * http://www.opensource.org/licenses/gpl-license.html
 287 + * http://www.gnu.org/copyleft/gpl.html
 288 + */
 289 +
 290 +#include <linux/module.h>
 291 +#include <linux/kernel.h>
 292 +#include <linux/types.h>
 293 +#include <linux/err.h>
 294 +#include <linux/errno.h>
 295 +#include <linux/init.h>
 296 +#include <linux/io.h>
 297 +#include <linux/irq.h>
 298 +#include <linux/platform_device.h>
 299 +#include <linux/delay.h>
 300 +#include <linux/fsl_devices.h>
 301 +#include <linux/usb/fsl_xcvr.h>
 302 +
 303 +#include <asm/system.h>
 304 +#include <asm/coldfire.h>
 305 +
 306 +extern void fsl_usb_enable_clk(void);
 307 +extern void fsl_usb_disable_clk(void);
 308 +extern int fsl_usb_mem_init(struct platform_device *pdev);
 309 +
 310 +extern struct fsl_xcvr_ops *xc_ops[];
 311 +
 312 +static int otg_used;
 313 +
 314 +int usbotg_init(struct platform_device *pdev)
 315 +{
 316 +       struct fsl_usb2_platform_data *pdata;
 317 +       struct fsl_xcvr_ops *xops = xc_ops[USB_CTRLR_OTG];
 318 +       int rc;
 319 +
 320 +       pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
 321 +
 322 +       pr_debug("%s: pdev=0x%p  pdata=0x%p\n", __FUNCTION__, pdev, pdata);
 323 +
 324 +       if (!xops) {
 325 +               printk(KERN_ERR "OTG transceiver ops missing\n");
 326 +               return -EINVAL;
 327 +       }
 328 +       pdata->xcvr_ops = xops;
 329 +       pdata->xcvr_type = xops->xcvr_type;
 330 +
 331 +       if (!otg_used) {
 332 +               /* request_mem_region and ioremap registers */
 333 +               rc = fsl_usb_mem_init(pdev);
 334 +               if (rc)
 335 +                       return rc;
 336 +
 337 +               fsl_usb_enable_clk();
 338 +
 339 +               if (xops->init)
 340 +                       xops->init(pdev);
 341 +       }
 342 +
 343 +       otg_used++;
 344 +       pr_debug("%s: success\n", __FUNCTION__);
 345 +       return 0;
 346 +}
 347 +
 348 +void usbotg_uninit(struct platform_device *pdev)
 349 +{
 350 +       struct fsl_usb2_platform_data *pdata;
 351 +       pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
 352 +
 353 +       pr_debug("%s\n", __FUNCTION__);
 354 +
 355 +       otg_used--;
 356 +       if (!otg_used) {
 357 +               if (pdata->xcvr_ops && pdata->xcvr_ops->uninit)
 358 +                       pdata->xcvr_ops->uninit(pdev);
 359 +
 360 +               iounmap(pdata->regs);
 361 +               release_mem_region(pdata->r_start, pdata->r_len);
 362 +
 363 +               pdata->regs = NULL;
 364 +               pdata->r_start = pdata->r_len = 0;
 365 +
 366 +               fsl_usb_disable_clk();
 367 +       }
 368 +}
 369 +
 370 +struct fsl_usb2_platform_data mxc_otg_config = {
 371 +       .name            = "OTG",
 372 +       .platform_init   = usbotg_init,
 373 +       .platform_uninit = usbotg_uninit,
 374 +       .es              = 1,
 375 +       .big_endian_mmio = 1,
 376 +       .big_endian_desc = 1,
 377 +       .le_setup_buf    = 1,
 378 +       .does_otg        = 1,
 379 +       .power_budget    = 500,         /* 500 mA max power */
 380 +       .max_ep_nr       = 4,           /* DDD read from a register ? */
 381 +       .phy_mode        = FSL_USB2_PHY_ULPI, /* DDD redundant with xcvr_type */
 382 +};
 383 --- /dev/null
 384 +++ b/arch/m68k/coldfire/usb/otg_device.c
 385 @@ -0,0 +1,89 @@
 386 +/*
 387 + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 388 + */
 389 +
 390 +/*
 391 + * The code contained herein is licensed under the GNU General Public
 392 + * License. You may obtain a copy of the GNU General Public License
 393 + * Version 2 or later at the following locations:
 394 + *
 395 + * http://www.opensource.org/licenses/gpl-license.html
 396 + * http://www.gnu.org/copyleft/gpl.html
 397 + */
 398 +
 399 +#include <linux/module.h>
 400 +#include <linux/kernel.h>
 401 +#include <linux/types.h>
 402 +#include <linux/errno.h>
 403 +#include <linux/init.h>
 404 +#include <linux/io.h>
 405 +#include <linux/irq.h>
 406 +#include <linux/err.h>
 407 +#include <linux/platform_device.h>
 408 +#include <linux/usb/otg.h>
 409 +#include <linux/delay.h>
 410 +#include <linux/fsl_devices.h>
 411 +#include <linux/usb/fsl_xcvr.h>
 412 +
 413 +#include <asm/system.h>
 414 +#include <asm/coldfire.h>
 415 +
 416 +#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000)
 417 +#define INT_USB                (64 + 64 + 47)  /* INTC1:47 16.2.9.1 */
 418 +#define INT_UOCSR      (64 + 64 + 53)  /* INTC1:53 16.2.9.1 */
 419 +
 420 +extern int usbotg_init(struct platform_device *pdev);
 421 +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
 422 +extern struct fsl_usb2_platform_data mxc_otg_config;
 423 +
 424 +struct platform_device otg_udc_device;
 425 +
 426 +/*!
 427 + * OTG Gadget device
 428 + */
 429 +
 430 +static void usb_release(struct device *dev)
 431 +{
 432 +       /* normally not freed */
 433 +}
 434 +
 435 +static u64 udc_dmamask = ~(u32) 0;
 436 +static struct resource otg_udc_resources[] = {
 437 +       [0] = {
 438 +               .start = (u32) (&USB_OTGREGS_BASE),
 439 +               .end   = (u32) (&USB_OTGREGS_BASE + 0x1ff),
 440 +               .flags = IORESOURCE_MEM,
 441 +       },
 442 +       [1] = {
 443 +               .start = INT_USB,
 444 +               .flags = IORESOURCE_IRQ,
 445 +       },
 446 +};
 447 +
 448 +
 449 +struct platform_device otg_udc_device = {
 450 +       .name = "fsl-usb2-udc",
 451 +       .id   = -1,
 452 +       .dev  = {
 453 +               .release           = usb_release,
 454 +               .dma_mask          = &udc_dmamask,
 455 +               .coherent_dma_mask = 0xffffffff,
 456 +               .platform_data     = &mxc_otg_config,
 457 +               },
 458 +       .resource = otg_udc_resources,
 459 +       .num_resources = ARRAY_SIZE(otg_udc_resources),
 460 +};
 461 +
 462 +static int __init udc_init(void)
 463 +{
 464 +       int rc __attribute((unused));
 465 +
 466 +       rc = platform_device_register(&otg_udc_device);
 467 +       if (rc)
 468 +               printk(KERN_ERR "usb: can't register OTG Gadget, rc=%d\n", rc);
 469 +       else
 470 +               printk(KERN_INFO "usb: OTG Gadget registered\n");
 471 +       return rc;
 472 +}
 473 +
 474 +subsys_initcall(udc_init);
 475 --- /dev/null
 476 +++ b/arch/m68k/coldfire/usb/otg_host.c
 477 @@ -0,0 +1,68 @@
 478 +/*
 479 + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 480 + */
 481 +
 482 +/*
 483 + * The code contained herein is licensed under the GNU General Public
 484 + * License. You may obtain a copy of the GNU General Public License
 485 + * Version 2 or later at the following locations:
 486 + *
 487 + * http://www.opensource.org/licenses/gpl-license.html
 488 + * http://www.gnu.org/copyleft/gpl.html
 489 + */
 490 +
 491 +#include <linux/module.h>
 492 +#include <linux/kernel.h>
 493 +#include <linux/types.h>
 494 +#include <linux/errno.h>
 495 +#include <linux/init.h>
 496 +#include <linux/io.h>
 497 +#include <linux/irq.h>
 498 +#include <linux/err.h>
 499 +#include <linux/platform_device.h>
 500 +#include <linux/delay.h>
 501 +#include <linux/fsl_devices.h>
 502 +#include <linux/usb/fsl_xcvr.h>
 503 +
 504 +#include <asm/system.h>
 505 +#include <asm/mcfsim.h>
 506 +
 507 +#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000)
 508 +#define INT_USB                (64 + 64 + 47)  /* INTC1:47 16.2.9.1 */
 509 +#define INT_UOCSR      (64 + 64 + 53)  /* INTC1:53 16.2.9.1 */
 510 +
 511 +struct platform_device *otg_host_device;
 512 +
 513 +extern struct platform_device *host_pdev_register(struct resource *res,
 514 +                                                 int n_res,
 515 +                                                 struct fsl_usb2_platform_data
 516 +                                                 *config);
 517 +
 518 +extern int usbotg_init(struct platform_device *pdev);
 519 +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
 520 +extern struct fsl_usb2_platform_data mxc_otg_config;
 521 +
 522 +/*!
 523 + * OTG host config
 524 + */
 525 +static struct resource otg_host_resources[] = {
 526 +       [0] = {
 527 +               .start = (u32) (&USB_OTGREGS_BASE),
 528 +               .end   = (u32) (&USB_OTGREGS_BASE + 0x1ff),
 529 +               .flags = IORESOURCE_MEM,
 530 +       },
 531 +       [1] = {
 532 +               .start = INT_USB,
 533 +               .flags = IORESOURCE_IRQ,
 534 +       },
 535 +};
 536 +
 537 +static int __init otg_host_init(void)
 538 +{
 539 +       otg_host_device = host_pdev_register(otg_host_resources,
 540 +                                            ARRAY_SIZE(otg_host_resources),
 541 +                                            &mxc_otg_config);
 542 +       return 0;
 543 +}
 544 +
 545 +subsys_initcall(otg_host_init);
 546 --- /dev/null
 547 +++ b/arch/m68k/coldfire/usb/otg_otg.c
 548 @@ -0,0 +1,96 @@
 549 +/*
 550 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 551 + */
 552 +
 553 +/*
 554 + * The code contained herein is licensed under the GNU General Public
 555 + * License. You may obtain a copy of the GNU General Public License
 556 + * Version 2 or later at the following locations:
 557 + *
 558 + * http://www.opensource.org/licenses/gpl-license.html
 559 + * http://www.gnu.org/copyleft/gpl.html
 560 + */
 561 +
 562 +/*
 563 + * platform_device registration for ULPI OTG device
 564 + */
 565 +
 566 +#include <linux/module.h>
 567 +#include <linux/kernel.h>
 568 +#include <linux/types.h>
 569 +#include <linux/errno.h>
 570 +#include <linux/init.h>
 571 +#include <linux/err.h>
 572 +#include <linux/platform_device.h>
 573 +#include <linux/fsl_devices.h>
 574 +
 575 +#include <asm/mcfsim.h>
 576 +
 577 +#define USB_OTGREGS_BASE MCF_REG32(0xFC0B0000)
 578 +#define INT_USB                (64 + 64 + 47)  /* INTC1:47 16.2.9.1 */
 579 +#define INT_UOCSR      (64 + 64 + 53)  /* INTC1:53 16.2.9.1 */
 580 +
 581 +extern int usbotg_init(struct platform_device *pdev);
 582 +extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
 583 +extern struct fsl_usb2_platform_data mxc_otg_config;
 584 +
 585 +static void otg_otg_release(struct device *dev)
 586 +{
 587 +       /* normally not freed */
 588 +}
 589 +
 590 +/* *INDENT-OFF* */
 591 +static struct resource otg_otg_resources[] = {
 592 +       [0] = {
 593 +               .start = (u32) (&USB_OTGREGS_BASE),
 594 +               .end   = (u32) (&USB_OTGREGS_BASE + 0x1ff),
 595 +               .flags = IORESOURCE_MEM,
 596 +       },
 597 +       [1] = {
 598 +               .start = INT_USB,
 599 +               .flags = IORESOURCE_IRQ,
 600 +       },
 601 +};
 602 +
 603 +/*!
 604 + * OTG device
 605 + */
 606 +static u64 otg_otg_dmamask = ~(u32) 0;
 607 +static struct platform_device otg_otg_device = {
 608 +       .name = "fsl-usb2-otg",
 609 +       .id   = -1,
 610 +       .dev  = {
 611 +               .release           = otg_otg_release,
 612 +               .dma_mask          = &otg_otg_dmamask,
 613 +               .coherent_dma_mask = 0xffffffff,
 614 +               .platform_data     = &mxc_otg_config,
 615 +       },
 616 +       .resource = otg_otg_resources,
 617 +       .num_resources = ARRAY_SIZE(otg_otg_resources),
 618 +};
 619 +/* *INDENT-ON* */
 620 +
 621 +static int __init mx31_otg_otg_init(void)
 622 +{
 623 +       int rc = 0;
 624 +
 625 +       pr_debug("register OTG otg res=0x%p, size=%d\n",
 626 +                otg_otg_device.resource, otg_otg_device.num_resources);
 627 +
 628 +       rc = platform_device_register(&otg_otg_device);
 629 +       if (rc) {
 630 +               pr_debug("can't register ULPI OTG dvc, %d\n", rc);
 631 +       } else {
 632 +               printk(KERN_INFO "usb: OTG ULPI transceiver registered\n");
 633 +               pr_debug("otg_otg_device=0x%p  resources=0x%p.\n",
 634 +                        &otg_otg_device, otg_otg_device.resource);
 635 +       }
 636 +
 637 +       return rc;
 638 +}
 639 +
 640 +subsys_initcall(mx31_otg_otg_init);
 641 +
 642 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 643 +MODULE_DESCRIPTION("ULPI OTG device registration");
 644 +MODULE_LICENSE("GPL");
 645 --- /dev/null
 646 +++ b/arch/m68k/coldfire/usb/xcvr.c
 647 @@ -0,0 +1,156 @@
 648 +/*
 649 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 650 + */
 651 +
 652 +/*
 653 + * The code contained herein is licensed under the GNU General Public
 654 + * License. You may obtain a copy of the GNU General Public License
 655 + * Version 2 or later at the following locations:
 656 + *
 657 + * http://www.opensource.org/licenses/gpl-license.html
 658 + * http://www.gnu.org/copyleft/gpl.html
 659 + */
 660 +
 661 +#include <linux/module.h>
 662 +#include <linux/kernel.h>
 663 +#include <linux/types.h>
 664 +#include <linux/errno.h>
 665 +#include <linux/init.h>
 666 +#include <linux/err.h>
 667 +#include <linux/platform_device.h>
 668 +#include <linux/delay.h>
 669 +#include <linux/fsl_devices.h>
 670 +#include <linux/usb/fsl_xcvr.h>
 671 +#include <linux/usb/fsl_usb2.h>
 672 +
 673 +#include <asm/mcfsim.h>
 674 +
 675 +extern void fsl_usb_xcvr_register(struct fsl_xcvr_ops *xcvr_ops);
 676 +extern void fsl_usb_xcvr_unregister(enum fsl_usb_ctrlr ctrlr);
 677 +
 678 +#define MCF_SCM_BCR            MCF_REG32(0xFC040024)
 679 +#define MCF_SCM_BCR_GBR                (1 << 9)        /* global bursts for read */
 680 +#define MCF_SCM_BCR_GBW                (1 << 8)        /* global bursts for write */
 681 +#define MCF_SCM_BCR_SBE_ALL    (0xff << 0)     /* slave burst enable */
 682 +
 683 +
 684 +#ifdef ULPI_DEBUG
 685 +void print_ulpi_regs(void)
 686 +{
 687 +       pr_debug("MCF_SCM_BCR=0x%08lx  MCF_CCM_MISCCR=0x%08x  "
 688 +                "MCF_GPIO_PAR_DMA=0x%08x  MCF_GPIO_PAR_USB=08%08x  "
 689 +                "MCF_GPIO_PAR_FEC=08%08x\n",
 690 +                MCF_SCM_BCR, MCF_CCM_MISCCR, MCF_GPIO_PAR_DMA,
 691 +                MCF_GPIO_PAR_USB, MCF_GPIO_PAR_FEC);
 692 +}
 693 +EXPORT_SYMBOL(print_ulpi_regs);
 694 +#endif
 695 +
 696 +
 697 +static void xcvr_init(struct platform_device *pdev)
 698 +{
 699 +       struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
 700 +       struct fsl_xcvr_ops *this = pdata->xcvr_ops;
 701 +       struct fsl_usb_host_regs *regs = pdata->regs;
 702 +
 703 +       pr_debug("%s: ctrlr=%d  pdata=0x%p  regs=0x%p\n", __FUNCTION__,
 704 +                this->ctrlr, pdata, pdata->regs);
 705 +
 706 +       /* enable USB read, write and slave bursts */
 707 +       MCF_SCM_BCR = MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW | MCF_SCM_BCR_SBE_ALL;
 708 +
 709 +       /* Use external clock source if PLL isn't a multiple of 60MHz */
 710 +       MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_USBSRC;
 711 +
 712 +       /* Initialize the USB Clock: use USB input clock */
 713 +       MCF_GPIO_PAR_DMA = (MCF_GPIO_PAR_DMA & MCF_GPIO_PAR_DMA_DREQ1_MASK) |
 714 +                          MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN;
 715 +
 716 +       switch (this->xcvr_type) {
 717 +       case PORTSCX_PTS_ULPI:
 718 +               /* Enable the required ULPI signals */
 719 +               MCF_GPIO_PAR_DMA = (MCF_GPIO_PAR_DMA &
 720 +                                   MCF_GPIO_PAR_DMA_DACK1_MASK) |
 721 +                                   MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR;
 722 +
 723 +               MCF_GPIO_PAR_USB = MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT |
 724 +                                  MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP;
 725 +
 726 +               MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC &
 727 +                                   MCF_GPIO_PAR_FEC_FEC0_MASK) |
 728 +                                   MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI;
 729 +               break;
 730 +       case PORTSCX_PTS_ONCHIP:
 731 +               /* Enable VBUS_EN and VBUS_OC signals */
 732 +               MCF_GPIO_PAR_USB = MCF_GPIO_PAR_USB_VBUSEN_VBUSEN |
 733 +                                  MCF_GPIO_PAR_USB_VBUSOC_VBUSOC;
 734 +
 735 +               /* Setup USB_VBUS_OC signal to be active-low */
 736 +               MCF_CCM_MISCCR |= MCF_CCM_MISCCR_USBOC;
 737 +
 738 +               break;
 739 +       }
 740 +
 741 +       pr_debug("&regs->portsc1=0x%p  old portsc1=0x%x \n", &regs->portsc1,
 742 +                regs->portsc1);
 743 +
 744 +       regs->portsc1 &= ~PORTSCX_PTS_MASK;
 745 +       regs->portsc1 |= this->xcvr_type;
 746 +
 747 +       /*
 748 +        * need to reset the controller here so that the ID pin
 749 +        * is correctly detected.
 750 +        */
 751 +       regs->usbcmd |= USB_CMD_CTRL_RESET;
 752 +
 753 +       /*
 754 +        * allow controller to reset, and leave time for
 755 +        * the ULPI transceiver to reset too.
 756 +        */
 757 +       mdelay(10);
 758 +
 759 +       pr_debug("DDD %s: done.  portsc1=0x%x\n", __FUNCTION__, regs->portsc1);
 760 +}
 761 +
 762 +static void xcvr_uninit(struct platform_device *pdev)
 763 +{
 764 +       pr_debug("%s: pdev=0x%p\n", __FUNCTION__, pdev);
 765 +}
 766 +
 767 +
 768 +struct fsl_xcvr_ops xcvr_ops_otg = {
 769 +       .ctrlr          = USB_CTRLR_OTG,
 770 +       .init           = xcvr_init,
 771 +       .uninit         = xcvr_uninit,
 772 +
 773 +#ifdef CONFIG_USB_M5445X_ULPI
 774 +       .xcvr_type      = PORTSCX_PTS_ULPI,
 775 +#elif defined CONFIG_USB_M5445X_FSLS
 776 +       .xcvr_type      = PORTSCX_PTS_ONCHIP,
 777 +#else
 778 +#error "Invalid USB transceiver selection."
 779 +#endif
 780 +};
 781 +
 782 +static int __init usb_xcvr_init(void)
 783 +{
 784 +       pr_debug("%s\n", __FUNCTION__);
 785 +
 786 +       fsl_usb_xcvr_register(&xcvr_ops_otg);
 787 +
 788 +       pr_debug("%s done\n", __FUNCTION__);
 789 +       return 0;
 790 +}
 791 +
 792 +static void __exit usb_xcvr_exit(void)
 793 +{
 794 +       fsl_usb_xcvr_unregister(USB_CTRLR_OTG);
 795 +}
 796 +
 797 +module_init(usb_xcvr_init);
 798 +module_exit(usb_xcvr_exit);
 799 +
 800 +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 801 +MODULE_DESCRIPTION("External ULPI xcvr driver");
 802 +MODULE_LICENSE("GPL");
 803 +
 804 --- a/drivers/usb/Kconfig
 805 +++ b/drivers/usb/Kconfig
 806 @@ -55,6 +55,7 @@ config USB_ARCH_HAS_EHCI
 807         default y if PPC_83xx
 808         default y if SOC_AU1200
 809         default y if ARCH_IXP4XX
 810 +       default y if M54455
 811         default PCI
 812
 813  # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
 814 --- a/drivers/usb/Makefile
 815 +++ b/drivers/usb/Makefile
 816 @@ -32,3 +32,5 @@ obj-$(CONFIG_USB)             += misc/
 817
 818  obj-$(CONFIG_USB_ATM)          += atm/
 819  obj-$(CONFIG_USB_SPEEDTOUCH)   += atm/
 820 +
 821 +obj-$(CONFIG_USB_OTG)          += otg/
 822 --- a/drivers/usb/core/usb.c
 823 +++ b/drivers/usb/core/usb.c
 824 @@ -52,7 +52,7 @@ static int nousb;     /* Disable USB when bu
 825  struct workqueue_struct *ksuspend_usb_wq;
 826
 827  #ifdef CONFIG_USB_SUSPEND
 828 -static int usb_autosuspend_delay = 2;          /* Default delay value,
 829 +static int usb_autosuspend_delay = -1;         /* Default delay value,
 830                                                  * in seconds */
 831  module_param_named(autosuspend, usb_autosuspend_delay, int, 0644);
 832  MODULE_PARM_DESC(autosuspend, "default autosuspend delay");
 833 --- a/drivers/usb/gadget/Kconfig
 834 +++ b/drivers/usb/gadget/Kconfig
 835 @@ -231,6 +231,26 @@ config SUPERH_BUILT_IN_M66592
 836            However, this problem is improved if change a value of
 837            NET_IP_ALIGN to 4.
 838
 839 +config USB_GADGET_MCF5445X
 840 +       boolean "MCF5445X USB Device Controller"
 841 +       depends on M54455 && USB_M5445X_ULPI
 842 +       select USB_GADGET_DUALSPEED
 843 +       help
 844 +          Freescale's MCF5445X processors include
 845 +          an integrated device controller (as part of the OTG module).
 846 +          It has four programmable, bidirectional endpoints,
 847 +          including endpoint 0.
 848 +
 849 +          Say "y" to link the driver statically, or "m" to build a
 850 +          dynamically linked module called "mcf5445_udc" and force all
 851 +          gadget drivers to also be dynamically linked.
 852 +
 853 +config USB_MCF5445X
 854 +       tristate
 855 +       depends on USB_GADGET_MCF5445X
 856 +       default USB_GADGET
 857 +       select USB_GADGET_SELECTED
 858 +
 859  config USB_GADGET_GOKU
 860         boolean "Toshiba TC86C001 'Goku-S'"
 861         depends on PCI
 862 @@ -285,17 +305,6 @@ config USB_OMAP
 863         default USB_GADGET
 864         select USB_GADGET_SELECTED
 865
 866 -config USB_OTG
 867 -       boolean "OTG Support"
 868 -       depends on USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD
 869 -       help
 870 -          The most notable feature of USB OTG is support for a
 871 -          "Dual-Role" device, which can act as either a device
 872 -          or a host.  The initial role choice can be changed
 873 -          later, when two dual-role devices talk to each other.
 874 -
 875 -          Select this only if your OMAP board has a Mini-AB connector.
 876 -
 877  config USB_GADGET_S3C2410
 878         boolean "S3C2410 USB Device Controller"
 879         depends on ARCH_S3C2410
 880 @@ -369,6 +378,18 @@ config USB_DUMMY_HCD
 881
 882  endchoice
 883
 884 +config USB_OTG
 885 +       boolean "OTG Support"
 886 +       depends on (USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD) || \
 887 +                  (USB_GADGET_MCF5445X && USB_M5445X_ULPI)
 888 +       help
 889 +          The most notable feature of USB OTG is support for a
 890 +          "Dual-Role" device, which can act as either a device
 891 +          or a host.  The initial role choice can be changed
 892 +          later, when two dual-role devices talk to each other.
 893 +
 894 +          Select this only if your OMAP board has a Mini-AB connector.
 895 +
 896  config USB_GADGET_DUALSPEED
 897         bool
 898         depends on USB_GADGET
 899 --- a/drivers/usb/gadget/Makefile
 900 +++ b/drivers/usb/gadget/Makefile
 901 @@ -17,6 +17,7 @@ obj-$(CONFIG_USB_AT91)                += at91_udc.o
 902  obj-$(CONFIG_USB_ATMEL_USBA)   += atmel_usba_udc.o
 903  obj-$(CONFIG_USB_FSL_USB2)     += fsl_usb2_udc.o
 904  obj-$(CONFIG_USB_M66592)       += m66592-udc.o
 905 +obj-$(CONFIG_USB_MCF5445X)     += mcf5445x_udc.o
 906
 907  #
 908  # USB gadget drivers
 909 --- a/drivers/usb/gadget/ether.c
 910 +++ b/drivers/usb/gadget/ether.c
 911 @@ -287,6 +287,9 @@ MODULE_PARM_DESC(host_addr, "Host Ethern
 912  #define        DEV_CONFIG_CDC
 913  #endif
 914
 915 +#ifdef CONFIG_USB_GADGET_MCF5445X
 916 +#define DEV_CONFIG_CDC
 917 +#endif
 918
 919  /*-------------------------------------------------------------------------*/
 920
 921 --- a/drivers/usb/gadget/fsl_usb2_udc.h
 922 +++ b/drivers/usb/gadget/fsl_usb2_udc.h
 923 @@ -83,16 +83,6 @@ struct usb_dr_host {
 924         u32 endptctrl[6];       /* Endpoint Control Registers */
 925  };
 926
 927 - /* non-EHCI USB system interface registers (Big Endian) */
 928 -struct usb_sys_interface {
 929 -       u32 snoop1;
 930 -       u32 snoop2;
 931 -       u32 age_cnt_thresh;     /* Age Count Threshold Register */
 932 -       u32 pri_ctrl;           /* Priority Control Register */
 933 -       u32 si_ctrl;            /* System Interface Control Register */
 934 -       u8 res[236];
 935 -       u32 control;            /* General Purpose Control Register */
 936 -};
 937
 938  /* ep0 transfer state */
 939  #define WAIT_FOR_SETUP          0
 940 @@ -101,10 +91,6 @@ struct usb_sys_interface {
 941  #define WAIT_FOR_OUT_STATUS     3
 942  #define DATA_STATE_RECV         4
 943
 944 -/* Device Controller Capability Parameter register */
 945 -#define DCCPARAMS_DC                           0x00000080
 946 -#define DCCPARAMS_DEN_MASK                     0x0000001f
 947 -
 948  /* Frame Index Register Bit Masks */
 949  #define        USB_FRINDEX_MASKS                       0x3fff
 950  /* USB CMD  Register Bit Masks */
 951 @@ -180,172 +166,6 @@ struct usb_sys_interface {
 952  /* endpoint list address bit masks */
 953  #define USB_EP_LIST_ADDRESS_MASK              0xfffff800
 954
 955 -/* PORTSCX  Register Bit Masks */
 956 -#define  PORTSCX_CURRENT_CONNECT_STATUS       0x00000001
 957 -#define  PORTSCX_CONNECT_STATUS_CHANGE        0x00000002
 958 -#define  PORTSCX_PORT_ENABLE                  0x00000004
 959 -#define  PORTSCX_PORT_EN_DIS_CHANGE           0x00000008
 960 -#define  PORTSCX_OVER_CURRENT_ACT             0x00000010
 961 -#define  PORTSCX_OVER_CURRENT_CHG             0x00000020
 962 -#define  PORTSCX_PORT_FORCE_RESUME            0x00000040
 963 -#define  PORTSCX_PORT_SUSPEND                 0x00000080
 964 -#define  PORTSCX_PORT_RESET                   0x00000100
 965 -#define  PORTSCX_LINE_STATUS_BITS             0x00000C00
 966 -#define  PORTSCX_PORT_POWER                   0x00001000
 967 -#define  PORTSCX_PORT_INDICTOR_CTRL           0x0000C000
 968 -#define  PORTSCX_PORT_TEST_CTRL               0x000F0000
 969 -#define  PORTSCX_WAKE_ON_CONNECT_EN           0x00100000
 970 -#define  PORTSCX_WAKE_ON_CONNECT_DIS          0x00200000
 971 -#define  PORTSCX_WAKE_ON_OVER_CURRENT         0x00400000
 972 -#define  PORTSCX_PHY_LOW_POWER_SPD            0x00800000
 973 -#define  PORTSCX_PORT_FORCE_FULL_SPEED        0x01000000
 974 -#define  PORTSCX_PORT_SPEED_MASK              0x0C000000
 975 -#define  PORTSCX_PORT_WIDTH                   0x10000000
 976 -#define  PORTSCX_PHY_TYPE_SEL                 0xC0000000
 977 -
 978 -/* bit 11-10 are line status */
 979 -#define  PORTSCX_LINE_STATUS_SE0              0x00000000
 980 -#define  PORTSCX_LINE_STATUS_JSTATE           0x00000400
 981 -#define  PORTSCX_LINE_STATUS_KSTATE           0x00000800
 982 -#define  PORTSCX_LINE_STATUS_UNDEF            0x00000C00
 983 -#define  PORTSCX_LINE_STATUS_BIT_POS          10
 984 -
 985 -/* bit 15-14 are port indicator control */
 986 -#define  PORTSCX_PIC_OFF                      0x00000000
 987 -#define  PORTSCX_PIC_AMBER                    0x00004000
 988 -#define  PORTSCX_PIC_GREEN                    0x00008000
 989 -#define  PORTSCX_PIC_UNDEF                    0x0000C000
 990 -#define  PORTSCX_PIC_BIT_POS                  14
 991 -
 992 -/* bit 19-16 are port test control */
 993 -#define  PORTSCX_PTC_DISABLE                  0x00000000
 994 -#define  PORTSCX_PTC_JSTATE                   0x00010000
 995 -#define  PORTSCX_PTC_KSTATE                   0x00020000
 996 -#define  PORTSCX_PTC_SEQNAK                   0x00030000
 997 -#define  PORTSCX_PTC_PACKET                   0x00040000
 998 -#define  PORTSCX_PTC_FORCE_EN                 0x00050000
 999 -#define  PORTSCX_PTC_BIT_POS                  16
1000 -
1001 -/* bit 27-26 are port speed */
1002 -#define  PORTSCX_PORT_SPEED_FULL              0x00000000
1003 -#define  PORTSCX_PORT_SPEED_LOW               0x04000000
1004 -#define  PORTSCX_PORT_SPEED_HIGH              0x08000000
1005 -#define  PORTSCX_PORT_SPEED_UNDEF             0x0C000000
1006 -#define  PORTSCX_SPEED_BIT_POS                26
1007 -
1008 -/* bit 28 is parallel transceiver width for UTMI interface */
1009 -#define  PORTSCX_PTW                          0x10000000
1010 -#define  PORTSCX_PTW_8BIT                     0x00000000
1011 -#define  PORTSCX_PTW_16BIT                    0x10000000
1012 -
1013 -/* bit 31-30 are port transceiver select */
1014 -#define  PORTSCX_PTS_UTMI                     0x00000000
1015 -#define  PORTSCX_PTS_ULPI                     0x80000000
1016 -#define  PORTSCX_PTS_FSLS                     0xC0000000
1017 -#define  PORTSCX_PTS_BIT_POS                  30
1018 -
1019 -/* otgsc Register Bit Masks */
1020 -#define  OTGSC_CTRL_VUSB_DISCHARGE            0x00000001
1021 -#define  OTGSC_CTRL_VUSB_CHARGE               0x00000002
1022 -#define  OTGSC_CTRL_OTG_TERM                  0x00000008
1023 -#define  OTGSC_CTRL_DATA_PULSING              0x00000010
1024 -#define  OTGSC_STS_USB_ID                     0x00000100
1025 -#define  OTGSC_STS_A_VBUS_VALID               0x00000200
1026 -#define  OTGSC_STS_A_SESSION_VALID            0x00000400
1027 -#define  OTGSC_STS_B_SESSION_VALID            0x00000800
1028 -#define  OTGSC_STS_B_SESSION_END              0x00001000
1029 -#define  OTGSC_STS_1MS_TOGGLE                 0x00002000
1030 -#define  OTGSC_STS_DATA_PULSING               0x00004000
1031 -#define  OTGSC_INTSTS_USB_ID                  0x00010000
1032 -#define  OTGSC_INTSTS_A_VBUS_VALID            0x00020000
1033 -#define  OTGSC_INTSTS_A_SESSION_VALID         0x00040000
1034 -#define  OTGSC_INTSTS_B_SESSION_VALID         0x00080000
1035 -#define  OTGSC_INTSTS_B_SESSION_END           0x00100000
1036 -#define  OTGSC_INTSTS_1MS                     0x00200000
1037 -#define  OTGSC_INTSTS_DATA_PULSING            0x00400000
1038 -#define  OTGSC_INTR_USB_ID                    0x01000000
1039 -#define  OTGSC_INTR_A_VBUS_VALID              0x02000000
1040 -#define  OTGSC_INTR_A_SESSION_VALID           0x04000000
1041 -#define  OTGSC_INTR_B_SESSION_VALID           0x08000000
1042 -#define  OTGSC_INTR_B_SESSION_END             0x10000000
1043 -#define  OTGSC_INTR_1MS_TIMER                 0x20000000
1044 -#define  OTGSC_INTR_DATA_PULSING              0x40000000
1045 -
1046 -/* USB MODE Register Bit Masks */
1047 -#define  USB_MODE_CTRL_MODE_IDLE              0x00000000
1048 -#define  USB_MODE_CTRL_MODE_DEVICE            0x00000002
1049 -#define  USB_MODE_CTRL_MODE_HOST              0x00000003
1050 -#define  USB_MODE_CTRL_MODE_RSV               0x00000001
1051 -#define  USB_MODE_SETUP_LOCK_OFF              0x00000008
1052 -#define  USB_MODE_STREAM_DISABLE              0x00000010
1053 -/* Endpoint Flush Register */
1054 -#define EPFLUSH_TX_OFFSET                    0x00010000
1055 -#define EPFLUSH_RX_OFFSET                    0x00000000
1056 -
1057 -/* Endpoint Setup Status bit masks */
1058 -#define  EP_SETUP_STATUS_MASK                 0x0000003F
1059 -#define  EP_SETUP_STATUS_EP0                 0x00000001
1060 -
1061 -/* ENDPOINTCTRLx  Register Bit Masks */
1062 -#define  EPCTRL_TX_ENABLE                     0x00800000
1063 -#define  EPCTRL_TX_DATA_TOGGLE_RST            0x00400000       /* Not EP0 */
1064 -#define  EPCTRL_TX_DATA_TOGGLE_INH            0x00200000       /* Not EP0 */
1065 -#define  EPCTRL_TX_TYPE                       0x000C0000
1066 -#define  EPCTRL_TX_DATA_SOURCE                0x00020000       /* Not EP0 */
1067 -#define  EPCTRL_TX_EP_STALL                   0x00010000
1068 -#define  EPCTRL_RX_ENABLE                     0x00000080
1069 -#define  EPCTRL_RX_DATA_TOGGLE_RST            0x00000040       /* Not EP0 */
1070 -#define  EPCTRL_RX_DATA_TOGGLE_INH            0x00000020       /* Not EP0 */
1071 -#define  EPCTRL_RX_TYPE                       0x0000000C
1072 -#define  EPCTRL_RX_DATA_SINK                  0x00000002       /* Not EP0 */
1073 -#define  EPCTRL_RX_EP_STALL                   0x00000001
1074 -
1075 -/* bit 19-18 and 3-2 are endpoint type */
1076 -#define  EPCTRL_EP_TYPE_CONTROL               0
1077 -#define  EPCTRL_EP_TYPE_ISO                   1
1078 -#define  EPCTRL_EP_TYPE_BULK                  2
1079 -#define  EPCTRL_EP_TYPE_INTERRUPT             3
1080 -#define  EPCTRL_TX_EP_TYPE_SHIFT              18
1081 -#define  EPCTRL_RX_EP_TYPE_SHIFT              2
1082 -
1083 -/* SNOOPn Register Bit Masks */
1084 -#define  SNOOP_ADDRESS_MASK                   0xFFFFF000
1085 -#define  SNOOP_SIZE_ZERO                      0x00     /* snooping disable */
1086 -#define  SNOOP_SIZE_4KB                       0x0B     /* 4KB snoop size */
1087 -#define  SNOOP_SIZE_8KB                       0x0C
1088 -#define  SNOOP_SIZE_16KB                      0x0D
1089 -#define  SNOOP_SIZE_32KB                      0x0E
1090 -#define  SNOOP_SIZE_64KB                      0x0F
1091 -#define  SNOOP_SIZE_128KB                     0x10
1092 -#define  SNOOP_SIZE_256KB                     0x11
1093 -#define  SNOOP_SIZE_512KB                     0x12
1094 -#define  SNOOP_SIZE_1MB                       0x13
1095 -#define  SNOOP_SIZE_2MB                       0x14
1096 -#define  SNOOP_SIZE_4MB                       0x15
1097 -#define  SNOOP_SIZE_8MB                       0x16
1098 -#define  SNOOP_SIZE_16MB                      0x17
1099 -#define  SNOOP_SIZE_32MB                      0x18
1100 -#define  SNOOP_SIZE_64MB                      0x19
1101 -#define  SNOOP_SIZE_128MB                     0x1A
1102 -#define  SNOOP_SIZE_256MB                     0x1B
1103 -#define  SNOOP_SIZE_512MB                     0x1C
1104 -#define  SNOOP_SIZE_1GB                       0x1D
1105 -#define  SNOOP_SIZE_2GB                       0x1E     /* 2GB snoop size */
1106 -
1107 -/* pri_ctrl Register Bit Masks */
1108 -#define  PRI_CTRL_PRI_LVL1                    0x0000000C
1109 -#define  PRI_CTRL_PRI_LVL0                    0x00000003
1110 -
1111 -/* si_ctrl Register Bit Masks */
1112 -#define  SI_CTRL_ERR_DISABLE                  0x00000010
1113 -#define  SI_CTRL_IDRC_DISABLE                 0x00000008
1114 -#define  SI_CTRL_RD_SAFE_EN                   0x00000004
1115 -#define  SI_CTRL_RD_PREFETCH_DISABLE          0x00000002
1116 -#define  SI_CTRL_RD_PREFEFETCH_VAL            0x00000001
1117 -
1118 -/* control Register Bit Masks */
1119 -#define  USB_CTRL_IOENB                       0x00000004
1120 -#define  USB_CTRL_ULPI_INT0EN                 0x00000001
1121
1122  /* Endpoint Queue Head data struct
1123   * Rem: all the variables of qh are LittleEndian Mode
1124 @@ -477,7 +297,10 @@ struct fsl_udc {
1125         unsigned int irq;
1126
1127         struct usb_ctrlrequest local_setup_buff;
1128 -       spinlock_t lock;
1129 +       spinlock_t lock;                /* udc lock */
1130 +       struct fsl_usb2_platform_data *pdata;
1131 +       u32 xcvr_type;
1132 +
1133         struct otg_transceiver *transceiver;
1134         unsigned softconnect:1;
1135         unsigned vbus_active:1;
1136 @@ -514,7 +337,7 @@ struct fsl_udc {
1137  #define DBG(fmt, args...)      printk(KERN_DEBUG "[%s]  " fmt "\n", \
1138                                 __FUNCTION__, ## args)
1139  #else
1140 -#define DBG(fmt, args...)      do{}while(0)
1141 +#define DBG(fmt, args...)      do {} while (0)
1142  #endif
1143
1144  #if 0
1145 @@ -548,7 +371,7 @@ static void dump_msg(const char *label,
1146  #ifdef VERBOSE
1147  #define VDBG           DBG
1148  #else
1149 -#define VDBG(stuff...) do{}while(0)
1150 +#define VDBG(stuff...) do {} while (0)
1151  #endif
1152
1153  #define ERR(stuff...)          pr_err("udc: " stuff)
1154 @@ -573,11 +396,14 @@ static void dump_msg(const char *label,
1155  #define ep_maxpacket(EP)       ((EP)->ep.maxpacket)
1156  #define ep_is_in(EP)   ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
1157                         USB_DIR_IN ):((EP)->desc->bEndpointAddress \
1158 -                       & USB_DIR_IN)==USB_DIR_IN)
1159 +                       & USB_DIR_IN) == USB_DIR_IN)
1160  #define get_ep_by_pipe(udc, pipe)      ((pipe == 1)? &udc->eps[0]: \
1161                                         &udc->eps[pipe])
1162  #define get_pipe_by_windex(windex)     ((windex & USB_ENDPOINT_NUMBER_MASK) \
1163                                         * 2 + ((windex & USB_DIR_IN) ? 1 : 0))
1164  #define get_pipe_by_ep(EP)     (ep_index(EP) * 2 + ep_is_in(EP))
1165
1166 +/* Bulk only class request */
1167 +#define USB_BULK_RESET_REQUEST          0xff
1168 +
1169  #endif
1170 --- a/drivers/usb/gadget/gadget_chips.h
1171 +++ b/drivers/usb/gadget/gadget_chips.h
1172 @@ -147,6 +147,11 @@
1173  #define        gadget_is_m66592(g)     0
1174  #endif
1175
1176 +#ifdef CONFIG_USB_GADGET_MCF5445X
1177 +#define gadget_is_mcf5445x(g)  !strcmp("fsl-usb2-udc", (g)->name)
1178 +#else
1179 +#define gadget_is_mcf5445x(g)  0
1180 +#endif
1181
1182  // CONFIG_USB_GADGET_SX2
1183  // CONFIG_USB_GADGET_AU1X00
1184 @@ -212,5 +217,7 @@ static inline int usb_gadget_controller_
1185                 return 0x20;
1186         else if (gadget_is_m66592(gadget))
1187                 return 0x21;
1188 +       else if (gadget_is_mcf5445x(gadget))
1189 +               return 0x22;
1190         return -ENOENT;
1191  }
1192 --- /dev/null
1193 +++ b/drivers/usb/gadget/mcf5445x_udc.c
1194 @@ -0,0 +1,2758 @@
1195 +/*
1196 + * Copyright Freescale Semiconductor, Inc. 2006-2007
1197 + *
1198 + *      Based on mpc_udc.c code
1199 + *      of Li Yang and Jiang Bo (Freescale Semiconductor, Inc.)
1200 + *
1201 + *
1202 + * This program is free software; you can redistribute  it and/or modify it
1203 + * under  the terms of  the GNU General  Public License as published by the
1204 + * Free Software Foundation;  either version 2 of the  License, or (at your
1205 + * option) any later version.
1206 + *
1207 + * This program is distributed in the hope that it will be useful,
1208 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1209 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1210 + * GNU General Public License for more details.
1211 + *
1212 + * You should have received a copy of the GNU General Public License
1213 + * along with this program; if not, write to the Free Software
1214 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
1215 + *
1216 + ***************************************************************************
1217 + * Changes:
1218 + *   v0.004    30 July 2007            Duck
1219 + *             mcf5445x port
1220 + *   v0.003    27 October 2006         Andrey Butok
1221 + *             Added M5329EVB support (without external transceiver).
1222 + *   v0.002    29 September 2006       Andrey Butok
1223 + *             Some little changes. Added OTG support.
1224 + *   v0.001    12 July 2006            Andrey Butok
1225 + *             Initial Release - developed on uClinux with 2.6.17.1 kernel.
1226 + *             Based on mpc_udc.c code
1227 + *             of Li Yang and Jiang Bo (Freescale Semiconductor, Inc.)
1228 + *
1229 + */
1230 +
1231 +#define DEBUG
1232 +#undef VERBOSE
1233 +
1234 +#include <linux/module.h>
1235 +#include <linux/kernel.h>
1236 +#include <linux/ioport.h>
1237 +#include <linux/types.h>
1238 +#include <linux/errno.h>
1239 +#include <linux/delay.h>
1240 +#include <linux/sched.h>
1241 +#include <linux/slab.h>
1242 +#include <linux/init.h>
1243 +#include <linux/io.h>
1244 +#include <linux/irq.h>
1245 +#include <linux/timer.h>
1246 +#include <linux/list.h>
1247 +#include <linux/interrupt.h>
1248 +#include <linux/proc_fs.h>
1249 +#include <linux/mm.h>
1250 +#include <linux/platform_device.h>
1251 +#include <linux/moduleparam.h>
1252 +#include <linux/device.h>
1253 +#include <linux/usb/ch9.h>
1254 +#include <linux/usb_gadget.h>
1255 +#include <linux/usb/otg.h>
1256 +#include <linux/dma-mapping.h>
1257 +#include <linux/dmapool.h>
1258 +#include <linux/fsl_devices.h>
1259 +#include <linux/usb/fsl_xcvr.h>
1260 +#include <linux/usb/fsl_usb2.h>
1261 +#include <linux/pm.h>
1262 +
1263 +#include <asm/byteorder.h>
1264 +#include <asm/system.h>
1265 +#include <asm/unaligned.h>
1266 +#include <asm/dma.h>
1267 +
1268 +#include <asm/mcfsim.h>
1269 +#include <asm/cacheflush.h>
1270 +
1271 +#include "fsl_usb2_udc.h"
1272 +
1273 +#define        DRIVER_DESC     "Freescale High-Speed USB SoC Device Controller driver"
1274 +#define        DRIVER_AUTHOR   "Freescale Semiconductor Inc."
1275 +#define        DRIVER_VERSION  "30 July 2007"
1276 +
1277 +#define cpu_to_hc32(x) (x)
1278 +#define hc32_to_cpu(x) (x)
1279 +
1280 +static int udc_suspend(struct fsl_udc *udc);
1281 +
1282 +#define        DMA_ADDR_INVALID        (~(dma_addr_t)0)
1283 +
1284 +static const char driver_name[] = "fsl-usb2-udc";
1285 +static const char driver_desc[] = DRIVER_DESC;
1286 +
1287 +volatile static struct fsl_usb_device_regs *dr_regs;
1288 +volatile static struct usb_sys_interface *usb_sys_regs;
1289 +
1290 +/* it is initialized in probe()  */
1291 +static struct fsl_udc *udc_controller;
1292 +
1293 +static const struct usb_endpoint_descriptor
1294 +fsl_ep0_desc = {
1295 +       .bLength =              USB_DT_ENDPOINT_SIZE,
1296 +       .bDescriptorType =      USB_DT_ENDPOINT,
1297 +       .bEndpointAddress =     0,
1298 +       .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
1299 +       .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
1300 +};
1301 +
1302 +static int fsl_udc_suspend(struct device *dev, pm_message_t state);
1303 +static int fsl_udc_resume(struct device *dev);
1304 +static void fsl_ep_fifo_flush(struct usb_ep *_ep);
1305 +
1306 +/********************************************************************
1307 + *     Internal Used Function
1308 +********************************************************************/
1309 +/*-----------------------------------------------------------------
1310 + * done() - retire a request; caller blocked irqs
1311 + * @status : request status to be set, only works when
1312 + *     request is still in progress.
1313 + *--------------------------------------------------------------*/
1314 +static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
1315 +{
1316 +       struct fsl_udc *udc = NULL;
1317 +       unsigned char stopped = ep->stopped;
1318 +
1319 +       udc = (struct fsl_udc *)ep->udc;
1320 +
1321 +       pr_debug("udc: req=0x%p\n", req);
1322 +       if (req->head) {
1323 +               pr_debug("udc: freeing head=0x%p\n", req->head);
1324 +               dma_pool_free(udc->td_pool, req->head, req->head->td_dma);
1325 +       }
1326 +
1327 +       /* the req->queue pointer is used by ep_queue() func, in which
1328 +        * the request will be added into a udc_ep->queue 'd tail
1329 +        * so here the req will be dropped from the ep->queue
1330 +        */
1331 +       list_del_init(&req->queue);
1332 +
1333 +       /* req.status should be set as -EINPROGRESS in ep_queue() */
1334 +       if (req->req.status == -EINPROGRESS)
1335 +               req->req.status = status;
1336 +       else
1337 +               status = req->req.status;
1338 +
1339 +       pr_debug("udc: req=0x%p  mapped=%x\n", req, req->mapped);
1340 +
1341 +       if (req->mapped) {
1342 +               pr_debug("udc: calling dma_unmap_single(buf,%s)  req=0x%p  "
1343 +                        "a=0x%x  len=%d\n",
1344 +                        ep_is_in(ep) ? "to_dvc" : "from_dvc",
1345 +                        req, req->req.dma, req->req.length);
1346 +
1347 +               dma_unmap_single(ep->udc->gadget.dev.parent,
1348 +                                req->req.dma, req->req.length, ep_is_in(ep) ?
1349 +                                DMA_TO_DEVICE : DMA_FROM_DEVICE);
1350 +
1351 +               req->req.dma = DMA_ADDR_INVALID;
1352 +               req->mapped = 0;
1353 +               pr_debug("udc: req=0x%p set req.dma=0x%x\n", req, req->req.dma);
1354 +       } else {
1355 +               if ((req->req.length != 0)
1356 +                   && (req->req.dma != DMA_ADDR_INVALID)) {
1357 +                       pr_debug("udc: calling dma_sync_single_for_cpu(buf,%s) "
1358 +                                "req=0x%p  dma=0x%x  len=%d\n",
1359 +                                ep_is_in(ep) ? "to_dvc" : "from_dvc", req,
1360 +                                req->req.dma, req->req.length);
1361 +
1362 +                       dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
1363 +                                               req->req.dma, req->req.length,
1364 +                                               ep_is_in(ep) ? DMA_TO_DEVICE :
1365 +                                               DMA_FROM_DEVICE);
1366 +               }
1367 +       }
1368 +
1369 +       if (status && (status != -ESHUTDOWN)) {
1370 +               pr_debug("udc: complete %s req 0c%p stat %d len %u/%u\n",
1371 +                        ep->ep.name, &req->req, status,
1372 +                        req->req.actual, req->req.length);
1373 +       }
1374 +
1375 +       /* don't modify queue heads during completion callback */
1376 +       ep->stopped = 1;
1377 +
1378 +       spin_unlock(&ep->udc->lock);
1379 +
1380 +       /* this complete() should a func implemented by gadget layer,
1381 +        * eg fsg->bulk_in_complete() */
1382 +       if (req->req.complete) {
1383 +               pr_debug("udc: calling gadget's complete()  req=0x%p\n", req);
1384 +               req->req.complete(&ep->ep, &req->req);
1385 +               pr_debug("udc: back from gadget's complete()\n");
1386 +       }
1387 +
1388 +       spin_lock(&ep->udc->lock);
1389 +       ep->stopped = stopped;
1390 +}
1391 +
1392 +/*
1393 + * nuke(): delete all requests related to this ep
1394 + * called with spinlock held
1395 + *--------------------------------------------------------------*/
1396 +static void nuke(struct fsl_ep *ep, int status)
1397 +{
1398 +       ep->stopped = 1;
1399 +
1400 +       /* Flush fifo */
1401 +       fsl_ep_fifo_flush(&ep->ep);
1402 +
1403 +       /* Whether this eq has request linked */
1404 +       while (!list_empty(&ep->queue)) {
1405 +               struct fsl_req *req = NULL;
1406 +
1407 +               req = list_entry(ep->queue.next, struct fsl_req, queue);
1408 +               done(ep, req, status);
1409 +       }
1410 +}
1411 +
1412 +/*------------------------------------------------------------------
1413 +       Internal Hardware related function
1414 + ------------------------------------------------------------------*/
1415 +
1416 +static int dr_controller_setup(struct fsl_udc *udc)
1417 +{
1418 +       unsigned int tmp;
1419 +       unsigned int __attribute((unused)) ctrl = 0;
1420 +       unsigned long timeout;
1421 +       struct fsl_usb2_platform_data *pdata;
1422 +
1423 +#define FSL_UDC_RESET_TIMEOUT 1000
1424 +
1425 +       /* before here, make sure dr_regs has been initialized */
1426 +       if (!udc)
1427 +               return -EINVAL;
1428 +       pdata = udc->pdata;
1429 +
1430 +       /* Stop and reset the usb controller */
1431 +       tmp = fsl_readl(&dr_regs->usbcmd);
1432 +       tmp &= ~USB_CMD_RUN_STOP;
1433 +       fsl_writel(tmp, &dr_regs->usbcmd);
1434 +
1435 +       tmp = fsl_readl(&dr_regs->usbcmd);
1436 +       tmp |= USB_CMD_CTRL_RESET;
1437 +       fsl_writel(tmp, &dr_regs->usbcmd);
1438 +
1439 +       /* Wait for reset to complete */
1440 +       timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
1441 +       while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
1442 +               if (time_after(jiffies, timeout)) {
1443 +                       ERR("udc reset timeout! \n");
1444 +                       return -ETIMEDOUT;
1445 +               }
1446 +               cpu_relax();
1447 +       }
1448 +
1449 +       tmp = fsl_readl(&dr_regs->usbmode);
1450 +       tmp &= ~0x3;    /* clear mode bits */
1451 +       tmp |= USB_MODE_CTRL_MODE_DEVICE;
1452 +       /* Disable Setup Lockout */
1453 +       tmp |= USB_MODE_SETUP_LOCK_OFF;
1454 +       if (pdata->es)
1455 +               tmp |= USBMODE_ES;
1456 +       fsl_writel(tmp, &dr_regs->usbmode);
1457 +
1458 +       if (pdata->xcvr_ops && pdata->xcvr_ops->set_device)
1459 +               pdata->xcvr_ops->set_device();
1460 +
1461 +       /* Clear the setup status */
1462 +       fsl_writel(0, &dr_regs->usbsts);
1463 +
1464 +       tmp = udc->ep_qh_dma;
1465 +       tmp &= USB_EP_LIST_ADDRESS_MASK;
1466 +       fsl_writel(tmp, &dr_regs->endpointlistaddr);
1467 +
1468 +       /*
1469 +       VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
1470 +               (int)udc->ep_qh, (int)tmp,
1471 +               fsl_readl(&dr_regs->endpointlistaddr));
1472 +       */
1473 +
1474 +
1475 +       if (pdata->have_sysif_regs) {
1476 +               /* Config control enable i/o output, cpu endian register */
1477 +               ctrl = __raw_readl(&usb_sys_regs->control);
1478 +               ctrl |= USB_CTRL_IOENB;
1479 +               __raw_writel(ctrl, &usb_sys_regs->control);
1480 +       }
1481 +
1482 +#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1483 +       /* Turn on cache snooping hardware, since some PowerPC platforms
1484 +        * wholly rely on hardware to deal with cache coherent. */
1485 +
1486 +       if (pdata->have_sysif_regs) {
1487 +               /* Setup Snooping for all the 4GB space */
1488 +               tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
1489 +               __raw_writel(tmp, &usb_sys_regs->snoop1);
1490 +               tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
1491 +               __raw_writel(tmp, &usb_sys_regs->snoop2);
1492 +       }
1493 +#endif
1494 +
1495 +       return 0;
1496 +}
1497 +
1498 +static void pullup_enable(struct fsl_udc *udc)
1499 +{
1500 +       u32 temp;
1501 +
1502 +       unsigned short ccm = fsl_readw(&MCF_CCM_UOCSR);
1503 +       ccm |= MCF_CCM_UOCSR_BVLD;
1504 +       ccm &= ~MCF_CCM_UOCSR_SEND;
1505 +       fsl_writew(ccm, &MCF_CCM_UOCSR);
1506 +
1507 +       /* Enable DR irq reg */
1508 +       temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
1509 +               | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
1510 +               | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
1511 +
1512 +       fsl_writel(temp, &dr_regs->usbintr);
1513 +
1514 +       /* Set controller to Run */
1515 +       temp = fsl_readl(&dr_regs->usbcmd);
1516 +       temp |= USB_CMD_RUN_STOP;
1517 +       fsl_writel(temp, &dr_regs->usbcmd);
1518 +
1519 +#ifdef NEVER /* DDD FIXME: we want this? */
1520 +       if (!udc->transceiver)
1521 +               *((u16 *)(MCF_FBCS1_CSAR)) &= ~0x1; /* Enable pullup register */
1522 +#endif
1523 +}
1524 +
1525 +static void pullup_disable(struct fsl_udc *udc)
1526 +{
1527 +       unsigned int tmp;
1528 +       unsigned short ccm;
1529 +
1530 +       VDBG();
1531 +       /* disable all INTRs */
1532 +       fsl_writel(0, &dr_regs->usbintr);
1533 +
1534 +       ccm = fsl_readw(&MCF_CCM_UOCSR);
1535 +       ccm &= ~MCF_CCM_UOCSR_BVLD;
1536 +       fsl_writew(ccm, &MCF_CCM_UOCSR);
1537 +
1538 +       /* set controller to Stop */
1539 +       tmp = fsl_readl(&dr_regs->usbcmd);
1540 +       tmp &= ~USB_CMD_RUN_STOP;
1541 +       fsl_writel(tmp, &dr_regs->usbcmd);
1542 +
1543 +#ifdef NEVER /* DDD FIXME: we want this? */
1544 +       if (!udc->transceiver)
1545 +               *((u16 *)(MCF_FBCS1_CSAR)) |= 0x1; /* Disable pullup register */
1546 +#endif
1547 +
1548 +}
1549 +
1550 +static void dr_controller_run(struct fsl_udc *udc)
1551 +{
1552 +       VDBG();
1553 +       pullup_enable(udc);
1554 +       udc->stopped = 0;
1555 +}
1556 +
1557 +static void dr_controller_stop(struct fsl_udc *udc)
1558 +{
1559 +       pullup_disable(udc);
1560 +       udc->stopped = 1;
1561 +       udc->gadget.b_hnp_enable = 0;
1562 +       udc->gadget.a_hnp_support = 0;
1563 +       udc->gadget.a_alt_hnp_support = 0;
1564 +}
1565 +
1566 +void dr_ep_setup(unsigned char ep_num, unsigned char dir, unsigned char ep_type)
1567 +{
1568 +       unsigned int tmp_epctrl = 0;
1569 +
1570 +       tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1571 +       if (dir) {
1572 +               if (ep_num)
1573 +                       tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
1574 +               tmp_epctrl |= EPCTRL_TX_ENABLE;
1575 +               tmp_epctrl |= ((unsigned int)(ep_type)
1576 +                               << EPCTRL_TX_EP_TYPE_SHIFT);
1577 +       } else {
1578 +               if (ep_num)
1579 +                       tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
1580 +               tmp_epctrl |= EPCTRL_RX_ENABLE;
1581 +               tmp_epctrl |= ((unsigned int)(ep_type)
1582 +                               << EPCTRL_RX_EP_TYPE_SHIFT);
1583 +       }
1584 +
1585 +       fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
1586 +}
1587 +
1588 +static void dr_ep_change_stall(unsigned char ep_num, unsigned char dir,
1589 +                              int value)
1590 +{
1591 +       u32 tmp_epctrl = 0;
1592 +
1593 +       tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1594 +
1595 +       if (value) {
1596 +               /* set the stall bit */
1597 +               if (dir)
1598 +                       tmp_epctrl |= EPCTRL_TX_EP_STALL;
1599 +               else
1600 +                       tmp_epctrl |= EPCTRL_RX_EP_STALL;
1601 +       } else {
1602 +               /* clear the stall bit and reset data toggle */
1603 +               if (dir) {
1604 +                       tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
1605 +                       tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
1606 +               } else {
1607 +                       tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
1608 +                       tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
1609 +               }
1610 +       }
1611 +       fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
1612 +}
1613 +
1614 +/* Get stall status of a specific ep
1615 +   Return: 0: not stalled; 1:stalled */
1616 +static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
1617 +{
1618 +       u32 epctrl;
1619 +
1620 +       epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1621 +       if (dir)
1622 +               return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
1623 +       else
1624 +               return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
1625 +}
1626 +
1627 +/********************************************************************
1628 +       Internal Structure Build up functions
1629 +********************************************************************/
1630 +
1631 +/*------------------------------------------------------------------
1632 +* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
1633 + * @zlt: Zero Length Termination Select (1: disable; 0: enable)
1634 + * @mult: Mult field
1635 + ------------------------------------------------------------------*/
1636 +static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
1637 +               unsigned char dir, unsigned char ep_type,
1638 +               unsigned int max_pkt_len,
1639 +               unsigned int zlt, unsigned char mult)
1640 +{
1641 +       struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
1642 +       unsigned int tmp = 0;
1643 +
1644 +       /* set the Endpoint Capabilites in QH */
1645 +       switch (ep_type) {
1646 +       case USB_ENDPOINT_XFER_CONTROL:
1647 +               /* Interrupt On Setup (IOS). for control ep  */
1648 +               tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
1649 +                       | EP_QUEUE_HEAD_IOS;
1650 +               break;
1651 +       case USB_ENDPOINT_XFER_ISOC:
1652 +               tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
1653 +                       | (mult << EP_QUEUE_HEAD_MULT_POS);
1654 +               break;
1655 +       case USB_ENDPOINT_XFER_BULK:
1656 +       case USB_ENDPOINT_XFER_INT:
1657 +               tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
1658 +               break;
1659 +       default:
1660 +               VDBG("error ep type is %d", ep_type);
1661 +               return;
1662 +       }
1663 +       if (zlt)
1664 +               tmp |= EP_QUEUE_HEAD_ZLT_SEL;
1665 +       p_QH->max_pkt_length = cpu_to_hc32(tmp);
1666 +
1667 +       return;
1668 +}
1669 +
1670 +/* Setup qh structure and ep register for ep0. */
1671 +static void ep0_setup(struct fsl_udc *udc)
1672 +{
1673 +       /* the intialization of an ep includes: fields in QH, Regs,
1674 +        * fsl_ep struct */
1675 +       struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
1676 +                       USB_MAX_CTRL_PAYLOAD, 0, 0);
1677 +       struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
1678 +                       USB_MAX_CTRL_PAYLOAD, 0, 0);
1679 +       dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
1680 +       dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
1681 +
1682 +       return;
1683 +
1684 +}
1685 +
1686 +/***********************************************************************
1687 +               Endpoint Management Functions
1688 +***********************************************************************/
1689 +
1690 +/*-------------------------------------------------------------------------
1691 + * when configurations are set, or when interface settings change
1692 + * for example the do_set_interface() in gadget layer,
1693 + * the driver will enable or disable the relevant endpoints
1694 + * ep0 doesn't use this routine. It is always enabled.
1695 +-------------------------------------------------------------------------*/
1696 +static int fsl_ep_enable(struct usb_ep *_ep,
1697 +               const struct usb_endpoint_descriptor *desc)
1698 +{
1699 +       struct fsl_udc *udc = NULL;
1700 +       struct fsl_ep *ep = NULL;
1701 +       unsigned short max = 0;
1702 +       unsigned char mult = 0, zlt;
1703 +       int retval = -EINVAL;
1704 +       unsigned long flags = 0;
1705 +
1706 +       ep = container_of(_ep, struct fsl_ep, ep);
1707 +
1708 +       /* catch various bogus parameters */
1709 +       if (!_ep || !desc || ep->desc
1710 +                       || (desc->bDescriptorType != USB_DT_ENDPOINT))
1711 +               return -EINVAL;
1712 +
1713 +       udc = ep->udc;
1714 +
1715 +       if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
1716 +               return -ESHUTDOWN;
1717 +
1718 +       max = le16_to_cpu(desc->wMaxPacketSize);
1719 +
1720 +       /* Disable automatic zlp generation.  Driver is reponsible to indicate
1721 +        * explicitly through req->req.zero.  This is needed to enable multi-td
1722 +        * request. */
1723 +       zlt = 1;
1724 +
1725 +       /* Assume the max packet size from gadget is always correct */
1726 +       switch (desc->bmAttributes & 0x03) {
1727 +       case USB_ENDPOINT_XFER_CONTROL:
1728 +       case USB_ENDPOINT_XFER_BULK:
1729 +       case USB_ENDPOINT_XFER_INT:
1730 +               /* mult = 0.  Execute N Transactions as demonstrated by
1731 +                * the USB variable length packet protocol where N is
1732 +                * computed using the Maximum Packet Length (dQH) and
1733 +                * the Total Bytes field (dTD) */
1734 +               mult = 0;
1735 +               break;
1736 +       case USB_ENDPOINT_XFER_ISOC:
1737 +               /* Calculate transactions needed for high bandwidth iso */
1738 +               mult = (unsigned char)(1 + ((max >> 11) & 0x03));
1739 +               max = max & 0x8ff;      /* bit 0~10 */
1740 +               /* 3 transactions at most */
1741 +               if (mult > 3)
1742 +                       goto en_done;
1743 +               break;
1744 +       default:
1745 +               goto en_done;
1746 +       }
1747 +
1748 +       spin_lock_irqsave(&udc->lock, flags);
1749 +       ep->ep.maxpacket = max;
1750 +       ep->desc = desc;
1751 +       ep->stopped = 0;
1752 +
1753 +       /* Controller related setup */
1754 +       /* Init EPx Queue Head (Ep Capabilites field in QH
1755 +        * according to max, zlt, mult) */
1756 +       struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
1757 +                       (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
1758 +                                       ?  USB_SEND : USB_RECV),
1759 +                       (unsigned char) (desc->bmAttributes
1760 +                                       & USB_ENDPOINT_XFERTYPE_MASK),
1761 +                       max, zlt, mult);
1762 +
1763 +       /* Init endpoint ctrl register */
1764 +       dr_ep_setup((unsigned char) ep_index(ep),
1765 +                       (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
1766 +                                       ? USB_SEND : USB_RECV),
1767 +                       (unsigned char) (desc->bmAttributes
1768 +                                       & USB_ENDPOINT_XFERTYPE_MASK));
1769 +
1770 +       spin_unlock_irqrestore(&udc->lock, flags);
1771 +       retval = 0;
1772 +
1773 +       VDBG("enabled %s (ep%d%s) maxpacket %d", ep->ep.name,
1774 +                       ep->desc->bEndpointAddress & 0x0f,
1775 +                       (desc->bEndpointAddress & USB_DIR_IN)
1776 +                               ? "in" : "out", max);
1777 +en_done:
1778 +       return retval;
1779 +}
1780 +
1781 +/*---------------------------------------------------------------------
1782 + * @ep : the ep being unconfigured. May not be ep0
1783 + * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
1784 +*---------------------------------------------------------------------*/
1785 +static int fsl_ep_disable(struct usb_ep *_ep)
1786 +{
1787 +       struct fsl_udc *udc = NULL;
1788 +       struct fsl_ep *ep = NULL;
1789 +       unsigned long flags = 0;
1790 +       u32 epctrl;
1791 +       int ep_num;
1792 +
1793 +       ep = container_of(_ep, struct fsl_ep, ep);
1794 +       if (!_ep || !ep->desc) {
1795 +               pr_debug("udc: %s not enabled\n", _ep ? ep->ep.name : NULL);
1796 +               return -EINVAL;
1797 +       }
1798 +
1799 +       /* disable ep on controller */
1800 +       ep_num = ep_index(ep);
1801 +       epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1802 +       if (ep_is_in(ep))
1803 +               epctrl &= ~EPCTRL_TX_ENABLE;
1804 +       else
1805 +               epctrl &= ~EPCTRL_RX_ENABLE;
1806 +       fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1807 +
1808 +       udc = (struct fsl_udc *)ep->udc;
1809 +       spin_lock_irqsave(&udc->lock, flags);
1810 +
1811 +       /* nuke all pending requests (does flush) */
1812 +       nuke(ep, -ESHUTDOWN);
1813 +
1814 +       ep->desc = 0;
1815 +       ep->stopped = 1;
1816 +       spin_unlock_irqrestore(&udc->lock, flags);
1817 +
1818 +       pr_debug("udc: disabled %s OK\n", _ep->name);
1819 +       return 0;
1820 +}
1821 +
1822 +/*---------------------------------------------------------------------
1823 + * allocate a request object used by this endpoint
1824 + * the main operation is to insert the req->queue to the eq->queue
1825 + * Returns the request, or null if one could not be allocated
1826 +*---------------------------------------------------------------------*/
1827 +static struct usb_request *
1828 +fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
1829 +{
1830 +       struct fsl_req *req = NULL;
1831 +
1832 +       req = kzalloc(sizeof *req, gfp_flags);
1833 +       if (!req)
1834 +               return NULL;
1835 +
1836 +       req->req.dma = DMA_ADDR_INVALID;
1837 +       pr_debug("udc: req=0x%p   set req.dma=0x%x\n", req, req->req.dma);
1838 +       INIT_LIST_HEAD(&req->queue);
1839 +
1840 +       return &req->req;
1841 +}
1842 +
1843 +static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
1844 +{
1845 +       struct fsl_req *req;
1846 +
1847 +       req = container_of(_req, struct fsl_req, req);
1848 +       pr_debug("udc: req=0x%p\n", req);
1849 +
1850 +       if (_req)
1851 +               kfree(req);
1852 +}
1853 +
1854 +/*-------------------------------------------------------------------------*/
1855 +static int fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
1856 +{
1857 +       int i = ep_index(ep) * 2 + ep_is_in(ep);
1858 +       u32 temp, bitmask, tmp_stat;
1859 +       struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
1860 +
1861 +       pr_debug("udc: queue req=0x%p to ep index %d\n", req, i);
1862 +
1863 +       bitmask = ep_is_in(ep)
1864 +               ? (1 << (ep_index(ep) + 16))
1865 +               : (1 << (ep_index(ep)));
1866 +
1867 +       /* check if the pipe is empty */
1868 +       if (!(list_empty(&ep->queue))) {
1869 +               /* Add td to the end */
1870 +               struct fsl_req *lastreq;
1871 +               lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
1872 +               lastreq->tail->next_td_ptr =
1873 +                       cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
1874 +               /* Read prime bit, if 1 goto done */
1875 +               if (fsl_readl(&dr_regs->endpointprime) & bitmask)
1876 +                       goto out;
1877 +
1878 +               do {
1879 +                       /* Set ATDTW bit in USBCMD */
1880 +                       temp = fsl_readl(&dr_regs->usbcmd);
1881 +                       fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
1882 +
1883 +                       /* Read correct status bit */
1884 +                       tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
1885 +
1886 +               } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
1887 +
1888 +               /* Write ATDTW bit to 0 */
1889 +               temp = fsl_readl(&dr_regs->usbcmd);
1890 +               fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
1891 +
1892 +               if (tmp_stat)
1893 +                       goto out;
1894 +       }
1895 +
1896 +       /* Write dQH next pointer and terminate bit to 0 */
1897 +       temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
1898 +       dQH->next_dtd_ptr = cpu_to_hc32(temp);
1899 +
1900 +       /* Clear active and halt bit */
1901 +       temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
1902 +                       | EP_QUEUE_HEAD_STATUS_HALT));
1903 +       dQH->size_ioc_int_sts &= temp;
1904 +
1905 +       /* Prime endpoint by writing 1 to ENDPTPRIME */
1906 +       temp = ep_is_in(ep)
1907 +               ? (1 << (ep_index(ep) + 16))
1908 +               : (1 << (ep_index(ep)));
1909 +       fsl_writel(temp, &dr_regs->endpointprime);
1910 +out:
1911 +       return 0;
1912 +}
1913 +
1914 +/* Fill in the dTD structure
1915 + * @req: request that the transfer belongs to
1916 + * @length: return actually data length of the dTD
1917 + * @dma: return dma address of the dTD
1918 + * @is_last: return flag if it is the last dTD of the request
1919 + * return: pointer to the built dTD */
1920 +static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
1921 +               dma_addr_t *dma, int *is_last)
1922 +{
1923 +       u32 swap_temp;
1924 +       struct ep_td_struct *dtd;
1925 +
1926 +       /* how big will this transfer be? */
1927 +       *length = min(req->req.length - req->req.actual,
1928 +                       (unsigned)EP_MAX_LENGTH_TRANSFER);
1929 +
1930 +       dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
1931 +       if (dtd == NULL)
1932 +               return dtd;
1933 +
1934 +       dtd->td_dma = *dma;
1935 +       /* Clear reserved field */
1936 +       swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
1937 +       swap_temp &= ~DTD_RESERVED_FIELDS;
1938 +       dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
1939 +
1940 +       /* Init all of buffer page pointers */
1941 +       swap_temp = (u32) (req->req.dma + req->req.actual);
1942 +       dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
1943 +       dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
1944 +       dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
1945 +       dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
1946 +       dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
1947 +
1948 +       req->req.actual += *length;
1949 +
1950 +       /* zlp is needed if req->req.zero is set */
1951 +       if (req->req.zero) {
1952 +               if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
1953 +                       *is_last = 1;
1954 +               else
1955 +                       *is_last = 0;
1956 +       } else if (req->req.length == req->req.actual)
1957 +               *is_last = 1;
1958 +       else
1959 +               *is_last = 0;
1960 +
1961 +       if ((*is_last) == 0)
1962 +               VDBG("multi-dtd request!\n");
1963 +       /* Fill in the transfer size; set active bit */
1964 +       swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
1965 +
1966 +       /* Enable interrupt for the last dtd of a request */
1967 +       if (*is_last && !req->req.no_interrupt)
1968 +               swap_temp |= DTD_IOC;
1969 +
1970 +       dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
1971 +
1972 +       mb();
1973 +
1974 +       VDBG("length = %d address= 0x%x", *length, (int)*dma);
1975 +
1976 +       return dtd;
1977 +}
1978 +
1979 +/* Generate dtd chain for a request */
1980 +static int fsl_req_to_dtd(struct fsl_req *req)
1981 +{
1982 +       unsigned        count;
1983 +       int             is_last;
1984 +       int             is_first = 1;
1985 +       struct ep_td_struct     *last_dtd = NULL, *dtd;
1986 +       dma_addr_t dma;
1987 +
1988 +       do {
1989 +               dtd = fsl_build_dtd(req, &count, &dma, &is_last);
1990 +               if (dtd == NULL)
1991 +                       return -ENOMEM;
1992 +
1993 +               if (is_first) {
1994 +                       is_first = 0;
1995 +                       req->head = dtd;
1996 +               } else {
1997 +                       last_dtd->next_td_ptr = hc32_to_cpu(dma);
1998 +                       last_dtd->next_td_virt = dtd;
1999 +               }
2000 +               last_dtd = dtd;
2001 +
2002 +               req->dtd_count++;
2003 +       } while (!is_last);
2004 +
2005 +       dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
2006 +
2007 +       req->tail = dtd;
2008 +
2009 +       return 0;
2010 +}
2011 +
2012 +/* queues (submits) an I/O request to an endpoint */
2013 +static int
2014 +fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
2015 +{
2016 +       struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
2017 +       struct fsl_req *req = container_of(_req, struct fsl_req, req);
2018 +       struct fsl_udc *udc;
2019 +       unsigned long flags;
2020 +       int is_iso = 0;
2021 +
2022 +       /* catch various bogus parameters */
2023 +       if (!_req || !req->req.complete || !req->req.buf
2024 +                       || !list_empty(&req->queue)) {
2025 +               VDBG("%s, bad params\n", __FUNCTION__);
2026 +               return -EINVAL;
2027 +       }
2028 +       if (!_ep || (!ep->desc && ep_index(ep))) {
2029 +               VDBG("%s, bad ep\n", __FUNCTION__);
2030 +               return -EINVAL;
2031 +       }
2032 +       if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
2033 +               if (req->req.length > ep->ep.maxpacket)
2034 +                       return -EMSGSIZE;
2035 +               is_iso = 1;
2036 +       }
2037 +
2038 +       udc = ep->udc;
2039 +       if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
2040 +               return -ESHUTDOWN;
2041 +
2042 +       req->ep = ep;
2043 +
2044 +       /* map virtual address to hardware */
2045 +       if (req->req.dma == DMA_ADDR_INVALID) {
2046 +               req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
2047 +                                       req->req.buf,
2048 +                                       req->req.length, ep_is_in(ep)
2049 +                                               ? DMA_TO_DEVICE
2050 +                                               : DMA_FROM_DEVICE);
2051 +               req->mapped = 1;
2052 +       } else {
2053 +               dma_sync_single_for_device(ep->udc->gadget.dev.parent,
2054 +                                       req->req.dma, req->req.length,
2055 +                                       ep_is_in(ep)
2056 +                                               ? DMA_TO_DEVICE
2057 +                                               : DMA_FROM_DEVICE);
2058 +               req->mapped = 0;
2059 +       }
2060 +
2061 +       req->req.status = -EINPROGRESS;
2062 +       req->req.actual = 0;
2063 +       req->dtd_count = 0;
2064 +
2065 +       spin_lock_irqsave(&udc->lock, flags);
2066 +
2067 +       /* build dtds and push them to device queue */
2068 +       if (!fsl_req_to_dtd(req)) {
2069 +               fsl_queue_td(ep, req);
2070 +       } else {
2071 +               spin_unlock_irqrestore(&udc->lock, flags);
2072 +               return -ENOMEM;
2073 +       }
2074 +
2075 +       /* Update ep0 state */
2076 +       if ((ep_index(ep) == 0))
2077 +               udc->ep0_state = DATA_STATE_XMIT;
2078 +
2079 +       /* irq handler advances the queue */
2080 +       if (req != NULL)
2081 +               list_add_tail(&req->queue, &ep->queue);
2082 +       spin_unlock_irqrestore(&udc->lock, flags);
2083 +
2084 +       return 0;
2085 +}
2086 +
2087 +/* dequeues (cancels, unlinks) an I/O request from an endpoint */
2088 +static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
2089 +{
2090 +       struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
2091 +       struct fsl_req *req;
2092 +       unsigned long flags;
2093 +       int ep_num, stopped, ret = 0;
2094 +       u32 epctrl;
2095 +
2096 +       if (!_ep || !_req)
2097 +               return -EINVAL;
2098 +
2099 +       spin_lock_irqsave(&ep->udc->lock, flags);
2100 +       stopped = ep->stopped;
2101 +
2102 +       /* Stop the ep before we deal with the queue */
2103 +       ep->stopped = 1;
2104 +       ep_num = ep_index(ep);
2105 +       epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
2106 +       if (ep_is_in(ep))
2107 +               epctrl &= ~EPCTRL_TX_ENABLE;
2108 +       else
2109 +               epctrl &= ~EPCTRL_RX_ENABLE;
2110 +       fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
2111 +
2112 +       /* make sure it's actually queued on this endpoint */
2113 +       list_for_each_entry(req, &ep->queue, queue) {
2114 +               if (&req->req == _req)
2115 +                       break;
2116 +       }
2117 +       if (&req->req != _req) {
2118 +               ret = -EINVAL;
2119 +               goto out;
2120 +       }
2121 +
2122 +       /* The request is in progress, or completed but not dequeued */
2123 +       if (ep->queue.next == &req->queue) {
2124 +               _req->status = -ECONNRESET;
2125 +               fsl_ep_fifo_flush(_ep); /* flush current transfer */
2126 +
2127 +               /* The request isn't the last request in this ep queue */
2128 +               if (req->queue.next != &ep->queue) {
2129 +                       struct ep_queue_head *qh;
2130 +                       struct fsl_req *next_req;
2131 +
2132 +                       qh = ep->qh;
2133 +                       next_req = list_entry(req->queue.next, struct fsl_req,
2134 +                                       queue);
2135 +
2136 +                       /* Point the QH to the first TD of next request */
2137 +                       fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
2138 +               }
2139 +
2140 +               /* The request hasn't been processed, patch up the TD chain */
2141 +       } else {
2142 +               struct fsl_req *prev_req;
2143 +
2144 +               prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
2145 +               fsl_writel(fsl_readl(&req->tail->next_td_ptr),
2146 +                               &prev_req->tail->next_td_ptr);
2147 +
2148 +       }
2149 +
2150 +       done(ep, req, -ECONNRESET);
2151 +
2152 +       /* Enable EP */
2153 +out:   epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
2154 +       if (ep_is_in(ep))
2155 +               epctrl |= EPCTRL_TX_ENABLE;
2156 +       else
2157 +               epctrl |= EPCTRL_RX_ENABLE;
2158 +       fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
2159 +       ep->stopped = stopped;
2160 +
2161 +       spin_unlock_irqrestore(&ep->udc->lock, flags);
2162 +       return ret;
2163 +}
2164 +
2165 +/*-------------------------------------------------------------------------*/
2166 +
2167 +/*-----------------------------------------------------------------
2168 + * modify the endpoint halt feature
2169 + * @ep: the non-isochronous endpoint being stalled
2170 + * @value: 1--set halt  0--clear halt
2171 + * Returns zero, or a negative error code.
2172 +*----------------------------------------------------------------*/
2173 +static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
2174 +{
2175 +       struct fsl_ep *ep = NULL;
2176 +       unsigned long flags = 0;
2177 +       int status = -EOPNOTSUPP;       /* operation not supported */
2178 +       unsigned char ep_dir = 0, ep_num = 0;
2179 +       struct fsl_udc *udc = NULL;
2180 +
2181 +       ep = container_of(_ep, struct fsl_ep, ep);
2182 +       udc = ep->udc;
2183 +       if (!_ep || !ep->desc) {
2184 +               status = -EINVAL;
2185 +               goto out;
2186 +       }
2187 +
2188 +       if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
2189 +               status = -EOPNOTSUPP;
2190 +               goto out;
2191 +       }
2192 +
2193 +       /* Attempt to halt IN ep will fail if any transfer requests
2194 +        * are still queue */
2195 +       if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
2196 +               status = -EAGAIN;
2197 +               goto out;
2198 +       }
2199 +
2200 +       status = 0;
2201 +       ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
2202 +       ep_num = (unsigned char)(ep_index(ep));
2203 +       spin_lock_irqsave(&ep->udc->lock, flags);
2204 +       dr_ep_change_stall(ep_num, ep_dir, value);
2205 +       spin_unlock_irqrestore(&ep->udc->lock, flags);
2206 +
2207 +       if (ep_index(ep) == 0) {
2208 +               udc->ep0_state = WAIT_FOR_SETUP;
2209 +               udc->ep0_dir = 0;
2210 +       }
2211 +out:
2212 +       VDBG(" %s %s halt stat %d", ep->ep.name,
2213 +                       value ?  "set" : "clear", status);
2214 +
2215 +       return status;
2216 +}
2217 +
2218 +static void fsl_ep_fifo_flush(struct usb_ep *_ep)
2219 +{
2220 +       struct fsl_ep *ep;
2221 +       int ep_num, ep_dir;
2222 +       u32 bits;
2223 +       unsigned long timeout;
2224 +#define FSL_UDC_FLUSH_TIMEOUT 1000
2225 +
2226 +       if (!_ep) {
2227 +               return;
2228 +       } else {
2229 +               ep = container_of(_ep, struct fsl_ep, ep);
2230 +               if (!ep->desc)
2231 +                       return;
2232 +       }
2233 +       ep_num = ep_index(ep);
2234 +       ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
2235 +
2236 +       if (ep_num == 0)
2237 +               bits = (1 << 16) | 1;
2238 +       else if (ep_dir == USB_SEND)
2239 +               bits = 1 << (16 + ep_num);
2240 +       else
2241 +               bits = 1 << ep_num;
2242 +
2243 +       timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
2244 +       do {
2245 +               fsl_writel(bits, &dr_regs->endptflush);
2246 +
2247 +               /* Wait until flush complete */
2248 +               while (fsl_readl(&dr_regs->endptflush)) {
2249 +                       if (time_after(jiffies, timeout)) {
2250 +                               ERR("ep flush timeout\n");
2251 +                               return;
2252 +                       }
2253 +                       cpu_relax();
2254 +               }
2255 +               /* See if we need to flush again */
2256 +       } while (fsl_readl(&dr_regs->endptstatus) & bits);
2257 +}
2258 +
2259 +static struct usb_ep_ops fsl_ep_ops = {
2260 +       .enable = fsl_ep_enable,
2261 +       .disable = fsl_ep_disable,
2262 +
2263 +       .alloc_request = fsl_alloc_request,
2264 +       .free_request = fsl_free_request,
2265 +
2266 +       .queue = fsl_ep_queue,
2267 +       .dequeue = fsl_ep_dequeue,
2268 +
2269 +       .set_halt = fsl_ep_set_halt,
2270 +       .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
2271 +};
2272 +
2273 +/*-------------------------------------------------------------------------
2274 +               Gadget Driver Layer Operations
2275 +-------------------------------------------------------------------------*/
2276 +
2277 +/*----------------------------------------------------------------------
2278 + * Get the current frame number (from DR frame_index Reg )
2279 + *----------------------------------------------------------------------*/
2280 +static int fsl_get_frame(struct usb_gadget *gadget)
2281 +{
2282 +       return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
2283 +}
2284 +
2285 +/*-----------------------------------------------------------------------
2286 + * Tries to wake up the host connected to this gadget
2287 + -----------------------------------------------------------------------*/
2288 +static int fsl_wakeup(struct usb_gadget *gadget)
2289 +{
2290 +       struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
2291 +       u32 portsc;
2292 +
2293 +       /* Remote wakeup feature not enabled by host */
2294 +       if (!udc->remote_wakeup)
2295 +               return -ENOTSUPP;
2296 +
2297 +       portsc = fsl_readl(&dr_regs->portsc1);
2298 +       /* not suspended? */
2299 +       if (!(portsc & PORTSCX_PORT_SUSPEND))
2300 +               return 0;
2301 +       /* trigger force resume */
2302 +       portsc |= PORTSCX_PORT_FORCE_RESUME;
2303 +       fsl_writel(portsc, &dr_regs->portsc1);
2304 +       return 0;
2305 +}
2306 +
2307 +static int can_pullup(struct fsl_udc *udc)
2308 +{
2309 +       return udc->driver && udc->softconnect && udc->vbus_active;
2310 +}
2311 +
2312 +/*
2313 + * Notify controller that VBUS is powered, Called by whatever
2314 + * detects VBUS sessions
2315 + * @param gadger    gadger pointer
2316 + * @param is_active is active?
2317 + * @return Returns zero on success , or a negative error code
2318 + */
2319 +static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
2320 +{
2321 +       struct fsl_udc  *udc;
2322 +       unsigned long   flags;
2323 +
2324 +       udc = container_of(gadget, struct fsl_udc, gadget);
2325 +       spin_lock_irqsave(&udc->lock, flags);
2326 +
2327 +       pr_debug("udc: VBUS %s\n", is_active ? "on" : "off");
2328 +       udc->vbus_active = (is_active != 0);
2329 +
2330 +       if (can_pullup(udc)) {
2331 +               pullup_enable(udc);
2332 +               udc_controller->usb_state = USB_STATE_ATTACHED;
2333 +       } else {
2334 +               pullup_disable(udc);
2335 +               udc_controller->usb_state = USB_STATE_NOTATTACHED;
2336 +       }
2337 +       udc_controller->ep0_state = WAIT_FOR_SETUP;
2338 +       udc_controller->ep0_dir = 0;
2339 +
2340 +       spin_unlock_irqrestore(&udc->lock, flags);
2341 +       return 0;
2342 +}
2343 +
2344 +/* constrain controller's VBUS power usage
2345 + * This call is used by gadget drivers during SET_CONFIGURATION calls,
2346 + * reporting how much power the device may consume.  For example, this
2347 + * could affect how quickly batteries are recharged.
2348 + *
2349 + * Returns zero on success, else negative errno.
2350 + */
2351 +static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
2352 +{
2353 +#ifdef CONFIG_USB_OTG
2354 +       struct fsl_udc *udc;
2355 +
2356 +       udc = container_of(gadget, struct fsl_udc, gadget);
2357 +
2358 +       if (udc->transceiver)
2359 +               return otg_set_power(udc->transceiver, mA);
2360 +#endif
2361 +       return -ENOTSUPP;
2362 +}
2363 +
2364 +/*
2365 + * Change Data+ pullup status
2366 + * this func is used by usb_gadget_connect/disconnet
2367 + */
2368 +static int fsl_pullup(struct usb_gadget *gadget, int is_on)
2369 +{
2370 +       struct fsl_udc *udc;
2371 +
2372 +       udc = container_of(gadget, struct fsl_udc, gadget);
2373 +       udc->softconnect = (is_on != 0);
2374 +       if (can_pullup(udc))
2375 +               fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
2376 +                               &dr_regs->usbcmd);
2377 +       else
2378 +               fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
2379 +                               &dr_regs->usbcmd);
2380 +
2381 +       return 0;
2382 +}
2383 +
2384 +/* defined in usb_gadget.h */
2385 +static struct usb_gadget_ops fsl_gadget_ops = {
2386 +       .get_frame = fsl_get_frame,
2387 +       .wakeup = fsl_wakeup,
2388 +       .vbus_session = fsl_vbus_session,
2389 +       .vbus_draw = fsl_vbus_draw,
2390 +       .pullup = fsl_pullup,
2391 +};
2392 +
2393 +/* Set protocol stall on ep0, protocol stall will automatically be cleared
2394 +   on new transaction */
2395 +static void ep0stall(struct fsl_udc *udc)
2396 +{
2397 +       u32 tmp;
2398 +
2399 +       /* must set tx and rx to stall at the same time */
2400 +       tmp = fsl_readl(&dr_regs->endptctrl[0]);
2401 +       tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
2402 +       fsl_writel(tmp, &dr_regs->endptctrl[0]);
2403 +       udc->ep0_state = WAIT_FOR_SETUP;
2404 +       udc->ep0_dir = 0;
2405 +}
2406 +
2407 +/* Prime a status phase for ep0 */
2408 +static int ep0_prime_status(struct fsl_udc *udc, int direction)
2409 +{
2410 +       struct fsl_req *req = udc->status_req;
2411 +       struct fsl_ep *ep;
2412 +       int status = 0;
2413 +
2414 +       if (direction == EP_DIR_IN)
2415 +               udc->ep0_dir = USB_DIR_IN;
2416 +       else
2417 +               udc->ep0_dir = USB_DIR_OUT;
2418 +
2419 +       ep = &udc->eps[0];
2420 +       udc->ep0_state = WAIT_FOR_OUT_STATUS;
2421 +
2422 +       req->ep = ep;
2423 +       req->req.length = 0;
2424 +       req->req.status = -EINPROGRESS;
2425 +       req->req.actual = 0;
2426 +       req->req.complete = NULL;
2427 +       req->dtd_count = 0;
2428 +
2429 +       if (fsl_req_to_dtd(req) == 0)
2430 +               status = fsl_queue_td(ep, req);
2431 +       else
2432 +               return -ENOMEM;
2433 +
2434 +       if (status)
2435 +               ERR("Can't queue ep0 status request \n");
2436 +       list_add_tail(&req->queue, &ep->queue);
2437 +
2438 +       return status;
2439 +}
2440 +
2441 +static inline int udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
2442 +{
2443 +       struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
2444 +
2445 +       if (!ep->name)
2446 +               return 0;
2447 +
2448 +       nuke(ep, -ESHUTDOWN);
2449 +
2450 +       return 0;
2451 +}
2452 +
2453 +/*
2454 + * ch9 Set address
2455 + */
2456 +static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
2457 +{
2458 +       /* Save the new address to device struct */
2459 +       udc->device_address = (u8) value;
2460 +       /* Update usb state */
2461 +       udc->usb_state = USB_STATE_ADDRESS;
2462 +       /* Status phase */
2463 +       if (ep0_prime_status(udc, EP_DIR_IN))
2464 +               ep0stall(udc);
2465 +}
2466 +
2467 +/*
2468 + * ch9 Get status
2469 + */
2470 +static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
2471 +                        u16 index, u16 length)
2472 +{
2473 +       u16 tmp = 0;            /* Status, cpu endian */
2474 +
2475 +       struct fsl_req *req;
2476 +       struct fsl_ep *ep;
2477 +       int status = 0;
2478 +
2479 +       ep = &udc->eps[0];
2480 +
2481 +       if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
2482 +               /* Get device status */
2483 +               tmp = 1 << USB_DEVICE_SELF_POWERED;
2484 +               tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
2485 +       } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
2486 +               /* Get interface status */
2487 +               /* We don't have interface information in udc driver */
2488 +               tmp = 0;
2489 +       } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
2490 +               /* Get endpoint status */
2491 +               struct fsl_ep *target_ep;
2492 +
2493 +               target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
2494 +
2495 +               /* stall if endpoint doesn't exist */
2496 +               if (!target_ep->desc)
2497 +                       goto stall;
2498 +               tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
2499 +                               << USB_ENDPOINT_HALT;
2500 +       }
2501 +
2502 +       udc->ep0_dir = USB_DIR_IN;
2503 +       /* Borrow the per device status_req */
2504 +       req = udc->status_req;
2505 +       /* Fill in the reqest structure */
2506 +       *((u16 *) req->req.buf) = cpu_to_le16(tmp);
2507 +       req->ep = ep;
2508 +       req->req.length = 2;
2509 +       req->req.status = -EINPROGRESS;
2510 +       req->req.actual = 0;
2511 +       req->req.complete = NULL;
2512 +       req->dtd_count = 0;
2513 +
2514 +       /* prime the data phase */
2515 +       if ((fsl_req_to_dtd(req) == 0))
2516 +               status = fsl_queue_td(ep, req);
2517 +       else                    /* no mem */
2518 +               goto stall;
2519 +
2520 +       if (status) {
2521 +               ERR("Can't respond to getstatus request \n");
2522 +               goto stall;
2523 +       }
2524 +       list_add_tail(&req->queue, &ep->queue);
2525 +       udc->ep0_state = DATA_STATE_XMIT;
2526 +       return;
2527 +stall:
2528 +       ep0stall(udc);
2529 +}
2530 +
2531 +static void ch9setconfig(struct fsl_udc *udc, u16 value, u16 index,
2532 +                        u16 length)
2533 +{
2534 +       pr_debug("udc: 1 calling gadget driver->setup\n");
2535 +       udc->ep0_dir = USB_DIR_IN;
2536 +       if (udc->driver->setup(&udc->gadget, &udc->local_setup_buff) >= 0) {
2537 +               /* gadget layer deal with the status phase */
2538 +               udc->usb_state = USB_STATE_CONFIGURED;
2539 +               udc->ep0_state = WAIT_FOR_OUT_STATUS;
2540 +               pr_debug("udc: ep0_state now WAIT_FOR_OUT_STATUS\n");
2541 +       }
2542 +}
2543 +
2544 +static void setup_received_irq(struct fsl_udc *udc,
2545 +                              struct usb_ctrlrequest *setup)
2546 +{
2547 +       u32 tmp;
2548 +       u16 ptc = 0;            /* port test control */
2549 +       int handled = 1;        /* set to zero if we do not handle the message,
2550 +                                  and should pass it to the gadget driver */
2551 +
2552 +       /*
2553 +        * gadget drivers expect the setup pkt to be in wire format,
2554 +        * so leave it alone and make local copies of stuff we need.
2555 +        */
2556 +       u16 wValue = le16_to_cpu(setup->wValue);
2557 +       u16 wIndex = le16_to_cpu(setup->wIndex);
2558 +       u16 wLength = le16_to_cpu(setup->wLength);
2559 +
2560 +
2561 +       pr_debug("udc: request=0x%x\n", setup->bRequest);
2562 +
2563 +       udc_reset_ep_queue(udc, 0);
2564 +
2565 +       /* We asume setup only occurs on EP0 */
2566 +       if (setup->bRequestType & USB_DIR_IN)
2567 +               udc->ep0_dir = USB_DIR_IN;
2568 +       else
2569 +               udc->ep0_dir = USB_DIR_OUT;
2570 +
2571 +       if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS) {
2572 +               /* handle class requests */
2573 +               switch (setup->bRequest) {
2574 +
2575 +               case USB_BULK_RESET_REQUEST:
2576 +                       udc->ep0_dir = USB_DIR_IN;
2577 +                       if (udc->driver->setup(&udc->gadget,
2578 +                                              &udc->local_setup_buff) >= 0) {
2579 +                               udc->ep0_state = WAIT_FOR_SETUP;
2580 +                               pr_debug("udc: ep0_state now WAIT_FOR_SETUP\n");
2581 +                       }
2582 +                       break;
2583 +
2584 +               default:
2585 +                       handled = 0;
2586 +                       break;
2587 +               }
2588 +       } else if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
2589 +               /* handle standard requests */
2590 +               switch (setup->bRequest) {
2591 +
2592 +               case USB_REQ_GET_STATUS:
2593 +                       if ((setup->
2594 +                            bRequestType & (USB_DIR_IN | USB_TYPE_STANDARD))
2595 +                           != (USB_DIR_IN | USB_TYPE_STANDARD))
2596 +                               break;
2597 +                       ch9getstatus(udc, setup->bRequestType, wValue, wIndex,
2598 +                                    wLength);
2599 +                       break;
2600 +
2601 +               case USB_REQ_SET_ADDRESS:
2602 +                       if (setup->bRequestType !=
2603 +                           (USB_DIR_OUT | USB_TYPE_STANDARD |
2604 +                            USB_RECIP_DEVICE))
2605 +                               break;
2606 +                       ch9setaddress(udc, wValue, wIndex, wLength);
2607 +                       break;
2608 +
2609 +               case USB_REQ_SET_CONFIGURATION:
2610 +                       if (setup->bRequestType !=
2611 +                           (USB_DIR_OUT | USB_TYPE_STANDARD |
2612 +                            USB_RECIP_DEVICE))
2613 +                               break;
2614 +                       /* gadget layer take over the status phase */
2615 +                       ch9setconfig(udc, wValue, wIndex, wLength);
2616 +                       break;
2617 +               case USB_REQ_SET_INTERFACE:
2618 +                       if (setup->bRequestType !=
2619 +                           (USB_DIR_OUT | USB_TYPE_STANDARD |
2620 +                            USB_RECIP_INTERFACE))
2621 +                               break;
2622 +                       udc->ep0_dir = USB_DIR_IN;
2623 +                       if (udc->driver->setup(&udc->gadget,
2624 +                                              &udc->local_setup_buff) >= 0)
2625 +                               /* gadget layer take over the status phase */
2626 +                               break;
2627 +                       /* Requests with no data phase */
2628 +               case USB_REQ_CLEAR_FEATURE:
2629 +               case USB_REQ_SET_FEATURE:
2630 +                       {       /* status transaction */
2631 +                               int rc = -EOPNOTSUPP;
2632 +
2633 +                               if ((setup->bRequestType & USB_TYPE_MASK) !=
2634 +                                   USB_TYPE_STANDARD)
2635 +                                       break;
2636 +
2637 +                               /* we only support set/clear feature for
2638 +                                * endpoint */
2639 +                               if (setup->bRequestType == USB_RECIP_ENDPOINT) {
2640 +                                       int dir = (wIndex & 0x0080) ?
2641 +                                           EP_DIR_IN : EP_DIR_OUT;
2642 +                                       int num = (wIndex & 0x000f);
2643 +                                       struct fsl_ep *ep;
2644 +
2645 +                                       if (wValue != 0
2646 +                                           || wLength != 0
2647 +                                           || (num * 2 + dir) > udc->max_ep)
2648 +                                               break;
2649 +                                       ep = &udc->eps[num * 2 + dir];
2650 +
2651 +                                       if (setup->bRequest ==
2652 +                                           USB_REQ_SET_FEATURE) {
2653 +                                               pr_debug("udc: udc: SET_FEATURE"
2654 +                                                        " doing set_halt\n");
2655 +                                               rc = fsl_ep_set_halt(&ep-> ep,
2656 +                                                                    1);
2657 +                                       } else {
2658 +                                               pr_debug("udc: CLEAR_FEATURE"
2659 +                                                        " doing clear_halt\n");
2660 +                                               rc = fsl_ep_set_halt(&ep-> ep,
2661 +                                                                    0);
2662 +                                       }
2663 +
2664 +                               } else if (setup->bRequestType ==
2665 +                                          USB_RECIP_DEVICE) {
2666 +                                       if (setup->bRequest ==
2667 +                                           USB_REQ_SET_FEATURE) {
2668 +                                               ptc = wIndex >> 8;
2669 +                                               rc = 0;
2670 +                                       }
2671 +                                       if (!udc->gadget.is_otg)
2672 +                                               break;
2673 +                                       else if (setup->bRequest ==
2674 +                                                USB_DEVICE_B_HNP_ENABLE)
2675 +                                               udc->gadget.b_hnp_enable = 1;
2676 +                                       else if (setup->bRequest ==
2677 +                                                USB_DEVICE_A_HNP_SUPPORT)
2678 +                                               udc->gadget.a_hnp_support = 1;
2679 +                                       else if (setup->bRequest ==
2680 +                                                USB_DEVICE_A_ALT_HNP_SUPPORT)
2681 +                                               udc->gadget.a_alt_hnp_support =
2682 +                                                   1;
2683 +                                       rc = 0;
2684 +                               }
2685 +                               if (rc == 0) {
2686 +                                       /* send status only if
2687 +                                        * fsl_ep_set_halt success */
2688 +                                       if (ep0_prime_status(udc, EP_DIR_IN))
2689 +                                               ep0stall(udc);
2690 +                               }
2691 +                               break;
2692 +                       }
2693 +               default:
2694 +                       handled = 0;
2695 +                       break;
2696 +               }
2697 +       } else {
2698 +               /* vendor requests */
2699 +               handled = 0;
2700 +       }
2701 +
2702 +       if (!handled) {
2703 +               if (udc->driver->setup(&udc->gadget, &udc->local_setup_buff)
2704 +                   != 0) {
2705 +                       ep0stall(udc);
2706 +               } else if (setup->bRequestType & USB_DIR_IN) {
2707 +                       udc->ep0_state = DATA_STATE_XMIT;
2708 +                       pr_debug("udc: ep0_state now DATA_STATE_XMIT\n");
2709 +               } else {
2710 +                       udc->ep0_state = DATA_STATE_RECV;
2711 +                       pr_debug("udc: ep0_state now DATA_STATE_RECV\n");
2712 +               }
2713 +       }
2714 +
2715 +       if (ptc) {
2716 +               tmp =fsl_readl(&dr_regs->portsc1) | ptc << 16;
2717 +               fsl_writel(tmp, &dr_regs->portsc1);
2718 +               pr_debug("udc: switch to test mode.\n");
2719 +       }
2720 +}
2721 +
2722 +/* Process request for Data or Status phase of ep0
2723 + * prime status phase if needed */
2724 +static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
2725 +               struct fsl_req *req)
2726 +{
2727 +       if (udc->usb_state == USB_STATE_ADDRESS) {
2728 +               /* Set the new address */
2729 +               u32 new_address = (u32) udc->device_address;
2730 +               fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
2731 +                               &dr_regs->deviceaddr);
2732 +       }
2733 +
2734 +       done(ep0, req, 0);
2735 +
2736 +       switch (udc->ep0_state) {
2737 +       case DATA_STATE_XMIT:
2738 +               /* receive status phase */
2739 +               if (ep0_prime_status(udc, EP_DIR_OUT))
2740 +                       ep0stall(udc);
2741 +               break;
2742 +       case DATA_STATE_RECV:
2743 +               /* send status phase */
2744 +               if (ep0_prime_status(udc, EP_DIR_IN))
2745 +                       ep0stall(udc);
2746 +               break;
2747 +       case WAIT_FOR_OUT_STATUS:
2748 +               udc->ep0_state = WAIT_FOR_SETUP;
2749 +               break;
2750 +       case WAIT_FOR_SETUP:
2751 +               ERR("Unexpect ep0 packets \n");
2752 +               break;
2753 +       default:
2754 +               ep0stall(udc);
2755 +               break;
2756 +       }
2757 +}
2758 +
2759 +/* Tripwire mechanism to ensure a setup packet payload is extracted without
2760 + * being corrupted by another incoming setup packet */
2761 +static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
2762 +{
2763 +       u32 temp;
2764 +       struct ep_queue_head *qh;
2765 +       struct fsl_usb2_platform_data *pdata = udc->pdata;
2766 +
2767 +       qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
2768 +
2769 +       /* Clear bit in ENDPTSETUPSTAT */
2770 +       temp = fsl_readl(&dr_regs->endptsetupstat);
2771 +       fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
2772 +
2773 +       /* while a hazard exists when setup package arrives */
2774 +       do {
2775 +               /* Set Setup Tripwire */
2776 +               temp = fsl_readl(&dr_regs->usbcmd);
2777 +               fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
2778 +
2779 +               /* Copy the setup packet to local buffer */
2780 +               if (pdata->le_setup_buf) {
2781 +                       u32 *p = (u32 *)buffer_ptr;
2782 +                       u32 *s = (u32 *)qh->setup_buffer;
2783 +
2784 +                       /* Convert little endian setup buffer to CPU endian */
2785 +                       *p++ = le32_to_cpu(*s++);
2786 +                       *p = le32_to_cpu(*s);
2787 +               } else {
2788 +                       memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
2789 +               }
2790 +       } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
2791 +
2792 +       /* Clear Setup Tripwire */
2793 +       temp = fsl_readl(&dr_regs->usbcmd);
2794 +       fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
2795 +}
2796 +
2797 +/* process-ep_req(): free the completed Tds for this req */
2798 +static int process_ep_req(struct fsl_udc *udc, int pipe,
2799 +               struct fsl_req *curr_req)
2800 +{
2801 +       struct ep_td_struct *curr_td;
2802 +       int     td_complete, actual, remaining_length, j, tmp;
2803 +       int     status = 0;
2804 +       int     errors = 0;
2805 +       struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
2806 +       int direction = pipe % 2;
2807 +
2808 +       curr_td = curr_req->head;
2809 +       td_complete = 0;
2810 +       actual = curr_req->req.length;
2811 +
2812 +       for (j = 0; j < curr_req->dtd_count; j++) {
2813 +               remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
2814 +                                       & DTD_PACKET_SIZE)
2815 +                               >> DTD_LENGTH_BIT_POS;
2816 +               actual -= remaining_length;
2817 +
2818 +               (errors = hc32_to_cpu(curr_td->size_ioc_sts) & DTD_ERROR_MASK);
2819 +               if (errors) {
2820 +                       if (errors & DTD_STATUS_HALTED) {
2821 +                               ERR("dTD error %08x QH=%d\n", errors, pipe);
2822 +                               /* Clear the errors and Halt condition */
2823 +                               tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
2824 +                               tmp &= ~errors;
2825 +                               curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
2826 +                               status = -EPIPE;
2827 +                               /* FIXME: continue with next queued TD? */
2828 +
2829 +                               break;
2830 +                       }
2831 +                       if (errors & DTD_STATUS_DATA_BUFF_ERR) {
2832 +                               VDBG("Transfer overflow");
2833 +                               status = -EPROTO;
2834 +                               break;
2835 +                       } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
2836 +                               VDBG("ISO error");
2837 +                               status = -EILSEQ;
2838 +                               break;
2839 +                       } else
2840 +                               ERR("Unknown error has occured (0x%x)!\r\n",
2841 +                                       errors);
2842 +
2843 +               } else if (hc32_to_cpu(curr_td->size_ioc_sts) &
2844 +                                       DTD_STATUS_ACTIVE) {
2845 +                       VDBG("Request not complete");
2846 +                       status = REQ_UNCOMPLETE;
2847 +                       return status;
2848 +               } else if (remaining_length) {
2849 +                       if (direction) {
2850 +                               VDBG("Transmit dTD remaining length not zero");
2851 +                               status = -EPROTO;
2852 +                               break;
2853 +                       } else {
2854 +                               td_complete++;
2855 +                               break;
2856 +                       }
2857 +               } else {
2858 +                       td_complete++;
2859 +                       VDBG("dTD transmitted successful ");
2860 +               }
2861 +
2862 +               if (j != curr_req->dtd_count - 1)
2863 +                       curr_td = curr_td->next_td_virt;
2864 +       }
2865 +
2866 +       if (status)
2867 +               return status;
2868 +
2869 +       curr_req->req.actual = actual;
2870 +
2871 +       return 0;
2872 +}
2873 +
2874 +/* Process a DTD completion interrupt */
2875 +static void dtd_complete_irq(struct fsl_udc *udc)
2876 +{
2877 +       u32 bit_pos;
2878 +       int i, ep_num, direction, bit_mask, status;
2879 +       struct fsl_ep *curr_ep;
2880 +       struct fsl_req *curr_req, *temp_req;
2881 +
2882 +       /* Clear the bits in the register */
2883 +       bit_pos = fsl_readl(&dr_regs->endptcomplete);
2884 +       fsl_writel(bit_pos, &dr_regs->endptcomplete);
2885 +
2886 +       if (!bit_pos)
2887 +               return;
2888 +
2889 +       for (i = 0; i < udc->max_ep * 2; i++) {
2890 +               ep_num = i >> 1;
2891 +               direction = i % 2;
2892 +
2893 +               bit_mask = 1 << (ep_num + 16 * direction);
2894 +
2895 +               if (!(bit_pos & bit_mask))
2896 +                       continue;
2897 +
2898 +               curr_ep = get_ep_by_pipe(udc, i);
2899 +
2900 +               /* If the ep is configured */
2901 +               if (curr_ep->name == NULL) {
2902 +                       WARN("Invalid EP?");
2903 +                       continue;
2904 +               }
2905 +
2906 +               /* process the req queue until an uncomplete request */
2907 +               list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
2908 +                               queue) {
2909 +                       status = process_ep_req(udc, i, curr_req);
2910 +
2911 +                       VDBG("status of process_ep_req= %d, ep = %d",
2912 +                                       status, ep_num);
2913 +                       if (status == REQ_UNCOMPLETE)
2914 +                               break;
2915 +                       /* write back status to req */
2916 +                       curr_req->req.status = status;
2917 +
2918 +                       if (ep_num == 0) {
2919 +                               ep0_req_complete(udc, curr_ep, curr_req);
2920 +                               break;
2921 +                       } else {
2922 +                               done(curr_ep, curr_req, status);
2923 +                       }
2924 +               }
2925 +       }
2926 +}
2927 +
2928 +/* Process a port change interrupt */
2929 +static void port_change_irq(struct fsl_udc *udc)
2930 +{
2931 +       u32 speed;
2932 +
2933 +       VDBG("portsc=0x%x", fsl_readl(&dr_regs->portsc1) );
2934 +       if (udc->bus_reset)
2935 +               udc->bus_reset = 0;
2936 +
2937 +       /* Bus resetting is finished */
2938 +       if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
2939 +               /* Get the speed */
2940 +               speed = fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SPEED_MASK;
2941 +               switch (speed) {
2942 +               case PORTSCX_PORT_SPEED_HIGH:
2943 +                       udc->gadget.speed = USB_SPEED_HIGH;
2944 +                       break;
2945 +               case PORTSCX_PORT_SPEED_FULL:
2946 +                       udc->gadget.speed = USB_SPEED_FULL;
2947 +                       break;
2948 +               case PORTSCX_PORT_SPEED_LOW:
2949 +                       udc->gadget.speed = USB_SPEED_LOW;
2950 +                       break;
2951 +               default:
2952 +                       udc->gadget.speed = USB_SPEED_UNKNOWN;
2953 +                       break;
2954 +               }
2955 +       }
2956 +
2957 +       /* Update USB state */
2958 +       if (!udc->resume_state)
2959 +               udc->usb_state = USB_STATE_DEFAULT;
2960 +}
2961 +
2962 +/* Process suspend interrupt */
2963 +static void suspend_irq(struct fsl_udc *udc)
2964 +{
2965 +       udc->resume_state = udc->usb_state;
2966 +       udc->usb_state = USB_STATE_SUSPENDED;
2967 +
2968 +       /* report suspend to the driver, serial.c does not support this */
2969 +       if (udc->driver->suspend)
2970 +               udc->driver->suspend(&udc->gadget);
2971 +}
2972 +
2973 +static void bus_resume(struct fsl_udc *udc)
2974 +{
2975 +       udc->usb_state = udc->resume_state;
2976 +       udc->resume_state = 0;
2977 +
2978 +       /* report resume to the driver, serial.c does not support this */
2979 +       if (udc->driver->resume)
2980 +               udc->driver->resume(&udc->gadget);
2981 +}
2982 +
2983 +/* Clear up all ep queues */
2984 +static int reset_queues(struct fsl_udc *udc)
2985 +{
2986 +       u8 pipe;
2987 +
2988 +       for (pipe = 0; pipe < udc->max_pipes; pipe++)
2989 +               udc_reset_ep_queue(udc, pipe);
2990 +
2991 +       /* report disconnect; the driver is already quiesced */
2992 +       udc->driver->disconnect(&udc->gadget);
2993 +
2994 +       return 0;
2995 +}
2996 +
2997 +/* Process reset interrupt */
2998 +static void reset_irq(struct fsl_udc *udc)
2999 +{
3000 +       u32 temp;
3001 +       unsigned long timeout;
3002 +
3003 +       /* Clear the device address */
3004 +       temp = fsl_readl(&dr_regs->deviceaddr);
3005 +       fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
3006 +
3007 +       udc->device_address = 0;
3008 +
3009 +       /* Clear usb state */
3010 +       udc->resume_state = 0;
3011 +       udc->ep0_dir = 0;
3012 +       udc->ep0_state = WAIT_FOR_SETUP;
3013 +       udc->remote_wakeup = 0; /* default to 0 on reset */
3014 +       udc->gadget.b_hnp_enable = 0;
3015 +       udc->gadget.a_hnp_support = 0;
3016 +       udc->gadget.a_alt_hnp_support = 0;
3017 +
3018 +       /* Clear all the setup token semaphores */
3019 +       temp = fsl_readl(&dr_regs->endptsetupstat);
3020 +       fsl_writel(temp, &dr_regs->endptsetupstat);
3021 +
3022 +       /* Clear all the endpoint complete status bits */
3023 +       temp = fsl_readl(&dr_regs->endptcomplete);
3024 +       fsl_writel(temp, &dr_regs->endptcomplete);
3025 +
3026 +       timeout = jiffies + 100;
3027 +       while (fsl_readl(&dr_regs->endpointprime)) {
3028 +               /* Wait until all endptprime bits cleared */
3029 +               if (time_after(jiffies, timeout)) {
3030 +                       ERR("Timeout for reset\n");
3031 +                       break;
3032 +               }
3033 +               cpu_relax();
3034 +       }
3035 +
3036 +       /* Write 1s to the flush register */
3037 +       fsl_writel(0xffffffff, &dr_regs->endptflush);
3038 +
3039 +       if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
3040 +               VDBG("Bus reset");
3041 +               /* Bus is reseting */
3042 +               udc->bus_reset = 1;
3043 +               /* Reset all the queues, include XD, dTD, EP queue
3044 +                * head and TR Queue */
3045 +               reset_queues(udc);
3046 +               udc->usb_state = USB_STATE_DEFAULT;
3047 +       } else {
3048 +               VDBG("Controller reset");
3049 +               /* initialize usb hw reg except for regs for EP, not
3050 +                * touch usbintr reg */
3051 +               dr_controller_setup(udc);
3052 +
3053 +               /* Reset all internal used Queues */
3054 +               reset_queues(udc);
3055 +
3056 +               ep0_setup(udc);
3057 +
3058 +               /* Enable DR IRQ reg, Set Run bit, change udc state */
3059 +               dr_controller_run(udc);
3060 +               udc->usb_state = USB_STATE_ATTACHED;
3061 +       }
3062 +}
3063 +
3064 +/*
3065 + * USB device controller interrupt handler
3066 + */
3067 +static irqreturn_t fsl_udc_irq(int irq, void *_udc)
3068 +{
3069 +       struct fsl_udc *udc = _udc;
3070 +       u32 irq_src;
3071 +       irqreturn_t status = IRQ_NONE;
3072 +       unsigned long flags;
3073 +
3074 +       /* Disable ISR for OTG host mode */
3075 +       if (udc->stopped)
3076 +               return IRQ_NONE;
3077 +       spin_lock_irqsave(&udc->lock, flags);
3078 +       irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
3079 +       /* Clear notification bits */
3080 +       fsl_writel(irq_src, &dr_regs->usbsts);
3081 +
3082 +       VDBG("irq_src [0x%8x]  portsc=0x%x", irq_src,
3083 +            fsl_readl(&dr_regs->portsc1));
3084 +
3085 +       /* Need to resume? */
3086 +       if (udc->usb_state == USB_STATE_SUSPENDED)
3087 +               if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
3088 +                       bus_resume(udc);
3089 +
3090 +       /* USB Interrupt */
3091 +       if (irq_src & USB_STS_INT) {
3092 +               VDBG("Packet int");
3093 +               /* Setup package, we only support ep0 as control ep */
3094 +               if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
3095 +                       tripwire_handler(udc, 0,
3096 +                                       (u8 *) (&udc->local_setup_buff));
3097 +                       setup_received_irq(udc, &udc->local_setup_buff);
3098 +                       status = IRQ_HANDLED;
3099 +               }
3100 +
3101 +               /* completion of dtd */
3102 +               if (fsl_readl(&dr_regs->endptcomplete)) {
3103 +                       dtd_complete_irq(udc);
3104 +                       status = IRQ_HANDLED;
3105 +               }
3106 +       }
3107 +
3108 +       /* SOF (for ISO transfer) */
3109 +       if (irq_src & USB_STS_SOF) {
3110 +               status = IRQ_HANDLED;
3111 +       }
3112 +
3113 +       /* Port Change */
3114 +       if (irq_src & USB_STS_PORT_CHANGE) {
3115 +               port_change_irq(udc);
3116 +               status = IRQ_HANDLED;
3117 +       }
3118 +
3119 +       /* Reset Received */
3120 +       if (irq_src & USB_STS_RESET) {
3121 +               reset_irq(udc);
3122 +               status = IRQ_HANDLED;
3123 +       }
3124 +
3125 +       /* Sleep Enable (Suspend) */
3126 +       if (irq_src & USB_STS_SUSPEND) {
3127 +               suspend_irq(udc);
3128 +               status = IRQ_HANDLED;
3129 +       }
3130 +
3131 +       if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
3132 +               VDBG("Error IRQ %x ", irq_src);
3133 +       }
3134 +
3135 +       spin_unlock_irqrestore(&udc->lock, flags);
3136 +       return status;
3137 +}
3138 +
3139 +/*----------------------------------------------------------------*
3140 + * Hook to gadget drivers
3141 + * Called by initialization code of gadget drivers
3142 +*----------------------------------------------------------------*/
3143 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
3144 +{
3145 +       int retval = -ENODEV;
3146 +       unsigned long flags = 0;
3147 +       struct fsl_udc *udc = udc_controller;
3148 +
3149 +       pr_debug("udc: udc=0x%p\n", udc);
3150 +
3151 +       if (!udc)
3152 +               return -ENODEV;
3153 +
3154 +       if (!driver || (driver->speed != USB_SPEED_FULL
3155 +                       && driver->speed != USB_SPEED_HIGH)
3156 +                       || !driver->bind || !driver->disconnect
3157 +                       || !driver->setup)
3158 +               return -EINVAL;
3159 +
3160 +       if (udc->driver)
3161 +               return -EBUSY;
3162 +
3163 +       /* lock is needed but whether should use this lock or another */
3164 +       spin_lock_irqsave(&udc->lock, flags);
3165 +
3166 +       driver->driver.bus = 0;
3167 +       udc->softconnect = 1;
3168 +       /* hook up the driver */
3169 +       udc->driver = driver;
3170 +       udc->gadget.dev.driver = &driver->driver;
3171 +       spin_unlock_irqrestore(&udc->lock, flags);
3172 +
3173 +       /* bind udc driver to gadget driver */
3174 +       retval = driver->bind(&udc->gadget);
3175 +       if (retval) {
3176 +               pr_debug("bind to %s --> %d\n", driver->driver.name, retval);
3177 +               udc->gadget.dev.driver = 0;
3178 +               udc->driver = 0;
3179 +               goto out;
3180 +       }
3181 +
3182 +       /* Enable DR IRQ reg and Set usbcmd reg  Run bit */
3183 +       if (udc->transceiver) {
3184 +               /* Suspend the controller until OTG enables it */
3185 +               udc_suspend(udc);
3186 +               pr_debug("udc: suspend udc for OTG auto detect \n");
3187 +
3188 +               /* Export udc suspend/resume call to OTG */
3189 +               udc->gadget.dev.parent->driver->suspend = fsl_udc_suspend;
3190 +               udc->gadget.dev.parent->driver->resume = fsl_udc_resume;
3191 +
3192 +               retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
3193 +               if (retval < 0) {
3194 +                       printk(KERN_ERR "can't bind to transceiver\n");
3195 +                       driver->unbind(&udc->gadget);
3196 +                       udc->gadget.dev.driver = 0;
3197 +                       udc->driver = 0;
3198 +                       return retval;
3199 +               }
3200 +       } else {
3201 +               /* Enable DR IRQ reg and Set usbcmd reg  Run bit */
3202 +               dr_controller_run(udc);
3203 +               udc->usb_state = USB_STATE_ATTACHED;
3204 +               udc->ep0_state = WAIT_FOR_SETUP;
3205 +               pr_debug("udc: ep0_state now WAIT_FOR_SETUP\n");
3206 +               udc->ep0_dir = 0;
3207 +       }
3208 +
3209 +       printk(KERN_INFO "%s: bind to driver %s \n", udc->gadget.name,
3210 +               driver->driver.name);
3211 +
3212 +out:
3213 +       return retval;
3214 +}
3215 +EXPORT_SYMBOL(usb_gadget_register_driver);
3216 +
3217 +/* Disconnect from gadget driver */
3218 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
3219 +{
3220 +       struct fsl_ep *loop_ep;
3221 +       unsigned long flags;
3222 +
3223 +       if (!udc_controller)
3224 +               return -ENODEV;
3225 +
3226 +       if (!driver || driver != udc_controller->driver || !driver->unbind)
3227 +               return -EINVAL;
3228 +
3229 +#ifdef CONFIG_USB_OTG
3230 +       if (udc_controller->transceiver)
3231 +               (void)otg_set_peripheral(udc_controller->transceiver, 0);
3232 +#endif
3233 +
3234 +       /* stop DR, disable intr */
3235 +       dr_controller_stop(udc_controller);
3236 +
3237 +       /* in fact, no needed */
3238 +       udc_controller->usb_state = USB_STATE_ATTACHED;
3239 +       udc_controller->ep0_state = WAIT_FOR_SETUP;
3240 +       udc_controller->ep0_dir = 0;
3241 +
3242 +       /* stand operation */
3243 +       spin_lock_irqsave(&udc_controller->lock, flags);
3244 +       udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
3245 +       nuke(&udc_controller->eps[0], -ESHUTDOWN);
3246 +       list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
3247 +                       ep.ep_list)
3248 +               nuke(loop_ep, -ESHUTDOWN);
3249 +       spin_unlock_irqrestore(&udc_controller->lock, flags);
3250 +
3251 +       /* unbind gadget and unhook driver. */
3252 +       driver->unbind(&udc_controller->gadget);
3253 +       udc_controller->gadget.dev.driver = 0;
3254 +       udc_controller->driver = 0;
3255 +
3256 +       printk(KERN_INFO "unregistered gadget '%s'\n", driver->driver.name);
3257 +       return 0;
3258 +}
3259 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
3260 +
3261 +/*-------------------------------------------------------------------------
3262 +               PROC File System Support
3263 +-------------------------------------------------------------------------*/
3264 +#ifdef CONFIG_USB_GADGET_DEBUG_FILES
3265 +
3266 +#include <linux/seq_file.h>
3267 +
3268 +static const char proc_filename[] = "driver/fsl_usb2_udc";
3269 +
3270 +static int fsl_proc_read(char *page, char **start, off_t off, int count,
3271 +               int *eof, void *_dev)
3272 +{
3273 +       char *buf = page;
3274 +       char *next = buf;
3275 +       unsigned size = count;
3276 +       unsigned long flags;
3277 +       int t, i;
3278 +       u32 tmp_reg;
3279 +       struct fsl_ep *ep = NULL;
3280 +       struct fsl_req *req;
3281 +
3282 +       struct fsl_udc *udc = udc_controller;
3283 +       if (off != 0)
3284 +               return 0;
3285 +
3286 +       spin_lock_irqsave(&udc->lock, flags);
3287 +
3288 +       /* ------basic driver infomation ---- */
3289 +       t = scnprintf(next, size,
3290 +                       DRIVER_DESC "\n"
3291 +                       "%s version: %s\n"
3292 +                       "Gadget driver: %s\n\n",
3293 +                       driver_name, DRIVER_VERSION,
3294 +                       udc->driver ? udc->driver->driver.name : "(none)");
3295 +       size -= t;
3296 +       next += t;
3297 +
3298 +       /* ------ DR Registers ----- */
3299 +       tmp_reg = fsl_readl(&dr_regs->usbcmd);
3300 +       t = scnprintf(next, size,
3301 +                       "USBCMD reg: 0x%08x\n"
3302 +                       "\tSetupTW: %d\n"
3303 +                       "\tRun/Stop: %s\n\n",
3304 +                       tmp_reg,
3305 +                       (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
3306 +                       (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
3307 +       size -= t;
3308 +       next += t;
3309 +
3310 +       tmp_reg = fsl_readl(&dr_regs->usbsts);
3311 +       t = scnprintf(next, size,
3312 +                       "USB Status Reg: 0x%08x\n"
3313 +                       "\tDr Suspend: %d   Reset Received: %d   "
3314 +                       "System Error: %s  USB Error Interrupt: %s\n\n",
3315 +                       tmp_reg,
3316 +                       (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
3317 +                       (tmp_reg & USB_STS_RESET) ? 1 : 0,
3318 +                       (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
3319 +                       (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
3320 +       size -= t;
3321 +       next += t;
3322 +
3323 +       tmp_reg = fsl_readl(&dr_regs->usbintr);
3324 +       t = scnprintf(next, size,
3325 +                       "USB Interrupt Enable Reg: 0x%08x\n"
3326 +                       "\tSleep Enable: %d   SOF Received Enable: %d  "
3327 +                       "Reset Enable: %d\n"
3328 +                       "\tSystem Error Enable: %d  "
3329 +                       "Port Change Dectected Enable: %d\n"
3330 +                       "\tUSB Error Intr Enable: %d  USB Intr Enable: %d\n\n",
3331 +                       tmp_reg,
3332 +                       (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
3333 +                       (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
3334 +                       (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
3335 +                       (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
3336 +                       (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
3337 +                       (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
3338 +                       (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
3339 +       size -= t;
3340 +       next += t;
3341 +
3342 +       tmp_reg = fsl_readl(&dr_regs->frindex);
3343 +       t = scnprintf(next, size,
3344 +                       "USB Frame Index Reg:  Frame Number is 0x%x\n\n",
3345 +                       (tmp_reg & USB_FRINDEX_MASKS));
3346 +       size -= t;
3347 +       next += t;
3348 +
3349 +       tmp_reg = fsl_readl(&dr_regs->deviceaddr);
3350 +       t = scnprintf(next, size,
3351 +                       "USB Device Address Reg:  Device Addr is 0x%x\n\n",
3352 +                       (tmp_reg & USB_DEVICE_ADDRESS_MASK));
3353 +       size -= t;
3354 +       next += t;
3355 +
3356 +       tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
3357 +       t = scnprintf(next, size,
3358 +                       "USB Endpoint List Address Reg:"
3359 +                       "Device Addr is 0x%x\n\n",
3360 +                       (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
3361 +       size -= t;
3362 +       next += t;
3363 +
3364 +       tmp_reg = fsl_readl(&dr_regs->portsc1);
3365 +       t = scnprintf(next, size,
3366 +               "USB Port Status&Control Reg:\n"
3367 +               "\tPort Transceiver Type : %s" "Port Speed: %s \n"
3368 +               "\tPHY Low Power Suspend: %s" "Port Reset: %s  "
3369 +               "Port Suspend Mode: %s \n" "\tOver-current Change: %s  "
3370 +               "Port Enable/Disable Change: %s\n"
3371 +               "\tPort Enabled/Disabled: %s"
3372 +               "Current Connect Status: %s\n\n", ( {
3373 +                       char *s;
3374 +                       switch (tmp_reg & PORTSCX_PTS_FSLS) {
3375 +                       case PORTSCX_PTS_UTMI:
3376 +                               s = "UTMI"; break;
3377 +                       case PORTSCX_PTS_ULPI:
3378 +                               s = "ULPI "; break;
3379 +                       case PORTSCX_PTS_FSLS:
3380 +                               s = "FS/LS Serial"; break;
3381 +                       default:
3382 +                               s = "None"; break;
3383 +                       }
3384 +                       s; } ), ( {
3385 +                       char *s;
3386 +                       switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) {
3387 +                       case PORTSCX_PORT_SPEED_FULL:
3388 +                               s = "Full Speed"; break;
3389 +                       case PORTSCX_PORT_SPEED_LOW:
3390 +                               s = "Low Speed"; break;
3391 +                       case PORTSCX_PORT_SPEED_HIGH:
3392 +                               s = "High Speed"; break;
3393 +                       default:
3394 +                               s = "Undefined"; break;
3395 +                       }
3396 +                       s;
3397 +               } ),
3398 +               (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
3399 +               "Normal PHY mode" : "Low power mode",
3400 +               (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
3401 +               "Not in Reset",
3402 +               (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
3403 +               (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
3404 +               "No",
3405 +               (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
3406 +               "Not change",
3407 +               (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
3408 +               "Not correct",
3409 +               (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
3410 +               "Attached" : "Not-Att");
3411 +       size -= t;
3412 +       next += t;
3413 +
3414 +       tmp_reg = fsl_readl(&dr_regs->usbmode);
3415 +       t = scnprintf(next, size,
3416 +                       "USB Mode Reg:" "Controller Mode is : %s\n\n", ( {
3417 +                               char *s;
3418 +                               switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
3419 +                               case USB_MODE_CTRL_MODE_IDLE:
3420 +                                       s = "Idle"; break;
3421 +                               case USB_MODE_CTRL_MODE_DEVICE:
3422 +                                       s = "Device Controller"; break;
3423 +                               case USB_MODE_CTRL_MODE_HOST:
3424 +                                       s = "Host Controller"; break;
3425 +                               default:
3426 +                                       s = "None"; break;
3427 +                               }
3428 +                               s;
3429 +                       } ));
3430 +       size -= t;
3431 +       next += t;
3432 +
3433 +       tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
3434 +       t = scnprintf(next, size,
3435 +                       "Endpoint Setup Status Reg:" "SETUP on ep 0x%x\n\n",
3436 +                       (tmp_reg & EP_SETUP_STATUS_MASK));
3437 +       size -= t;
3438 +       next += t;
3439 +
3440 +       for (i = 0; i < udc->max_ep / 2; i++) {
3441 +               tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
3442 +               t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
3443 +                               i, tmp_reg);
3444 +               size -= t;
3445 +               next += t;
3446 +       }
3447 +       tmp_reg = fsl_readl(&dr_regs->endpointprime);
3448 +       t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n", tmp_reg);
3449 +       size -= t;
3450 +       next += t;
3451 +
3452 +#ifdef HAVE_SYS_REGS
3453 +       tmp_reg = usb_sys_regs->snoop1;
3454 +       t = scnprintf(next, size, "\nSnoop1 Reg : = [0x%x]\n\n", tmp_reg);
3455 +       size -= t;
3456 +       next += t;
3457 +
3458 +       tmp_reg = usb_sys_regs->control;
3459 +       t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
3460 +                       tmp_reg);
3461 +       size -= t;
3462 +       next += t;
3463 +#endif
3464 +
3465 +       /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
3466 +       ep = &udc->eps[0];
3467 +       t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
3468 +                       ep->ep.name, ep_maxpacket(ep), ep_index(ep));
3469 +       size -= t;
3470 +       next += t;
3471 +
3472 +       if (list_empty(&ep->queue)) {
3473 +               t = scnprintf(next, size, "its req queue is empty\n\n");
3474 +               size -= t;
3475 +               next += t;
3476 +       } else {
3477 +               list_for_each_entry(req, &ep->queue, queue) {
3478 +                       t = scnprintf(next, size,
3479 +                               "req %p actual 0x%x length 0x%x  buf %p\n",
3480 +                               &req->req, req->req.actual,
3481 +                               req->req.length, req->req.buf);
3482 +                       size -= t;
3483 +                       next += t;
3484 +               }
3485 +       }
3486 +       /* other gadget->eplist ep */
3487 +       list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
3488 +               if (ep->desc) {
3489 +                       t = scnprintf(next, size,
3490 +                                       "\nFor %s Maxpkt is 0x%x "
3491 +                                       "index is 0x%x\n",
3492 +                                       ep->ep.name, ep_maxpacket(ep),
3493 +                                       ep_index(ep));
3494 +                       size -= t;
3495 +                       next += t;
3496 +
3497 +                       if (list_empty(&ep->queue)) {
3498 +                               t = scnprintf(next, size,
3499 +                                               "its req queue is empty\n\n");
3500 +                               size -= t;
3501 +                               next += t;
3502 +                       } else {
3503 +                               list_for_each_entry(req, &ep->queue, queue) {
3504 +                                       t = scnprintf(next, size,
3505 +                                               "req %p actual 0x%x length"
3506 +                                               "0x%x  buf %p\n",
3507 +                                               &req->req, req->req.actual,
3508 +                                               req->req.length, req->req.buf);
3509 +                                       size -= t;
3510 +                                       next += t;
3511 +                                       } /* end for each_entry of ep req */
3512 +                               }       /* end for else */
3513 +                       }       /* end for if(ep->queue) */
3514 +               }               /* end (ep->desc) */
3515 +
3516 +       spin_unlock_irqrestore(&udc->lock, flags);
3517 +
3518 +       *eof = 1;
3519 +       return count - size;
3520 +}
3521 +
3522 +#define create_proc_file()     create_proc_read_entry(proc_filename, \
3523 +                               0, NULL, fsl_proc_read, NULL)
3524 +
3525 +#define remove_proc_file()     remove_proc_entry(proc_filename, NULL)
3526 +
3527 +#else                          /* !CONFIG_USB_GADGET_DEBUG_FILES */
3528 +
3529 +#define create_proc_file()     do {} while (0)
3530 +#define remove_proc_file()     do {} while (0)
3531 +
3532 +#endif                         /* CONFIG_USB_GADGET_DEBUG_FILES */
3533 +
3534 +/*-------------------------------------------------------------------------*/
3535 +
3536 +/* Release udc structures */
3537 +static void fsl_udc_release(struct device *dev)
3538 +{
3539 +       complete(udc_controller->done);
3540 +       dma_free_coherent(dev, udc_controller->ep_qh_size,
3541 +                       udc_controller->ep_qh, udc_controller->ep_qh_dma);
3542 +       kfree(udc_controller);
3543 +}
3544 +
3545 +/******************************************************************
3546 +       Internal structure setup functions
3547 +*******************************************************************/
3548 +/*------------------------------------------------------------------
3549 + * init resource for globle controller
3550 + * Return the udc handle on success or NULL on failure
3551 + ------------------------------------------------------------------*/
3552 +static struct fsl_udc *__init struct_udc_setup(struct platform_device *pdev)
3553 +{
3554 +       struct fsl_udc *udc;
3555 +       struct fsl_usb2_platform_data *pdata;
3556 +       size_t size;
3557 +
3558 +       udc = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
3559 +       if (udc == NULL) {
3560 +               ERR("malloc udc failed\n");
3561 +               return NULL;
3562 +       }
3563 +
3564 +       pdata = pdev->dev.platform_data;
3565 +       udc->phy_mode = pdata->phy_mode;        /* DDD FIXME */
3566 +
3567 +       /* max_ep_nr is bidirectional ep number, max_ep doubles the number */
3568 +       udc->max_ep = pdata->max_ep_nr * 2;
3569 +
3570 +       udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
3571 +       if (!udc->eps) {
3572 +               ERR("malloc fsl_ep failed\n");
3573 +               goto cleanup;
3574 +       }
3575 +
3576 +       /* initialized QHs, take care of alignment */
3577 +       size = udc->max_ep * sizeof(struct ep_queue_head);
3578 +       if (size < QH_ALIGNMENT)
3579 +               size = QH_ALIGNMENT;
3580 +       else if ((size % QH_ALIGNMENT) != 0) {
3581 +               size += QH_ALIGNMENT + 1;
3582 +               size &= ~(QH_ALIGNMENT - 1);
3583 +       }
3584 +       udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
3585 +                                       &udc->ep_qh_dma, GFP_KERNEL);
3586 +       if (!udc->ep_qh) {
3587 +               ERR("malloc QHs for udc failed\n");
3588 +               kfree(udc->eps);
3589 +               goto cleanup;
3590 +       }
3591 +
3592 +       udc->ep_qh_size = size;
3593 +
3594 +       /* Initialize ep0 status request structure */
3595 +       udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
3596 +                       struct fsl_req, req);
3597 +       /* allocate a small amount of memory to get valid address */
3598 +       udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
3599 +       udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
3600 +
3601 +       udc->resume_state = USB_STATE_NOTATTACHED;
3602 +       udc->usb_state = USB_STATE_POWERED;
3603 +       udc->ep0_dir = 0;
3604 +       udc->remote_wakeup = 0; /* default to 0 on reset */
3605 +       spin_lock_init(&udc->lock);
3606 +
3607 +       return udc;
3608 +
3609 +cleanup:
3610 +       kfree(udc);
3611 +       return NULL;
3612 +}
3613 +
3614 +/*----------------------------------------------------------------
3615 + * Setup the fsl_ep struct for eps
3616 + * Link fsl_ep->ep to gadget->ep_list
3617 + * ep0out is not used so do nothing here
3618 + * ep0in should be taken care
3619 + *--------------------------------------------------------------*/
3620 +static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
3621 +               char *name, int link)
3622 +{
3623 +       struct fsl_ep *ep = &udc->eps[index];
3624 +
3625 +       ep->udc = udc;
3626 +       strcpy(ep->name, name);
3627 +       ep->ep.name = ep->name;
3628 +
3629 +       ep->ep.ops = &fsl_ep_ops;
3630 +       ep->stopped = 0;
3631 +
3632 +       /* for ep0: maxP defined in desc
3633 +        * for other eps, maxP is set by epautoconfig() called by gadget layer
3634 +        */
3635 +       ep->ep.maxpacket = (unsigned short) ~0;
3636 +
3637 +       /* the queue lists any req for this ep */
3638 +       INIT_LIST_HEAD(&ep->queue);
3639 +
3640 +       /* gagdet.ep_list used for ep_autoconfig so no ep0 */
3641 +       if (link)
3642 +               list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
3643 +       ep->gadget = &udc->gadget;
3644 +       ep->qh = &udc->ep_qh[index];
3645 +
3646 +       return 0;
3647 +}
3648 +
3649 +static int board_init(struct platform_device *pdev)
3650 +{
3651 +       struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
3652 +
3653 +       pr_debug("udc: pdev=0x%p  pdata=0x%p\n", pdev, pdata);
3654 +
3655 +       /*
3656 +        * do platform specific init: check the clock, grab/config pins, etc.
3657 +        */
3658 +       if (pdata->platform_init && pdata->platform_init(pdev) != 0)
3659 +               return -EINVAL;
3660 +
3661 +       return 0;
3662 +}
3663 +
3664 +/* Driver probe functions */
3665 +
3666 +static int __init fsl_udc_probe(struct platform_device *pdev)
3667 +{
3668 +       struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
3669 +       struct fsl_udc *udc;
3670 +       unsigned int i;
3671 +       struct otg_transceiver *transceiver = NULL;
3672 +       int status = -ENODEV;
3673 +       u32 id;
3674 +       int irq_number;
3675 +       u64 rsrc_start, rsrc_len;
3676 +       int ret = -ENODEV;
3677 +
3678 +       pr_debug("udc: pdev=0x%p  pdata=0x%p\n", pdev, pdata);
3679 +
3680 +       if (board_init(pdev) != 0)
3681 +               return -EINVAL;
3682 +
3683 +       /* Initialize the udc structure including QH member and other member */
3684 +       udc = (struct fsl_udc *) struct_udc_setup(pdev);
3685 +       udc_controller = udc;
3686 +
3687 +       if (!udc) {
3688 +               ERR("udc is NULL \n");
3689 +               return -ENOMEM;
3690 +       }
3691 +       dev_set_drvdata(&pdev->dev, udc);
3692 +       pr_debug("udc_controller=0x%p", udc_controller);
3693 +
3694 +       udc->pdata = pdata;
3695 +       udc->xcvr_type = pdata->xcvr_type;
3696 +
3697 +#ifdef CONFIG_USB_OTG
3698 +       udc->transceiver = otg_get_transceiver();
3699 +       pr_debug("udc: otg_get_transceiver returns 0x%p", udc->transceiver);
3700 +#endif
3701 +
3702 +       if (pdev->resource[1].flags != IORESOURCE_IRQ)
3703 +               return -ENODEV;
3704 +
3705 +       rsrc_start = pdev->resource[0].start;
3706 +       rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
3707 +
3708 +       pr_debug("     start=0x%ux   end=0x%ux\n",
3709 +                pdev->resource[0].start, pdev->resource[0].end);
3710 +       pr_debug("rsrc_start=0x%llx  rsrc_len=0x%llx\n", rsrc_start, rsrc_len);
3711 +
3712 +       dr_regs = (struct fsl_usb_device_regs *)pdata->regs;
3713 +
3714 +       pr_debug("udc: pdate=0x%p dr_regs=0x%p\n", pdata, dr_regs);
3715 +       pr_debug("udc: hci_version=0x%x\n", dr_regs->hciversion);
3716 +       pr_debug("udc: otgsc at 0x%p\n", &dr_regs->otgsc);
3717 +
3718 +       id = fsl_readl(&dr_regs->id);
3719 +       printk(KERN_INFO "FSL2 USBOTG h/w ID=0x%x  revision=0x%x\n",
3720 +              id & 0x3f, id >> 16);
3721 +
3722 +       /* USB OTG module IRQ */
3723 +       irq_number = platform_get_irq(pdev, 0);
3724 +       if (irq_number > 128) {
3725 +               status = request_irq(irq_number, fsl_udc_irq, IRQF_SHARED,
3726 +                                    driver_name, udc);
3727 +               if (status) {
3728 +                       ERR("can't get irq %d, err=%d\n", irq_number, status);
3729 +                       goto err2;
3730 +               }
3731 +       } else {
3732 +               status = -ENODEV;
3733 +               goto err2;
3734 +       }
3735 +
3736 +       if (!udc->transceiver) {
3737 +               /* initialize usb hw reg except for regs for EP,
3738 +                * leave usbintr reg untouched*/
3739 +               dr_controller_setup(udc);
3740 +       }
3741 +
3742 +       /* here comes the stand operations for probe
3743 +        * set the fsl_udc->gadget.xxx
3744 +        */
3745 +       udc->gadget.ops = &fsl_gadget_ops;
3746 +
3747 +       /* gadget.ep0 is a pointer */
3748 +       udc->gadget.ep0 = &udc->eps[0].ep;
3749 +       INIT_LIST_HEAD(&udc->gadget.ep_list);
3750 +       udc->gadget.speed = USB_SPEED_UNKNOWN;
3751 +       udc->gadget.name = driver_name;
3752 +
3753 +       /* Setup gadget.dev and register with kernel */
3754 +       strcpy(udc->gadget.dev.bus_id, "gadget");
3755 +       udc->gadget.dev.release = fsl_udc_release;
3756 +       udc->gadget.dev.parent = &pdev->dev;
3757 +
3758 +       ret = device_register(&udc->gadget.dev);
3759 +       if (ret < 0)
3760 +               goto err3;
3761 +
3762 +       if (udc->transceiver)
3763 +               udc->gadget.is_otg = 1;
3764 +
3765 +       /* setup QH and epctrl for ep0 */
3766 +       ep0_setup(udc);
3767 +
3768 +       /* setup udc->eps[] for ep0 */
3769 +       struct_ep_setup(udc_controller, 0, "ep0", 0);
3770 +       /* for ep0: the desc defined here;
3771 +        * for other eps, gadget layer called ep_enable with defined desc
3772 +        */
3773 +       udc->eps[0].desc = &fsl_ep0_desc;
3774 +       udc->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
3775 +
3776 +       /* setup the udc->eps[] for non-control endpoints and link
3777 +        * to gadget.ep_list */
3778 +       for (i = 1; i < (int)(udc->max_ep / 2); i++) {
3779 +               char name[14];
3780 +
3781 +               sprintf(name, "ep%dout", i);
3782 +               struct_ep_setup(udc, i * 2, name, 1);
3783 +               sprintf(name, "ep%din", i);
3784 +               struct_ep_setup(udc, i * 2 + 1, name, 1);
3785 +       }
3786 +
3787 +       /* use dma_pool for TD management */
3788 +       udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
3789 +                       sizeof(struct ep_td_struct),
3790 +                       DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
3791 +       if (udc->td_pool == NULL) {
3792 +               ret = -ENOMEM;
3793 +               goto err4;
3794 +       }
3795 +#if 0 // DDD why this? hoarks OTG host
3796 +       pullup_disable(udc);
3797 +#endif
3798 +
3799 +       create_proc_file();
3800 +       return 0;
3801 +
3802 +err4:
3803 +       device_unregister(&udc_controller->gadget.dev);
3804 +err3:
3805 +       free_irq(udc_controller->irq, udc_controller);
3806 +err2:
3807 +       kfree(udc);
3808 +       if (transceiver)
3809 +               put_device(transceiver->dev);
3810 +       release_mem_region(pdev->resource[0].start,
3811 +                          pdev->resource[0].end - pdev->resource[0].start + 1);
3812 +       return status;
3813 +
3814 +}
3815 +
3816 +/* Driver removal functions
3817 + * Free resources
3818 + * Finish pending transaction
3819 + */
3820 +static int __exit fsl_udc_remove(struct platform_device *pdev)
3821 +{
3822 +       struct device *dev = &pdev->dev;
3823 +       struct fsl_udc *udc = (struct fsl_udc *)dev_get_drvdata(dev);
3824 +       struct fsl_usb2_platform_data *pdata;
3825 +       int irq_number;
3826 +
3827 +       DECLARE_COMPLETION(done);
3828 +
3829 +       pdata = pdev->dev.platform_data;
3830 +
3831 +       if (!udc)
3832 +               return -ENODEV;
3833 +
3834 +       udc->done = &done;
3835 +
3836 +       /* DR has been stopped in usb_gadget_unregister_driver() */
3837 +
3838 +       if (udc->transceiver) {
3839 +               put_device(udc->transceiver->dev);
3840 +               udc->transceiver = NULL;
3841 +       }
3842 +
3843 +       /* remove proc */
3844 +       remove_proc_file();
3845 +
3846 +       /* free irq */
3847 +       irq_number = udc->irq;
3848 +       free_irq(pdev->resource[1].start, udc);
3849 +       udc->irq = 0;
3850 +
3851 +       /* Free allocated memory */
3852 +       kfree(udc->status_req->req.buf);
3853 +       kfree(udc->status_req);
3854 +       kfree(udc_controller->eps);
3855 +
3856 +       dma_pool_destroy(udc_controller->td_pool);
3857 +       /* deinitlaize all ep: strcut */
3858 +       /* deinitialize ep0: reg and QH */
3859 +
3860 +       device_unregister(&udc->gadget.dev);
3861 +       /* free udc --wait for the release() finished */
3862 +       wait_for_completion(&done);
3863 +
3864 +       /*
3865 +        * do platform specific un-initialization:
3866 +        * release iomux pins, etc.
3867 +        */
3868 +       if (pdata->platform_uninit)
3869 +               pdata->platform_uninit(pdev);
3870 +
3871 +       return 0;
3872 +}
3873 +
3874 +static int udc_suspend(struct fsl_udc *udc)
3875 +{
3876 +       udc->stopped = 1;
3877 +       return 0;
3878 +}
3879 +
3880 +/*
3881 + * Modify Power management attributes
3882 + * Used by OTG statemachine to disable gadget temporarily
3883 + * Here we stop the DR controller and disable the irq
3884 + * @param dev device controller pointer
3885 + * @param state current state
3886 + * @return The function returns 0 on success or -1 if failed
3887 + */
3888 +static int fsl_udc_suspend(struct device *dev, pm_message_t state)
3889 +{
3890 +       struct fsl_udc *udc = (struct fsl_udc *)dev_get_drvdata(dev);
3891 +       pr_debug("udc: Suspend. state=%d\n", state.event);
3892 +       return udc_suspend(udc);
3893 +}
3894 +
3895 +static int udc_resume(struct fsl_udc *udc)
3896 +{
3897 +       /*Enable DR irq reg and set controller Run */
3898 +       if (udc->stopped) {
3899 +               dr_controller_setup(udc);
3900 +               dr_controller_run(udc);
3901 +       }
3902 +       udc->usb_state = USB_STATE_ATTACHED;
3903 +       udc->ep0_state = WAIT_FOR_SETUP;
3904 +       udc->ep0_dir = 0;
3905 +       return 0;
3906 +}
3907 +
3908 +/*
3909 + * Invoked on USB resume. May be called in_interrupt.
3910 + * Here we start the DR controller and enable the irq
3911 + * @param dev device controller pointer
3912 + * @return The function returns 0 on success or -1 if failed
3913 + */
3914 +static int fsl_udc_resume(struct device *dev)
3915 +{
3916 +       struct fsl_udc *udc = (struct fsl_udc *)dev_get_drvdata(dev);
3917 +       pr_debug("udc: Resume dev=0x%p udc=0x%p\n", dev, udc);
3918 +
3919 +       return udc_resume(udc);
3920 +}
3921 +
3922 +/*-------------------------------------------------------------------------
3923 +       Register entry point for the peripheral controller driver
3924 +--------------------------------------------------------------------------*/
3925 +static struct platform_driver udc_driver = {
3926 +       .probe   = fsl_udc_probe,
3927 +       .remove  = __exit_p(fsl_udc_remove),
3928 +       .driver  = {
3929 +               .name = (char *)driver_name,
3930 +               .owner = THIS_MODULE,
3931 +       },
3932 +};
3933 +
3934 +static int __init udc_init(void)
3935 +{
3936 +       printk(KERN_INFO "%s version %s init \n", driver_desc, DRIVER_VERSION);
3937 +       return platform_driver_register(&udc_driver);
3938 +}
3939 +
3940 +module_init(udc_init);
3941 +
3942 +static void __exit udc_exit(void)
3943 +{
3944 +       platform_driver_unregister(&udc_driver);
3945 +       printk(KERN_INFO "%s unregistered \n", driver_desc);
3946 +}
3947 +
3948 +module_exit(udc_exit);
3949 +
3950 +MODULE_DESCRIPTION(DRIVER_DESC);
3951 +MODULE_AUTHOR(DRIVER_AUTHOR);
3952 +MODULE_LICENSE("GPL");
3953 --- a/drivers/usb/host/Kconfig
3954 +++ b/drivers/usb/host/Kconfig
3955 @@ -32,6 +32,7 @@ config USB_EHCI_HCD
3956  config USB_EHCI_ROOT_HUB_TT
3957         bool "Root Hub Transaction Translators (EXPERIMENTAL)"
3958         depends on USB_EHCI_HCD && EXPERIMENTAL
3959 +       default y if M54455
3960         ---help---
3961           Some EHCI chips have vendor-specific extensions to integrate
3962           transaction translators, so that no OHCI or UHCI companion
3963 @@ -60,12 +61,12 @@ config USB_EHCI_TT_NEWSCHED
3964
3965  config USB_EHCI_BIG_ENDIAN_MMIO
3966         bool
3967 -       depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX)
3968 +       depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX || M54455)
3969         default y
3970
3971  config USB_EHCI_BIG_ENDIAN_DESC
3972         bool
3973 -       depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX)
3974 +       depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || M54455)
3975         default y
3976
3977  config USB_EHCI_FSL
3978 @@ -260,3 +261,19 @@ config USB_R8A66597_HCD
3979           To compile this driver as a module, choose M here: the
3980           module will be called r8a66597-hcd.
3981
3982 +choice
3983 +       prompt "Select transceiver"
3984 +       depends on M54455
3985 +       default USB_M5445X_ULPI
3986 +
3987 +config USB_M5445X_ULPI
3988 +       bool "External ULPI"
3989 +       ---help---
3990 +         Enable support for the external HS ULPI transceiver.
3991 +
3992 +config USB_M5445X_FSLS
3993 +       bool "On-chip (FL/LS only)"
3994 +       ---help---
3995 +         Enable support for the on-chip FL/LS transceiver.
3996 +endchoice
3997 +
3998 --- /dev/null
3999 +++ b/drivers/usb/host/ehci-arc.c
4000 @@ -0,0 +1,431 @@
4001 +/*
4002 + * drivers/usb/host/ehci-arc.c
4003 + *
4004 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
4005 + */
4006 +
4007 +/*
4008 + * The code contained herein is licensed under the GNU General Public
4009 + * License. You may obtain a copy of the GNU General Public License
4010 + * Version 2 or later at the following locations:
4011 + *
4012 + * http://www.opensource.org/licenses/gpl-license.html
4013 + * http://www.gnu.org/copyleft/gpl.html
4014 + */
4015 +
4016 +/* Note: this file is #included by ehci-hcd.c */
4017 +
4018 +#include <linux/platform_device.h>
4019 +#include <linux/usb/fsl_usb2.h>
4020 +#include <linux/fsl_devices.h>
4021 +#include <linux/usb/otg.h>
4022 +
4023 +#include "ehci-fsl.h"
4024 +
4025 +
4026 +/* FIXME: Power Managment is un-ported so temporarily disable it */
4027 +#undef CONFIG_PM
4028 +
4029 +/* PCI-based HCs are common, but plenty of non-PCI HCs are used too */
4030 +
4031 +/* configure so an HC device and id are always provided */
4032 +/* always called with process context; sleeping is OK */
4033 +
4034 +/**
4035 + * usb_hcd_fsl_probe - initialize FSL-based HCDs
4036 + * @drvier: Driver to be used for this HCD
4037 + * @pdev: USB Host Controller being probed
4038 + * Context: !in_interrupt()
4039 + *
4040 + * Allocates basic resources for this USB host controller.
4041 + *
4042 + */
4043 +static int usb_hcd_fsl_probe(const struct hc_driver *driver,
4044 +                            struct platform_device *pdev)
4045 +{
4046 +       struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
4047 +       struct usb_hcd *hcd;
4048 +       struct resource *res;
4049 +       int irq;
4050 +       int retval;
4051 +
4052 +       pr_debug("initializing FSL-SOC USB Controller\n");
4053 +
4054 +       /* Need platform data for setup */
4055 +       if (!pdata) {
4056 +               dev_err(&pdev->dev,
4057 +                       "No platform data for %s.\n", pdev->dev.bus_id);
4058 +               return -ENODEV;
4059 +       }
4060 +
4061 +       retval = fsl_platform_verify(pdev);
4062 +       if (retval)
4063 +               return retval;
4064 +
4065 +       /*
4066 +        * do platform specific init: check the clock, grab/config pins, etc.
4067 +        */
4068 +       if (pdata->platform_init && pdata->platform_init(pdev)) {
4069 +               retval = -ENODEV;
4070 +               goto err1;
4071 +       }
4072 +
4073 +       res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
4074 +       if (!res) {
4075 +               dev_err(&pdev->dev,
4076 +                       "Found HC with no IRQ. Check %s setup!\n",
4077 +                       pdev->dev.bus_id);
4078 +               return -ENODEV;
4079 +       }
4080 +       irq = res->start;
4081 +
4082 +       fsl_platform_set_vbus_power(pdev, 1);
4083 +
4084 +       hcd = usb_create_hcd(driver, &pdev->dev, pdev->dev.bus_id);
4085 +       if (!hcd) {
4086 +               retval = -ENOMEM;
4087 +               goto err1;
4088 +       }
4089 +
4090 +       if (pdata->regs) {
4091 +               pr_debug("REGS: using pdata->regs (0x%p)\n", pdata->regs);
4092 +               hcd->regs = pdata->regs;
4093 +               hcd->rsrc_start = pdata->r_start;
4094 +               hcd->rsrc_len = pdata->r_len;
4095 +       } else {
4096 +               pr_debug("REGS: NO pdata->regs\n");
4097 +               res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4098 +               if (!res) {
4099 +                       dev_err(&pdev->dev, "Found HC with no register addr. "
4100 +                               "Check %s setup!\n", pdev->dev.bus_id);
4101 +                       retval = -ENODEV;
4102 +                       goto err2;
4103 +               }
4104 +               hcd->rsrc_start = res->start;
4105 +               hcd->rsrc_len = res->end - res->start + 1;
4106 +
4107 +               /*
4108 +               printk("DDD %s(): rsrc_start=0x%llx  rsrc_len=0x%llx  "
4109 +                       "pdata=0x%p\n", __FUNCTION__,
4110 +                       hcd->rsrc_start, hcd->rsrc_len, pdata);
4111 +               */
4112 +
4113 +               if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
4114 +                                       driver->description)) {
4115 +                       dev_dbg(&pdev->dev, "request_mem_region failed\n");
4116 +                       retval = -EBUSY;
4117 +                       goto err2;
4118 +               }
4119 +               hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
4120 +
4121 +               if (hcd->regs == NULL) {
4122 +                       dev_dbg(&pdev->dev, "error mapping memory\n");
4123 +                       retval = -EFAULT;
4124 +                       goto err3;
4125 +               }
4126 +       }
4127 +       hcd->power_budget = pdata->power_budget;
4128 +
4129 +       /* DDD
4130 +        * the following must be done by this point, otherwise the OTG
4131 +        * host port doesn't make it thru initializtion.
4132 +        * ehci_halt(), called by ehci_fsl_setup() returns -ETIMEDOUT
4133 +        */
4134 +       fsl_platform_set_host_mode(hcd);
4135 +
4136 +       retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
4137 +       if (retval != 0)
4138 +               goto err4;
4139 +
4140 +#if defined(CONFIG_USB_OTG)
4141 +       if (pdata->does_otg) {
4142 +               struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4143 +
4144 +               ehci->transceiver = otg_get_transceiver();
4145 +
4146 +               if (ehci->transceiver) {
4147 +                       retval = otg_set_host(ehci->transceiver,
4148 +                                             &ehci_to_hcd(ehci)->self);
4149 +                       if (retval) {
4150 +                               if (ehci->transceiver)
4151 +                                       put_device(ehci->transceiver->dev);
4152 +                               goto err3;
4153 +                       }
4154 +               } else {
4155 +                       printk(KERN_ERR "can't find transceiver\n");
4156 +                       retval = -ENODEV;
4157 +                       goto err3;
4158 +               }
4159 +       }
4160 +#endif
4161 +
4162 +       return retval;
4163 +
4164 +err4:
4165 +       /* DDD only if we did the iomap() iounmap(hcd->regs); */
4166 +err3:
4167 +       /* DDD only if we did a request_
4168 +        * release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
4169 +        */
4170 +err2:
4171 +       usb_put_hcd(hcd);
4172 +err1:
4173 +       dev_err(&pdev->dev, "init %s fail, %d\n", pdev->dev.bus_id, retval);
4174 +       if (pdata->platform_uninit)
4175 +               pdata->platform_uninit(pdev);
4176 +       return retval;
4177 +}
4178 +
4179 +/* may be called without controller electrically present */
4180 +/* may be called with controller, bus, and devices active */
4181 +
4182 +/**
4183 + * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
4184 + * @dev: USB Host Controller being removed
4185 + * Context: !in_interrupt()
4186 + *
4187 + * Reverses the effect of usb_hcd_fsl_probe().
4188 + *
4189 + */
4190 +static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
4191 +                              struct platform_device *pdev)
4192 +{
4193 +       struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4194 +       struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
4195 +
4196 +       /* DDD shouldn't we turn off the power here? */
4197 +       fsl_platform_set_vbus_power(pdev, 0);
4198 +
4199 +       usb_remove_hcd(hcd);
4200 +
4201 +       if (ehci->transceiver) {
4202 +               (void)otg_set_host(ehci->transceiver, 0);
4203 +               put_device(ehci->transceiver->dev);
4204 +       }
4205 +       usb_put_hcd(hcd);
4206 +
4207 +       /*
4208 +        * do platform specific un-initialization:
4209 +        * release iomux pins, etc.
4210 +        */
4211 +       if (pdata->platform_uninit)
4212 +               pdata->platform_uninit(pdev);
4213 +}
4214 +
4215 +/* called after powerup, by probe or system-pm "wakeup" */
4216 +static int ehci_fsl_reinit(struct ehci_hcd *ehci)
4217 +{
4218 +       fsl_platform_usb_setup(ehci_to_hcd(ehci));
4219 +       ehci_port_power(ehci, 0);
4220 +
4221 +       return 0;
4222 +}
4223 +
4224 +/* called during probe() after chip reset completes */
4225 +static int ehci_fsl_setup(struct usb_hcd *hcd)
4226 +{
4227 +       struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4228 +       int retval;
4229 +       struct fsl_usb2_platform_data *pdata;
4230 +       pdata = hcd->self.controller-> platform_data;
4231 +
4232 +       ehci->big_endian_desc = pdata->big_endian_desc;
4233 +       ehci->big_endian_mmio = pdata->big_endian_mmio;
4234 +
4235 +       /* EHCI registers start at offset 0x100 */
4236 +       ehci->caps = hcd->regs + 0x100;
4237 +       ehci->regs = hcd->regs + 0x100 +
4238 +           HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
4239 +
4240 +       pr_debug("%s(): ehci->caps=0x%p  ehci->regs=0x%p\n", __FUNCTION__,
4241 +                ehci->caps, ehci->regs);
4242 +
4243 +       dbg_hcs_params(ehci, "reset");
4244 +       dbg_hcc_params(ehci, "reset");
4245 +
4246 +       /* cache this readonly data; minimize chip reads */
4247 +       ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
4248 +
4249 +       retval = ehci_halt(ehci);
4250 +       if (retval)
4251 +               return retval;
4252 +
4253 +       /* data structure init */
4254 +       retval = ehci_init(hcd);
4255 +       if (retval)
4256 +               return retval;
4257 +
4258 +       ehci->is_tdi_rh_tt = 1;
4259 +
4260 +       ehci->sbrn = 0x20;
4261 +
4262 +       ehci_reset(ehci);
4263 +
4264 +       retval = ehci_fsl_reinit(ehci);
4265 +       return retval;
4266 +}
4267 +
4268 +static const struct hc_driver ehci_fsl_hc_driver = {
4269 +       .description = hcd_name,
4270 +       .product_desc = "Freescale On-Chip EHCI Host Controller",
4271 +       .hcd_priv_size = sizeof(struct ehci_hcd),
4272 +
4273 +       /*
4274 +        * generic hardware linkage
4275 +        */
4276 +       .irq = ehci_irq,
4277 +       .flags = FSL_PLATFORM_HC_FLAGS,
4278 +
4279 +       /*
4280 +        * basic lifecycle operations
4281 +        */
4282 +       .reset = ehci_fsl_setup,
4283 +       .start = ehci_run,
4284 +       .stop = ehci_stop,
4285 +       .shutdown = ehci_shutdown,
4286 +
4287 +       /*
4288 +        * managing i/o requests and associated device resources
4289 +        */
4290 +       .urb_enqueue = ehci_urb_enqueue,
4291 +       .urb_dequeue = ehci_urb_dequeue,
4292 +       .endpoint_disable = ehci_endpoint_disable,
4293 +
4294 +       /*
4295 +        * scheduling support
4296 +        */
4297 +       .get_frame_number = ehci_get_frame,
4298 +
4299 +       /*
4300 +        * root hub support
4301 +        */
4302 +       .hub_status_data = ehci_hub_status_data,
4303 +       .hub_control = ehci_hub_control,
4304 +       .bus_suspend = ehci_bus_suspend,
4305 +       .bus_resume = ehci_bus_resume,
4306 +};
4307 +
4308 +#ifdef CONFIG_USB_OTG
4309 +/*
4310 + * Holding pen for all the EHCI registers except port_status,
4311 + * which is a zero element array and hence takes no space.
4312 + * The port_status register is saved in usb_ehci_portsc.
4313 + */
4314 +volatile static struct ehci_regs usb_ehci_regs;
4315 +static u32 usb_ehci_portsc;
4316 +
4317 +/* suspend/resume, section 4.3 */
4318 +
4319 +/* These routines rely on the bus (pci, platform, etc)
4320 + * to handle powerdown and wakeup, and currently also on
4321 + * transceivers that don't need any software attention to set up
4322 + * the right sort of wakeup.
4323 + *
4324 + * They're also used for turning on/off the port when doing OTG.
4325 + */
4326 +static int ehci_fsl_drv_suspend(struct platform_device *pdev,
4327 +                               pm_message_t message)
4328 +{
4329 +       struct usb_hcd *hcd = platform_get_drvdata(pdev);
4330 +       struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4331 +       u32 tmp;
4332 +
4333 +       pr_debug("%s pdev=0x%p  ehci=0x%p  hcd=0x%p\n",
4334 +                __FUNCTION__, pdev, ehci, hcd);
4335 +       pr_debug("%s ehci->regs=0x%p  hcd->regs=0x%p  hcd->state=%d\n",
4336 +                __FUNCTION__, ehci->regs, hcd->regs, hcd->state);
4337 +
4338 +       hcd->state = HC_STATE_SUSPENDED;
4339 +       pdev->dev.power.power_state = PMSG_SUSPEND;
4340 +
4341 +       if (hcd->driver->suspend)
4342 +               return hcd->driver->suspend(hcd, message);
4343 +
4344 +       /* ignore non-host interrupts */
4345 +       clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4346 +
4347 +       tmp = ehci_readl(ehci, &ehci->regs->command);
4348 +       tmp &= ~CMD_RUN;
4349 +       ehci_writel(ehci, tmp, &ehci->regs->command);
4350 +
4351 +       memcpy((void *)&usb_ehci_regs, ehci->regs, sizeof(struct ehci_regs));
4352 +       usb_ehci_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
4353 +
4354 +       /* clear the W1C bits */
4355 +       usb_ehci_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
4356 +
4357 +       fsl_platform_set_vbus_power(pdev, 0);
4358 +       /* clear PP to cut power to the port */
4359 +       tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
4360 +       tmp &= ~PORT_POWER;
4361 +       ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
4362 +
4363 +       return 0;
4364 +}
4365 +
4366 +static int ehci_fsl_drv_resume(struct platform_device *pdev)
4367 +{
4368 +       struct usb_hcd *hcd = platform_get_drvdata(pdev);
4369 +       struct ehci_hcd *ehci = hcd_to_ehci(hcd);
4370 +       u32 tmp;
4371 +       struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
4372 +
4373 +       pr_debug("%s pdev=0x%p  pdata=0x%p  ehci=0x%p  hcd=0x%p\n",
4374 +                __FUNCTION__, pdev, pdata, ehci, hcd);
4375 +
4376 +       pr_debug("%s ehci->regs=0x%p  hcd->regs=0x%p",
4377 +                __FUNCTION__, ehci->regs, hcd->regs);
4378 +
4379 +       memcpy(ehci->regs, (void *)&usb_ehci_regs, sizeof(struct ehci_regs));
4380 +       ehci_writel(ehci, usb_ehci_portsc, &ehci->regs->port_status[0]);
4381 +
4382 +       tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
4383 +       ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
4384 +
4385 +       set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4386 +       hcd->state = HC_STATE_RUNNING;
4387 +       pdev->dev.power.power_state = PMSG_ON;
4388 +
4389 +       tmp = ehci_readl(ehci, &ehci->regs->command);
4390 +       tmp |= CMD_RUN;
4391 +       ehci_writel(ehci, tmp, &ehci->regs->command);
4392 +
4393 +       fsl_platform_set_vbus_power(pdev, 1);
4394 +
4395 +       usb_hcd_resume_root_hub(hcd);
4396 +
4397 +       return 0;
4398 +}
4399 +#endif                         /* CONFIG_USB_OTG */
4400 +
4401 +static int ehci_fsl_drv_probe(struct platform_device *pdev)
4402 +{
4403 +       if (usb_disabled())
4404 +               return -ENODEV;
4405 +
4406 +       return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
4407 +}
4408 +
4409 +static int ehci_fsl_drv_remove(struct platform_device *pdev)
4410 +{
4411 +       struct usb_hcd *hcd = platform_get_drvdata(pdev);
4412 +
4413 +       usb_hcd_fsl_remove(hcd, pdev);
4414 +
4415 +       return 0;
4416 +}
4417 +
4418 +MODULE_ALIAS("fsl-ehci");
4419 +
4420 +static struct platform_driver ehci_fsl_driver = {
4421 +       .probe = ehci_fsl_drv_probe,
4422 +       .remove = ehci_fsl_drv_remove,
4423 +       .shutdown = usb_hcd_platform_shutdown,
4424 +#ifdef CONFIG_USB_OTG
4425 +       .suspend = ehci_fsl_drv_suspend,
4426 +       .resume  = ehci_fsl_drv_resume,
4427 +#endif
4428 +       .driver = {
4429 +                  .name = "fsl-ehci",
4430 +                  },
4431 +};
4432 --- a/drivers/usb/host/ehci-fsl.h
4433 +++ b/drivers/usb/host/ehci-fsl.h
4434 @@ -18,6 +18,8 @@
4435  #ifndef _EHCI_FSL_H
4436  #define _EHCI_FSL_H
4437
4438 +#include <linux/usb/fsl_xcvr.h>
4439 +
4440  /* offsets for the non-ehci registers in the FSL SOC USB controller */
4441  #define FSL_SOC_USB_ULPIVP     0x170
4442  #define FSL_SOC_USB_PORTSC1    0x184
4443 @@ -34,5 +36,29 @@
4444  #define FSL_SOC_USB_PRICTRL    0x40c   /* NOTE: big-endian */
4445  #define FSL_SOC_USB_SICTRL     0x410   /* NOTE: big-endian */
4446  #define FSL_SOC_USB_CTRL       0x500   /* NOTE: big-endian */
4447 -#define SNOOP_SIZE_2GB         0x1e
4448 +
4449 +#ifdef CONFIG_MPC834x
4450 +#include <sysdev/fsl_usb.h>
4451 +#endif
4452 +
4453 +#ifdef CONFIG_ARCH_MX3
4454 +#include <asm/arch/mx31_usb.h>
4455 +#endif
4456 +
4457 +#ifdef CONFIG_ARCH_MX27
4458 +#include <asm/arch/mx27_usb.h>
4459 +#endif
4460 +
4461 +#ifdef CONFIG_M54455
4462 +#include <asm-m68k/mcf5445x_usb.h>
4463 +#endif
4464 +
4465 +
4466 +static void fsl_platform_set_vbus_power(struct platform_device *pdev, int on)
4467 +{
4468 +       struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
4469 +
4470 +       if (pdata->xcvr_ops && pdata->xcvr_ops->set_vbus_power)
4471 +               pdata->xcvr_ops->set_vbus_power(pdata, on);
4472 +}
4473  #endif                         /* _EHCI_FSL_H */
4474 --- a/drivers/usb/host/ehci-hcd.c
4475 +++ b/drivers/usb/host/ehci-hcd.c
4476 @@ -1043,6 +1043,11 @@ MODULE_LICENSE ("GPL");
4477  #define        PLATFORM_DRIVER         ixp4xx_ehci_driver
4478  #endif
4479
4480 +#ifdef CONFIG_M54455
4481 +#include "ehci-arc.c"
4482 +#define        PLATFORM_DRIVER         ehci_fsl_driver
4483 +#endif
4484 +
4485  #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
4486      !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
4487  #error "missing bus glue for ehci-hcd"
4488 --- a/drivers/usb/host/ehci-mem.c
4489 +++ b/drivers/usb/host/ehci-mem.c
4490 @@ -40,7 +40,8 @@ static inline void ehci_qtd_init(struct
4491  {
4492         memset (qtd, 0, sizeof *qtd);
4493         qtd->qtd_dma = dma;
4494 -       qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
4495 +       // DDD official code` has: qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
4496 +       qtd->hw_token = cpu_to_hc32 (ehci, QTD_STS_HALT);
4497         qtd->hw_next = EHCI_LIST_END(ehci);
4498         qtd->hw_alt_next = EHCI_LIST_END(ehci);
4499         INIT_LIST_HEAD (&qtd->qtd_list);
4500 @@ -211,9 +212,11 @@ static int ehci_mem_init (struct ehci_hc
4501         }
4502
4503         /* Hardware periodic table */
4504 -       ehci->periodic = (__le32 *)
4505 +       // DDD official code has: ehci->periodic = (__le32 *)
4506 +       ehci->periodic = (__hc32 *)
4507                 dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
4508 -                       ehci->periodic_size * sizeof(__le32),
4509 +                       // DDD official: ehci->periodic_size * sizeof(__le32),
4510 +                       ehci->periodic_size * sizeof(__hc32),
4511                         &ehci->periodic_dma, 0);
4512         if (ehci->periodic == NULL) {
4513                 goto fail;
4514 --- a/drivers/usb/host/ehci.h
4515 +++ b/drivers/usb/host/ehci.h
4516 @@ -122,6 +122,12 @@ struct ehci_hcd {                  /* one per controlle
4517
4518         u8                      sbrn;           /* packed release number */
4519
4520 +       /*
4521 +        * OTG controllers and transceivers need software interaction;
4522 +        * other external transceivers should be software-transparent
4523 +        */
4524 +       struct otg_transceiver  *transceiver;
4525 +
4526         /* irq statistics */
4527  #ifdef EHCI_STATS
4528         struct ehci_stats       stats;
4529 @@ -753,6 +759,22 @@ ehci_port_speed(struct ehci_hcd *ehci, u
4530  #define writel_be(val, addr)   __raw_writel(val, (__force unsigned *)addr)
4531  #endif
4532
4533 +#if defined(CONFIG_COLDFIRE)
4534 +/*
4535 + * Sorry, include/asm-m68k/io.h is messed up.  It will give you a
4536 + * BE readl or a LE readl depending on whether or not CONFIG_PCI is set.
4537 + * how broken is that?  Do the right thing here.
4538 + */
4539 +#undef readl
4540 +#undef writel
4541 +
4542 +#define readl(addr)            in_le32((__force unsigned *)(addr))
4543 +#define writel(val,addr)       out_le32((__force unsigned *)(addr),(val))
4544 +
4545 +#define readl_be(addr)         in_be32((__force unsigned *)(addr))
4546 +#define writel_be(val, addr)   out_be32((__force unsigned *)(addr), (val))
4547 +#endif
4548 +
4549  static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
4550                 __u32 __iomem * regs)
4551  {
4552 --- /dev/null
4553 +++ b/drivers/usb/otg/Makefile
4554 @@ -0,0 +1,5 @@
4555 +#
4556 +# Makefile for USB OTG controller  driver
4557 +#
4558 +fsl_usb2_otg-objs              := fsl_otg.o otg_fsm.o
4559 +obj-y                          += fsl_usb2_otg.o
4560 --- /dev/null
4561 +++ b/drivers/usb/otg/fsl_otg.c
4562 @@ -0,0 +1,1515 @@
4563 +/*
4564 + * Copyright (c) Freescale Semiconductor, Inc. 2006-2007
4565 + *
4566 + * USB OTG ULPI driver
4567 + *
4568 + * Based on code for MPC from:
4569 + *  Leo Li<LeoLi@freescale.com>
4570 + *  Jerry Huang<Chang-Ming.Huang@freescale.com>
4571 + *
4572 + * and M5329 code from
4573 + *  Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
4574 + *  Andrey Butok
4575 + *
4576 + *  Initialization based on code from Shlomi Gridish.
4577 + *
4578 + * This program is free software; you can redistribute it and/or modify
4579 + * it under the terms of the GNU General Public License as published by
4580 + * the Free Software Foundation; either version 2 of the License, or
4581 + * (at your option) any later version.
4582 + *
4583 + * This program is distributed in the hope that it will be useful, but
4584 + * WITHOUT ANY WARRANTY; without even the implied warranty of
4585 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
4586 + * General Public License for more details.
4587 + *
4588 + * You should have received a copy of the  GNU General Public License along
4589 + * with this program; if not, write  to the Free Software Foundation, Inc.,
4590 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4591 + ***************************************************************************
4592 + * Changes:
4593 + *   v0.3      08 August 2007          Duck
4594 + *   v0.2      20 October 2006         Andrey Butok
4595 + *             Issues fixing and some changes.
4596 + *   v0.1      September 2006          Yaroslav Vinogradov
4597 + *             Initial version.
4598 + *
4599 + */
4600 +
4601 +#include <linux/module.h>
4602 +#include <linux/moduleparam.h>
4603 +#include <linux/kernel.h>
4604 +#include <linux/delay.h>
4605 +#include <linux/ioport.h>
4606 +#include <linux/sched.h>
4607 +#include <linux/slab.h>
4608 +#include <linux/smp_lock.h>
4609 +#include <linux/proc_fs.h>
4610 +#include <linux/errno.h>
4611 +#include <linux/init.h>
4612 +#include <linux/reboot.h>
4613 +#include <linux/timer.h>
4614 +#include <linux/list.h>
4615 +#include <linux/interrupt.h>
4616 +#include <linux/usb.h>
4617 +#include <linux/device.h>
4618 +#include <linux/platform_device.h>
4619 +#include <linux/usb/ch9.h>
4620 +#include <linux/usb_gadget.h>
4621 +#include <linux/workqueue.h>
4622 +#include <linux/time.h>
4623 +#include <linux/fsl_devices.h>
4624 +#include <linux/usb/fsl_usb2.h>
4625 +
4626 +#include <linux/io.h>
4627 +
4628 +#if defined CONFIG_M54455
4629 +#include <asm/mcfsim.h>
4630 +#endif
4631 +
4632 +#define USE_WORK_QUEUES
4633 +#include "fsl_otg.h"
4634 +
4635 +#define CONFIG_USB_OTG_DEBUG_FILES
4636 +#define DRIVER_VERSION "Revision: 1.56"
4637 +#define DRIVER_AUTHOR "Freescale Semiconductor Inc."
4638 +#define DRIVER_DESC "Freescale USB OTG ULPI Driver"
4639 +#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
4640 +
4641 +MODULE_DESCRIPTION("Freescale USB OTG Controller Driver");
4642 +
4643 +static const char driver_name[] = "fsl-usb2-otg";
4644 +
4645 +static spinlock_t usb_dr_regs_lock;
4646 +
4647 +/*#define HA_DATA_PULSE 1*/
4648 +
4649 +volatile static struct fsl_usb_device_regs *usb_dr_regs;
4650 +static struct fsl_otg *fsl_otg_dev;
4651 +static int srp_wait_done;
4652 +
4653 +/* Driver specific timers */
4654 +struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr,
4655 +       *b_srp_wait_tmr, *a_wait_enum_tmr;
4656 +
4657 +static struct list_head active_timers;
4658 +
4659 +static struct fsl_otg_config fsl_otg_initdata = {
4660 +       .otg_port = 1,
4661 +};
4662 +
4663 +static void dump_state(const char *string, struct otg_fsm *fsm)
4664 +{
4665 +       printk(KERN_DEBUG "%s\n\tOTG state: %s\n", string,
4666 +              state_string(fsl_otg_dev->otg.state));
4667 +       printk(KERN_DEBUG "\tFSM protocol=%s\n", fsm->protocol ?
4668 +              (fsm->protocol == PROTO_HOST ? "Host" : "Gadget")
4669 +              : "None");
4670 +
4671 +       /* regs */
4672 +       printk(KERN_DEBUG "\t  OTGSC 0x%08x\n",
4673 +              fsl_readl(&usb_dr_regs->otgsc));
4674 +       printk(KERN_DEBUG "\tPORTSC1 0x%08x\n",
4675 +              fsl_readl(&usb_dr_regs->portsc1));
4676 +       printk(KERN_DEBUG "\tUSBMODE 0x%08x\n",
4677 +              fsl_readl(&usb_dr_regs->usbmode));
4678 +       printk(KERN_DEBUG "\t USBCMD 0x%08x\n",
4679 +              fsl_readl(&usb_dr_regs->usbcmd));
4680 +       printk(KERN_DEBUG "\t USBSTS 0x%08x\n",
4681 +              fsl_readl(&usb_dr_regs->usbsts));
4682 +
4683 +       /* ------ State Machine Variables ----- */
4684 +       printk(KERN_DEBUG "\ta_bus_req: %d\n", fsm->a_bus_req);
4685 +       printk(KERN_DEBUG "\tb_bus_req: %d\n", fsm->b_bus_req);
4686 +       printk(KERN_DEBUG "\ta_bus_resume: %d\n", fsm->a_bus_resume);
4687 +       printk(KERN_DEBUG "\ta_bus_suspend: %d\n", fsm->a_bus_suspend);
4688 +       printk(KERN_DEBUG "\ta_conn: %d\n", fsm->a_conn);
4689 +       printk(KERN_DEBUG "\ta_sess_vld: %d\n", fsm->a_sess_vld);
4690 +       printk(KERN_DEBUG "\ta_srp_det: %d\n", fsm->a_srp_det);
4691 +       printk(KERN_DEBUG "\ta_vbus_vld: %d\n", fsm->a_vbus_vld);
4692 +       printk(KERN_DEBUG "\tb_bus_resume: %d\n", fsm->b_bus_resume);
4693 +       printk(KERN_DEBUG "\tb_bus_suspend: %d\n", fsm->b_bus_suspend);
4694 +       printk(KERN_DEBUG "\tb_conn: %d\n", fsm->b_conn);
4695 +       printk(KERN_DEBUG "\tb_se0_srp: %d\n", fsm->b_se0_srp);
4696 +       printk(KERN_DEBUG "\tb_sess_end: %d\n", fsm->b_sess_end);
4697 +       printk(KERN_DEBUG "\tb_sess_vld: %d\n", fsm->b_sess_vld);
4698 +       printk(KERN_DEBUG "\tid: %d\n", fsm->id);
4699 +}
4700 +
4701 +
4702 +/* Routines to access transceiver ULPI registers */
4703 +u8 view_ulpi(u8 addr)
4704 +{
4705 +       u32 temp;
4706 +
4707 +       temp = 0x40000000 | (addr << 16);
4708 +       fsl_writel(temp, &usb_dr_regs->ulpiview);
4709 +
4710 +       udelay(1000);
4711 +
4712 +       /* DDD timeout this loop: */
4713 +       do {
4714 +               temp = fsl_readl(&usb_dr_regs->ulpiview);
4715 +       } while (temp & 0x40000000);
4716 +
4717 +       return (temp & 0x0000ff00) >> 8;
4718 +}
4719 +
4720 +int write_ulpi(u8 addr, u8 data)
4721 +{
4722 +       u32 temp;
4723 +
4724 +       temp = 0x60000000 | (addr << 16) | data;
4725 +       fsl_writel(temp, &usb_dr_regs->ulpiview);
4726 +       return 0;
4727 +}
4728 +
4729 +/* prototype declaration */
4730 +void fsl_otg_add_timer(void *timer);
4731 +void fsl_otg_del_timer(void *timer);
4732 +
4733 +/* -------------------------------------------------------------*/
4734 +/* Operations that will be called from OTG Finite State Machine */
4735 +
4736 +/* Charge vbus for vbus pulsing in SRP */
4737 +void fsl_otg_chrg_vbus(int on)
4738 +{
4739 +       u32 tmp;
4740 +
4741 +       VDBG(" %d\n", on);
4742 +
4743 +       tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
4744 +
4745 +       if (on) {
4746 +               tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE;
4747 +               tmp |= OTGSC_CTRL_VBUS_CHARGE;
4748 +       } else {
4749 +               tmp &= ~OTGSC_CTRL_VBUS_CHARGE;
4750 +       }
4751 +       fsl_writel(tmp, &usb_dr_regs->otgsc);
4752 +}
4753 +
4754 +/* Discharge vbus through a resistor to ground */
4755 +void fsl_otg_dischrg_vbus(int on)
4756 +{
4757 +       u32 tmp;
4758 +
4759 +       VDBG(" %d\n", on);
4760 +
4761 +       tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
4762 +
4763 +       if (on)
4764 +               tmp |= OTGSC_CTRL_VBUS_DISCHARGE;
4765 +       else
4766 +               tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE;
4767 +
4768 +       fsl_writel(tmp, &usb_dr_regs->otgsc);
4769 +}
4770 +
4771 +/* A-device driver vbus, controlled through PP bit in PORTSC */
4772 +void fsl_otg_drv_vbus(int on)
4773 +{
4774 +       u32 tmp;
4775 +
4776 +       VDBG(" %d\n", on);
4777 +
4778 +       tmp = fsl_readl(&usb_dr_regs->portsc1) & ~PORTSCX_W1C_BITS;
4779 +
4780 +       if (on)
4781 +               tmp |= PORTSCX_PORT_POWER;
4782 +       else
4783 +               tmp &= ~PORTSCX_PORT_POWER;
4784 +
4785 +       fsl_writel(tmp, &usb_dr_regs->portsc1);
4786 +}
4787 +
4788 +/* Pull-up D+, signalling connect by periperal. Also used in
4789 + * data-line pulsing in SRP */
4790 +void fsl_otg_loc_conn(int on)
4791 +{
4792 +       u32 tmp;
4793 +
4794 +       VDBG(" %d\n", on);
4795 +
4796 +       tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
4797 +
4798 +       if (on)
4799 +               tmp |= OTGSC_CTRL_DATA_PULSING;
4800 +       else
4801 +               tmp &= ~OTGSC_CTRL_DATA_PULSING;
4802 +
4803 +       fsl_writel(tmp, &usb_dr_regs->otgsc);
4804 +}
4805 +
4806 +/* Generate SOF by host.  This is controlled through suspend/resume the
4807 + * port.  In host mode, controller will automatically send SOF.
4808 + * Suspend will block the data on the port.
4809 + */
4810 +void fsl_otg_loc_sof(int on)
4811 +{
4812 +       u32 tmp;
4813 +
4814 +       VDBG(" %d\n", on);
4815 +
4816 +       tmp = fsl_readl(&usb_dr_regs->portsc1) & ~PORTSCX_W1C_BITS;
4817 +
4818 +       if (on)
4819 +               tmp |= PORTSCX_PORT_FORCE_RESUME;
4820 +       else
4821 +               tmp |= PORTSCX_PORT_SUSPEND;
4822 +
4823 +       fsl_writel(tmp, &usb_dr_regs->portsc1);
4824 +}
4825 +
4826 +/* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */
4827 +void fsl_otg_start_pulse(void)
4828 +{
4829 +       u32 __attribute__ ((unused)) tmp;
4830 +
4831 +       VDBG("\n");
4832 +       srp_wait_done = 0;
4833 +
4834 +#ifdef HA_DATA_PULSE
4835 +       tmp = fsl_readl(&usb_dr_regs->otgsc) &= ~OTGSC_INTSTS_MASK;
4836 +       tmp |= OTGSC_HA_DATA_PULSE;
4837 +       fsl_writel(tmp, &usb_dr_regs->otgsc);
4838 +#else
4839 +       fsl_otg_loc_conn(1);
4840 +#endif
4841 +
4842 +       fsl_otg_add_timer(b_data_pulse_tmr);
4843 +}
4844 +
4845 +void fsl_otg_pulse_vbus(void);
4846 +
4847 +void b_data_pulse_end(unsigned long foo)
4848 +{
4849 +#ifdef HA_DATA_PULSE
4850 +#else
4851 +       fsl_otg_loc_conn(0);
4852 +#endif
4853 +
4854 +       /* Do VBUS pulse after data pulse */
4855 +       fsl_otg_pulse_vbus();
4856 +}
4857 +
4858 +void fsl_otg_pulse_vbus(void)
4859 +{
4860 +       srp_wait_done = 0;
4861 +       fsl_otg_chrg_vbus(1);
4862 +       /* start the timer to end vbus charge */
4863 +       fsl_otg_add_timer(b_vbus_pulse_tmr);
4864 +}
4865 +
4866 +void b_vbus_pulse_end(unsigned long foo)
4867 +{
4868 +       fsl_otg_chrg_vbus(0);
4869 +
4870 +       /* As USB3300 using the same a_sess_vld and b_sess_vld voltage
4871 +        * we need to discharge the bus for a while to distinguish
4872 +        * residual voltage of vbus pulsing and A device pull up */
4873 +       fsl_otg_dischrg_vbus(1);
4874 +       fsl_otg_add_timer(b_srp_wait_tmr);
4875 +}
4876 +
4877 +void b_srp_end(unsigned long foo)
4878 +{
4879 +       fsl_otg_dischrg_vbus(0);
4880 +       srp_wait_done = 1;
4881 +
4882 +       if ((fsl_otg_dev->otg.state == OTG_STATE_B_SRP_INIT) &&
4883 +           fsl_otg_dev->fsm.b_sess_vld)
4884 +               fsl_otg_dev->fsm.b_srp_done = 1;
4885 +}
4886 +
4887 +/* Workaround for a_host suspending too fast.  When a_bus_req=0,
4888 + * a_host will start by SRP.  It needs to set b_hnp_enable before
4889 + * actually suspending to start HNP
4890 + */
4891 +void a_wait_enum(unsigned long foo)
4892 +{
4893 +       VDBG("a_wait_enum timeout\n");
4894 +       if (!fsl_otg_dev->otg.host->b_hnp_enable)
4895 +               fsl_otg_add_timer(a_wait_enum_tmr);
4896 +       else
4897 +               otg_statemachine(&fsl_otg_dev->fsm);
4898 +}
4899 +
4900 +/* ------------------------------------------------------*/
4901 +
4902 +/* The timeout callback function to set time out bit */
4903 +void set_tmout(unsigned long indicator)
4904 +{
4905 +       *(int *)indicator = 1;
4906 +}
4907 +
4908 +/* Initialize timers */
4909 +void fsl_otg_init_timers(struct otg_fsm *fsm)
4910 +{
4911 +       /* FSM used timers */
4912 +       fsm->a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
4913 +                               (unsigned long)&fsm->a_wait_vrise_tmout);
4914 +       fsm->a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON,
4915 +                               (unsigned long)&fsm->a_wait_bcon_tmout);
4916 +       fsm->a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
4917 +                               (unsigned long)&fsm->a_aidl_bdis_tmout);
4918 +       fsm->b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST,
4919 +                               (unsigned long)&fsm->b_ase0_brst_tmout);
4920 +       fsm->b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
4921 +                               (unsigned long)&fsm->b_se0_srp);
4922 +       fsm->b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL,
4923 +                               (unsigned long)&fsm->b_srp_done);
4924 +       fsm->a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10,
4925 +                               (unsigned long)&fsm);
4926 +
4927 +       /* device driver used timers */
4928 +       b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0);
4929 +       b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end,
4930 +                               TB_DATA_PLS, 0);
4931 +       b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end,
4932 +                               TB_VBUS_PLS, 0);
4933 +
4934 +}
4935 +
4936 +/* Add timer to timer list */
4937 +void fsl_otg_add_timer(void *gtimer)
4938 +{
4939 +       struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer;
4940 +       struct fsl_otg_timer *tmp_timer;
4941 +
4942 +       /* Check if the timer is already in the active list,
4943 +        * if so update timer count
4944 +        */
4945 +       list_for_each_entry(tmp_timer, &active_timers, list)
4946 +           if (tmp_timer == timer) {
4947 +               timer->count = timer->expires;
4948 +               return;
4949 +       }
4950 +       timer->count = timer->expires;
4951 +       list_add_tail(&timer->list, &active_timers);
4952 +}
4953 +
4954 +/* Remove timer from the timer list; clear timeout status */
4955 +void fsl_otg_del_timer(void *gtimer)
4956 +{
4957 +       struct fsl_otg_timer *timer = (struct fsl_otg_timer *)gtimer;
4958 +       struct fsl_otg_timer *tmp_timer, *del_tmp;
4959 +
4960 +       list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
4961 +               if (tmp_timer == timer)
4962 +                       list_del(&timer->list);
4963 +}
4964 +
4965 +/*
4966 + * Reduce timer count by 1, and find timeout conditions.
4967 + * Called by fsl_otg 1ms timer interrupt
4968 + */
4969 +int fsl_otg_tick_timer(void)
4970 +{
4971 +       struct fsl_otg_timer *tmp_timer, *del_tmp;
4972 +       int expired = 0;
4973 +
4974 +       list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
4975 +               tmp_timer->count--;
4976 +               /* check if timer expires */
4977 +               if (!tmp_timer->count) {
4978 +                       list_del(&tmp_timer->list);
4979 +                       tmp_timer->function(tmp_timer->data);
4980 +                       expired = 1;
4981 +               }
4982 +       }
4983 +
4984 +       return expired;
4985 +}
4986 +
4987 +/* Reset controller, not reset the bus */
4988 +void otg_reset_controller(void)
4989 +{
4990 +       u32 command;
4991 +       unsigned long flags;
4992 +       int timeout;
4993 +
4994 +       VDBG("\n");
4995 +
4996 +       spin_lock_irqsave(&usb_dr_regs_lock, flags);
4997 +
4998 +       command = fsl_readl(&usb_dr_regs->usbcmd);
4999 +       command |= USB_CMD_CTRL_RESET;
5000 +       fsl_writel(command, &usb_dr_regs->usbcmd);
5001 +       spin_unlock_irqrestore(&usb_dr_regs_lock, flags);
5002 +
5003 +       /* Wait reset completed */
5004 +       timeout = 500;
5005 +       while (fsl_readl(&usb_dr_regs->usbcmd) & USB_CMD_CTRL_RESET)
5006 +               udelay(1);
5007 +       if (timeout <= 0)
5008 +               ERR("%s - USBCMD_RST never clear. Timeout is %d \n",
5009 +                       __FUNCTION__, timeout);
5010 +}
5011 +
5012 +/* Call suspend/resume routines in host driver */
5013 +int fsl_otg_start_host(struct otg_fsm *fsm, int on)
5014 +{
5015 +       struct otg_transceiver *xceiv = fsm->transceiver;
5016 +       struct device *dev;
5017 +       struct fsl_otg *otg_dev = container_of(xceiv, struct fsl_otg, otg);
5018 +       u32 retval = 0;
5019 +
5020 +       if (!xceiv->host)
5021 +               return -ENODEV;
5022 +
5023 +       dev = xceiv->host->controller;
5024 +
5025 +       /*
5026 +        * Update a_vbus_vld state as a_vbus_vld int is disabled
5027 +        * in device mode
5028 +        */
5029 +       fsm->a_vbus_vld =
5030 +               !!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID);
5031 +       if (on) {
5032 +               /* start fsl usb host controller */
5033 +               if (otg_dev->host_working)
5034 +                       goto end;
5035 +               else {
5036 +                       otg_reset_controller();
5037 +                       VDBG("host on......\n");
5038 +                       if (dev->driver->resume) {
5039 +                               retval = dev->driver->resume(dev);
5040 +                               if (fsm->id) {
5041 +                                       /* default-b */
5042 +                                       fsl_otg_drv_vbus(1);
5043 +                                       /* Workaround: b_host can't driver
5044 +                                        * vbus, but PP in PORTSC needs to
5045 +                                        * be 1 for host to work.
5046 +                                        * So we set drv_vbus bit in
5047 +                                        * transceiver to 0 thru ULPI. */
5048 +                                       write_ulpi(0x0c, 0x20);
5049 +                               }
5050 +                       }
5051 +
5052 +                       otg_dev->host_working = 1;
5053 +               }
5054 +       } else {
5055 +               /* stop fsl usb host controller */
5056 +               if (!otg_dev->host_working)
5057 +                       goto end;
5058 +               else {
5059 +                       VDBG("host off......\n");
5060 +                       if (dev && dev->driver) {
5061 +                               retval = dev->driver->suspend(dev, PMSG_SUSPEND);
5062 +                               if (fsm->id)
5063 +                                       /* default-b */
5064 +                                       fsl_otg_drv_vbus(0);
5065 +                       }
5066 +                       otg_dev->host_working = 0;
5067 +               }
5068 +       }
5069 +end:
5070 +       return retval;
5071 +}
5072 +
5073 +/*
5074 + * Call suspend and resume function in udc driver
5075 + * to stop and start udc driver.
5076 + */
5077 +int fsl_otg_start_gadget(struct otg_fsm *fsm, int on)
5078 +{
5079 +       struct otg_transceiver *xceiv = fsm->transceiver;
5080 +       struct device *dev;
5081 +
5082 +       VDBG("DDD fsm=%p  xceiv=%p\n", fsm, xceiv);
5083 +       if (!xceiv->gadget || !xceiv->gadget->dev.parent)
5084 +               return -ENODEV;
5085 +
5086 +       VDBG("DDD xceiv=%p  xceiv->gadget=%p  parent=%p\n", xceiv, xceiv->gadget,
5087 +               xceiv->gadget->dev.parent);
5088 +
5089 +       VDBG("gadget %s\n", on ? "on" : "off");
5090 +       /* DDD  dump_state("starting gadget", fsm); */
5091 +
5092 +       dev = xceiv->gadget->dev.parent;
5093 +
5094 +       if (on)
5095 +               dev->driver->resume(dev);
5096 +       else
5097 +               dev->driver->suspend(dev, PMSG_SUSPEND);
5098 +
5099 +       return 0;
5100 +}
5101 +
5102 +static void fsl_otg_enable(struct otg_transceiver *otg_p)
5103 +{
5104 +       struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
5105 +       struct otg_fsm *fsm = &(otg_dev)->fsm;
5106 +       u32 otg_sc;
5107 +
5108 +       /* DDD VDBG(""); */
5109 +       /* enable OTG interrupt */
5110 +       otg_sc = fsl_readl(&usb_dr_regs->otgsc);
5111 +       otg_sc |= OTGSC_INTERRUPT_ENABLE_BITS_MASK;
5112 +       otg_sc &= ~OTGSC_IE_1ms_TIMER;
5113 +       otg_sc &= ~OTGSC_CTRL_VBUS_DISCHARGE;
5114 +       otg_sc |= OTGSC_IE_USB_ID;      /* DDD added this */
5115 +       fsl_writel(otg_sc, &usb_dr_regs->otgsc);
5116 +
5117 +       fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
5118 +
5119 +       if (fsm->id) {
5120 +               otg_p->state = OTG_STATE_UNDEFINED;
5121 +       } else {
5122 +               otg_p->state = OTG_STATE_A_IDLE;
5123 +       }
5124 +
5125 +       otg_p->default_a = (fsm->id == 0);
5126 +       otg_p->host->is_b_host = fsm->id;
5127 +       otg_p->gadget->is_a_peripheral = !fsm->id;
5128 +
5129 +       fsm->a_vbus_vld = 1;
5130 +
5131 +       fsm->b_sess_vld = (otg_sc & OTGSC_STS_B_SESSION_VALID) ? 1 : 0;
5132 +       fsm->a_sess_vld = (otg_sc & OTGSC_STS_A_SESSION_VALID) ? 1 : 0;
5133 +       fsm->b_sess_end = (otg_sc & OTGSC_STS_B_SESSION_END) ? 1 : 0;
5134 +}
5135 +
5136 +/*
5137 + * Called by initialization code of host driver.  Register host controller
5138 + * to the OTG.  Suspend host for OTG role detection.
5139 + */
5140 +static int fsl_otg_set_host(struct otg_transceiver *otg_p, struct usb_bus *host)
5141 +{
5142 +#if 0 // DDD beta-final
5143 +       struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
5144 +       struct device *dev = host->controller;
5145 +
5146 +       if (!otg_p || otg_dev != fsl_otg_dev)
5147 +               return -ENODEV;
5148 +
5149 +       otg_p->host = host;
5150 +       otg_p->host->is_b_host = otg_dev->fsm.id;
5151 +
5152 +       otg_dev->fsm.a_bus_drop = 0;
5153 +       otg_dev->fsm.a_bus_req = 1;
5154 +
5155 +       otg_p->host->otg_port = fsl_otg_initdata.otg_port;
5156 +
5157 +       if (dev && dev->driver) {
5158 +               VDBG("suspending host\n");
5159 +               dev->driver->suspend(dev, PMSG_SUSPEND);
5160 +               otg_dev->host_working = 0;
5161 +               VDBG("back\n");
5162 +       }
5163 +
5164 +
5165 +       /* dump_state("set_host running statemachine", &otg_dev->fsm); DDD */
5166 +       otg_statemachine(&otg_dev->fsm);
5167 +
5168 +       return 0;
5169 +#else
5170 +       struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
5171 +
5172 +       if (!otg_p || otg_dev != fsl_otg_dev)
5173 +               return -ENODEV;
5174 +
5175 +       otg_p->host = host;
5176 +
5177 +       otg_dev->fsm.a_bus_drop = 0;
5178 +       otg_dev->fsm.a_bus_req = 1;
5179 +
5180 +       if (host) {
5181 +               VDBG("host off......\n");
5182 +
5183 +               otg_p->host->otg_port = fsl_otg_initdata.otg_port;
5184 +               otg_p->host->is_b_host = otg_dev->fsm.id;
5185 +               /* must leave time for khubd to finish its thing
5186 +                * before yanking the host driver out from under it,
5187 +                * so suspend the host after a short delay.
5188 +                */
5189 +               otg_dev->host_working = 1;
5190 +               schedule_delayed_work(&otg_dev->otg_event, 100);
5191 +               return 0;
5192 +       } else {                /* host driver going away */
5193 +
5194 +               if (!(le32_to_cpu(otg_dev->dr_mem_map->otgsc) &
5195 +                     OTGSC_STS_USB_ID)) {
5196 +                       /* Mini-A cable connected */
5197 +                       struct otg_fsm *fsm = &otg_dev->fsm;
5198 +
5199 +                       otg_p->state = OTG_STATE_UNDEFINED;
5200 +                       fsm->protocol = PROTO_UNDEF;
5201 +               }
5202 +       }
5203 +
5204 +       otg_dev->host_working = 0;
5205 +
5206 +       otg_statemachine(&otg_dev->fsm);
5207 +
5208 +       return 0;
5209 +#endif
5210 +}
5211 +
5212 +/* Called by initialization code of udc.  Register udc to OTG.*/
5213 +static int fsl_otg_set_peripheral(struct otg_transceiver *otg_p,
5214 +                                 struct usb_gadget *gadget)
5215 +{
5216 +       struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
5217 +
5218 +       VDBG("\n");
5219 +
5220 +       if (!otg_p || otg_dev != fsl_otg_dev)
5221 +               return -ENODEV;
5222 +
5223 +       if (!gadget) {
5224 +               if (!otg_dev->otg.default_a)
5225 +                       otg_p->gadget->ops->vbus_draw(otg_p->gadget, 0);
5226 +               usb_gadget_vbus_disconnect(otg_dev->otg.gadget);
5227 +               otg_dev->otg.gadget = 0;
5228 +               otg_dev->fsm.b_bus_req = 0;
5229 +               otg_statemachine(&otg_dev->fsm);
5230 +               return 0;
5231 +       }
5232 +
5233 +       otg_p->gadget = gadget;
5234 +       otg_p->gadget->is_a_peripheral = !otg_dev->fsm.id;
5235 +
5236 +       otg_dev->fsm.b_bus_req = 1;
5237 +
5238 +#if 0 /* DDD uClinux */
5239 +       if (otg_p->host) {
5240 +               fsl_otg_enable(otg_p);
5241 +               otg_statemachine(&otg_dev->fsm);
5242 +       }
5243 +#endif
5244 +       /* start the gadget right away if the ID pin says Mini-B */
5245 +       DBG("ID pin=%d\n", otg_dev->fsm.id);
5246 +       if (otg_dev->fsm.id == 1) {
5247 +               fsl_otg_start_host(&otg_dev->fsm, 0);
5248 +               fsl_otg_drv_vbus(0);
5249 +               fsl_otg_start_gadget(&otg_dev->fsm, 1);
5250 +       }
5251 +
5252 +       return 0;
5253 +}
5254 +
5255 +/* Set OTG port power, only for B-device */
5256 +static int fsl_otg_set_power(struct otg_transceiver *otg_p, unsigned mA)
5257 +{
5258 +       if (!fsl_otg_dev)
5259 +               return -ENODEV;
5260 +       if (otg_p->state == OTG_STATE_B_PERIPHERAL)
5261 +               printk(KERN_DEBUG "FSL OTG:Draw %d mA\n", mA);
5262 +
5263 +       return 0;
5264 +}
5265 +
5266 +/* Delayed pin detect interrupt processing.
5267 + *
5268 + * When the Mini-A cable is disconnected from the board,
5269 + * the pin-detect interrupt happens before the disconnnect
5270 + * interrupts for the connected device(s).  In order to
5271 + * process the disconnect interrupt(s) prior to switching
5272 + * roles, the pin-detect interrupts are delayed, and handled
5273 + * by this routine.
5274 + */
5275 +static void fsl_otg_event(struct work_struct *work)
5276 +{
5277 +       struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work);
5278 +       struct otg_fsm *fsm = &og->fsm;
5279 +
5280 +       VDBG("DDD fsm->id=%d\n", fsm->id);
5281 +       if (fsm->id) {          /* switch to gadget */
5282 +               fsl_otg_start_host(fsm, 0);
5283 +               fsl_otg_drv_vbus(0);
5284 +               fsl_otg_start_gadget(fsm, 1);
5285 +       }
5286 +}
5287 +
5288 +/* B-device start SRP */
5289 +static int fsl_otg_start_srp(struct otg_transceiver *otg_p)
5290 +{
5291 +       struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
5292 +
5293 +       if (!otg_p || otg_dev != fsl_otg_dev
5294 +           || otg_p->state != OTG_STATE_B_IDLE)
5295 +               return -ENODEV;
5296 +
5297 +       otg_dev->fsm.b_bus_req = 1;
5298 +       otg_statemachine(&otg_dev->fsm);
5299 +
5300 +       return 0;
5301 +}
5302 +
5303 +/* A_host suspend will call this function to start hnp */
5304 +static int fsl_otg_start_hnp(struct otg_transceiver *otg_p)
5305 +{
5306 +       struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
5307 +
5308 +       if (!otg_p || otg_dev != fsl_otg_dev)
5309 +               return -ENODEV;
5310 +
5311 +       VDBG("start_hnp.............\n");
5312 +       /* clear a_bus_req to enter a_suspend state */
5313 +       otg_dev->fsm.a_bus_req = 0;
5314 +       otg_statemachine(&otg_dev->fsm);
5315 +
5316 +       return 0;
5317 +}
5318 +
5319 +/*
5320 + * Interrupt handler.  OTG/host/peripheral share the same int line.
5321 + * OTG driver clears OTGSC interrupts and leaves USB interrupts
5322 + * intact.  It needs to have knowledge of some USB interrupts
5323 + * such as port change.
5324 + */
5325 +irqreturn_t fsl_otg_isr(int irq, void *dev_id)
5326 +{
5327 +       struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
5328 +       struct otg_transceiver *otg = &((struct fsl_otg *)dev_id)->otg;
5329 +       u32 otg_int_src, otg_sc;
5330 +
5331 +       otg_sc = fsl_readl(&usb_dr_regs->otgsc);
5332 +       otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8);
5333 +
5334 +       /* Only clear otg interrupts */
5335 +       fsl_writel(otg_sc, &usb_dr_regs->otgsc);
5336 +
5337 +       /*FIXME: ID change not generate when init to 0 */
5338 +       fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
5339 +       otg->default_a = (fsm->id == 0);
5340 +
5341 +       /* process OTG interrupts */
5342 +       if (otg_int_src) {
5343 +               VDBG("\nOTG irq 0x%08x\n", otg_int_src);
5344 +
5345 +               if (otg_int_src & OTGSC_INTSTS_USB_ID) {
5346 +                       fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
5347 +                       otg->default_a = (fsm->id == 0);
5348 +                       /* clear conn information */
5349 +                       if (fsm->id)
5350 +                               fsm->b_conn = 0;
5351 +                       else
5352 +                               fsm->a_conn = 0;
5353 +
5354 +                       if (otg->host)
5355 +                               otg->host->is_b_host = fsm->id;
5356 +                       if (otg->gadget)
5357 +                               otg->gadget->is_a_peripheral = !fsm->id;
5358 +                       VDBG("ID int (ID is %d)\n", fsm->id);
5359 +
5360 +                       if (fsm->id) {  /* switch to gadget */
5361 +                               schedule_delayed_work(&((struct fsl_otg *)
5362 +                                                       dev_id)->otg_event, 25);
5363 +                       } else {        /* switch to host */
5364 +                               cancel_delayed_work(&
5365 +                                                   ((struct fsl_otg *)dev_id)->
5366 +                                                   otg_event);
5367 +                               fsl_otg_start_gadget(fsm, 0);
5368 +                               fsl_otg_drv_vbus(1);
5369 +                               fsl_otg_start_host(fsm, 1);
5370 +                       }
5371 +
5372 +                       return IRQ_HANDLED;
5373 +               }
5374 +       }
5375 +
5376 +       return IRQ_NONE;
5377 +}
5378 +
5379 +
5380 +#if 0 // DDD feta-final
5381 +irqreturn_t foo_fsl_otg_isr(int irq, void *dev_id)
5382 +{
5383 +       struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
5384 +       struct otg_transceiver *otg = &((struct fsl_otg *)dev_id)->otg;
5385 +       u32 otg_int_src, usb_int_src, otg_sc;
5386 +       int trigger = 0;
5387 +       int tmp;
5388 +
5389 +       usb_int_src = fsl_readl(&usb_dr_regs->usbsts);
5390 +       otg_sc = fsl_readl(&usb_dr_regs->otgsc);
5391 +       otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8);
5392 +
5393 +       /* Only clear otg interrupts */
5394 +       fsl_writel(otg_sc, &usb_dr_regs->otgsc);
5395 +
5396 +       /*FIXME: ID change not generate when init to 0 */
5397 +       /* process OTG interrupts */
5398 +       if (otg_int_src) {
5399 +               VDBG("\nOTG irq 0x%08x\n", otg_int_src);
5400 +               if (otg_int_src & OTGSC_INTSTS_1MS_TIMER)
5401 +                       trigger = fsl_otg_tick_timer();
5402 +
5403 +               if (otg_int_src & OTGSC_INTSTS_USB_ID) {
5404 +                       fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
5405 +                       otg->default_a = (fsm->id == 0);
5406 +                       if (otg->host)
5407 +                               otg->host->is_b_host = fsm->id;
5408 +                       if (otg->gadget)
5409 +                               otg->gadget->is_a_peripheral = !fsm->id;
5410 +                       VDBG("IRQ=ID now=%d\n", fsm->id);
5411 +
5412 +                       if (fsm->id) {  /* switch to gadget */
5413 +                               schedule_delayed_work(&((struct fsl_otg *)
5414 +                                                       dev_id)->otg_event, 25);
5415 +                       } else {        /* switch to host */
5416 +                               cancel_delayed_work(&
5417 +                                                   ((struct fsl_otg *)dev_id)->
5418 +                                                   otg_event);
5419 +                               fsl_otg_start_gadget(fsm, 0);
5420 +                               fsl_otg_drv_vbus(1);
5421 +                               fsl_otg_start_host(fsm, 1);
5422 +                       }
5423 +
5424 +                       return IRQ_HANDLED;
5425 +               }
5426 +               if (otg_int_src & OTGSC_INTSTS_DATA_PULSE) {
5427 +                       fsm->a_srp_det = 1;
5428 +                       trigger = 1;
5429 +                       VDBG("!!!!Data pulse int\n");
5430 +               }
5431 +               if (otg_int_src & OTGSC_INTSTS_A_SESSION_VALID) {
5432 +                       fsm->a_sess_vld =
5433 +                           (otg_sc & OTGSC_STS_A_SESSION_VALID) ? 1 : 0;
5434 +                       /* detect VBUS pulsing */
5435 +                       if ((fsm->transceiver->state == OTG_STATE_A_IDLE)
5436 +                           && fsm->a_sess_vld)
5437 +                               fsm->a_srp_det = 1;
5438 +                       trigger = 1;
5439 +                       VDBG("!!!a_sess_vld int state=%d\n", fsm->a_sess_vld);
5440 +               }
5441 +               if (otg_int_src & OTGSC_INTSTS_A_VBUS_VALID) {
5442 +                       fsm->a_vbus_vld = !!(otg_sc & OTGSC_STS_A_VBUS_VALID);
5443 +                       trigger = 1;
5444 +                       VDBG("!!!a_vbus_vld int state=%d\n", fsm->a_vbus_vld);
5445 +
5446 +#if 1
5447 +               if ((fsm->a_vbus_vld == 0) && (fsm->id == 0)) {
5448 +                       if (fsm->transceiver->state != OTG_STATE_A_WAIT_VFALL)
5449 +                               /* Warning insted of transfer to Error state. */
5450 +                               printk(KERN_WARNING "ulpi: The USB Device is "
5451 +                                      "sinking too much current!!\n");
5452 +                       fsm->a_vbus_vld = 1;
5453 +               }
5454 +#endif
5455 +
5456 +
5457 +               }
5458 +               if (otg_int_src & OTGSC_INTSTS_B_SESSION_VALID) {
5459 +                       fsm->b_sess_vld =
5460 +                           (otg_sc & OTGSC_STS_B_SESSION_VALID) ? 1 : 0;
5461 +                       trigger = 1;
5462 +                       /* SRP done */
5463 +                       if ((fsl_otg_dev->otg.state == OTG_STATE_B_SRP_INIT) &&
5464 +                           fsm->b_sess_vld && srp_wait_done)
5465 +                               fsm->b_srp_done = 1;
5466 +                       VDBG("!!!!b_sess_vld int state=%d\n", fsm->b_sess_vld);
5467 +               }
5468 +               if (otg_int_src & OTGSC_INTSTS_B_SESSION_END) {
5469 +                       fsm->b_sess_end =
5470 +                           (otg_sc & OTGSC_STS_B_SESSION_END) ? 1 : 0;
5471 +                       trigger = 1;
5472 +                       VDBG("!!!!b_sess_end int state=%d\n", fsm->b_sess_end);
5473 +               }
5474 +       }
5475 +
5476 +       /* process USB interrupts */
5477 +       if ((usb_int_src & USB_STS_PORT_CHANGE)
5478 +           && (fsm->protocol == PROTO_HOST)) {
5479 +               VDBG("\nUSB irq A 0x%08x\n", usb_int_src);
5480 +               /* Device resume do not generate statemachine change */
5481 +               if (fsl_readl(&usb_dr_regs->portsc1) &
5482 +                   PORTSCX_PORT_FORCE_RESUME) {
5483 +                       if (otg->default_a) {
5484 +                               fsm->b_bus_resume = 1;
5485 +                               trigger = 1;
5486 +                       } else {
5487 +                               fsm->a_bus_resume = 1;
5488 +                               trigger = 1;
5489 +                       }
5490 +               }
5491 +
5492 +               tmp = (fsl_readl(&usb_dr_regs->portsc1) &
5493 +                      PORTSCX_CURRENT_CONNECT_STATUS) ? 1 : 0;
5494 +               if (otg->default_a && (fsm->b_conn != tmp)) {
5495 +                       fsm->b_conn = tmp;
5496 +                       trigger = 1;
5497 +               } else if (!otg->default_a && (fsm->a_conn != tmp)) {
5498 +                       fsm->a_conn = tmp;
5499 +                       trigger = 1;
5500 +               }
5501 +       }
5502 +       /* Workaround: sometimes CSC bit will lost.  We change to
5503 +        * polling CCS bit for connect change */
5504 +       if (fsm->protocol == PROTO_GADGET) {
5505 +               if (usb_int_src & USB_STS_SUSPEND) {
5506 +                       VDBG("\nUSB irq B 0x%08x\n", usb_int_src);
5507 +                       VDBG("peripheral detected suspend\n");
5508 +                       if (otg->default_a)
5509 +                               /* A-device detects B suspend */
5510 +                               fsm->b_bus_suspend = 1;
5511 +                       else
5512 +                               /* B-device detects A suspend */
5513 +                               fsm->a_bus_suspend = 1;
5514 +                       trigger = 1;
5515 +               } else if (usb_int_src & USB_STS_PORT_CHANGE) {
5516 +                       VDBG("\nUSB irq C 0x%08x\n", usb_int_src);
5517 +                       VDBG("peripheral resumed\n");
5518 +                       if (otg->default_a)
5519 +                               fsm->b_bus_suspend = 0;
5520 +                       else
5521 +                               fsm->a_bus_suspend = 0;
5522 +                       trigger = 1;
5523 +               }
5524 +       }
5525 +
5526 +       /* Invoke statemachine until state is stable */
5527 +       while (trigger) {
5528 +               trigger = otg_statemachine(fsm);
5529 +       }
5530 +
5531 +       return IRQ_HANDLED;
5532 +}
5533 +#endif
5534 +
5535 +
5536 +static struct otg_fsm_ops fsl_otg_ops = {
5537 +       .chrg_vbus = fsl_otg_chrg_vbus,
5538 +       .drv_vbus = fsl_otg_drv_vbus,
5539 +       .loc_conn = fsl_otg_loc_conn,
5540 +       .loc_sof = fsl_otg_loc_sof,
5541 +       .start_pulse = fsl_otg_start_pulse,
5542 +
5543 +       .add_timer = fsl_otg_add_timer,
5544 +       .del_timer = fsl_otg_del_timer,
5545 +
5546 +       .start_host = fsl_otg_start_host,
5547 +       .start_gadget = fsl_otg_start_gadget,
5548 +};
5549 +
5550 +/* Initialize the global variable fsl_otg_dev and request IRQ for OTG */
5551 +int fsl_otg_cfg(struct platform_device *pdev)
5552 +{
5553 +       int status;
5554 +       struct fsl_otg *fsl_otg_tc;
5555 +       struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
5556 +       struct resource *res;
5557 +
5558 +       DBG("\n");
5559 +
5560 +       if (fsl_otg_dev)
5561 +               return 0;
5562 +
5563 +       /* allocate space to fsl otg device */
5564 +       fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL);
5565 +       if (!fsl_otg_tc)
5566 +               return -ENODEV;
5567 +
5568 +#if 1 // DDD
5569 +       if (pdata->regs) {
5570 +               fsl_otg_tc->dr_mem_map = pdata->regs;
5571 +       } else {
5572 +               res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5573 +               if (!res) {
5574 +                       dev_err(&pdev->dev, "no register addr.\n");
5575 +                       return -ENODEV;
5576 +               }
5577 +
5578 +               printk("DDD %s(): rsrc_start=0x%x  rsrc_len=0x%x\n",
5579 +                    __FUNCTION__, res->start, res->end - res->start + 1);
5580 +
5581 +               if (!request_mem_region(res->start, res->end - res->start + 1,
5582 +                                       "OTG")) {
5583 +                       dev_dbg(&pdev->dev, "request_mem_region failed\n");
5584 +                       return -EBUSY;
5585 +               }
5586 +               fsl_otg_tc->dr_mem_map = ioremap(res->start,
5587 +                                                res->end - res->start + 1);
5588 +       }
5589 +       DBG("set dr_mem_map to 0x%p\n", fsl_otg_tc->dr_mem_map);
5590 +
5591 +#endif
5592 +       INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event);
5593 +
5594 +       INIT_LIST_HEAD(&active_timers);
5595 +       fsl_otg_init_timers(&fsl_otg_tc->fsm);
5596 +
5597 +       /* Set OTG state machine operations */
5598 +       fsl_otg_tc->fsm.ops = &fsl_otg_ops;
5599 +
5600 +#if 1 /* DDD */
5601 +       /* record initial state of ID pin */
5602 +       fsl_otg_tc->fsm.id = (fsl_otg_tc->dr_mem_map->otgsc & OTGSC_STS_USB_ID)
5603 +           ? 1 : 0;
5604 +       DBG("initial ID pin=%d\n", fsl_otg_tc->fsm.id);
5605 +#endif
5606 +       /* initialize the otg structure */
5607 +       fsl_otg_tc->otg.label = DRIVER_DESC;
5608 +       fsl_otg_tc->otg.set_host = fsl_otg_set_host;
5609 +       fsl_otg_tc->otg.set_peripheral = fsl_otg_set_peripheral;
5610 +       fsl_otg_tc->otg.set_power = fsl_otg_set_power;
5611 +       fsl_otg_tc->otg.start_hnp = fsl_otg_start_hnp;
5612 +       fsl_otg_tc->otg.start_srp = fsl_otg_start_srp;
5613 +
5614 +       fsl_otg_dev = fsl_otg_tc;
5615 +
5616 +       /* Store the otg transceiver */
5617 +       status = otg_set_transceiver(&fsl_otg_tc->otg);
5618 +       if (status) {
5619 +               printk(KERN_WARNING ": unable to register OTG transceiver.\n");
5620 +               return status;
5621 +       }
5622 +
5623 +       return 0;
5624 +}
5625 +
5626 +/* OTG Initialization*/
5627 +int usb_otg_start(struct platform_device *pdev)
5628 +{
5629 +       struct fsl_otg *p_otg;
5630 +       struct otg_transceiver *otg_trans = otg_get_transceiver();
5631 +       struct otg_fsm *fsm;
5632 +       int status;
5633 +       u32 temp;
5634 +       struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
5635 +       int timeout;
5636 +
5637 +       DBG("\n");
5638 +
5639 +       p_otg = container_of(otg_trans, struct fsl_otg, otg);
5640 +       fsm = &p_otg->fsm;
5641 +
5642 +       /* Initialize the state machine structure with default values */
5643 +       SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED);
5644 +       fsm->transceiver = &p_otg->otg;
5645 +
5646 +       usb_dr_regs = p_otg->dr_mem_map;
5647 +       DBG("set usb_dr_regs to 0x%p\n", usb_dr_regs);
5648 +
5649 +       /* request irq */
5650 +       p_otg->irq = platform_get_irq(pdev, 0);
5651 +       status = request_irq(p_otg->irq, fsl_otg_isr,
5652 +                               IRQF_SHARED, driver_name, p_otg);
5653 +       if (status) {
5654 +               dev_dbg(p_otg->otg.dev, "can't get IRQ %d, error %d\n",
5655 +                       p_otg->irq, status);
5656 +               kfree(p_otg);
5657 +               return status;
5658 +       }
5659 +
5660 +
5661 +       /* stop the controller */
5662 +       temp = fsl_readl(&usb_dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
5663 +       fsl_writel(temp, &usb_dr_regs->usbcmd);
5664 +
5665 +       /* reset the controller */
5666 +       temp = fsl_readl(&usb_dr_regs->usbcmd);
5667 +       temp |= USB_CMD_CTRL_RESET;
5668 +       fsl_writel(temp, &usb_dr_regs->usbcmd);
5669 +
5670 +       /* wait reset completed */
5671 +       timeout = 500;
5672 +       while (timeout-- &&
5673 +               fsl_readl(&usb_dr_regs->usbcmd) & USB_CMD_CTRL_RESET)
5674 +               udelay(1);
5675 +       if (timeout <= 0)
5676 +               ERR("%s - USBCMD_RST never clear. Timeout is %d \n",
5677 +                       __FUNCTION__, timeout);
5678 +
5679 +       /* configure the VBUSHS as IDLE(both host and device) */
5680 +#if 0
5681 +       /* DDD really have to check into setting the following */
5682 +       fsl_writel(USB_MODE_STREAM_DISABLE, &usb_dr_regs->usbmode);
5683 +#else
5684 +       temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USBMODE_ES : 0);
5685 +       fsl_writel(temp, &usb_dr_regs->usbmode);
5686 +#endif
5687 +
5688 +       /* configure PHY interface */
5689 +       temp = fsl_readl(&usb_dr_regs->portsc1);
5690 +       temp &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PTW_8BIT);
5691 +
5692 +       /* DDD wrong xcvr setting stuff follows */
5693 +       temp |= PORTSCX_PTS_ULPI;
5694 +       fsl_writel(temp, &usb_dr_regs->portsc1);
5695 +
5696 +
5697 +       /* disable all interrupt and clear all OTGSC status */
5698 +       temp = fsl_readl(&usb_dr_regs->otgsc);
5699 +       temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
5700 +#if 0 // DDD
5701 +       /* DDD only want ID int
5702 +        * temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE;
5703 +        */
5704 +       temp |= OTGSC_IE_USB_ID;        /* DDD added this */
5705 +       temp &= ~OTGSC_IE_1ms_TIMER;    /* DDD added this */
5706 +#else
5707 +       temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE;
5708 +#endif
5709 +       fsl_writel(temp, &usb_dr_regs->otgsc);
5710 +
5711 +       fsl_otg_drv_vbus(0);
5712 +
5713 +#if 0 // DDD beta-final
5714 +       temp = fsl_readl(&usb_dr_regs->otgsc);
5715 +       temp |= OTGSC_IE_A_SESSION_VALID;
5716 +       fsl_writel(temp, &usb_dr_regs->otgsc);
5717 +#else
5718 +       /*
5719 +        * The identification (id) input is FALSE when a Mini-A plug is inserted
5720 +        * in the devices Mini-AB receptacle. Otherwise, this input is TRUE.
5721 +        * Also: record initial state of ID pin
5722 +        */
5723 +       if (fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_USB_ID) {
5724 +               p_otg->otg.state = OTG_STATE_UNDEFINED;
5725 +               p_otg->fsm.id = 1;
5726 +       } else {
5727 +               p_otg->otg.state = OTG_STATE_A_IDLE;
5728 +               p_otg->fsm.id = 0;
5729 +       }
5730 +
5731 +       DBG("initial ID pin=%d\n", p_otg->fsm.id);
5732 +
5733 +       /* enable OTG ID pin interrupt */
5734 +       temp = fsl_readl(&usb_dr_regs->otgsc);
5735 +       temp |= OTGSC_IE_USB_ID;
5736 +       temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_IE_1ms_TIMER);
5737 +       fsl_writel(temp, &usb_dr_regs->otgsc);
5738 +#endif
5739 +
5740 +       return 0;
5741 +}
5742 +
5743 +/* Initialize board specific registers,PIB board,clock and pin multiplexing */
5744 +static int board_init(struct platform_device *pdev)
5745 +{
5746 +       struct fsl_usb2_platform_data *pdata;
5747 +       pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
5748 +
5749 +       /*
5750 +        * do platform specific init: check the clock, grab/config pins, etc.
5751 +        */
5752 +       if (pdata->platform_init(pdev) != 0)
5753 +               return -EINVAL;
5754 +
5755 +       return 0;
5756 +}
5757 +
5758 +/*-------------------------------------------------------------------------
5759 +               PROC File System Support
5760 +-------------------------------------------------------------------------*/
5761 +#ifdef CONFIG_USB_OTG_DEBUG_FILES
5762 +
5763 +#include <linux/seq_file.h>
5764 +
5765 +static const char proc_filename[] = "driver/fsl_usb2_otg";
5766 +
5767 +static int otg_proc_read(char *page, char **start, off_t off, int count,
5768 +                        int *eof, void *_dev)
5769 +{
5770 +       struct otg_fsm *fsm = &fsl_otg_dev->fsm;
5771 +       char *buf = page;
5772 +       char *next = buf;
5773 +       unsigned size = count;
5774 +       unsigned long flags;
5775 +       int t;
5776 +       u32 tmp_reg;
5777 +
5778 +       if (off != 0)
5779 +               return 0;
5780 +
5781 +       spin_lock_irqsave(&fsm->lock, flags);
5782 +
5783 +       /* ------basic driver infomation ---- */
5784 +       t = scnprintf(next, size,
5785 +                     DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n",
5786 +                     DRIVER_VERSION);
5787 +       size -= t;
5788 +       next += t;
5789 +
5790 +       /* ------ Registers ----- */
5791 +       /* tmp_reg = le32_to_cpu(usb_dr_regs->otgsc); */
5792 +       tmp_reg = fsl_readl(&usb_dr_regs->otgsc);
5793 +       t = scnprintf(next, size, "OTGSC reg: 0x%08x\n", tmp_reg);
5794 +       size -= t;
5795 +       next += t;
5796 +
5797 +       /* tmp_reg = le32_to_cpu(usb_dr_regs->portsc); */
5798 +       tmp_reg = fsl_readl(&usb_dr_regs->portsc1);
5799 +       t = scnprintf(next, size, "PORTSC reg: 0x%08x\n", tmp_reg);
5800 +       size -= t;
5801 +       next += t;
5802 +
5803 +       /* tmp_reg = le32_to_cpu(usb_dr_regs->usbmode); */
5804 +       tmp_reg = fsl_readl(&usb_dr_regs->usbmode);
5805 +       t = scnprintf(next, size, "USBMODE reg: 0x%08x\n", tmp_reg);
5806 +       size -= t;
5807 +       next += t;
5808 +
5809 +       /* tmp_reg = le32_to_cpu(usb_dr_regs->usbcmd); */
5810 +       tmp_reg = fsl_readl(&usb_dr_regs->usbcmd);
5811 +       t = scnprintf(next, size, "USBCMD reg: 0x%08x\n", tmp_reg);
5812 +       size -= t;
5813 +       next += t;
5814 +
5815 +       /* tmp_reg = le32_to_cpu(usb_dr_regs->usbsts); */
5816 +       tmp_reg = fsl_readl(&usb_dr_regs->usbsts);
5817 +       t = scnprintf(next, size, "USBSTS reg: 0x%08x\n", tmp_reg);
5818 +       size -= t;
5819 +       next += t;
5820 +
5821 +       /* ------ State ----- */
5822 +       t = scnprintf(next, size, "FSM protocol=%d %s\n", fsm->protocol,
5823 +               fsm->protocol ?
5824 +               (fsm->protocol == PROTO_HOST ? "Host" : "Gadget")
5825 +               : "None");
5826 +       size -= t;
5827 +       next += t;
5828 +
5829 +       t = scnprintf(next, size,
5830 +                     "OTG state: %s\n\n",
5831 +                     state_string(fsl_otg_dev->otg.state));
5832 +       size -= t;
5833 +       next += t;
5834 +
5835 +       /* ------ State Machine Variables ----- */
5836 +       t = scnprintf(next, size, "a_bus_req: %d\n", fsm->a_bus_req);
5837 +       size -= t;
5838 +       next += t;
5839 +
5840 +       t = scnprintf(next, size, "b_bus_req: %d\n", fsm->b_bus_req);
5841 +       size -= t;
5842 +       next += t;
5843 +
5844 +       t = scnprintf(next, size, "a_bus_resume: %d\n", fsm->a_bus_resume);
5845 +       size -= t;
5846 +       next += t;
5847 +
5848 +       t = scnprintf(next, size, "a_bus_suspend: %d\n", fsm->a_bus_suspend);
5849 +       size -= t;
5850 +       next += t;
5851 +
5852 +       t = scnprintf(next, size, "a_conn: %d\n", fsm->a_conn);
5853 +       size -= t;
5854 +       next += t;
5855 +
5856 +       t = scnprintf(next, size, "a_sess_vld: %d\n", fsm->a_sess_vld);
5857 +       size -= t;
5858 +       next += t;
5859 +
5860 +       t = scnprintf(next, size, "a_srp_det: %d\n", fsm->a_srp_det);
5861 +       size -= t;
5862 +       next += t;
5863 +
5864 +       t = scnprintf(next, size, "a_vbus_vld: %d\n", fsm->a_vbus_vld);
5865 +       size -= t;
5866 +       next += t;
5867 +
5868 +       t = scnprintf(next, size, "b_bus_resume: %d\n", fsm->b_bus_resume);
5869 +       size -= t;
5870 +       next += t;
5871 +
5872 +       t = scnprintf(next, size, "b_bus_suspend: %d\n", fsm->b_bus_suspend);
5873 +       size -= t;
5874 +       next += t;
5875 +
5876 +       t = scnprintf(next, size, "b_conn: %d\n", fsm->b_conn);
5877 +       size -= t;
5878 +       next += t;
5879 +
5880 +       t = scnprintf(next, size, "b_se0_srp: %d\n", fsm->b_se0_srp);
5881 +       size -= t;
5882 +       next += t;
5883 +
5884 +       t = scnprintf(next, size, "b_sess_end: %d\n", fsm->b_sess_end);
5885 +       size -= t;
5886 +       next += t;
5887 +
5888 +       t = scnprintf(next, size, "b_sess_vld: %d\n", fsm->b_sess_vld);
5889 +       size -= t;
5890 +       next += t;
5891 +
5892 +       t = scnprintf(next, size, "id: %d\n", fsm->id);
5893 +       size -= t;
5894 +       next += t;
5895 +
5896 +       spin_unlock_irqrestore(&fsm->lock, flags);
5897 +
5898 +       *eof = 1;
5899 +       return count - size;
5900 +}
5901 +
5902 +#define create_proc_file()     create_proc_read_entry(proc_filename, \
5903 +                               0, NULL, otg_proc_read, NULL)
5904 +
5905 +#define remove_proc_file()     remove_proc_entry(proc_filename, NULL)
5906 +
5907 +#else                          /* !CONFIG_USB_OTG_DEBUG_FILES */
5908 +
5909 +#define create_proc_file()     do {} while (0)
5910 +#define remove_proc_file()     do {} while (0)
5911 +
5912 +#endif                         /*CONFIG_USB_OTG_DEBUG_FILES */
5913 +
5914 +/*----------------------------------------------------------*/
5915 +/* Char driver interface to control some OTG input */
5916 +
5917 +/*
5918 + * This function handle some ioctl command,such as get otg
5919 + * status and set host suspend
5920 + */
5921 +static int fsl_otg_ioctl(struct inode *inode, struct file *file,
5922 +                        unsigned int cmd, unsigned long arg)
5923 +{
5924 +       u32 retval = 0;
5925 +
5926 +       switch (cmd) {
5927 +       case GET_OTG_STATUS:
5928 +               retval = fsl_otg_dev->host_working;
5929 +               break;
5930 +
5931 +       case SET_A_SUSPEND_REQ:
5932 +               fsl_otg_dev->fsm.a_suspend_req = arg;
5933 +               break;
5934 +
5935 +       case SET_A_BUS_DROP:
5936 +               fsl_otg_dev->fsm.a_bus_drop = arg;
5937 +               break;
5938 +
5939 +       case SET_A_BUS_REQ:
5940 +               fsl_otg_dev->fsm.a_bus_req = arg;
5941 +               break;
5942 +
5943 +       case SET_B_BUS_REQ:
5944 +               fsl_otg_dev->fsm.b_bus_req = arg;
5945 +               break;
5946 +
5947 +       default:
5948 +               break;
5949 +       }
5950 +
5951 +       otg_statemachine(&fsl_otg_dev->fsm);
5952 +
5953 +       return retval;
5954 +}
5955 +
5956 +static int fsl_otg_open(struct inode *inode, struct file *file)
5957 +{
5958 +
5959 +       return 0;
5960 +}
5961 +
5962 +static int fsl_otg_release(struct inode *inode, struct file *file)
5963 +{
5964 +
5965 +       return 0;
5966 +}
5967 +
5968 +static struct file_operations otg_fops = {
5969 +       .owner = THIS_MODULE,
5970 +       .llseek = NULL,
5971 +       .read = NULL,
5972 +       .write = NULL,
5973 +       .ioctl = fsl_otg_ioctl,
5974 +       .open = fsl_otg_open,
5975 +       .release = fsl_otg_release,
5976 +};
5977 +
5978 +static int __init fsl_otg_probe(struct platform_device *pdev)
5979 +{
5980 +       int status;
5981 +       struct fsl_usb2_platform_data *pdata;
5982 +
5983 +       DBG("pdev=0x%p\n", pdev);
5984 +
5985 +       if (!pdev)
5986 +               return -ENODEV;
5987 +
5988 +       if (!pdev->dev.platform_data)
5989 +               return -ENOMEM;
5990 +
5991 +       pdata = pdev->dev.platform_data;
5992 +#if 1 // DDD do this elsewhere
5993 +       /* Initialize the clock, multiplexing pin and PHY interface */
5994 +       board_init(pdev);
5995 +#endif
5996 +
5997 +       /* configure the OTG */
5998 +       status = fsl_otg_cfg(pdev);
5999 +       if (status) {
6000 +               printk(KERN_INFO "Couldn't init OTG module\n");
6001 +               return -status;
6002 +       }
6003 +
6004 +       /* start OTG */
6005 +       status = usb_otg_start(pdev);
6006 +
6007 +       if (register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops)) {
6008 +               printk(KERN_WARNING FSL_OTG_NAME
6009 +                      ": unable to register FSL OTG device\n");
6010 +               return -EIO;
6011 +       }
6012 +
6013 +       create_proc_file();
6014 +       return status;
6015 +}
6016 +
6017 +static int fsl_otg_remove(struct platform_device *pdev)
6018 +{
6019 +       u32 ie;
6020 +       struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
6021 +       unsigned long flags;
6022 +
6023 +       DBG("pdev=0x%p  pdata=0x%p\n", pdev, pdata);
6024 +
6025 +       otg_set_transceiver(NULL);
6026 +
6027 +       /* disable and clear OTGSC interrupts */
6028 +       spin_lock_irqsave(&usb_dr_regs_lock, flags);
6029 +       ie = fsl_readl(&usb_dr_regs->otgsc);
6030 +       ie &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
6031 +       ie |= OTGSC_INTERRUPT_STATUS_BITS_MASK;
6032 +       fsl_writel(ie, &usb_dr_regs->otgsc);
6033 +       spin_unlock_irqrestore(&usb_dr_regs_lock, flags);
6034 +
6035 +       free_irq(fsl_otg_dev->irq, fsl_otg_dev);
6036 +
6037 +       kfree(fsl_otg_dev);
6038 +
6039 +       remove_proc_file();
6040 +
6041 +       unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME);
6042 +
6043 +       if (pdata->platform_uninit)
6044 +               pdata->platform_uninit(pdev);
6045 +
6046 +       fsl_otg_dev = NULL;
6047 +       return 0;
6048 +}
6049 +
6050 +struct platform_driver fsl_otg_driver = {
6051 +       .probe = fsl_otg_probe,
6052 +       .remove = fsl_otg_remove,
6053 +       .driver = {
6054 +               .name  = driver_name,
6055 +               .owner = THIS_MODULE,
6056 +       },
6057 +};
6058 +
6059 +/*-------------------------------------------------------------------------*/
6060 +
6061 +static int __init fsl_usb_otg_init(void)
6062 +{
6063 +       printk(KERN_INFO DRIVER_DESC " loaded, %s\n", DRIVER_VERSION);
6064 +       return platform_driver_register(&fsl_otg_driver);
6065 +}
6066 +
6067 +static void __exit fsl_usb_otg_exit(void)
6068 +{
6069 +       platform_driver_unregister(&fsl_otg_driver);
6070 +}
6071 +
6072 +module_init(fsl_usb_otg_init);
6073 +module_exit(fsl_usb_otg_exit);
6074 +
6075 +MODULE_DESCRIPTION(DRIVER_INFO);
6076 +MODULE_AUTHOR(DRIVER_AUTHOR);
6077 +MODULE_LICENSE("GPL");
6078 --- /dev/null
6079 +++ b/drivers/usb/otg/fsl_otg.h
6080 @@ -0,0 +1,139 @@
6081 +/*
6082 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6083 + */
6084 +
6085 +/*
6086 + * The code contained herein is licensed under the GNU General Public
6087 + * License. You may obtain a copy of the GNU General Public License
6088 + * Version 2 or later at the following locations:
6089 + *
6090 + * http://www.opensource.org/licenses/gpl-license.html
6091 + * http://www.gnu.org/copyleft/gpl.html
6092 + */
6093 +
6094 +#ifndef FSL_OTG_H
6095 +#define FSL_OTG_H
6096 +#include <linux/usb/otg.h>
6097 +#include "otg_fsm.h"
6098 +#include <linux/ioctl.h>
6099 +
6100 +#define ERR(format, arg...) \
6101 +printk(KERN_ERR "%s:%s: " format "\n" , __FILE__,  __FUNCTION__ , ## arg)
6102 +
6103 +/*
6104 + *  A-DEVICE timing  constants
6105 + */
6106 +
6107 +/* Wait for VBUS Rise  */
6108 +#define TA_WAIT_VRISE  (100)   /* a_wait_vrise 100 ms, section: 6.6.5.1 */
6109 +
6110 +/* Wait for B-Connect */
6111 +#define TA_WAIT_BCON   (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2
6112 +                                * This is only used to get out of
6113 +                                * OTG_STATE_A_WAIT_BCON state if there was
6114 +                                * no connection for these many milliseconds
6115 +                                */
6116 +
6117 +/* A-Idle to B-Disconnect */
6118 +/* It is necessary for this timer to be more than 750 ms because of a bug in OPT
6119 + * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated
6120 + * in the test description
6121 + */
6122 +#define TA_AIDL_BDIS   (5000)  /* a_suspend minimum 200 ms, section: 6.6.5.3 */
6123 +
6124 +/* B-Idle to A-Disconnect */
6125 +#define TA_BIDL_ADIS   (12)    /* 3 to 200 ms */
6126 +
6127 +/* B-device timing constants */
6128 +
6129 +/* Data-Line Pulse Time*/
6130 +#define TB_DATA_PLS    (10)    /* b_srp_init,continue 5~10ms, section:5.3.3 */
6131 +#define TB_DATA_PLS_MIN        (5)     /* minimum 5 ms */
6132 +#define TB_DATA_PLS_MAX        (10)    /* maximum 10 ms */
6133 +
6134 +/* SRP Initiate Time  */
6135 +#define TB_SRP_INIT    (100)   /* b_srp_init,maximum 100 ms, section:5.3.8 */
6136 +
6137 +/* SRP Fail Time  */
6138 +#define TB_SRP_FAIL    (7000)  /* b_srp_init,Fail time 5~30s, section:6.8.2.2 */
6139 +
6140 +/* SRP result wait time */
6141 +#define TB_SRP_WAIT    (60)
6142 +
6143 +/* VBus time */
6144 +#define TB_VBUS_PLS    (30)    /* time to keep vbus pulsing asserted */
6145 +
6146 +/* Discharge time */
6147 +/* This time should be less than 10ms. It varies from system to system. */
6148 +#define TB_VBUS_DSCHRG (8)
6149 +
6150 +/* A-SE0 to B-Reset  */
6151 +#define TB_ASE0_BRST   (20)    /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */
6152 +
6153 +/* A bus suspend timer before we can switch to b_wait_aconn */
6154 +#define TB_A_SUSPEND   (7)
6155 +#define TB_BUS_RESUME  (12)
6156 +
6157 +/* SE0 Time Before SRP */
6158 +#define TB_SE0_SRP     (2)     /* b_idle,minimum 2 ms, section:5.3.2 */
6159 +
6160 +#define SET_OTG_STATE(otg_ptr, newstate)       ((otg_ptr)->state = newstate)
6161 +
6162 +
6163 +struct fsl_otg_timer {
6164 +       unsigned long expires;  /* Number of count increase to timeout */
6165 +       unsigned long count;    /* Tick counter */
6166 +       void (*function) (unsigned long);       /* Timeout function */
6167 +       unsigned long data;     /* Data passed to function */
6168 +       struct list_head list;
6169 +};
6170 +
6171 +struct fsl_otg_timer inline *otg_timer_initializer
6172 +    (void (*function) (unsigned long), unsigned long expires,
6173 +     unsigned long data) {
6174 +       struct fsl_otg_timer *timer;
6175 +       timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL);
6176 +       if (timer == NULL)
6177 +               return NULL;
6178 +       timer->function = function;
6179 +       timer->expires = expires;
6180 +       timer->data = data;
6181 +       return timer;
6182 +}
6183 +
6184 +struct fsl_otg {
6185 +       struct otg_transceiver otg;
6186 +       struct otg_fsm fsm;
6187 +       struct fsl_usb_device_regs *dr_mem_map;
6188 +       struct delayed_work otg_event;
6189 +
6190 +       /*used for usb host */
6191 +       u8 host_working;
6192 +       u8 on_off;
6193 +
6194 +       int irq;
6195 +};
6196 +
6197 +struct fsl_otg_config {
6198 +       u8 otg_port;
6199 +};
6200 +
6201 +/*For SRP and HNP handle*/
6202 +#define FSL_OTG_MAJOR  66
6203 +#define FSL_OTG_NAME   "fsl-otg"
6204 +/*Command to OTG driver(ioctl)*/
6205 +#define OTG_IOCTL_MAGIC                FSL_OTG_MAJOR
6206 +/*if otg work as host,it should return 1,otherwise it return 0*/
6207 +#define GET_OTG_STATUS         _IOR(OTG_IOCTL_MAGIC, 1, int)
6208 +#define SET_A_SUSPEND_REQ      _IOW(OTG_IOCTL_MAGIC, 2, int)
6209 +#define SET_A_BUS_DROP         _IOW(OTG_IOCTL_MAGIC, 3, int)
6210 +#define SET_A_BUS_REQ          _IOW(OTG_IOCTL_MAGIC, 4, int)
6211 +#define SET_B_BUS_REQ          _IOW(OTG_IOCTL_MAGIC, 5, int)
6212 +#define GET_A_SUSPEND_REQ      _IOR(OTG_IOCTL_MAGIC, 6, int)
6213 +#define GET_A_BUS_DROP         _IOR(OTG_IOCTL_MAGIC, 7, int)
6214 +#define GET_A_BUS_REQ          _IOR(OTG_IOCTL_MAGIC, 8, int)
6215 +#define GET_B_BUS_REQ          _IOR(OTG_IOCTL_MAGIC, 9, int)
6216 +
6217 +
6218 +/********************************************************************/
6219 +#endif
6220 --- /dev/null
6221 +++ b/drivers/usb/otg/otg_fsm.c
6222 @@ -0,0 +1,381 @@
6223 +/* OTG Finite State Machine from OTG spec
6224 + *
6225 + * Copyright (C) 2007 Freescale Semiconductor, Inc.
6226 + *
6227 + * Author:     Li Yang <LeoLi@freescale.com>
6228 + *             Jerry Huang <Chang-Ming.Huang@freescale.com>
6229 + *
6230 + * This program is free software; you can redistribute  it and/or modify it
6231 + * under  the terms of  the GNU General  Public License as published by the
6232 + * Free Software Foundation;  either version 2 of the  License, or (at your
6233 + * option) any later version.
6234 + *
6235 + * This program is distributed in the hope that it will be useful, but
6236 + * WITHOUT ANY WARRANTY; without even the implied warranty of
6237 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
6238 + * General Public License for more details.
6239 + *
6240 + * You should have received a copy of the  GNU General Public License along
6241 + * with this program; if not, write  to the Free Software Foundation, Inc.,
6242 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6243 + */
6244 +
6245 +#include <linux/kernel.h>
6246 +#include <linux/types.h>
6247 +#include <linux/usb/otg.h>
6248 +#include <linux/spinlock.h>
6249 +#include <linux/delay.h>
6250 +#include <linux/usb.h>
6251 +#include <linux/usb_gadget.h>
6252 +
6253 +#include "otg_fsm.h"
6254 +
6255 +
6256 +/* Defined by device specific driver, for different timer implementation */
6257 +extern void *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
6258 +       *b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_fail_tmr, *a_wait_enum_tmr;
6259 +
6260 +const char *state_string(enum usb_otg_state state)
6261 +{
6262 +       switch (state) {
6263 +       case OTG_STATE_A_IDLE:          return "a_idle";
6264 +       case OTG_STATE_A_WAIT_VRISE:    return "a_wait_vrise";
6265 +       case OTG_STATE_A_WAIT_BCON:     return "a_wait_bcon";
6266 +       case OTG_STATE_A_HOST:          return "a_host";
6267 +       case OTG_STATE_A_SUSPEND:       return "a_suspend";
6268 +       case OTG_STATE_A_PERIPHERAL:    return "a_peripheral";
6269 +       case OTG_STATE_A_WAIT_VFALL:    return "a_wait_vfall";
6270 +       case OTG_STATE_A_VBUS_ERR:      return "a_vbus_err";
6271 +       case OTG_STATE_B_IDLE:          return "b_idle";
6272 +       case OTG_STATE_B_SRP_INIT:      return "b_srp_init";
6273 +       case OTG_STATE_B_PERIPHERAL:    return "b_peripheral";
6274 +       case OTG_STATE_B_WAIT_ACON:     return "b_wait_acon";
6275 +       case OTG_STATE_B_HOST:          return "b_host";
6276 +       default:                        return "UNDEFINED";
6277 +       }
6278 +}
6279 +EXPORT_SYMBOL(state_string);
6280 +
6281 +/* Change USB protocol when there is a protocol change */
6282 +static int otg_set_protocol(struct otg_fsm *fsm, int protocol)
6283 +{
6284 +       int ret = 0;
6285 +
6286 +       VDBG("DDD old fsm->protocol= %d; new protocol= %d\n",
6287 +                    fsm->protocol, protocol);
6288 +       if (fsm->protocol != protocol) {
6289 +               VDBG("Changing role fsm->protocol= %d; new protocol= %d\n",
6290 +                               fsm->protocol, protocol);
6291 +               /* stop old protocol */
6292 +               if (fsm->protocol == PROTO_HOST)
6293 +                       ret = fsm->ops->start_host(fsm, 0);
6294 +               else if (fsm->protocol == PROTO_GADGET)
6295 +                       ret = fsm->ops->start_gadget(fsm, 0);
6296 +               if (ret)
6297 +                       return ret;
6298 +
6299 +               /* start new protocol */
6300 +               if (protocol == PROTO_HOST)
6301 +                       ret = fsm->ops->start_host(fsm, 1);
6302 +               else if (protocol == PROTO_GADGET)
6303 +                       ret = fsm->ops->start_gadget(fsm, 1);
6304 +               if (ret)
6305 +                       return ret;
6306 +
6307 +               fsm->protocol = protocol;
6308 +               return 0;
6309 +       }
6310 +
6311 +       return 0;
6312 +}
6313 +
6314 +static int state_changed;
6315 +
6316 +/* Called when leaving a state.  Do state clean up jobs here */
6317 +static void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state)
6318 +{
6319 +       switch (old_state) {
6320 +       case OTG_STATE_B_IDLE:
6321 +               otg_del_timer(fsm, fsm->b_se0_srp_tmr);
6322 +               fsm->b_se0_srp = 0;
6323 +               break;
6324 +       case OTG_STATE_B_SRP_INIT:
6325 +               fsm->b_srp_done = 0;
6326 +               break;
6327 +       case OTG_STATE_B_PERIPHERAL:
6328 +               break;
6329 +       case OTG_STATE_B_WAIT_ACON:
6330 +               otg_del_timer(fsm, fsm->b_ase0_brst_tmr);
6331 +               fsm->b_ase0_brst_tmout = 0;
6332 +               break;
6333 +       case OTG_STATE_B_HOST:
6334 +               break;
6335 +       case OTG_STATE_A_IDLE:
6336 +               break;
6337 +       case OTG_STATE_A_WAIT_VRISE:
6338 +               otg_del_timer(fsm, fsm->a_wait_vrise_tmr);
6339 +               fsm->a_wait_vrise_tmout = 0;
6340 +               break;
6341 +       case OTG_STATE_A_WAIT_BCON:
6342 +               otg_del_timer(fsm, fsm->a_wait_bcon_tmr);
6343 +               fsm->a_wait_bcon_tmout = 0;
6344 +               break;
6345 +       case OTG_STATE_A_HOST:
6346 +               otg_del_timer(fsm, fsm->a_wait_enum_tmr);
6347 +               break;
6348 +       case OTG_STATE_A_SUSPEND:
6349 +               otg_del_timer(fsm, fsm->a_aidl_bdis_tmr);
6350 +               fsm->a_aidl_bdis_tmout = 0;
6351 +               fsm->a_suspend_req = 0;
6352 +               fsm->a_bus_req = 1;     /* FIXME */
6353 +               break;
6354 +       case OTG_STATE_A_PERIPHERAL:
6355 +               break;
6356 +       case OTG_STATE_A_WAIT_VFALL:
6357 +               otg_del_timer(fsm, fsm->a_wait_vrise_tmr);
6358 +               break;
6359 +       case OTG_STATE_A_VBUS_ERR:
6360 +               break;
6361 +       default:
6362 +               break;
6363 +       }
6364 +}
6365 +
6366 +/* Called when entering a state */
6367 +static int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state)
6368 +{
6369 +       state_changed = 1;
6370 +       VDBG("State: old=%s new=%s \n",
6371 +               state_string(fsm->transceiver->state), state_string(new_state));
6372 +
6373 +       if (fsm->transceiver->state == new_state)
6374 +               return 0;
6375 +
6376 +       otg_leave_state(fsm, fsm->transceiver->state);
6377 +       switch (new_state) {
6378 +       case OTG_STATE_B_IDLE:
6379 +               otg_drv_vbus(fsm, 0);
6380 +               otg_chrg_vbus(fsm, 0);
6381 +               otg_loc_conn(fsm, 0);
6382 +               otg_loc_sof(fsm, 0);
6383 +               otg_set_protocol(fsm, PROTO_UNDEF);
6384 +               otg_add_timer(fsm, fsm->b_se0_srp_tmr);
6385 +               break;
6386 +       case OTG_STATE_B_SRP_INIT:
6387 +               otg_start_pulse(fsm);
6388 +               otg_loc_sof(fsm, 0);
6389 +               otg_set_protocol(fsm, PROTO_UNDEF);
6390 +               otg_add_timer(fsm, fsm->b_srp_fail_tmr);
6391 +               break;
6392 +       case OTG_STATE_B_PERIPHERAL:
6393 +               otg_chrg_vbus(fsm, 0);
6394 +               otg_loc_conn(fsm, 1);
6395 +               otg_loc_sof(fsm, 0);
6396 +               otg_set_protocol(fsm, PROTO_GADGET);
6397 +               break;
6398 +       case OTG_STATE_B_WAIT_ACON:
6399 +               otg_chrg_vbus(fsm, 0);
6400 +               otg_loc_conn(fsm, 0);
6401 +               otg_loc_sof(fsm, 0);
6402 +               otg_set_protocol(fsm, PROTO_HOST);
6403 +               otg_add_timer(fsm, fsm->b_ase0_brst_tmr);
6404 +               fsm->a_bus_suspend = 0;
6405 +               break;
6406 +       case OTG_STATE_B_HOST:
6407 +               otg_chrg_vbus(fsm, 0);
6408 +               otg_loc_conn(fsm, 0);
6409 +               otg_loc_sof(fsm, 1);
6410 +               otg_set_protocol(fsm, PROTO_HOST);
6411 +               usb_bus_start_enum(fsm->transceiver->host,
6412 +                                  fsm->transceiver->host->otg_port);
6413 +               break;
6414 +       case OTG_STATE_A_IDLE:
6415 +               otg_drv_vbus(fsm, 0);
6416 +               otg_chrg_vbus(fsm, 0);
6417 +               otg_loc_conn(fsm, 0);
6418 +               otg_loc_sof(fsm, 0);
6419 +               otg_set_protocol(fsm, PROTO_HOST);
6420 +               break;
6421 +       case OTG_STATE_A_WAIT_VRISE:
6422 +               otg_drv_vbus(fsm, 1);
6423 +               otg_loc_conn(fsm, 0);
6424 +               otg_loc_sof(fsm, 0);
6425 +               otg_set_protocol(fsm, PROTO_HOST);
6426 +               otg_add_timer(fsm, fsm->a_wait_vrise_tmr);
6427 +               break;
6428 +       case OTG_STATE_A_WAIT_BCON:
6429 +               otg_drv_vbus(fsm, 1);
6430 +               otg_loc_conn(fsm, 0);
6431 +               otg_loc_sof(fsm, 0);
6432 +               otg_set_protocol(fsm, PROTO_HOST);
6433 +               otg_add_timer(fsm, fsm->a_wait_bcon_tmr);
6434 +               break;
6435 +       case OTG_STATE_A_HOST:
6436 +               otg_drv_vbus(fsm, 1);
6437 +               otg_loc_conn(fsm, 0);
6438 +               otg_loc_sof(fsm, 1);
6439 +               otg_set_protocol(fsm, PROTO_HOST);
6440 +               /*
6441 +                * When HNP is triggered while a_bus_req = 0, a_host will
6442 +                * suspend too fast to complete a_set_b_hnp_en
6443 +                */
6444 +               if (!fsm->a_bus_req || fsm->a_suspend_req)
6445 +                       otg_add_timer(fsm, fsm->a_wait_enum_tmr);
6446 +               break;
6447 +       case OTG_STATE_A_SUSPEND:
6448 +               otg_drv_vbus(fsm, 1);
6449 +               otg_loc_conn(fsm, 0);
6450 +               otg_loc_sof(fsm, 0);
6451 +               otg_set_protocol(fsm, PROTO_HOST);
6452 +               otg_add_timer(fsm, fsm->a_aidl_bdis_tmr);
6453 +
6454 +               break;
6455 +       case OTG_STATE_A_PERIPHERAL:
6456 +               otg_loc_conn(fsm, 1);
6457 +               otg_loc_sof(fsm, 0);
6458 +               otg_set_protocol(fsm, PROTO_GADGET);
6459 +               otg_drv_vbus(fsm, 1);
6460 +               break;
6461 +       case OTG_STATE_A_WAIT_VFALL:
6462 +               otg_drv_vbus(fsm, 0);
6463 +               otg_loc_conn(fsm, 0);
6464 +               otg_loc_sof(fsm, 0);
6465 +               otg_set_protocol(fsm, PROTO_HOST);
6466 +               break;
6467 +       case OTG_STATE_A_VBUS_ERR:
6468 +               otg_drv_vbus(fsm, 0);
6469 +               otg_loc_conn(fsm, 0);
6470 +               otg_loc_sof(fsm, 0);
6471 +               otg_set_protocol(fsm, PROTO_UNDEF);
6472 +               break;
6473 +       default:
6474 +               break;
6475 +       }
6476 +
6477 +       fsm->transceiver->state = new_state;
6478 +       return 0;
6479 +}
6480 +
6481 +/* State change judgement */
6482 +int otg_statemachine(struct otg_fsm *fsm)
6483 +{
6484 +       enum usb_otg_state state;
6485 +       unsigned long flags;
6486 +
6487 +       spin_lock_irqsave(&fsm->lock, flags);
6488 +
6489 +       state = fsm->transceiver->state;
6490 +       state_changed = 0;
6491 +       /* State machine state change judgement */
6492 +
6493 +       VDBG(" State: %s \n", state_string(state));
6494 +
6495 +       switch (state) {
6496 +       case OTG_STATE_UNDEFINED:
6497 +               if (fsm->id)
6498 +                       otg_set_state(fsm, OTG_STATE_B_IDLE);
6499 +               else
6500 +                       otg_set_state(fsm, OTG_STATE_A_IDLE);
6501 +               break;
6502 +       case OTG_STATE_B_IDLE:
6503 +               if (!fsm->id)
6504 +                       otg_set_state(fsm, OTG_STATE_A_IDLE);
6505 +               else if (fsm->b_sess_vld && fsm->transceiver->gadget)
6506 +                       otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
6507 +               else if (fsm->b_bus_req && fsm->b_sess_end && fsm->b_se0_srp)
6508 +                       otg_set_state(fsm, OTG_STATE_B_SRP_INIT);
6509 +               break;
6510 +       case OTG_STATE_B_SRP_INIT:
6511 +               if (!fsm->id || fsm->b_srp_done)
6512 +                       otg_set_state(fsm, OTG_STATE_B_IDLE);
6513 +               break;
6514 +       case OTG_STATE_B_PERIPHERAL:
6515 +               if (!fsm->id || !fsm->b_sess_vld)
6516 +                       otg_set_state(fsm, OTG_STATE_B_IDLE);
6517 +               else if (fsm->b_bus_req &&
6518 +                        fsm->transceiver->
6519 +                        gadget->b_hnp_enable && fsm->a_bus_suspend)
6520 +                       otg_set_state(fsm, OTG_STATE_B_WAIT_ACON);
6521 +               break;
6522 +       case OTG_STATE_B_WAIT_ACON:
6523 +               if (fsm->a_conn)
6524 +                       otg_set_state(fsm, OTG_STATE_B_HOST);
6525 +               else if (!fsm->id || !fsm->b_sess_vld)
6526 +                       otg_set_state(fsm, OTG_STATE_B_IDLE);
6527 +               else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) {
6528 +                       fsm->b_ase0_brst_tmout = 0;
6529 +                       otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
6530 +               }
6531 +               break;
6532 +       case OTG_STATE_B_HOST:
6533 +               if (!fsm->id || !fsm->b_sess_vld)
6534 +                       otg_set_state(fsm, OTG_STATE_B_IDLE);
6535 +               else if (!fsm->b_bus_req || !fsm->a_conn)
6536 +                       otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
6537 +               break;
6538 +       case OTG_STATE_A_IDLE:
6539 +               if (fsm->id)
6540 +                       otg_set_state(fsm, OTG_STATE_B_IDLE);
6541 +               else if (!fsm->a_bus_drop && (fsm->a_bus_req || fsm->a_srp_det))
6542 +                       otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE);
6543 +               break;
6544 +       case OTG_STATE_A_WAIT_VRISE:
6545 +               if (fsm->id || fsm->a_bus_drop || fsm->a_vbus_vld ||
6546 +                   fsm->a_wait_vrise_tmout) {
6547 +                       otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
6548 +               }
6549 +               break;
6550 +       case OTG_STATE_A_WAIT_BCON:
6551 +               if (!fsm->a_vbus_vld)
6552 +                       otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
6553 +               else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout)
6554 +                       otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
6555 +               else if (fsm->b_conn)
6556 +                       otg_set_state(fsm, OTG_STATE_A_HOST);
6557 +               break;
6558 +       case OTG_STATE_A_HOST:
6559 +               if ((!fsm->a_bus_req || fsm->a_suspend_req) &&
6560 +                   fsm->transceiver->host->b_hnp_enable)
6561 +                       otg_set_state(fsm, OTG_STATE_A_SUSPEND);
6562 +               else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop)
6563 +                       otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
6564 +               else if (!fsm->a_vbus_vld)
6565 +                       otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
6566 +               break;
6567 +       case OTG_STATE_A_SUSPEND:
6568 +               if (!fsm->b_conn && fsm->transceiver->host->b_hnp_enable)
6569 +                       otg_set_state(fsm, OTG_STATE_A_PERIPHERAL);
6570 +               else if (!fsm->b_conn && !fsm->transceiver->host->b_hnp_enable)
6571 +                       otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
6572 +               else if (fsm->a_bus_req || fsm->b_bus_resume)
6573 +                       otg_set_state(fsm, OTG_STATE_A_HOST);
6574 +               else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout)
6575 +                       otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
6576 +               else if (!fsm->a_vbus_vld)
6577 +                       otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
6578 +               break;
6579 +       case OTG_STATE_A_PERIPHERAL:
6580 +               if (fsm->id || fsm->a_bus_drop)
6581 +                       otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
6582 +               else if (fsm->b_bus_suspend)
6583 +                       otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
6584 +               else if (!fsm->a_vbus_vld)
6585 +                       otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
6586 +               break;
6587 +       case OTG_STATE_A_WAIT_VFALL:
6588 +               if (fsm->id || fsm->a_bus_req || (!fsm->a_sess_vld &&
6589 +                                                 !fsm->b_conn))
6590 +                       otg_set_state(fsm, OTG_STATE_A_IDLE);
6591 +               break;
6592 +       case OTG_STATE_A_VBUS_ERR:
6593 +               if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err)
6594 +                       otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
6595 +               break;
6596 +       default:
6597 +               break;
6598 +       }
6599 +       spin_unlock_irqrestore(&fsm->lock, flags);
6600 +
6601 +       return state_changed;
6602 +}
6603 +EXPORT_SYMBOL(otg_statemachine);
6604 --- /dev/null
6605 +++ b/drivers/usb/otg/otg_fsm.h
6606 @@ -0,0 +1,170 @@
6607 +/* Copyright (C) 2006-2007 Freescale Semiconductor, Inc.
6608 + *
6609 + * This program is free software; you can redistribute  it and/or modify it
6610 + * under  the terms of  the GNU General  Public License as published by the
6611 + * Free Software Foundation;  either version 2 of the  License, or (at your
6612 + * option) any later version.
6613 + *
6614 + * This program is distributed in the hope that it will be useful, but
6615 + * WITHOUT ANY WARRANTY; without even the implied warranty of
6616 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
6617 + * General Public License for more details.
6618 + *
6619 + * You should have received a copy of the  GNU General Public License along
6620 + * with this program; if not, write  to the Free Software Foundation, Inc.,
6621 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6622 + */
6623 +
6624 +#ifndef OTG_FSM_H
6625 +#define OTG_FSM_H
6626 +
6627 +#if 1
6628 +#define DEBUG  1
6629 +#define VERBOSE        1
6630 +#endif
6631 +
6632 +#ifdef DEBUG
6633 +#define DBG(fmt, args...)      printk(KERN_DEBUG "[%s]  " fmt , \
6634 +                               __FUNCTION__, ## args)
6635 +#else
6636 +#define DBG(fmt, args...)      do {} while (0)
6637 +#endif
6638 +
6639 +#ifdef VERBOSE
6640 +#define VDBG           DBG
6641 +#else
6642 +#define VDBG(stuff...) do {} while (0)
6643 +#endif
6644 +
6645 +#ifdef VERBOSE
6646 +#define MPC_LOC printk("Current Location [%s]:[%d]\n", __FILE__, __LINE__)
6647 +#else
6648 +#define MPC_LOC do {} while (0)
6649 +#endif
6650 +
6651 +#define PROTO_UNDEF    0
6652 +#define PROTO_HOST     1
6653 +#define PROTO_GADGET   2
6654 +
6655 +
6656 +
6657 +
6658 +
6659 +/* OTG state machine according to the OTG spec */
6660 +struct otg_fsm {
6661 +       /* Input */
6662 +       int a_bus_resume;
6663 +       int a_bus_suspend;
6664 +       int a_conn;
6665 +       int a_sess_vld;
6666 +       int a_srp_det;
6667 +       int a_vbus_vld;
6668 +       int b_bus_resume;
6669 +       int b_bus_suspend;
6670 +       int b_conn;
6671 +       int b_se0_srp;
6672 +       int b_sess_end;
6673 +       int b_sess_vld;
6674 +       int id;
6675 +
6676 +       /* Internal variables */
6677 +       int a_set_b_hnp_en;
6678 +       int b_srp_done;
6679 +       int b_hnp_enable;
6680 +
6681 +       /* Timeout indicator for timers */
6682 +       int a_wait_vrise_tmout;
6683 +       int a_wait_bcon_tmout;
6684 +       int a_aidl_bdis_tmout;
6685 +       int b_ase0_brst_tmout;
6686 +
6687 +       /* Informative variables */
6688 +       int a_bus_drop;
6689 +       int a_bus_req;
6690 +       int a_clr_err;
6691 +       int a_suspend_req;
6692 +       int b_bus_req;
6693 +
6694 +       /* Output */
6695 +       int drv_vbus;
6696 +       int loc_conn;
6697 +       int loc_sof;
6698 +
6699 +       struct otg_fsm_ops *ops;
6700 +       struct otg_transceiver *transceiver;
6701 +
6702 +       void *a_wait_vrise_tmr;
6703 +       void *a_wait_bcon_tmr;
6704 +       void *a_aidl_bdis_tmr;
6705 +       void *b_ase0_brst_tmr;
6706 +       void *b_se0_srp_tmr;
6707 +       void *b_srp_fail_tmr;
6708 +       void *a_wait_enum_tmr;
6709 +
6710 +       /* Current usb protocol used: 0:undefine; 1:host; 2:client */
6711 +       int protocol;
6712 +       spinlock_t lock;                /* fsm lock */
6713 +};
6714 +
6715 +struct otg_fsm_ops {
6716 +       void    (*chrg_vbus)(int on);
6717 +       void    (*drv_vbus)(int on);
6718 +       void    (*loc_conn)(int on);
6719 +       void    (*loc_sof)(int on);
6720 +       void    (*start_pulse)(void);
6721 +       void    (*add_timer)(void *timer);
6722 +       void    (*del_timer)(void *timer);
6723 +       int     (*start_host)(struct otg_fsm *fsm, int on);
6724 +       int     (*start_gadget)(struct otg_fsm *fsm, int on);
6725 +};
6726 +
6727 +
6728 +static inline void otg_chrg_vbus(struct otg_fsm *fsm, int on)
6729 +{
6730 +       fsm->ops->chrg_vbus(on);
6731 +}
6732 +
6733 +static inline void otg_drv_vbus(struct otg_fsm *fsm, int on)
6734 +{
6735 +       if (fsm->drv_vbus != on) {
6736 +               fsm->drv_vbus = on;
6737 +               fsm->ops->drv_vbus(on);
6738 +       }
6739 +}
6740 +
6741 +static inline void otg_loc_conn(struct otg_fsm *fsm, int on)
6742 +{
6743 +       if (fsm->loc_conn != on) {
6744 +               fsm->loc_conn = on;
6745 +               fsm->ops->loc_conn(on);
6746 +       }
6747 +}
6748 +
6749 +static inline void otg_loc_sof(struct otg_fsm *fsm, int on)
6750 +{
6751 +       if (fsm->loc_sof != on) {
6752 +               fsm->loc_sof = on;
6753 +               fsm->ops->loc_sof(on);
6754 +       }
6755 +}
6756 +
6757 +static inline void otg_start_pulse(struct otg_fsm *fsm)
6758 +{
6759 +       fsm->ops->start_pulse();
6760 +}
6761 +
6762 +static inline void otg_add_timer(struct otg_fsm *fsm, void *timer)
6763 +{
6764 +       fsm->ops->add_timer(timer);
6765 +}
6766 +
6767 +static inline void otg_del_timer(struct otg_fsm *fsm, void *timer)
6768 +{
6769 +       fsm->ops->del_timer(timer);
6770 +}
6771 +
6772 +extern int otg_statemachine(struct otg_fsm *fsm);
6773 +
6774 +extern const char *state_string(enum usb_otg_state state);
6775 +
6776 +#endif
6777 --- a/include/asm-m68k/mcf5445x_usb.h
6778 +++ b/include/asm-m68k/mcf5445x_usb.h
6779 @@ -41,7 +41,8 @@ static inline void fsl_platform_set_host
6780
6781         /* set host mode and select "big endian" */
6782         temp = fsl_readl(&regs->usbmode);
6783 -       fsl_writel(temp | USBMODE_CM_HOST | USBMODE_ES, &regs->usbmode);
6784 +       temp |= USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
6785 +       fsl_writel(temp, &regs->usbmode);
6786
6787         pr_debug("%s: set usbmode to 0x%x\n\n", __FUNCTION__,
6788                 fsl_readl(&regs->usbmode));
6789 --- a/include/linux/fsl_devices.h
6790 +++ b/include/linux/fsl_devices.h
6791 @@ -91,6 +91,19 @@ enum fsl_usb2_operating_modes {
6792         FSL_USB2_DR_OTG,
6793  };
6794
6795 +/* DDD
6796 + * replace _operating_modes with _controller
6797 + *
6798 + * the operating_mode tests in fsl_platform_verify() aren't needed,
6799 + * since the ehci driver isn't going to be probe()d unless it's
6800 + * "fsl-ehci" device anyway, and what we really need to know is
6801 + * which controller (MPH/DR) we're dealing with
6802 + */
6803 +enum fsl_usb2_controller {
6804 +       FSL_USB2_MPH,
6805 +       FSL_USB2_DR,
6806 +};
6807 +
6808  enum fsl_usb2_phy_modes {
6809         FSL_USB2_PHY_NONE,
6810         FSL_USB2_PHY_ULPI,
6811 @@ -101,9 +114,36 @@ enum fsl_usb2_phy_modes {
6812
6813  struct fsl_usb2_platform_data {
6814         /* board specific information */
6815 -       enum fsl_usb2_operating_modes   operating_mode;
6816 +       /*
6817 +        * DDD see note above
6818 +        * enum fsl_usb2_operating_modes        operating_mode;
6819 +        */
6820 +       enum fsl_usb2_controller        controller;
6821         enum fsl_usb2_phy_modes         phy_mode;
6822         unsigned int                    port_enables;
6823 +       /*
6824 +        * DDD this could arguably be moved to a separate
6825 +        * fsl usb2 device header file
6826 +        */
6827 +       char *name;                     /* pretty print */
6828 +       int (*platform_init) (struct platform_device *);
6829 +       void (*platform_uninit) (struct platform_device *);
6830 +       int (*platform_verify) (struct platform_device *);
6831 +       u32                             xcvr_type;      /* PORTSCX_PTS_* */
6832 +       u32                             view;           /* ULPI viewport register */
6833 +       u32                             r_start;        /* start of MEM resource */
6834 +       u32                             r_len;          /* length of MEM resource */
6835 +       void __iomem                    *regs;          /* ioremap'd register base */
6836 +       unsigned                        big_endian_mmio : 1;
6837 +       unsigned                        big_endian_desc : 1;
6838 +       unsigned                        es : 1;         /* need USBMODE:ES */
6839 +       unsigned                        have_sysif_regs : 1;
6840 +       unsigned                        le_setup_buf : 1;
6841 +       unsigned                        does_otg : 1;   /* set IFF it's an OTG port */
6842 +
6843 +       unsigned                        power_budget;   /* for hcd->power_budget */
6844 +       struct fsl_xcvr_ops             *xcvr_ops;
6845 +       int                             max_ep_nr;      /* max # of endpoints */
6846  };
6847
6848  /* Flags in fsl_usb2_mph_platform_data */
6849 --- /dev/null
6850 +++ b/include/linux/usb/fsl_usb2.h
6851 @@ -0,0 +1,464 @@
6852 +/*
6853 + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6854 + */
6855 +
6856 +/*
6857 + * The code contained herein is licensed under the GNU General Public
6858 + * License. You may obtain a copy of the GNU General Public License
6859 + * Version 2 or later at the following locations:
6860 + *
6861 + * http://www.opensource.org/licenses/gpl-license.html
6862 + * http://www.gnu.org/copyleft/gpl.html
6863 + */
6864 +
6865 +/*
6866 + * Freescale USB device/endpoint management registers
6867 + */
6868 +#ifndef __FSL_USB2_H
6869 +#define __FSL_USB2_H
6870 +
6871 +
6872 + /* USB DR device mode registers (Little Endian) */
6873 +struct fsl_usb_device_regs {
6874 +       /* Capability register */
6875 +       u32 id;
6876 +       u32 res1[63];
6877 +       u16 caplength;          /* Capability Register Length */
6878 +       u16 hciversion;         /* Host Controller Interface Version */
6879 +       u32 hcsparams;          /* Host Controller Structual Parameters */
6880 +       u32 hccparams;          /* Host Controller Capability Parameters */
6881 +       u32 res2[5];
6882 +       u32 dciversion;         /* Device Controller Interface Version */
6883 +       u32 dccparams;          /* Device Controller Capability Parameters */
6884 +       u32 res3[6];
6885 +       /* Operation register */
6886 +       u32 usbcmd;             /* USB Command Register */
6887 +       u32 usbsts;             /* USB Status Register */
6888 +       u32 usbintr;            /* USB Interrupt Enable Register */
6889 +       u32 frindex;            /* Frame Index Register */
6890 +       u32 res4;
6891 +       u32 deviceaddr;         /* Device Address */
6892 +       u32 endpointlistaddr;   /* Endpoint List Address Register */
6893 +       u32 res5;
6894 +       u32 burstsize;          /* Master Interface Data Burst Size Register */
6895 +       u32 txttfilltuning;     /* Transmit FIFO Tuning Controls Register */
6896 +       u32 res6[2];
6897 +       u32 ulpiview;
6898 +       u32 res7[3];
6899 +       u32 configflag;         /* Configure Flag Register */
6900 +       u32 portsc1;            /* Port 1 Status and Control Register */
6901 +       u32 res8[7];
6902 +       u32 otgsc;              /* On-The-Go Status and Control */
6903 +       u32 usbmode;            /* USB Mode Register */
6904 +       u32 endptsetupstat;     /* Endpoint Setup Status Register */
6905 +       u32 endpointprime;      /* Endpoint Initialization Register */
6906 +       u32 endptflush;         /* Endpoint Flush Register */
6907 +       u32 endptstatus;        /* Endpoint Status Register */
6908 +       u32 endptcomplete;      /* Endpoint Complete Register */
6909 +#if 0
6910 +       u32 endptctrl[USB_MAX_ENDPOINTS]; /* Endpoint Control Registers */
6911 +#else
6912 +       // DDD see DCCPARAMS:DEN for the real number of device endpoints
6913 +       // DDD 16 is the max
6914 +       u32 endptctrl[16];      /* Endpoint Control Registers */
6915 +#endif
6916 +};
6917 +
6918 + /* USB DR host mode registers (Little Endian) */
6919 +struct fsl_usb_host_regs {
6920 +       /* Capability register */
6921 +       u32 id;
6922 +       u32 res1[63];
6923 +       u16 caplength;          /* Capability Register Length */
6924 +       u16 hciversion;         /* Host Controller Interface Version */
6925 +       u32 hcsparams;          /* Host Controller Structual Parameters */
6926 +       u32 hccparams;          /* Host Controller Capability Parameters */
6927 +       u32 res2[5];
6928 +       u32 dciversion;         /* Device Controller Interface Version */
6929 +       u32 dccparams;          /* Device Controller Capability Parameters */
6930 +       u32 res3[6];
6931 +       /* Operation register */
6932 +       u32 usbcmd;             /* USB Command Register */
6933 +       u32 usbsts;             /* USB Status Register */
6934 +       u32 usbintr;            /* USB Interrupt Enable Register */
6935 +       u32 frindex;            /* Frame Index Register */
6936 +       u32 res4;
6937 +       u32 periodiclistbase;   /* Periodic Frame List Base Address Register */
6938 +       u32 asynclistaddr;      /* Current Asynchronous List Address Register */
6939 +       u32 res5;
6940 +       u32 burstsize;          /* Master Interface Data Burst Size Register */
6941 +       u32 txttfilltuning;     /* Transmit FIFO Tuning Controls Register */
6942 +       u32 res6[2];
6943 +       u32 ulpiview;
6944 +       u32 res7[3];
6945 +       u32 configflag;         /* Configure Flag Register */
6946 +       u32 portsc1;            /* Port 1 Status and Control Register */
6947 +       u32 res8[7];
6948 +       u32 otgsc;              /* On-The-Go Status and Control */
6949 +       u32 usbmode;            /* USB Mode Register */
6950 +       u32 endptsetupstat;     /* Endpoint Setup Status Register */
6951 +       u32 endpointprime;      /* Endpoint Initialization Register */
6952 +       u32 endptflush;         /* Endpoint Flush Register */
6953 +       u32 endptstatus;        /* Endpoint Status Register */
6954 +       u32 endptcomplete;      /* Endpoint Complete Register */
6955 +#if 0
6956 +       u32 endptctrl[USB_MAX_ENDPOINTS]; /* Endpoint Control Registers */
6957 +#else
6958 +       // DDD: do these exits in the host register set??
6959 +       // DDD see DCCPARAMS:DEN for the real number of device endpoints
6960 +       // DDD 16 is the max
6961 +       u32 endptctrl[16];      /* Endpoint Control Registers */
6962 +#endif
6963 +};
6964 +
6965 + /* non-EHCI USB system interface registers (Big Endian) */
6966 +struct usb_sys_interface {
6967 +       u32 snoop1;
6968 +       u32 snoop2;
6969 +       u32 age_cnt_thresh;     /* Age Count Threshold Register */
6970 +       u32 pri_ctrl;           /* Priority Control Register */
6971 +       u32 si_ctrl;            /* System Interface Control Register */
6972 +       u32 res[59];
6973 +       u32 control;            /* General Purpose Control Register */
6974 +};
6975 +
6976 +/* ep0 transfer state */
6977 +#define WAIT_FOR_SETUP         0
6978 +#define DATA_STATE_XMIT                1
6979 +#define DATA_STATE_NEED_ZLP    2
6980 +#define WAIT_FOR_OUT_STATUS    3
6981 +#define DATA_STATE_RECV                4
6982 +
6983 +/* Frame Index Register Bit Masks */
6984 +#define        USB_FRINDEX_MASKS                       0x3fff
6985 +
6986 +
6987 +
6988 +/* USBCMD Register Bit Masks */
6989 +#define USB_CMD_RUN_STOP                       0x00000001
6990 +#define USB_CMD_CTRL_RESET                     0x00000002
6991 +#define USB_CMD_PERIODIC_SCHEDULE_EN           0x00000010
6992 +#define USB_CMD_ASYNC_SCHEDULE_EN              0x00000020
6993 +#define USB_CMD_INT_AA_DOORBELL                        0x00000040
6994 +#define USB_CMD_ASP                            0x00000300
6995 +#define USB_CMD_ASYNC_SCH_PARK_EN              0x00000800
6996 +#define USB_CMD_SUTW                           0x00002000
6997 +#define USB_CMD_ATDTW                          0x00004000
6998 +#define USB_CMD_ITC                            0x00FF0000
6999 +
7000 +/* bit 15,3,2 are frame list size */
7001 +#define USB_CMD_FRAME_SIZE_1024                        0x00000000
7002 +#define USB_CMD_FRAME_SIZE_512                 0x00000004
7003 +#define USB_CMD_FRAME_SIZE_256                 0x00000008
7004 +#define USB_CMD_FRAME_SIZE_128                 0x0000000C
7005 +#define USB_CMD_FRAME_SIZE_64                  0x00008000
7006 +#define USB_CMD_FRAME_SIZE_32                  0x00008004
7007 +#define USB_CMD_FRAME_SIZE_16                  0x00008008
7008 +#define USB_CMD_FRAME_SIZE_8                   0x0000800C
7009 +
7010 +/* bit 9-8 are async schedule park mode count */
7011 +#define USB_CMD_ASP_00                         0x00000000
7012 +#define USB_CMD_ASP_01                         0x00000100
7013 +#define USB_CMD_ASP_10                         0x00000200
7014 +#define USB_CMD_ASP_11                         0x00000300
7015 +#define USB_CMD_ASP_BIT_POS                    8
7016 +
7017 +/* bit 23-16 are interrupt threshold control */
7018 +#define USB_CMD_ITC_NO_THRESHOLD               0x00000000
7019 +#define USB_CMD_ITC_1_MICRO_FRM                        0x00010000
7020 +#define USB_CMD_ITC_2_MICRO_FRM                        0x00020000
7021 +#define USB_CMD_ITC_4_MICRO_FRM                        0x00040000
7022 +#define USB_CMD_ITC_8_MICRO_FRM                        0x00080000
7023 +#define USB_CMD_ITC_16_MICRO_FRM               0x00100000
7024 +#define USB_CMD_ITC_32_MICRO_FRM               0x00200000
7025 +#define USB_CMD_ITC_64_MICRO_FRM               0x00400000
7026 +#define USB_CMD_ITC_BIT_POS                    16
7027 +
7028 +
7029 +
7030 +
7031 +/* USB STS Register Bit Masks */
7032 +#define USB_STS_INT                            0x00000001
7033 +#define USB_STS_ERR                            0x00000002
7034 +#define USB_STS_PORT_CHANGE                    0x00000004
7035 +#define USB_STS_FRM_LST_ROLL                   0x00000008
7036 +#define USB_STS_SYS_ERR                                0x00000010
7037 +#define USB_STS_IAA                            0x00000020
7038 +#define USB_STS_RESET                          0x00000040
7039 +#define USB_STS_SOF                            0x00000080
7040 +#define USB_STS_SUSPEND                                0x00000100
7041 +#define USB_STS_HC_HALTED                      0x00001000
7042 +#define USB_STS_RCL                            0x00002000
7043 +#define USB_STS_PERIODIC_SCHEDULE              0x00004000
7044 +#define USB_STS_ASYNC_SCHEDULE                 0x00008000
7045 +
7046 +/* USB INTR Register Bit Masks */
7047 +#define USB_INTR_INT_EN                                0x00000001
7048 +#define USB_INTR_ERR_INT_EN                    0x00000002
7049 +#define USB_INTR_PTC_DETECT_EN                 0x00000004
7050 +#define USB_INTR_FRM_LST_ROLL_EN               0x00000008
7051 +#define USB_INTR_SYS_ERR_EN                    0x00000010
7052 +#define USB_INTR_ASYN_ADV_EN                   0x00000020
7053 +#define USB_INTR_RESET_EN                      0x00000040
7054 +#define USB_INTR_SOF_EN                                0x00000080
7055 +#define USB_INTR_DEVICE_SUSPEND                        0x00000100
7056 +
7057 +/* Device Address bit masks */
7058 +#define USB_DEVICE_ADDRESS_MASK                        0xFE000000
7059 +#define USB_DEVICE_ADDRESS_BIT_POS             25
7060 +
7061 +/* endpoint list address bit masks */
7062 +#define USB_EP_LIST_ADDRESS_MASK               0xfffff800
7063 +
7064 +
7065 +/* x_PORTSCx */
7066 +/* bit 31-30 are port transceiver select */
7067 +#define PORTSCX_PTS_MASK               (3 << 30)       /* parallel xcvr select mask */
7068 +#define PORTSCX_PHY_TYPE_SEL           PORTSCX_PTS_MASK
7069 +#define PORTSCX_PTS_UTMI               (0 << 30)       /* UTMI/UTMI+ */
7070 +#define PORTSCX_PTS_PHILIPS            (1 << 30)       /* Philips classic */
7071 +#define PORTSCX_PTS_ULPI               (2 << 30)       /* ULPI */
7072 +#define PORTSCX_PTS_SERIAL             (3 << 30)       /* serial */
7073 +#define PORTSCX_PTS_FSLS               PORTSCX_PTS_SERIAL
7074 +#define PORTSCX_PTS_ONCHIP             PORTSCX_PTS_FSLS
7075 +
7076 +#define PORTSCX_STS                    (1 << 29)       /* serial xcvr select */
7077 +
7078 +/* bit 28 is parallel transceiver width for UTMI interface */
7079 +#define PORTSCX_PTW_8BIT               (0 << 28)       /* 8 bit parallel xcvr */
7080 +#define PORTSCX_PTW_16BIT              (1 << 28)       /* 16 bi parallel xcvr */
7081 +
7082 +/* bit 27-26 are port speed */
7083 +#define PORTSCX_PORT_SPEED_FULL                (0 << 26)
7084 +#define PORTSCX_PORT_SPEED_LOW         (1 << 26)
7085 +#define PORTSCX_PORT_SPEED_HIGH                (2 << 26)
7086 +#define PORTSCX_PORT_SPEED_UNDEF       (3 << 26)
7087 +#define PORTSCX_PORT_SPEED_MASK                (3 << 26)
7088 +
7089 +#define PORTSCX_PHY_LOW_POWER_SPD      (1 << 23)       /* phy low pwr suspend/clk disable */
7090 +
7091 +/* bit 19-16 are port test control */
7092 +#define PORTSCX_PTC_DISABLE            (0 << 16)
7093 +#define PORTSCX_PTC_JSTATE             (1 << 16)
7094 +#define PORTSCX_PTC_KSTATE             (2 << 16)
7095 +#define PORTSCX_PTC_SEQNAK             (3 << 16)       /* SE0 (host) / NAK (device) */
7096 +#define PORTSCX_PTC_PACKET             (4 << 16)
7097 +#define PORTSCX_PTC_FORCE_EN_HS                (5 << 16)
7098 +#define PORTSCX_PTC_FORCE_EN_FS                (6 << 16)
7099 +#define PORTSCX_PTC_FORCE_EN_LS                (7 << 16)
7100 +
7101 +
7102 +/* bit 15-14 are port indicator control */
7103 +#define PORTSCX_PIC_OFF                        (0 << 14)
7104 +#define PORTSCX_PIC_AMBER              (1 << 14)
7105 +#define PORTSCX_PIC_GREEN              (2 << 14)
7106 +#define PORTSCX_PIC_UNDEF              (3 << 14)
7107 +
7108 +#define PORTSCX_PORT_POWER             (1 << 12)       /* port power */
7109 +
7110 +/* bit 11-10 are line status */
7111 +#define PORTSCX_LS_MASK                        (3 << 10)       /* Line State mask */
7112 +#define PORTSCX_LS_SE0                 (0 << 10)       /* SE0     */
7113 +#define PORTSCX_LS_K_STATE             (1 << 10)       /* K-state */
7114 +#define PORTSCX_LS_J_STATE             (2 << 10)       /* J-state */
7115 +
7116 +#define PORTSCX_PORT_RESET             (1 <<  8)       /* Port reset */
7117 +#define PORTSCX_PORT_SUSPEND           (1 <<  7)       /* Suspend */
7118 +#define PORTSCX_PORT_FORCE_RESUME      (1 <<  6)       /* Force port resume */
7119 +#define PORTSCX_OVER_CURRENT_CHG       (1 <<  5)       /* over current change */
7120 +#define PORTSCX_OVER_CURRENT_ACT       (1 <<  4)       /* over currrent active */
7121 +#define PORTSCX_PORT_EN_DIS_CHANGE     (1 <<  3)       /* port {en,dis}able change */
7122 +#define PORTSCX_PORT_ENABLE            (1 <<  2)       /* port enabled */
7123 +#define PORTSCX_CONNECT_STATUS_CHANGE  (1 <<  1)       /* connect status change */
7124 +#define PORTSCX_CURRENT_CONNECT_STATUS (1 <<  0)       /* current connect status */
7125 +
7126 +#define PORTSCX_W1C_BITS                     \
7127 +       ( PORTSCX_CONNECT_STATUS_CHANGE |     \
7128 +         PORTSCX_PORT_EN_DIS_CHANGE    |     \
7129 +         PORTSCX_OVER_CURRENT_CHG )
7130 +
7131 +
7132 +
7133 +/* UOG_OTGSC Register Bits */
7134 +/* control bits: */
7135 +#define  OTGSC_CTRL_VBUS_DISCHARGE     (1 <<  0)
7136 +#define  OTGSC_CTRL_VBUS_CHARGE                (1 <<  1)
7137 +#define  OTGSC_CTRL_OTG_TERM           (1 <<  3)       /* controls DM pulldown */
7138 +#define  OTGSC_CTRL_DATA_PULSING       (1 <<  4)
7139 +#define  OTGSC_CTRL_USB_ID_PU          (1 <<  5)       /* enable ID pullup */
7140 +/* current status: (R/O) */
7141 +#define  OTGSC_STS_USB_ID              (1 <<  8)       /* 0=A-device  1=B-device */
7142 +#define  OTGSC_STS_A_VBUS_VALID                (1 <<  9)
7143 +#define  OTGSC_STS_A_SESSION_VALID     (1 << 10)
7144 +#define  OTGSC_STS_B_SESSION_VALID     (1 << 11)
7145 +#define  OTGSC_STS_B_SESSION_END       (1 << 12)
7146 +#define  OTGSC_STS_1ms_TIMER           (1 << 13)
7147 +#define  OTGSC_STS_DATA_PULSE          (1 << 14)
7148 +/* interrupt status: (write to clear) */
7149 +#define  OTGSC_INTSTS_MASK             (0x7f << 16)
7150 +#define  OTGSC_INTSTS_USB_ID           (1 << 16)
7151 +#define  OTGSC_INTSTS_A_VBUS_VALID     (1 << 17)
7152 +#define  OTGSC_INTSTS_A_SESSION_VALID  (1 << 18)
7153 +#define  OTGSC_INTSTS_B_SESSION_VALID  (1 << 19)
7154 +#define  OTGSC_INTSTS_B_SESSION_END    (1 << 20)
7155 +#define  OTGSC_INTSTS_1MS_TIMER                (1 << 21)
7156 +#define  OTGSC_INTSTS_DATA_PULSE       (1 << 22)
7157 +/* interrupt enables: */
7158 +#define  OTGSC_IE_MASK                 (0x7f << 24)
7159 +#define  OTGSC_IE_USB_ID               (1 << 24)
7160 +#define  OTGSC_IE_A_VBUS_VALID         (1 << 25)
7161 +#define  OTGSC_IE_A_SESSION_VALID      (1 << 26)
7162 +#define  OTGSC_IE_B_SESSION_VALID      (1 << 27)
7163 +#define  OTGSC_IE_B_SESSION_END                (1 << 28)
7164 +#define  OTGSC_IE_1ms_TIMER            (1 << 29)
7165 +#define  OTGSC_IE_DATA_PULSE           (1 << 30)
7166 +
7167 +#if 1  /* DDD FIXME these here for compatibility between my names and Leo's */
7168 +/* OTG interrupt enable bit masks */
7169 +#define  OTGSC_INTERRUPT_ENABLE_BITS_MASK      OTGSC_IE_MASK
7170 +
7171 +/* OTG interrupt status bit masks */
7172 +#define  OTGSC_INTERRUPT_STATUS_BITS_MASK      OTGSC_INTSTS_MASK
7173 +#endif // 1
7174 +
7175 +
7176 +
7177 +/* x_USBMODE */
7178 +#undef USBMODE_SDIS    /* defined as bit 3 in drivers/usb/host/ehci.h */
7179 +#define USBMODE_SDIS           (1 << 4)        /* stream disable mode */
7180 +#define USBMODE_SLOM           (1 << 3)        /* setup lockout mode */
7181 +#define USBMODE_ES             (1 << 2)        /* (big) endian select */
7182 +#define USBMODE_CM_MASK                (3 << 0)        /* controller mode mask */
7183 +#define USBMODE_CM_HOST                (3 << 0)        /* host */
7184 +#define USBMODE_CM_DEVICE      (2 << 0)        /* device */
7185 +// DDD #define USBMODE_CM_IDLE         (0 << 0)        /* idle */
7186 +
7187 +/* DDD for compatibility for now */
7188 +#define USB_MODE_CTRL_MODE_IDLE                USBMODE_CM_IDLE
7189 +#define USB_MODE_CTRL_MODE_DEVICE      USBMODE_CM_DEVICE
7190 +#define USB_MODE_CTRL_MODE_HOST                USBMODE_CM_HOST
7191 +#define USB_MODE_SETUP_LOCK_OFF                USBMODE_SLOM
7192 +#define USB_MODE_STREAM_DISABLE                USBMODE_SDIS
7193 +
7194 +
7195 +/* ULPIVIEW register bits */
7196 +#define ULPIVW_WU              (1 << 31)       /* Wakeup */
7197 +#define ULPIVW_RUN             (1 << 30)       /* read/write run */
7198 +#define ULPIVW_WRITE           (1 << 29)       /* 0=read  1=write */
7199 +#define ULPIVW_SS              (1 << 27)       /* SyncState */
7200 +#define ULPIVW_PORT_MASK       0x07            /* Port field */
7201 +#define ULPIVW_PORT_SHIFT      24
7202 +#define ULPIVW_ADDR_MASK       0xFF            /* data address field */
7203 +#define ULPIVW_ADDR_SHIFT      16
7204 +#define ULPIVW_RDATA_MASK      0xFF            /* read data field */
7205 +#define ULPIVW_RDATA_SHIFT     8
7206 +#define ULPIVW_WDATA_MASK      0xFF            /* write data field */
7207 +#define ULPIVW_WDATA_SHIFT     0
7208 +
7209 +
7210 +/* Endpoint Flush Register */
7211 +#define EPFLUSH_TX_OFFSET                      0x00010000
7212 +#define EPFLUSH_RX_OFFSET                      0x00000000
7213 +
7214 +/* Endpoint Setup Status bit masks */
7215 +#define EP_SETUP_STATUS_MASK                   0x0000003F
7216 +#define EP_SETUP_STATUS_EP0                    0x00000001
7217 +
7218 +/* ENDPOINTCTRLx  Register Bit Masks */
7219 +#define EPCTRL_TX_ENABLE                       0x00800000
7220 +#define EPCTRL_TX_DATA_TOGGLE_RST              0x00400000      /* Not EP0 */
7221 +#define EPCTRL_TX_DATA_TOGGLE_INH              0x00200000      /* Not EP0 */
7222 +#define EPCTRL_TX_TYPE                         0x000C0000
7223 +#define EPCTRL_TX_DATA_SOURCE                  0x00020000      /* Not EP0 */
7224 +#define EPCTRL_TX_EP_STALL                     0x00010000
7225 +#define EPCTRL_RX_ENABLE                       0x00000080
7226 +#define EPCTRL_RX_DATA_TOGGLE_RST              0x00000040      /* Not EP0 */
7227 +#define EPCTRL_RX_DATA_TOGGLE_INH              0x00000020      /* Not EP0 */
7228 +#define EPCTRL_RX_TYPE                         0x0000000C
7229 +#define EPCTRL_RX_DATA_SINK                    0x00000002      /* Not EP0 */
7230 +#define EPCTRL_RX_EP_STALL                     0x00000001
7231 +
7232 +/* bit 19-18 and 3-2 are endpoint type */
7233 +#define EPCTRL_EP_TYPE_CONTROL                 0
7234 +#define EPCTRL_EP_TYPE_ISO                     1
7235 +#define EPCTRL_EP_TYPE_BULK                    2
7236 +#define EPCTRL_EP_TYPE_INTERRUPT               3
7237 +#define EPCTRL_TX_EP_TYPE_SHIFT                        18
7238 +#define EPCTRL_RX_EP_TYPE_SHIFT                        2
7239 +
7240 +/* SNOOPn Register Bit Masks */
7241 +#define SNOOP_ADDRESS_MASK                     0xFFFFF000
7242 +#define SNOOP_SIZE_ZERO                                0x00    /* snooping disable */
7243 +#define SNOOP_SIZE_4KB                         0x0B    /* 4KB snoop size */
7244 +#define SNOOP_SIZE_8KB                         0x0C
7245 +#define SNOOP_SIZE_16KB                                0x0D
7246 +#define SNOOP_SIZE_32KB                                0x0E
7247 +#define SNOOP_SIZE_64KB                                0x0F
7248 +#define SNOOP_SIZE_128KB                       0x10
7249 +#define SNOOP_SIZE_256KB                       0x11
7250 +#define SNOOP_SIZE_512KB                       0x12
7251 +#define SNOOP_SIZE_1MB                         0x13
7252 +#define SNOOP_SIZE_2MB                         0x14
7253 +#define SNOOP_SIZE_4MB                         0x15
7254 +#define SNOOP_SIZE_8MB                         0x16
7255 +#define SNOOP_SIZE_16MB                                0x17
7256 +#define SNOOP_SIZE_32MB                                0x18
7257 +#define SNOOP_SIZE_64MB                                0x19
7258 +#define SNOOP_SIZE_128MB                       0x1A
7259 +#define SNOOP_SIZE_256MB                       0x1B
7260 +#define SNOOP_SIZE_512MB                       0x1C
7261 +#define SNOOP_SIZE_1GB                         0x1D
7262 +#define SNOOP_SIZE_2GB                         0x1E    /* 2GB snoop size */
7263 +
7264 +/* pri_ctrl Register Bit Masks */
7265 +#define PRI_CTRL_PRI_LVL1                      0x0000000C
7266 +#define PRI_CTRL_PRI_LVL0                      0x00000003
7267 +
7268 +/* si_ctrl Register Bit Masks */
7269 +#define SI_CTRL_ERR_DISABLE                    0x00000010
7270 +#define SI_CTRL_IDRC_DISABLE                   0x00000008
7271 +#define SI_CTRL_RD_SAFE_EN                     0x00000004
7272 +#define SI_CTRL_RD_PREFETCH_DISABLE            0x00000002
7273 +#define SI_CTRL_RD_PREFEFETCH_VAL              0x00000001
7274 +
7275 +
7276 +/* control Register Bit Masks */
7277 +#define USB_CTRL_IOENB                         0x00000004
7278 +#define USB_CTRL_ULPI_INT0EN                   0x00000001
7279 +
7280 +
7281 +/* Endpoint Transfer Descriptor bit Masks */
7282 +#define DTD_NEXT_TERMINATE                     0x00000001
7283 +#define DTD_IOC                                        0x00008000
7284 +#define DTD_STATUS_ACTIVE                      0x00000080
7285 +#define DTD_STATUS_HALTED                      0x00000040
7286 +#define DTD_STATUS_DATA_BUFF_ERR               0x00000020
7287 +#define DTD_STATUS_TRANSACTION_ERR             0x00000008
7288 +#define DTD_RESERVED_FIELDS                    0x80007300
7289 +#define DTD_ADDR_MASK                          0xFFFFFFE0
7290 +#define DTD_PACKET_SIZE                                0x7FFF0000
7291 +#define DTD_LENGTH_BIT_POS                     16
7292 +#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \
7293 +                       DTD_STATUS_DATA_BUFF_ERR | \
7294 +                       DTD_STATUS_TRANSACTION_ERR)
7295 +/* Alignment requirements; must be a power of two */
7296 +#define DTD_ALIGNMENT                          0x20
7297 +#define QH_ALIGNMENT                           2048
7298 +
7299 +/* Controller dma boundary */
7300 +#define UDC_DMA_BOUNDARY                       0x1000
7301 +
7302 +#if defined CONFIG_PPC32
7303 +#define fsl_readl(addr)                in_le32((addr))
7304 +#define fsl_writel(addr, val32)        out_le32((addr), (val32))
7305 +#elif defined CONFIG_COLDFIRE
7306 +#define fsl_readl(addr)                in_be32((__force unsigned *)(addr))
7307 +#define fsl_writel(val32, addr)        out_be32((__force unsigned *)(addr), (val32))
7308 +
7309 +#define fsl_readw(addr)                in_be16((__force unsigned *)(addr))
7310 +#define fsl_writew(val16, addr)        out_be16((__force unsigned *)(addr), (val16))
7311 +#else
7312 +#error fsl_{readl, writel} must be defined
7313 +#endif
7314 +
7315 +#endif /* __FSL_USB2_H */
7316 --- /dev/null
7317 +++ b/include/linux/usb/fsl_xcvr.h
7318 @@ -0,0 +1,42 @@
7319 +/*
7320 + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
7321 + */
7322 +
7323 +/*
7324 + * The code contained herein is licensed under the GNU General Public
7325 + * License. You may obtain a copy of the GNU General Public License
7326 + * Version 2 or later at the following locations:
7327 + *
7328 + * http://www.opensource.org/licenses/gpl-license.html
7329 + * http://www.gnu.org/copyleft/gpl.html
7330 + */
7331 +
7332 +enum fsl_usb_ctrlr {
7333 +       USB_CTRLR_H1 = 0,
7334 +       USB_CTRLR_H2 = 1,
7335 +       USB_CTRLR_OTG = 2,
7336 +};
7337 +
7338 +
7339 +/**
7340 + * struct fsl_xcvr_ops - USB transceiver operations
7341 + *
7342 + * @xcvr_type: one of PORTSCX_PTS_{UTMI,SERIAL,ULPI}
7343 + * @init: transceiver- and board-specific initialization function
7344 + * @uninit: transceiver- and board-specific uninitialization function
7345 + * @set_host:
7346 + * @set_device:
7347 + *
7348 + */
7349 +struct fsl_xcvr_ops {
7350 +       enum fsl_usb_ctrlr ctrlr;       /* H1, H2, OTG */
7351 +       u32 xcvr_type;
7352 +
7353 +       void (*init)(struct platform_device *pdev);
7354 +       void (*uninit)(struct platform_device *pdev);
7355 +       void (*set_host)(void); /* DDD combine set_host and _device ? */
7356 +       void (*set_device)(void);
7357 +       void (*set_vbus_power)(struct fsl_usb2_platform_data *pdata, int on);
7358 +};
7359 +
7360 +