target/linux/brcm63xx/patches-3.8/025-MIPS-BCM63XX-add-basic-BCM6362-support.patch

   1 From 1071a9c9527d68eca4605e2eb1686609bfecf287 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Mon, 21 Nov 2011 00:48:52 +0100
   4 Subject: [PATCH 4/7] MIPS: BCM63XX: add basic BCM6362 support
   5
   6 Add basic support for detecting and booting the BCM6362.
   7
   8 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
   9 ---
  10  arch/mips/bcm63xx/Kconfig                         |    4 +
  11  arch/mips/bcm63xx/boards/board_bcm963xx.c         |    6 +-
  12  arch/mips/bcm63xx/cpu.c                           |   51 +++++++-
  13  arch/mips/bcm63xx/irq.c                           |   22 ++++
  14  arch/mips/bcm63xx/prom.c                          |    2 +
  15  arch/mips/bcm63xx/reset.c                         |   28 +++++
  16  arch/mips/bcm63xx/setup.c                         |    3 +
  17  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |  139 +++++++++++++++++++++
  18  arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |    2 +
  19  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   61 ++++++++-
  20  arch/mips/include/asm/mach-bcm63xx/ioremap.h      |    1 +
  21  11 files changed, 314 insertions(+), 5 deletions(-)
  22
  23 --- a/arch/mips/bcm63xx/Kconfig
  24 +++ b/arch/mips/bcm63xx/Kconfig
  25 @@ -25,6 +25,10 @@ config BCM63XX_CPU_6358
  26         bool "support 6358 CPU"
  27         select HW_HAS_PCI
  28
  29 +config BCM63XX_CPU_6362
  30 +       bool "support 6362 CPU"
  31 +       select HW_HAS_PCI
  32 +
  33  config BCM63XX_CPU_6368
  34         bool "support 6368 CPU"
  35         select HW_HAS_PCI
  36 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
  37 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
  38 @@ -726,11 +726,11 @@ void __init board_prom_init(void)
  39         u32 val;
  40
  41         /* read base address of boot chip select (0)
  42 -        * 6328 does not have MPI but boots from a fixed address
  43 +        * 6328/6362 do not have MPI but boot from a fixed address
  44          */
  45 -       if (BCMCPU_IS_6328())
  46 +       if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
  47                 val = 0x18000000;
  48 -       else {
  49 +       } else {
  50                 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
  51                 val &= MPI_CSBASE_BASE_MASK;
  52         }
  53 --- a/arch/mips/bcm63xx/cpu.c
  54 +++ b/arch/mips/bcm63xx/cpu.c
  55 @@ -71,6 +71,15 @@ static const int bcm6358_irqs[] = {
  56
  57  };
  58
  59 +static const unsigned long bcm6362_regs_base[] = {
  60 +       __GEN_CPU_REGS_TABLE(6362)
  61 +};
  62 +
  63 +static const int bcm6362_irqs[] = {
  64 +       __GEN_CPU_IRQ_TABLE(6362)
  65 +
  66 +};
  67 +
  68  static const unsigned long bcm6368_regs_base[] = {
  69         __GEN_CPU_REGS_TABLE(6368)
  70  };
  71 @@ -169,6 +178,42 @@ static unsigned int detect_cpu_clock(voi
  72                 return (16 * 1000000 * n1 * n2) / m1;
  73         }
  74
  75 +       case BCM6362_CPU_ID:
  76 +       {
  77 +               unsigned int tmp, mips_pll_fcvo;
  78 +
  79 +               tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
  80 +               mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
  81 +                               >> STRAPBUS_6362_FCVO_SHIFT;
  82 +               switch (mips_pll_fcvo) {
  83 +               case 0x03:
  84 +               case 0x0b:
  85 +               case 0x13:
  86 +               case 0x1b:
  87 +                       return 240000000;
  88 +               case 0x04:
  89 +               case 0x0c:
  90 +               case 0x14:
  91 +               case 0x1c:
  92 +                       return 160000000;
  93 +               case 0x05:
  94 +               case 0x0e:
  95 +               case 0x16:
  96 +               case 0x1e:
  97 +               case 0x1f:
  98 +                       return 400000000;
  99 +               case 0x06:
 100 +                       return 440000000;
 101 +               case 0x07:
 102 +               case 0x17:
 103 +                       return 384000000;
 104 +               case 0x15:
 105 +               case 0x1d:
 106 +                       return 200000000;
 107 +               default:
 108 +                       return 320000000;
 109 +               }
 110 +       }
 111         case BCM6368_CPU_ID:
 112         {
 113                 unsigned int tmp, p1, p2, ndiv, m1;
 114 @@ -205,7 +250,7 @@ static unsigned int detect_memory_size(v
 115         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 116         u32 val;
 117
 118 -       if (BCMCPU_IS_6328())
 119 +       if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
 120                 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
 121
 122         if (BCMCPU_IS_6345()) {
 123 @@ -297,6 +342,10 @@ void __init bcm63xx_cpu_init(void)
 124                 bcm63xx_regs_base = bcm6358_regs_base;
 125                 bcm63xx_irqs = bcm6358_irqs;
 126                 break;
 127 +       case BCM6362_CPU_ID:
 128 +               bcm63xx_regs_base = bcm6362_regs_base;
 129 +               bcm63xx_irqs = bcm6362_irqs;
 130 +               break;
 131         case BCM6368_CPU_ID:
 132                 bcm63xx_regs_base = bcm6368_regs_base;
 133                 bcm63xx_irqs = bcm6368_irqs;
 134 --- a/arch/mips/bcm63xx/irq.c
 135 +++ b/arch/mips/bcm63xx/irq.c
 136 @@ -82,6 +82,17 @@ static void __internal_irq_unmask_64(uns
 137  #define ext_irq_cfg_reg1       PERF_EXTIRQ_CFG_REG_6358
 138  #define ext_irq_cfg_reg2       0
 139  #endif
 140 +#ifdef CONFIG_BCM63XX_CPU_6362
 141 +#define irq_stat_reg           PERF_IRQSTAT_6362_REG
 142 +#define irq_mask_reg           PERF_IRQMASK_6362_REG
 143 +#define irq_bits               64
 144 +#define is_ext_irq_cascaded    1
 145 +#define ext_irq_start          (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
 146 +#define ext_irq_end            (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
 147 +#define ext_irq_count          4
 148 +#define ext_irq_cfg_reg1       PERF_EXTIRQ_CFG_REG_6362
 149 +#define ext_irq_cfg_reg2       0
 150 +#endif
 151  #ifdef CONFIG_BCM63XX_CPU_6368
 152  #define irq_stat_reg           PERF_IRQSTAT_6368_REG
 153  #define irq_mask_reg           PERF_IRQMASK_6368_REG
 154 @@ -170,6 +181,16 @@ static void bcm63xx_init_irq(void)
 155                 ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
 156                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
 157                 break;
 158 +       case BCM6362_CPU_ID:
 159 +               irq_stat_addr += PERF_IRQSTAT_6362_REG;
 160 +               irq_mask_addr += PERF_IRQMASK_6362_REG;
 161 +               irq_bits = 64;
 162 +               ext_irq_count = 4;
 163 +               is_ext_irq_cascaded = 1;
 164 +               ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
 165 +               ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
 166 +               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
 167 +               break;
 168         case BCM6368_CPU_ID:
 169                 irq_stat_addr += PERF_IRQSTAT_6368_REG;
 170                 irq_mask_addr += PERF_IRQMASK_6368_REG;
 171 @@ -458,6 +479,7 @@ static int bcm63xx_external_irq_set_type
 172         case BCM6338_CPU_ID:
 173         case BCM6345_CPU_ID:
 174         case BCM6358_CPU_ID:
 175 +       case BCM6362_CPU_ID:
 176         case BCM6368_CPU_ID:
 177                 if (levelsense)
 178                         reg |= EXTIRQ_CFG_LEVELSENSE(irq);
 179 --- a/arch/mips/bcm63xx/prom.c
 180 +++ b/arch/mips/bcm63xx/prom.c
 181 @@ -36,6 +36,8 @@ void __init prom_init(void)
 182                 mask = CKCTL_6348_ALL_SAFE_EN;
 183         else if (BCMCPU_IS_6358())
 184                 mask = CKCTL_6358_ALL_SAFE_EN;
 185 +       else if (BCMCPU_IS_6362())
 186 +               mask = CKCTL_6362_ALL_SAFE_EN;
 187         else if (BCMCPU_IS_6368())
 188                 mask = CKCTL_6368_ALL_SAFE_EN;
 189         else
 190 --- a/arch/mips/bcm63xx/reset.c
 191 +++ b/arch/mips/bcm63xx/reset.c
 192 @@ -85,6 +85,20 @@
 193  #define BCM6358_RESET_PCIE     0
 194  #define BCM6358_RESET_PCIE_EXT 0
 195
 196 +#define BCM6362_RESET_SPI      SOFTRESET_6362_SPI_MASK
 197 +#define BCM6362_RESET_ENET     0
 198 +#define BCM6362_RESET_USBH     SOFTRESET_6362_USBH_MASK
 199 +#define BCM6362_RESET_USBD     SOFTRESET_6362_USBS_MASK
 200 +#define BCM6362_RESET_DSL      0
 201 +#define BCM6362_RESET_SAR      SOFTRESET_6362_SAR_MASK
 202 +#define BCM6362_RESET_EPHY     SOFTRESET_6362_EPHY_MASK
 203 +#define BCM6362_RESET_ENETSW   SOFTRESET_6362_ENETSW_MASK
 204 +#define BCM6362_RESET_PCM      SOFTRESET_6362_PCM_MASK
 205 +#define BCM6362_RESET_MPI      0
 206 +#define BCM6362_RESET_PCIE      (SOFTRESET_6362_PCIE_MASK | \
 207 +                                SOFTRESET_6362_PCIE_CORE_MASK)
 208 +#define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK
 209 +
 210  #define BCM6368_RESET_SPI      SOFTRESET_6368_SPI_MASK
 211  #define BCM6368_RESET_ENET     0
 212  #define BCM6368_RESET_USBH     SOFTRESET_6368_USBH_MASK
 213 @@ -119,6 +133,10 @@ static const u32 bcm6358_reset_bits[] =
 214         __GEN_RESET_BITS_TABLE(6358)
 215  };
 216
 217 +static const u32 bcm6362_reset_bits[] = {
 218 +       __GEN_RESET_BITS_TABLE(6362)
 219 +};
 220 +
 221  static const u32 bcm6368_reset_bits[] = {
 222         __GEN_RESET_BITS_TABLE(6368)
 223  };
 224 @@ -140,6 +158,9 @@ static int __init bcm63xx_reset_bits_ini
 225         } else if (BCMCPU_IS_6358()) {
 226                 reset_reg = PERF_SOFTRESET_6358_REG;
 227                 bcm63xx_reset_bits = bcm6358_reset_bits;
 228 +       } else if (BCMCPU_IS_6362()) {
 229 +               reset_reg = PERF_SOFTRESET_6362_REG;
 230 +               bcm63xx_reset_bits = bcm6362_reset_bits;
 231         } else if (BCMCPU_IS_6368()) {
 232                 reset_reg = PERF_SOFTRESET_6368_REG;
 233                 bcm63xx_reset_bits = bcm6368_reset_bits;
 234 @@ -182,6 +203,13 @@ static const u32 bcm63xx_reset_bits[] =
 235  #define reset_reg PERF_SOFTRESET_6358_REG
 236  #endif
 237
 238 +#ifdef CONFIG_BCM63XX_CPU_6362
 239 +static const u32 bcm63xx_reset_bits[] = {
 240 +       __GEN_RESET_BITS_TABLE(6362)
 241 +};
 242 +#define reset_reg PERF_SOFTRESET_6362_REG
 243 +#endif
 244 +
 245  #ifdef CONFIG_BCM63XX_CPU_6368
 246  static const u32 bcm63xx_reset_bits[] = {
 247         __GEN_RESET_BITS_TABLE(6368)
 248 --- a/arch/mips/bcm63xx/setup.c
 249 +++ b/arch/mips/bcm63xx/setup.c
 250 @@ -83,6 +83,9 @@ void bcm63xx_machine_reboot(void)
 251         case BCM6358_CPU_ID:
 252                 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
 253                 break;
 254 +       case BCM6362_CPU_ID:
 255 +               perf_regs[0] = PERF_EXTIRQ_CFG_REG_6362;
 256 +               break;
 257         }
 258
 259         for (i = 0; i < 2; i++) {
 260 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 261 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
 262 @@ -14,6 +14,7 @@
 263  #define BCM6345_CPU_ID         0x6345
 264  #define BCM6348_CPU_ID         0x6348
 265  #define BCM6358_CPU_ID         0x6358
 266 +#define BCM6362_CPU_ID         0x6362
 267  #define BCM6368_CPU_ID         0x6368
 268
 269  void __init bcm63xx_cpu_init(void);
 270 @@ -86,6 +87,20 @@ unsigned int bcm63xx_get_cpu_freq(void);
 271  # define BCMCPU_IS_6358()      (0)
 272  #endif
 273
 274 +#ifdef CONFIG_BCM63XX_CPU_6362
 275 +# ifdef bcm63xx_get_cpu_id
 276 +#  undef bcm63xx_get_cpu_id
 277 +#  define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
 278 +#  define BCMCPU_RUNTIME_DETECT
 279 +# else
 280 +#  define bcm63xx_get_cpu_id() BCM6362_CPU_ID
 281 +# endif
 282 +# define BCMCPU_IS_6362()      (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
 283 +#else
 284 +# define BCMCPU_IS_6362()      (0)
 285 +#endif
 286 +
 287 +
 288  #ifdef CONFIG_BCM63XX_CPU_6368
 289  # ifdef bcm63xx_get_cpu_id
 290  #  undef bcm63xx_get_cpu_id
 291 @@ -406,6 +421,62 @@ enum bcm63xx_regs_set {
 292
 293
 294  /*
 295 + * 6362 register sets base address
 296 + */
 297 +#define BCM_6362_DSL_LMEM_BASE         (0xdeadbeef)
 298 +#define BCM_6362_PERF_BASE             (0xb0000000)
 299 +#define BCM_6362_TIMER_BASE            (0xb0000040)
 300 +#define BCM_6362_WDT_BASE              (0xb000005c)
 301 +#define BCM_6362_UART0_BASE             (0xb0000100)
 302 +#define BCM_6362_UART1_BASE            (0xb0000120)
 303 +#define BCM_6362_GPIO_BASE             (0xb0000080)
 304 +#define BCM_6362_SPI_BASE              (0xb0000800)
 305 +#define BCM_6362_HSSPI_BASE            (0xb0001000)
 306 +#define BCM_6362_UDC0_BASE             (0xdeadbeef)
 307 +#define BCM_6362_USBDMA_BASE           (0xb000c000)
 308 +#define BCM_6362_OHCI0_BASE            (0xb0002600)
 309 +#define BCM_6362_OHCI_PRIV_BASE                (0xdeadbeef)
 310 +#define BCM_6362_USBH_PRIV_BASE                (0xb0002700)
 311 +#define BCM_6362_USBD_BASE             (0xb0002400)
 312 +#define BCM_6362_MPI_BASE              (0xdeadbeef)
 313 +#define BCM_6362_PCMCIA_BASE           (0xdeadbeef)
 314 +#define BCM_6362_PCIE_BASE             (0xb0e40000)
 315 +#define BCM_6362_SDRAM_REGS_BASE       (0xdeadbeef)
 316 +#define BCM_6362_DSL_BASE              (0xdeadbeef)
 317 +#define BCM_6362_UBUS_BASE             (0xdeadbeef)
 318 +#define BCM_6362_ENET0_BASE            (0xdeadbeef)
 319 +#define BCM_6362_ENET1_BASE            (0xdeadbeef)
 320 +#define BCM_6362_ENETDMA_BASE          (0xb000d800)
 321 +#define BCM_6362_ENETDMAC_BASE         (0xb000da00)
 322 +#define BCM_6362_ENETDMAS_BASE         (0xb000dc00)
 323 +#define BCM_6362_ENETSW_BASE           (0xb0e00000)
 324 +#define BCM_6362_EHCI0_BASE            (0xb0002500)
 325 +#define BCM_6362_SDRAM_BASE            (0xdeadbeef)
 326 +#define BCM_6362_MEMC_BASE             (0xdeadbeef)
 327 +#define BCM_6362_DDR_BASE              (0xb0003000)
 328 +#define BCM_6362_M2M_BASE              (0xdeadbeef)
 329 +#define BCM_6362_ATM_BASE              (0xdeadbeef)
 330 +#define BCM_6362_XTM_BASE              (0xb0007800)
 331 +#define BCM_6362_XTMDMA_BASE           (0xb000b800)
 332 +#define BCM_6362_XTMDMAC_BASE          (0xdeadbeef)
 333 +#define BCM_6362_XTMDMAS_BASE          (0xdeadbeef)
 334 +#define BCM_6362_PCM_BASE              (0xb000a800)
 335 +#define BCM_6362_PCMDMA_BASE           (0xdeadbeef)
 336 +#define BCM_6362_PCMDMAC_BASE          (0xdeadbeef)
 337 +#define BCM_6362_PCMDMAS_BASE          (0xdeadbeef)
 338 +#define BCM_6362_RNG_BASE              (0xdeadbeef)
 339 +#define BCM_6362_MISC_BASE             (0xb0001800)
 340 +
 341 +#define BCM_6362_NAND_REG_BASE         (0xb0000200)
 342 +#define BCM_6362_NAND_CACHE_BASE       (0xb0000600)
 343 +#define BCM_6362_LED_BASE              (0xb0001900)
 344 +#define BCM_6362_IPSEC_BASE            (0xb0002800)
 345 +#define BCM_6362_IPSEC_DMA_BASE                (0xb000d000)
 346 +#define BCM_6362_WLAN_CHIPCOMMON_BASE  (0xb0004000)
 347 +#define BCM_6362_WLAN_D11_BASE         (0xb0005000)
 348 +#define BCM_6362_WLAN_SHIM_BASE                (0xb0007000)
 349 +
 350 +/*
 351   * 6368 register sets base address
 352   */
 353  #define BCM_6368_DSL_LMEM_BASE         (0xdeadbeef)
 354 @@ -564,6 +635,9 @@ static inline unsigned long bcm63xx_regs
 355  #ifdef CONFIG_BCM63XX_CPU_6358
 356         __GEN_RSET(6358)
 357  #endif
 358 +#ifdef CONFIG_BCM63XX_CPU_6362
 359 +       __GEN_RSET(6362)
 360 +#endif
 361  #ifdef CONFIG_BCM63XX_CPU_6368
 362         __GEN_RSET(6368)
 363  #endif
 364 @@ -820,6 +894,71 @@ enum bcm63xx_irq {
 365  #define BCM_6358_EXT_IRQ3              (IRQ_INTERNAL_BASE + 28)
 366
 367  /*
 368 + * 6362 irqs
 369 + */
 370 +#define BCM_6362_HIGH_IRQ_BASE         (IRQ_INTERNAL_BASE + 32)
 371 +
 372 +#define BCM_6362_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 373 +#define BCM_6362_SPI_IRQ               (IRQ_INTERNAL_BASE + 2)
 374 +#define BCM_6362_UART0_IRQ             (IRQ_INTERNAL_BASE + 3)
 375 +#define BCM_6362_UART1_IRQ             (IRQ_INTERNAL_BASE + 4)
 376 +#define BCM_6362_DSL_IRQ               (IRQ_INTERNAL_BASE + 28)
 377 +#define BCM_6362_UDC0_IRQ              0
 378 +#define BCM_6362_ENET0_IRQ             0
 379 +#define BCM_6362_ENET1_IRQ             0
 380 +#define BCM_6362_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 14)
 381 +#define BCM_6362_HSSPI_IRQ             (IRQ_INTERNAL_BASE + 5)
 382 +#define BCM_6362_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 9)
 383 +#define BCM_6362_EHCI0_IRQ             (IRQ_INTERNAL_BASE + 10)
 384 +#define BCM_6362_USBD_IRQ              (IRQ_INTERNAL_BASE + 11)
 385 +#define BCM_6362_USBD_RXDMA0_IRQ       (IRQ_INTERNAL_BASE + 20)
 386 +#define BCM_6362_USBD_TXDMA0_IRQ       (IRQ_INTERNAL_BASE + 21)
 387 +#define BCM_6362_USBD_RXDMA1_IRQ       (IRQ_INTERNAL_BASE + 22)
 388 +#define BCM_6362_USBD_TXDMA1_IRQ       (IRQ_INTERNAL_BASE + 23)
 389 +#define BCM_6362_USBD_RXDMA2_IRQ       (IRQ_INTERNAL_BASE + 24)
 390 +#define BCM_6362_USBD_TXDMA2_IRQ       (IRQ_INTERNAL_BASE + 25)
 391 +#define BCM_6362_PCMCIA_IRQ            0
 392 +#define BCM_6362_ENET0_RXDMA_IRQ       0
 393 +#define BCM_6362_ENET0_TXDMA_IRQ       0
 394 +#define BCM_6362_ENET1_RXDMA_IRQ       0
 395 +#define BCM_6362_ENET1_TXDMA_IRQ       0
 396 +#define BCM_6362_PCI_IRQ               (IRQ_INTERNAL_BASE + 30)
 397 +#define BCM_6362_ATM_IRQ               0
 398 +#define BCM_6362_ENETSW_RXDMA0_IRQ     (BCM_6362_HIGH_IRQ_BASE + 0)
 399 +#define BCM_6362_ENETSW_RXDMA1_IRQ     (BCM_6362_HIGH_IRQ_BASE + 1)
 400 +#define BCM_6362_ENETSW_RXDMA2_IRQ     (BCM_6362_HIGH_IRQ_BASE + 2)
 401 +#define BCM_6362_ENETSW_RXDMA3_IRQ     (BCM_6362_HIGH_IRQ_BASE + 3)
 402 +#define BCM_6362_ENETSW_TXDMA0_IRQ     0
 403 +#define BCM_6362_ENETSW_TXDMA1_IRQ     0
 404 +#define BCM_6362_ENETSW_TXDMA2_IRQ     0
 405 +#define BCM_6362_ENETSW_TXDMA3_IRQ     0
 406 +#define BCM_6362_XTM_IRQ               0
 407 +#define BCM_6362_XTM_DMA0_IRQ          (BCM_6362_HIGH_IRQ_BASE + 12)
 408 +
 409 +#define BCM_6362_RING_OSC_IRQ          (IRQ_INTERNAL_BASE + 1)
 410 +#define BCM_6362_WLAN_GPIO_IRQ         (IRQ_INTERNAL_BASE + 6)
 411 +#define BCM_6362_WLAN_IRQ              (IRQ_INTERNAL_BASE + 7)
 412 +#define BCM_6362_IPSEC_IRQ             (IRQ_INTERNAL_BASE + 8)
 413 +#define BCM_6362_NAND_IRQ              (IRQ_INTERNAL_BASE + 12)
 414 +#define BCM_6362_PCM_IRQ               (IRQ_INTERNAL_BASE + 13)
 415 +#define BCM_6362_DG_IRQ                        (IRQ_INTERNAL_BASE + 15)
 416 +#define BCM_6362_EPHY_ENERGY0_IRQ      (IRQ_INTERNAL_BASE + 16)
 417 +#define BCM_6362_EPHY_ENERGY1_IRQ      (IRQ_INTERNAL_BASE + 17)
 418 +#define BCM_6362_EPHY_ENERGY2_IRQ      (IRQ_INTERNAL_BASE + 18)
 419 +#define BCM_6362_EPHY_ENERGY3_IRQ      (IRQ_INTERNAL_BASE + 19)
 420 +#define BCM_6362_IPSEC_DMA0_IRQ                (IRQ_INTERNAL_BASE + 26)
 421 +#define BCM_6362_IPSEC_DMA1_IRQ                (IRQ_INTERNAL_BASE + 27)
 422 +#define BCM_6362_FAP0_IRQ              (IRQ_INTERNAL_BASE + 29)
 423 +#define BCM_6362_PCM_DMA0_IRQ          (BCM_6362_HIGH_IRQ_BASE + 4)
 424 +#define BCM_6362_PCM_DMA1_IRQ          (BCM_6362_HIGH_IRQ_BASE + 5)
 425 +#define BCM_6362_DECT0_IRQ             (BCM_6362_HIGH_IRQ_BASE + 6)
 426 +#define BCM_6362_DECT1_IRQ             (BCM_6362_HIGH_IRQ_BASE + 7)
 427 +#define BCM_6362_EXT_IRQ0              (BCM_6362_HIGH_IRQ_BASE + 8)
 428 +#define BCM_6362_EXT_IRQ1              (BCM_6362_HIGH_IRQ_BASE + 9)
 429 +#define BCM_6362_EXT_IRQ2              (BCM_6362_HIGH_IRQ_BASE + 10)
 430 +#define BCM_6362_EXT_IRQ3              (BCM_6362_HIGH_IRQ_BASE + 11)
 431 +
 432 +/*
 433   * 6368 irqs
 434   */
 435  #define BCM_6368_HIGH_IRQ_BASE         (IRQ_INTERNAL_BASE + 32)
 436 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
 437 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
 438 @@ -17,6 +17,8 @@ static inline unsigned long bcm63xx_gpio
 439                 return 8;
 440         case BCM6345_CPU_ID:
 441                 return 16;
 442 +       case BCM6362_CPU_ID:
 443 +               return 48;
 444         case BCM6368_CPU_ID:
 445                 return 38;
 446         case BCM6348_CPU_ID:
 447 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 448 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 449 @@ -112,6 +112,39 @@
 450                                         CKCTL_6358_USBSU_EN |           \
 451                                         CKCTL_6358_EPHY_EN)
 452
 453 +#define CKCTL_6362_ADSL_QPROC_EN       (1 << 1)
 454 +#define CKCTL_6362_ADSL_AFE_EN         (1 << 2)
 455 +#define CKCTL_6362_ADSL_EN             (1 << 3)
 456 +#define CKCTL_6362_MIPS_EN             (1 << 4)
 457 +#define CKCTL_6362_WLAN_OCP_EN         (1 << 5)
 458 +#define CKCTL_6362_SWPKT_USB_EN                (1 << 7)
 459 +#define CKCTL_6362_SWPKT_SAR_EN                (1 << 8)
 460 +#define CKCTL_6362_SAR_EN              (1 << 9)
 461 +#define CKCTL_6362_ROBOSW_EN           (1 << 10)
 462 +#define CKCTL_6362_PCM_EN              (1 << 11)
 463 +#define CKCTL_6362_USBD_EN             (1 << 12)
 464 +#define CKCTL_6362_USBH_EN             (1 << 13)
 465 +#define CKCTL_6362_IPSEC_EN            (1 << 14)
 466 +#define CKCTL_6362_SPI_EN              (1 << 15)
 467 +#define CKCTL_6362_HSSPI_EN            (1 << 16)
 468 +#define CKCTL_6362_PCIE_EN             (1 << 17)
 469 +#define CKCTL_6362_FAP_EN              (1 << 18)
 470 +#define CKCTL_6362_PHYMIPS_EN          (1 << 19)
 471 +#define CKCTL_6362_NAND_EN             (1 << 20)
 472 +
 473 +#define CKCTL_6362_ALL_SAFE_EN         (CKCTL_6362_PHYMIPS_EN |        \
 474 +                                       CKCTL_6362_ADSL_QPROC_EN |      \
 475 +                                       CKCTL_6362_ADSL_AFE_EN |        \
 476 +                                       CKCTL_6362_ADSL_EN |            \
 477 +                                       CKCTL_6362_SAR_EN  |            \
 478 +                                       CKCTL_6362_PCM_EN  |            \
 479 +                                       CKCTL_6362_IPSEC_EN |           \
 480 +                                       CKCTL_6362_USBD_EN |            \
 481 +                                       CKCTL_6362_USBH_EN |            \
 482 +                                       CKCTL_6362_ROBOSW_EN |          \
 483 +                                       CKCTL_6362_PCIE_EN)
 484 +
 485 +
 486  #define CKCTL_6368_VDSL_QPROC_EN       (1 << 2)
 487  #define CKCTL_6368_VDSL_AFE_EN         (1 << 3)
 488  #define CKCTL_6368_VDSL_BONDING_EN     (1 << 4)
 489 @@ -153,6 +186,7 @@
 490  #define PERF_IRQMASK_6345_REG          0xc
 491  #define PERF_IRQMASK_6348_REG          0xc
 492  #define PERF_IRQMASK_6358_REG          0xc
 493 +#define PERF_IRQMASK_6362_REG          0x20
 494  #define PERF_IRQMASK_6368_REG          0x20
 495
 496  /* Interrupt Status register */
 497 @@ -161,6 +195,7 @@
 498  #define PERF_IRQSTAT_6345_REG          0x10
 499  #define PERF_IRQSTAT_6348_REG          0x10
 500  #define PERF_IRQSTAT_6358_REG          0x10
 501 +#define PERF_IRQSTAT_6362_REG          0x28
 502  #define PERF_IRQSTAT_6368_REG          0x28
 503
 504  /* External Interrupt Configuration register */
 505 @@ -169,6 +204,7 @@
 506  #define PERF_EXTIRQ_CFG_REG_6345       0x14
 507  #define PERF_EXTIRQ_CFG_REG_6348       0x14
 508  #define PERF_EXTIRQ_CFG_REG_6358       0x14
 509 +#define PERF_EXTIRQ_CFG_REG_6362       0x18
 510  #define PERF_EXTIRQ_CFG_REG_6368       0x18
 511
 512  #define PERF_EXTIRQ_CFG_REG2_6368      0x1c
 513 @@ -197,6 +233,7 @@
 514  #define PERF_SOFTRESET_REG             0x28
 515  #define PERF_SOFTRESET_6328_REG                0x10
 516  #define PERF_SOFTRESET_6358_REG                0x34
 517 +#define PERF_SOFTRESET_6362_REG                0x10
 518  #define PERF_SOFTRESET_6368_REG                0x10
 519
 520  #define SOFTRESET_6328_SPI_MASK                (1 << 0)
 521 @@ -259,6 +296,22 @@
 522  #define SOFTRESET_6358_PCM_MASK                (1 << 13)
 523  #define SOFTRESET_6358_ADSL_MASK       (1 << 14)
 524
 525 +#define SOFTRESET_6362_SPI_MASK                (1 << 0)
 526 +#define SOFTRESET_6362_IPSEC_MASK      (1 << 1)
 527 +#define SOFTRESET_6362_EPHY_MASK       (1 << 2)
 528 +#define SOFTRESET_6362_SAR_MASK                (1 << 3)
 529 +#define SOFTRESET_6362_ENETSW_MASK     (1 << 4)
 530 +#define SOFTRESET_6362_USBS_MASK       (1 << 5)
 531 +#define SOFTRESET_6362_USBH_MASK       (1 << 6)
 532 +#define SOFTRESET_6362_PCM_MASK                (1 << 7)
 533 +#define SOFTRESET_6362_PCIE_CORE_MASK  (1 << 8)
 534 +#define SOFTRESET_6362_PCIE_MASK       (1 << 9)
 535 +#define SOFTRESET_6362_PCIE_EXT_MASK   (1 << 10)
 536 +#define SOFTRESET_6362_WLAN_SHIM_MASK  (1 << 11)
 537 +#define SOFTRESET_6362_DDR_PHY_MASK    (1 << 12)
 538 +#define SOFTRESET_6362_FAP_MASK                (1 << 13)
 539 +#define SOFTRESET_6362_WLAN_UBUS_MASK  (1 << 14)
 540 +
 541  #define SOFTRESET_6368_SPI_MASK                (1 << 0)
 542  #define SOFTRESET_6368_MPI_MASK                (1 << 3)
 543  #define SOFTRESET_6368_EPHY_MASK       (1 << 6)
 544 @@ -1240,7 +1293,7 @@
 545  #define SPI_6348_RX_DATA               0x80
 546  #define SPI_6348_RX_DATA_SIZE          0x3f
 547
 548 -/* BCM 6358/6368 SPI core */
 549 +/* BCM 6358/6262/6368 SPI core */
 550  #define SPI_6358_MSG_CTL               0x00    /* 16-bits register */
 551  #define SPI_6358_MSG_CTL_WIDTH         16
 552  #define SPI_6358_MSG_DATA              0x02
 553 @@ -1316,6 +1369,12 @@
 554  #define SERDES_PCIE_EN                 (1 << 0)
 555  #define SERDES_PCIE_EXD_EN             (1 << 15)
 556
 557 +#define MISC_STRAPBUS_6362_REG         0x14
 558 +#define STRAPBUS_6362_FCVO_SHIFT       1
 559 +#define STRAPBUS_6362_FCVO_MASK                (0x1f << STRAPBUS_6362_FCVO_SHIFT)
 560 +#define STRAPBUS_6362_BOOT_SEL_SERIAL  (1 << 15)
 561 +#define STRAPBUS_6362_BOOT_SEL_NAND    (0 << 15)
 562 +
 563  #define MISC_STRAPBUS_6328_REG         0x240
 564  #define STRAPBUS_6328_FCVO_SHIFT       7
 565  #define STRAPBUS_6328_FCVO_MASK                (0x1f << STRAPBUS_6328_FCVO_SHIFT)
 566 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
 567 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
 568 @@ -19,6 +19,7 @@ static inline int is_bcm63xx_internal_re
 569                         return 1;
 570                 break;
 571         case BCM6328_CPU_ID:
 572 +       case BCM6362_CPU_ID:
 573         case BCM6368_CPU_ID:
 574                 if (offset >= 0xb0000000 && offset < 0xb1000000)
 575                         return 1;