1 From c029c7520b110472164073f3a5b84841a2624c40 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Mon, 3 Sep 2012 01:07:40 +0200
4 Subject: [PATCH 2/3] MIPS: BCM63XX: add core reset helper
6 Add a reset helper for resetting the different cores.
8 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
10 arch/mips/bcm63xx/Makefile | 6 +-
11 arch/mips/bcm63xx/reset.c | 223 ++++++++++++++++++++
12 arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h | 21 ++
13 3 files changed, 247 insertions(+), 3 deletions(-)
14 create mode 100644 arch/mips/bcm63xx/reset.c
15 create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
17 --- a/arch/mips/bcm63xx/Makefile
18 +++ b/arch/mips/bcm63xx/Makefile
20 -obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
21 - dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \
22 - dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o
23 +obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o reset.o setup.o \
24 + timer.o dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o \
25 + dev-rng.o dev-spi.o dev-uart.o dev-wdt.o dev-usb-usbd.o
26 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
30 +++ b/arch/mips/bcm63xx/reset.c
33 + * This file is subject to the terms and conditions of the GNU General Public
34 + * License. See the file "COPYING" in the main directory of this archive
37 + * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
40 +#include <linux/module.h>
41 +#include <linux/mutex.h>
42 +#include <linux/err.h>
43 +#include <linux/clk.h>
44 +#include <linux/delay.h>
45 +#include <bcm63xx_cpu.h>
46 +#include <bcm63xx_io.h>
47 +#include <bcm63xx_regs.h>
48 +#include <bcm63xx_reset.h>
50 +#define __GEN_RESET_BITS_TABLE(__cpu) \
51 + [BCM63XX_RESET_SPI] = BCM## __cpu ##_RESET_SPI, \
52 + [BCM63XX_RESET_ENET] = BCM## __cpu ##_RESET_ENET, \
53 + [BCM63XX_RESET_USBH] = BCM## __cpu ##_RESET_USBH, \
54 + [BCM63XX_RESET_USBD] = BCM## __cpu ##_RESET_USBD, \
55 + [BCM63XX_RESET_DSL] = BCM## __cpu ##_RESET_DSL, \
56 + [BCM63XX_RESET_SAR] = BCM## __cpu ##_RESET_SAR, \
57 + [BCM63XX_RESET_EPHY] = BCM## __cpu ##_RESET_EPHY, \
58 + [BCM63XX_RESET_ENETSW] = BCM## __cpu ##_RESET_ENETSW, \
59 + [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \
60 + [BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \
61 + [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \
62 + [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT,
64 +#define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
65 +#define BCM6328_RESET_ENET 0
66 +#define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
67 +#define BCM6328_RESET_USBD SOFTRESET_6328_USBS_MASK
68 +#define BCM6328_RESET_DSL 0
69 +#define BCM6328_RESET_SAR SOFTRESET_6328_SAR_MASK
70 +#define BCM6328_RESET_EPHY SOFTRESET_6328_EPHY_MASK
71 +#define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK
72 +#define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK
73 +#define BCM6328_RESET_MPI 0
74 +#define BCM6328_RESET_PCIE \
75 + (SOFTRESET_6328_PCIE_MASK | \
76 + SOFTRESET_6328_PCIE_CORE_MASK | \
77 + SOFTRESET_6328_PCIE_HARD_MASK)
78 +#define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK
80 +#define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK
81 +#define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK
82 +#define BCM6338_RESET_USBH SOFTRESET_6338_USBH_MASK
83 +#define BCM6338_RESET_USBD SOFTRESET_6338_USBS_MASK
84 +#define BCM6338_RESET_DSL SOFTRESET_6338_ADSL_MASK
85 +#define BCM6338_RESET_SAR SOFTRESET_6338_SAR_MASK
86 +#define BCM6338_RESET_EPHY 0
87 +#define BCM6338_RESET_ENETSW 0
88 +#define BCM6338_RESET_PCM 0
89 +#define BCM6338_RESET_MPI 0
90 +#define BCM6338_RESET_PCIE 0
91 +#define BCM6338_RESET_PCIE_EXT 0
93 +#define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK
94 +#define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK
95 +#define BCM6348_RESET_USBH SOFTRESET_6348_USBH_MASK
96 +#define BCM6348_RESET_USBD SOFTRESET_6348_USBS_MASK
97 +#define BCM6348_RESET_DSL SOFTRESET_6348_ADSL_MASK
98 +#define BCM6348_RESET_SAR SOFTRESET_6348_SAR_MASK
99 +#define BCM6348_RESET_EPHY 0
100 +#define BCM6348_RESET_ENETSW 0
101 +#define BCM6348_RESET_PCM 0
102 +#define BCM6348_RESET_MPI 0
103 +#define BCM6348_RESET_PCIE 0
104 +#define BCM6348_RESET_PCIE_EXT 0
106 +#define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK
107 +#define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK
108 +#define BCM6358_RESET_USBH SOFTRESET_6358_USBH_MASK
109 +#define BCM6358_RESET_USBD 0
110 +#define BCM6358_RESET_DSL SOFTRESET_6358_ADSL_MASK
111 +#define BCM6358_RESET_SAR SOFTRESET_6358_SAR_MASK
112 +#define BCM6358_RESET_EPHY SOFTRESET_6358_EPHY_MASK
113 +#define BCM6358_RESET_ENETSW 0
114 +#define BCM6358_RESET_PCM SOFTRESET_6358_PCM_MASK
115 +#define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK
116 +#define BCM6358_RESET_PCIE 0
117 +#define BCM6358_RESET_PCIE_EXT 0
119 +#define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK
120 +#define BCM6368_RESET_ENET 0
121 +#define BCM6368_RESET_USBH SOFTRESET_6368_USBH_MASK
122 +#define BCM6368_RESET_USBD SOFTRESET_6368_USBS_MASK
123 +#define BCM6368_RESET_DSL 0
124 +#define BCM6368_RESET_SAR SOFTRESET_6368_SAR_MASK
125 +#define BCM6368_RESET_EPHY SOFTRESET_6368_EPHY_MASK
126 +#define BCM6368_RESET_ENETSW 0
127 +#define BCM6368_RESET_PCM SOFTRESET_6368_PCM_MASK
128 +#define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK
129 +#define BCM6368_RESET_PCIE 0
130 +#define BCM6368_RESET_PCIE_EXT 0
132 +#ifdef BCMCPU_RUNTIME_DETECT
137 +static const u32 bcm6328_reset_bits[] = {
138 + __GEN_RESET_BITS_TABLE(6328)
141 +static const u32 bcm6338_reset_bits[] = {
142 + __GEN_RESET_BITS_TABLE(6338)
145 +static const u32 bcm6348_reset_bits[] = {
146 + __GEN_RESET_BITS_TABLE(6348)
149 +static const u32 bcm6358_reset_bits[] = {
150 + __GEN_RESET_BITS_TABLE(6358)
153 +static const u32 bcm6368_reset_bits[] = {
154 + __GEN_RESET_BITS_TABLE(6368)
157 +const u32 *bcm63xx_reset_bits;
158 +static int reset_reg;
160 +static int __init bcm63xx_reset_bits_init(void)
162 + if (BCMCPU_IS_6328()) {
163 + reset_reg = PERF_SOFTRESET_6328_REG;
164 + bcm63xx_reset_bits = bcm6328_reset_bits;
165 + } else if (BCMCPU_IS_6338()) {
166 + reset_reg = PERF_SOFTRESET_REG;
167 + bcm63xx_reset_bits = bcm6338_reset_bits;
168 + } else if (BCMCPU_IS_6348()) {
169 + reset_reg = PERF_SOFTRESET_REG;
170 + bcm63xx_reset_bits = bcm6348_reset_bits;
171 + } else if (BCMCPU_IS_6358()) {
172 + reset_reg = PERF_SOFTRESET_6358_REG;
173 + bcm63xx_reset_bits = bcm6358_reset_bits;
174 + } else if (BCMCPU_IS_6368()) {
175 + reset_reg = PERF_SOFTRESET_6368_REG;
176 + bcm63xx_reset_bits = bcm6368_reset_bits;
183 +#ifdef CONFIG_BCM63XX_CPU_6328
184 +static const u32 bcm63xx_reset_bits[] = {
185 + __GEN_RESET_BITS_TABLE(6328)
187 +#define reset_reg PERF_SOFTRESET_6328_REG
190 +#ifdef CONFIG_BCM63XX_CPU_6338
191 +static const u32 bcm63xx_reset_bits[] = {
192 + __GEN_RESET_BITS_TABLE(6338)
194 +#define reset_reg PERF_SOFTRESET_REG
197 +#ifdef CONFIG_BCM63XX_CPU_6345
198 +static const u32 bcm63xx_reset_bits[] = { };
202 +#ifdef CONFIG_BCM63XX_CPU_6348
203 +static const u32 bcm63xx_reset_bits[] = {
204 + __GEN_RESET_BITS_TABLE(6348)
206 +#define reset_reg PERF_SOFTRESET_REG
209 +#ifdef CONFIG_BCM63XX_CPU_6358
210 +static const u32 bcm63xx_reset_bits[] = {
211 + __GEN_RESET_BITS_TABLE(6358)
213 +#define reset_reg PERF_SOFTRESET_6358_REG
216 +#ifdef CONFIG_BCM63XX_CPU_6368
217 +static const u32 bcm63xx_reset_bits[] = {
218 + __GEN_RESET_BITS_TABLE(6368)
220 +#define reset_reg PERF_SOFTRESET_6368_REG
223 +static int __init bcm63xx_reset_bits_init(void) { return 0; }
226 +static DEFINE_SPINLOCK(reset_mutex);
228 +static void __bcm63xx_core_set_reset(u32 mask, int enable)
230 + unsigned long flags;
236 + spin_lock_irqsave(&reset_mutex, flags);
237 + val = bcm_perf_readl(reset_reg);
244 + bcm_perf_writel(val, reset_reg);
245 + spin_unlock_irqrestore(&reset_mutex, flags);
248 +void bcm63xx_core_set_reset(enum bcm63xx_core_reset core, int reset)
250 + __bcm63xx_core_set_reset(bcm63xx_reset_bits[core], reset);
252 +EXPORT_SYMBOL(bcm63xx_core_set_reset);
254 +postcore_initcall(bcm63xx_reset_bits_init);
256 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
258 +#ifndef __BCM63XX_RESET_H
259 +#define __BCM63XX_RESET_H
261 +enum bcm63xx_core_reset {
263 + BCM63XX_RESET_ENET,
264 + BCM63XX_RESET_USBH,
265 + BCM63XX_RESET_USBD,
268 + BCM63XX_RESET_EPHY,
269 + BCM63XX_RESET_ENETSW,
272 + BCM63XX_RESET_PCIE,
273 + BCM63XX_RESET_PCIE_EXT,
276 +void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);