1 From 1cacd0f7b0d35f8e3d3f8a69ecb3b5e436d6b9e8 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sun, 22 Dec 2013 13:25:25 +0100
4 Subject: [PATCH 52/56] MIPS: BCM63XX: fixup mapped SPI flash access on boot
6 Some bootloaders leave the flash access in an invalid state with dual
7 read enabled; fix it by disabling it and falling back to simple fast
10 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
12 arch/mips/bcm63xx/dev-flash.c | 36 ++++++++++++++++++++++++++++++++++++
13 1 file changed, 36 insertions(+)
15 --- a/arch/mips/bcm63xx/dev-flash.c
16 +++ b/arch/mips/bcm63xx/dev-flash.c
17 @@ -110,9 +110,46 @@ static int __init bcm63xx_detect_flash_t
21 +#define HSSPI_FLASH_CTRL_REG 0x14
22 +#define FLASH_CTRL_READ_OPCODE_MASK 0xff
23 +#define FLASH_CTRL_ADDR_BYTES_MASK (0x3 << 8)
24 +#define FLASH_CTRL_ADDR_BYTES_2 (0 << 8)
25 +#define FLASH_CTRL_ADDR_BYTES_3 (1 << 8)
26 +#define FLASH_CTRL_ADDR_BYTES_4 (2 << 8)
27 +#define FLASH_CTRL_MB_EN (1 << 23)
29 void __init bcm63xx_flash_detect(void)
31 flash_type = bcm63xx_detect_flash_type();
33 + /* reduce flash mapping to single i/o reads for safety */
34 + if (flash_type == BCM63XX_FLASH_TYPE_SERIAL &&
35 + (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
36 + BCMCPU_IS_63268())) {
37 + u32 val = bcm_rset_readl(RSET_HSSPI, HSSPI_FLASH_CTRL_REG);
39 + if (!(val & FLASH_CTRL_MB_EN))
42 + val &= ~FLASH_CTRL_MB_EN;
43 + val &= ~FLASH_CTRL_READ_OPCODE_MASK;
45 + switch (val & FLASH_CTRL_ADDR_BYTES_MASK) {
46 + case FLASH_CTRL_ADDR_BYTES_3:
47 + val |= 0x0b; /* OPCODE_FAST_READ */
49 + case FLASH_CTRL_ADDR_BYTES_4:
50 + val |= 0x0c; /* OPCODE_FAST_READ_4B */
52 + case FLASH_CTRL_ADDR_BYTES_2:
54 + pr_warn("unsupported address byte mode (%x), not fixing up\n",
55 + val & FLASH_CTRL_ADDR_BYTES_MASK);
59 + bcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG);
63 int __init bcm63xx_flash_register(void)